ar71xx: fix DDR write buffer flushing issues with 4.4

[openwrt/openwrt.git] / target / linux / ar71xx / patches-4.4 / 620-MIPS-ath79-add-support-for-QCA953x-SoC.patch

diff --git a/target/linux/ar71xx/patches-4.4/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch b/target/linux/ar71xx/patches-4.4/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch
index 6fd6dafd47740953782bb0db0f694fd54abea47c..08a684becda6fada81927e6bbf3fbb5c6c8fe559 100644 (file)
--- a/target/linux/ar71xx/patches-4.4/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch
+++ b/target/linux/ar71xx/patches-4.4/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch
@@ -335,10 +335,10 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
 +      status = ath79_reset_rr(QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS);
 +
 +      if (status & QCA953X_PCIE_WMAC_INT_PCIE_ALL) {
-+              ath79_ddr_wb_flush(QCA953X_DDR_REG_FLUSH_PCIE);
++              ath79_ddr_wb_flush(3);
 +              generic_handle_irq(ATH79_IP2_IRQ(0));
 +      } else if (status & QCA953X_PCIE_WMAC_INT_WMAC_ALL) {
-+              ath79_ddr_wb_flush(QCA953X_DDR_REG_FLUSH_WMAC);
++              ath79_ddr_wb_flush(4);
 +              generic_handle_irq(ATH79_IP2_IRQ(1));
 +      } else {
 +              spurious_interrupt();