ar71xx: clean up spi controller related patches

[openwrt/openwrt.git] / target / linux / ar71xx / patches-4.4 / 601-MIPS-ath79-add-more-register-defines.patch

diff --git a/target/linux/ar71xx/patches-4.4/601-MIPS-ath79-add-more-register-defines.patch b/target/linux/ar71xx/patches-4.4/601-MIPS-ath79-add-more-register-defines.patch
index 8bf7658314dd997474002f29ef276894e1e39fb7..c5035778a20155d5b72ffba17b69017bff9d17ba 100644 (file)
--- a/target/linux/ar71xx/patches-4.4/601-MIPS-ath79-add-more-register-defines.patch
+++ b/target/linux/ar71xx/patches-4.4/601-MIPS-ath79-add-more-register-defines.patch
@@ -155,7 +155,7 @@
 +#define AR934X_RESET_LUT              BIT(2)
 +#define AR934X_RESET_MBOX             BIT(1)
 +#define AR934X_RESET_I2S              BIT(0)
-+
+ 
 +#define QCA955X_RESET_HOST            BIT(31)
 +#define QCA955X_RESET_SLIC            BIT(30)
 +#define QCA955X_RESET_HDMA            BIT(29)
@@ -188,13 +188,13 @@
 +#define QCA955X_RESET_LUT             BIT(2)
 +#define QCA955X_RESET_MBOX            BIT(1)
 +#define QCA955X_RESET_I2S             BIT(0)
- 
++
 +#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18)
 +#define AR933X_BOOTSTRAP_EEPBUSY      BIT(4)
  #define AR933X_BOOTSTRAP_REF_CLK_40   BIT(0)
  
  #define AR934X_BOOTSTRAP_SW_OPTION8   BIT(23)
-@@ -529,6 +626,12 @@
+@@ -529,8 +626,22 @@
  #define AR71XX_GPIO_REG_INT_ENABLE    0x24
  #define AR71XX_GPIO_REG_FUNC          0x28
  
@@ -206,8 +206,18 @@
 +#define AR934X_GPIO_REG_OUT_FUNC5     0x40
  #define AR934X_GPIO_REG_FUNC          0x6c
  
++#define QCA955X_GPIO_REG_OUT_FUNC0    0x2c
++#define QCA955X_GPIO_REG_OUT_FUNC1    0x30
++#define QCA955X_GPIO_REG_OUT_FUNC2    0x34
++#define QCA955X_GPIO_REG_OUT_FUNC3    0x38
++#define QCA955X_GPIO_REG_OUT_FUNC4    0x3c
++#define QCA955X_GPIO_REG_OUT_FUNC5    0x40
++#define QCA955X_GPIO_REG_FUNC         0x6c
++
  #define AR71XX_GPIO_COUNT             16
-@@ -560,4 +663,153 @@
+ #define AR7240_GPIO_COUNT             18
+ #define AR7241_GPIO_COUNT             20
+@@ -560,4 +671,235 @@
  #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT        13
  #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
  
@@ -288,6 +298,71 @@
 +#define AR934X_GPIO_OUT_EXT_LNA0      46
 +#define AR934X_GPIO_OUT_EXT_LNA1      47
 +
++#define QCA955X_GPIO_FUNC_CLK_OBS7_EN         BIT(9)
++#define QCA955X_GPIO_FUNC_CLK_OBS6_EN         BIT(8)
++#define QCA955X_GPIO_FUNC_CLK_OBS5_EN         BIT(7)
++#define QCA955X_GPIO_FUNC_CLK_OBS4_EN         BIT(6)
++#define QCA955X_GPIO_FUNC_CLK_OBS3_EN         BIT(5)
++#define QCA955X_GPIO_FUNC_CLK_OBS2_EN         BIT(4)
++#define QCA955X_GPIO_FUNC_CLK_OBS1_EN         BIT(3)
++#define QCA955X_GPIO_FUNC_JTAG_DISABLE                BIT(1)
++
++#define QCA955X_GPIO_OUT_GPIO         0
++#define QCA955X_MII_EXT_MDI           1
++#define QCA955X_SLIC_DATA_OUT         3
++#define QCA955X_SLIC_PCM_FS           4
++#define QCA955X_SLIC_PCM_CLK          5
++#define QCA955X_SPI_CLK                       8
++#define QCA955X_SPI_CS_0              9
++#define QCA955X_SPI_CS_1              10
++#define QCA955X_SPI_CS_2              11
++#define QCA955X_SPI_MISO              12
++#define QCA955X_I2S_CLK                       13
++#define QCA955X_I2S_WS                        14
++#define QCA955X_I2S_SD                        15
++#define QCA955X_I2S_MCK                       16
++#define QCA955X_SPDIF_OUT             17
++#define QCA955X_UART1_TD              18
++#define QCA955X_UART1_RTS             19
++#define QCA955X_UART1_RD              20
++#define QCA955X_UART1_CTS             21
++#define QCA955X_UART0_SOUT            22
++#define QCA955X_SPDIF2_OUT            23
++#define QCA955X_LED_SGMII_SPEED0      24
++#define QCA955X_LED_SGMII_SPEED1      25
++#define QCA955X_LED_SGMII_DUPLEX      26
++#define QCA955X_LED_SGMII_LINK_UP     27
++#define QCA955X_SGMII_SPEED0_INVERT   28
++#define QCA955X_SGMII_SPEED1_INVERT   29
++#define QCA955X_SGMII_DUPLEX_INVERT   30
++#define QCA955X_SGMII_LINK_UP_INVERT  31
++#define QCA955X_GE1_MII_MDO           32
++#define QCA955X_GE1_MII_MDC           33
++#define QCA955X_SWCOM2                        38
++#define QCA955X_SWCOM3                        39
++#define QCA955X_MAC2_GPIO             40
++#define QCA955X_MAC3_GPIO             41
++#define QCA955X_ATT_LED                       42
++#define QCA955X_PWR_LED                       43
++#define QCA955X_TX_FRAME              44
++#define QCA955X_RX_CLEAR_EXTERNAL     45
++#define QCA955X_LED_NETWORK_EN                46
++#define QCA955X_LED_POWER_EN          47
++#define QCA955X_WMAC_GLUE_WOW         68
++#define QCA955X_RX_CLEAR_EXTENSION    70
++#define QCA955X_CP_NAND_CS1           73
++#define QCA955X_USB_SUSPEND           74
++#define QCA955X_ETH_TX_ERR            75
++#define QCA955X_DDR_DQ_OE             76
++#define QCA955X_CLKREQ_N_EP           77
++#define QCA955X_CLKREQ_N_RC           78
++#define QCA955X_CLK_OBS0              79
++#define QCA955X_CLK_OBS1              80
++#define QCA955X_CLK_OBS2              81
++#define QCA955X_CLK_OBS3              82
++#define QCA955X_CLK_OBS4              83
++#define QCA955X_CLK_OBS5              84
++
 +/*
 + * MII_CTRL block
 + */
@@ -358,6 +433,23 @@
 +#define QCA955X_GMAC_REG_ETH_CFG      0x00
 +
 +#define QCA955X_ETH_CFG_RGMII_EN      BIT(0)
++#define QCA955X_ETH_CFG_MII_GE0               BIT(1)
++#define QCA955X_ETH_CFG_GMII_GE0      BIT(2)
++#define QCA955X_ETH_CFG_MII_GE0_MASTER        BIT(3)
++#define QCA955X_ETH_CFG_MII_GE0_SLAVE BIT(4)
++#define QCA955X_ETH_CFG_GE0_ERR_EN    BIT(5)
 +#define QCA955X_ETH_CFG_GE0_SGMII     BIT(6)
++#define QCA955X_ETH_CFG_RMII_GE0      BIT(10)
++#define QCA955X_ETH_CFG_MII_CNTL_SPEED        BIT(11)
++#define QCA955X_ETH_CFG_RMII_GE0_MASTER       BIT(12)
++#define QCA955X_ETH_CFG_RXD_DELAY_MASK        0x3
++#define QCA955X_ETH_CFG_RXD_DELAY_SHIFT       14
++#define QCA955X_ETH_CFG_RDV_DELAY     BIT(16)
++#define QCA955X_ETH_CFG_RDV_DELAY_MASK        0x3
++#define QCA955X_ETH_CFG_RDV_DELAY_SHIFT       16
++#define QCA955X_ETH_CFG_TXD_DELAY_MASK        0x3
++#define QCA955X_ETH_CFG_TXD_DELAY_SHIFT       18
++#define QCA955X_ETH_CFG_TXE_DELAY_MASK        0x3
++#define QCA955X_ETH_CFG_TXE_DELAY_SHIFT       20
 +
  #endif /* __ASM_MACH_AR71XX_REGS_H */