From: Jianhui Zhao Date: Tue, 17 Apr 2018 03:09:14 +0000 (+0800) Subject: samsung/s5pv210: New target X-Git-Url: http://git.openwrt.org/?a=commitdiff_plain;h=84c212da44cf5df210ae166ed7e64adf764ccf3f;p=openwrt%2Fstaging%2Fjow.git samsung/s5pv210: New target Signed-off-by: Jianhui Zhao --- diff --git a/target/linux/samsung/Makefile b/target/linux/samsung/Makefile new file mode 100644 index 0000000000..9227503096 --- /dev/null +++ b/target/linux/samsung/Makefile @@ -0,0 +1,26 @@ +# +# Copyright (C) 2018 Jianhui Zhao +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +include $(TOPDIR)/rules.mk + +ARCH:=arm +BOARD:=samsung +BOARDNAME:=Samsung s3c24xx/s5pv210 +SUBTARGETS:=s5pv210 +MAINTAINER:=Jianhui Zhao + +KERNEL_PATCHVER:=4.14 + +define Target/Description + Build firmware images for Samsung s3c24xx/s5pv210 based boards. +endef + +include $(INCLUDE_DIR)/target.mk + +KERNELNAME:=zImage dtbs + +$(eval $(call BuildTarget)) diff --git a/target/linux/samsung/dts/TQ210.dts b/target/linux/samsung/dts/TQ210.dts new file mode 100644 index 0000000000..86a25574e9 --- /dev/null +++ b/target/linux/samsung/dts/TQ210.dts @@ -0,0 +1,70 @@ +/* + * Samsung's S5PV210 SoC device tree source + * Copyright (C) 2018 Jianhui Zhao + * + * Board device tree source for TQ210 board. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; +#include +#include +#include "s5pv210.dtsi" + +/ { + model = "Embedsky TQ210 based on S5PV210"; + compatible = "embedsky,tq210", "samsung,s5pv210"; + + chosen { + bootargs = "console=ttySAC0,115200n8"; + }; + + memory@20000000 { + device_type = "memory"; + reg = <0x20000000 0x40000000>; + }; + + ethernet@88000000 { + compatible = "davicom,dm9000"; + reg = <0x88000000 0x2 0x88000004 0x2>; + interrupt-parent = <&gph1>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; + local-mac-address = [00 00 de ad be ef]; + davicom,no-eeprom; + clocks = <&clocks CLK_SROMC>; + clock-names = "sromc"; + }; +}; + +&xxti { + clock-frequency = <24000000>; +}; + +&uart0 { + status = "okay"; +}; + +&nand { + status = "okay"; + nand-ecc-mode = "soft"; + + partition@0 { + label = "boot"; + reg = <0x0 0x40000>; /* 246KB */ + read-only; + }; + + partition@40000 { + label = "kernel"; + reg = <0x40000 0x300000>; /* 3MB */ + }; + + partition@340000 { + label = "rootfs"; + reg = <0x340000 0x3fcc0000>; /* 1020MB */ + }; + +}; diff --git a/target/linux/samsung/files-4.14/drivers/mtd/nand/s5pxx_nand.c b/target/linux/samsung/files-4.14/drivers/mtd/nand/s5pxx_nand.c new file mode 100644 index 0000000000..26ec75dd19 --- /dev/null +++ b/target/linux/samsung/files-4.14/drivers/mtd/nand/s5pxx_nand.c @@ -0,0 +1,499 @@ +/* + * Copyright (c) 2018 Jianhui Zhao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#define S5P_NFCONF 0x00 +#define S5P_NFCONT 0x04 +#define S5P_NFCMD 0x08 +#define S5P_NFADDR 0x0c +#define S5P_NFDATA 0x10 +#define S5P_NFMECCDATA0 0x14 +#define S5P_NFMECCDATA1 0x18 +#define S5P_NFSECCDATA 0x1c +#define S5P_NFSBLK 0x20 +#define S5P_NFEBLK 0x24 +#define S5P_NFSTAT 0x28 +#define S5P_NFMECCERR0 0x2c +#define S5P_NFMECCERR1 0x30 +#define S5P_NFMECC0 0x34 +#define S5P_NFMECC1 0x38 +#define S5P_NFSECC 0x3c +#define S5P_NFMLCBITPT 0x40 +#define S5P_NF8ECCERR0 0x44 +#define S5P_NF8ECCERR1 0x48 +#define S5P_NF8ECCERR2 0x4C +#define S5P_NFM8ECC0 0x50 +#define S5P_NFM8ECC1 0x54 +#define S5P_NFM8ECC2 0x58 +#define S5P_NFM8ECC3 0x5C +#define S5P_NFMLC8BITPT0 0x60 +#define S5P_NFMLC8BITPT1 0x64 + +#define S5P_NFECCCONF 0x00 +#define S5P_NFECCCONT 0x20 +#define S5P_NFECCSTAT 0x30 +#define S5P_NFECCSECSTAT 0x40 +#define S5P_NFECCPRGECC 0x90 +#define S5P_NFECCERL 0xC0 +#define S5P_NFECCERP 0xF0 + +#define S5P_NFCONF_NANDBOOT (1 << 31) +#define S5P_NFCONF_ECCCLKCON (1 << 30) +#define S5P_NFCONF_ECC_MLC (1 << 24) +#define S5P_NFCONF_ECC_1BIT (0 << 23) +#define S5P_NFCONF_ECC_4BIT (2 << 23) +#define S5P_NFCONF_ECC_8BIT (1 << 23) +#define S5P_NFCONF_TACLS(x) ((x) << 12) +#define S5P_NFCONF_TWRPH0(x) ((x) << 8) +#define S5P_NFCONF_TWRPH1(x) ((x) << 4) +#define S5P_NFCONF_MLC (1 << 3) +#define S5P_NFCONF_PAGESIZE (1 << 2) +#define S5P_NFCONF_ADDRCYCLE (1 << 1) +#define S5P_NFCONF_BUSWIDTH (1 << 0) + +#define S5P_NFCONT_ECC_ENC (1 << 18) +#define S5P_NFCONT_LOCKTGHT (1 << 17) +#define S5P_NFCONT_LOCKSOFT (1 << 16) +#define S5P_NFCONT_MECCLOCK (1 << 7) +#define S5P_NFCONT_SECCLOCK (1 << 6) +#define S5P_NFCONT_INITMECC (1 << 5) +#define S5P_NFCONT_INITSECC (1 << 4) +#define S5P_NFCONT_nFCE1 (1 << 2) +#define S5P_NFCONT_nFCE0 (1 << 1) +#define S5P_NFCONT_MODE (1 << 0) + +#define S5P_NFSTAT_READY (1 << 0) + +#define S5P_NFECCCONT_MECCRESET (1 << 0) +#define S5P_NFECCCONT_MECCINIT (1 << 2) +#define S5P_NFECCCONT_ECCDIRWR (1 << 16) + +#define S5P_NFECCSTAT_ECCBUSY (1 << 31) + +enum s5p_cpu_type { + TYPE_S5PV210, +}; + +struct s5p_nand_host { + struct nand_chip nand_chip; + void __iomem *nf_base; + void __iomem *ecc_base; + struct clk *clk[2]; + enum s5p_cpu_type cpu_type; +}; + +/* + * See "S5PV210 iROM Application Note" for recommended ECC layout + * ECC layout for 8-bit ECC (13 bytes/page) + * Compatible with bl0 bootloader, see iROM appnote + */ +/* new oob placement block for use with hardware ecc generation + */ +static int s5pcxx_ooblayout_ecc(struct mtd_info *mtd, int section, + struct mtd_oob_region *oobregion) +{ + if (section) + return -ERANGE; + + oobregion->offset = 12; + oobregion->length = 52; + + return 0; +} + +static int s5pcxx_ooblayout_free(struct mtd_info *mtd, int section, + struct mtd_oob_region *oobregion) +{ + if (section) + return -ERANGE; + + oobregion->offset = 2; + oobregion->length = 10; + + return 0; +} + +static const struct mtd_ooblayout_ops s5pcxx_ooblayout_ops = { + .ecc = s5pcxx_ooblayout_ecc, + .free = s5pcxx_ooblayout_free, +}; + +static inline void rwl(void *reg, uint32_t rst, uint32_t set) +{ + uint32_t r; + r = readl(reg); + r &= ~rst; + r |= set; + writel(r, reg); +} + +/* + * Hardware specific access to control-lines function + */ +static void s5p_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl) +{ + struct nand_chip *nand_chip = mtd->priv; + struct s5p_nand_host *host = nand_chip->priv; + + if (dat == NAND_CMD_NONE) + return; + + if (ctrl & NAND_CLE) + writeb(dat, host->nf_base + S5P_NFCMD); + else + writeb(dat, host->nf_base + S5P_NFADDR); +} + +/* + * Function for checking device ready pin + */ +static int s5p_nand_device_ready(struct mtd_info *mtd) +{ + struct nand_chip *nand_chip = mtd->priv; + struct s5p_nand_host *host = nand_chip->priv; + + /* it's to check the RnB nand signal bit and + * return to device ready condition in nand_base.c + */ + return readl(host->nf_base + S5P_NFSTAT) & S5P_NFSTAT_READY; +} + +static void s3_nand_select_chip(struct mtd_info *mtd, int chip) +{ + struct nand_chip *nand_chip = mtd->priv; + struct s5p_nand_host *host = nand_chip->priv; + u32 value = readl(host->nf_base + S5P_NFCONT); + + if (chip == -1) + value |= S5P_NFCONT_nFCE0; /* deselect */ + else + value &= ~S5P_NFCONT_nFCE0; /* select */ + + writel(value, host->nf_base + S5P_NFCONT); +} + +static void s5pcxx_nand_enable_hwecc(struct mtd_info *mtd, int mode) +{ + struct nand_chip *chip = mtd->priv; + struct s5p_nand_host *host = chip->priv; + + uint32_t reg; + + /* Set ECC mode */ + reg = 3; /* 8-bit */ + reg |= (chip->ecc.size - 1) << 16; + writel(reg, host->ecc_base + S5P_NFECCCONF); + + /* Set ECC direction */ + rwl(host->ecc_base + S5P_NFECCCONT, S5P_NFECCCONT_ECCDIRWR, + (mode == NAND_ECC_WRITE) ? S5P_NFECCCONT_ECCDIRWR : 0); + + /* Reset status bits */ + rwl(host->ecc_base + S5P_NFECCSTAT, 0, (1 << 24) | (1 << 25)); + + /* Unlock ECC */ + rwl(host->nf_base + S5P_NFCONT, S5P_NFCONT_MECCLOCK, 0); + + /* Initialize ECC */ + rwl(host->ecc_base +S5P_NFECCCONT, 0, S5P_NFECCCONT_MECCINIT); +} + +static void readecc(void *eccbase, uint8_t *ecc_code, unsigned ecc_len) +{ + uint32_t i, j, reg; + + for (i = 0; i < ecc_len; i += 4) { + reg = readl(eccbase + i); + for (j = 0; (j < 4) && (i + j < ecc_len); ++j) { + ecc_code[i + j] = reg & 0xFF; + reg >>= 8; + } + } +} + +static int s5pcxx_nand_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, uint8_t *ecc_code) +{ + struct nand_chip *chip = mtd->priv; + struct s5p_nand_host *host = chip->priv; + + /* Lock ECC */ + rwl(host->nf_base + S5P_NFCONT, 0, S5P_NFCONT_MECCLOCK); + + if (ecc_code) /* NAND_ECC_WRITE */ { + /* ECC encoding is completed */ + while (!(readl(host->ecc_base + S5P_NFECCSTAT) & (1 << 25))); + readecc(host->ecc_base + S5P_NFECCPRGECC, ecc_code, chip->ecc.bytes); + } else { /* NAND_ECC_READ */ + /* ECC decoding is completed */ + while (!(readl(host->ecc_base + S5P_NFECCSTAT) & (1 << 24))); + } + + return 0; +} + +static int s5pcxx_nand_correct_data(struct mtd_info *mtd, u8 *dat, + u8 *read_ecc, u8 *calc_ecc) +{ + int ret = 0; + u32 errNo; + u32 erl0, erl1, erl2, erl3, erp0, erp1; + struct nand_chip *chip = mtd->priv; + struct s5p_nand_host *host = chip->priv; + + /* Wait until the 8-bit ECC decoding engine is Idle */ + while (readl(host->ecc_base + S5P_NFECCSTAT) & (1 << 31)); + + errNo = readl(host->ecc_base + S5P_NFECCSECSTAT) & 0x1F; + erl0 = readl(host->ecc_base + S5P_NFECCERL); + erl1 = readl(host->ecc_base + S5P_NFECCERL + 0x04); + erl2 = readl(host->ecc_base + S5P_NFECCERL + 0x08); + erl3 = readl(host->ecc_base + S5P_NFECCERL + 0x0C); + + erp0 = readl(host->ecc_base + S5P_NFECCERP); + erp1 = readl(host->ecc_base + S5P_NFECCERP + 0x04); + + switch (errNo) { + case 8: + dat[(erl3 >> 16) & 0x3FF] ^= (erp1 >> 24) & 0xFF; + case 7: + dat[erl3 & 0x3FF] ^= (erp1 >> 16) & 0xFF; + case 6: + dat[(erl2 >> 16) & 0x3FF] ^= (erp1 >> 8) & 0xFF; + case 5: + dat[erl2 & 0x3FF] ^= erp1 & 0xFF; + case 4: + dat[(erl1 >> 16) & 0x3FF] ^= (erp0 >> 24) & 0xFF; + case 3: + dat[erl1 & 0x3FF] ^= (erp0 >> 16) & 0xFF; + case 2: + dat[(erl0 >> 16) & 0x3FF] ^= (erp0 >> 8) & 0xFF; + case 1: + dat[erl0 & 0x3FF] ^= erp0 & 0xFF; + case 0: + break; + default: + ret = -1; + printk("ECC uncorrectable error detected:%d\n", errNo); + break; + } + + return ret; +} + +static int s5pcxx_nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, + uint8_t *buf, int oob_required, int page) +{ + struct mtd_oob_region oobregion = { }; + int i, eccsize = chip->ecc.size; + int eccbytes = chip->ecc.bytes; + int eccsteps = chip->ecc.steps; + uint8_t *oobecc; + int col, stat; + + /* Read the OOB area first */ + chip->ecc.read_oob(mtd, chip, page); + mtd_ooblayout_ecc(mtd, 0, &oobregion); + oobecc = chip->oob_poi + oobregion.offset; + + for (i = 0, col = 0; eccsteps; eccsteps--, i += eccbytes, buf += eccsize, col += eccsize) { + chip->cmdfunc(mtd, NAND_CMD_RNDOUT, col, -1); + chip->ecc.hwctl(mtd, NAND_ECC_READ); + chip->read_buf(mtd, buf, eccsize); + chip->write_buf(mtd, oobecc + i, eccbytes); + chip->ecc.calculate(mtd, NULL, NULL); + stat = chip->ecc.correct(mtd, buf, NULL, NULL); + if (stat < 0) + mtd->ecc_stats.failed++; + else + mtd->ecc_stats.corrected += stat; + } + return 0; +} + +static void s5p_nand_inithw_later(struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd->priv; + struct s5p_nand_host *host = chip->priv; + u32 value; + + value = readl(host->nf_base + S5P_NFCONF); + + if (nand_is_slc(chip)) { + value &= ~S5P_NFCONF_MLC; + + if (mtd->writesize == 512) { + value |= S5P_NFCONF_PAGESIZE; + + } else { + value &= ~S5P_NFCONF_PAGESIZE; + } + } else { + value |= S5P_NFCONF_MLC; + + if (mtd->writesize == 4096) + value &= ~S5P_NFCONF_PAGESIZE; + else + value |= S5P_NFCONF_PAGESIZE; + } +} + +static void s5p_nand_inithw(struct s5p_nand_host *host) +{ + u32 value; + + /* Enable NAND Flash Controller */ + value = readl(host->nf_base + S5P_NFCONT); + writel(value | S5P_NFCONT_MODE, host->nf_base + S5P_NFCONT); +} + +static void s5p_nand_parse_dt(struct s5p_nand_host *host, struct device *dev) +{ + host->cpu_type = (enum s5p_cpu_type)of_device_get_match_data(dev); +} + +static int s5p_nand_probe(struct platform_device *pdev) +{ + int ret; + struct s5p_nand_host *host; + struct nand_chip *nand_chip; + struct mtd_info *mtd; + struct resource *mem; + + /* Allocate memory for the device structure (and zero it) */ + host = devm_kzalloc(&pdev->dev, sizeof(struct s5p_nand_host), GFP_KERNEL); + if (!host) + return -ENOMEM; + + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + host->nf_base = devm_ioremap_resource(&pdev->dev, mem); + if (IS_ERR(host->nf_base)) + return PTR_ERR(host->nf_base); + + mem = platform_get_resource(pdev, IORESOURCE_MEM, 1); + host->ecc_base = devm_ioremap_resource(&pdev->dev, mem); + if (IS_ERR(host->ecc_base)) + return PTR_ERR(host->ecc_base); + + nand_chip = &host->nand_chip; + nand_chip->priv = host; + nand_set_flash_node(nand_chip, pdev->dev.of_node); + + mtd = nand_to_mtd(nand_chip); + mtd->dev.parent = &pdev->dev; + mtd->priv = nand_chip; + + /* Disable chip select and Enable NAND Flash Controller */ + writel((0x1 << 1) | (0x1 << 0), host->nf_base + S5P_NFCONT); + + /* Set address of NAND IO lines */ + nand_chip->IO_ADDR_R = host->nf_base + S5P_NFDATA; + nand_chip->IO_ADDR_W = host->nf_base + S5P_NFDATA; + + platform_set_drvdata(pdev, host); + + /* get the clock source and enable it */ + host->clk[0] = devm_clk_get(&pdev->dev, "nandxl"); + if (IS_ERR(host->clk[0])) { + dev_err(&pdev->dev, "cannot get clock of nandxl\n"); + return -ENOENT; + } + clk_prepare_enable(host->clk[0]); + + host->clk[1] = devm_clk_get(&pdev->dev, "nand"); + if (IS_ERR(host->clk[1])) { + dev_err(&pdev->dev, "cannot get clock of nand\n"); + return -ENOENT; + } + clk_prepare_enable(host->clk[1]); + + s5p_nand_parse_dt(host, &pdev->dev); + + nand_chip->select_chip = s3_nand_select_chip; + nand_chip->cmd_ctrl = s5p_cmd_ctrl; + nand_chip->dev_ready = s5p_nand_device_ready; + + s5p_nand_inithw(host); + + ret = nand_scan_ident(mtd, 1, NULL); + if (ret) + return ret; + + if (nand_chip->ecc.mode == NAND_ECC_HW) { + nand_chip->ecc.correct = s5pcxx_nand_correct_data; + nand_chip->ecc.calculate = s5pcxx_nand_calculate_ecc; + nand_chip->ecc.hwctl = s5pcxx_nand_enable_hwecc; + nand_chip->ecc.read_page = s5pcxx_nand_read_page_hwecc; + + nand_chip->ecc.size = 512; + nand_chip->ecc.bytes = 13; + + mtd_set_ooblayout(nand_to_mtd(nand_chip), &s5pcxx_ooblayout_ops); + } + + ret = nand_scan_tail(mtd); + if (ret) + return ret; + + /* After you get the actual hardware information */ + s5p_nand_inithw_later(mtd); + + return mtd_device_parse_register(mtd, NULL, NULL, NULL, 0); +} + +static int s5p_nand_remove(struct platform_device *pdev) +{ + struct s5p_nand_host *host = platform_get_drvdata(pdev); + struct mtd_info *mtd = nand_to_mtd(&host->nand_chip); + + nand_release(mtd); + clk_disable_unprepare(host->clk[0]); /* nandxl */ + clk_disable_unprepare(host->clk[1]); /* nand */ + + return 0; +} + +static const struct of_device_id s5p_nand_match[] = { + { .compatible = "samsung,s5pv210-nand", .data = TYPE_S5PV210 }, + {}, +}; +MODULE_DEVICE_TABLE(of, s5p_nand_match); + +static struct platform_driver s5p_nand_driver = { + .probe = s5p_nand_probe, + .remove = s5p_nand_remove, + .driver = { + .name = "s5p-nand", + .owner = THIS_MODULE, + .of_match_table = s5p_nand_match, + }, +}; +module_platform_driver(s5p_nand_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Jianhui Zhao "); +MODULE_DESCRIPTION("S5Pxx MTD NAND driver"); diff --git a/target/linux/samsung/image/Makefile b/target/linux/samsung/image/Makefile new file mode 100644 index 0000000000..f0b1842caa --- /dev/null +++ b/target/linux/samsung/image/Makefile @@ -0,0 +1,25 @@ +# +# Copyright (C) 2018 Jianhui Zhao +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/image.mk + +KERNEL_LOADADDR := 0x20008000 + +define Device/Default + PROFILES = Default + KERNEL_NAME := zImage + KERNEL := kernel-bin | append-dtb | uImage none +endef + +define Device/tq210 + DEVICE_DTS_DIR := ../dts + DEVICE_DTS := TQ210 + DEVICE_TITLE := TQ210 +endef +TARGET_DEVICES += tq210 + +$(eval $(call BuildImage)) diff --git a/target/linux/samsung/patches-4.14/001-s5pv210-nand.patch b/target/linux/samsung/patches-4.14/001-s5pv210-nand.patch new file mode 100644 index 0000000000..3a35e26f39 --- /dev/null +++ b/target/linux/samsung/patches-4.14/001-s5pv210-nand.patch @@ -0,0 +1,44 @@ +--- a/arch/arm/boot/dts/s5pv210.dtsi ++++ b/arch/arm/boot/dts/s5pv210.dtsi +@@ -95,6 +95,16 @@ + status = "disabled"; + }; + ++ nand: nand@b0000000 { ++ compatible = "samsung,s5pv210-nand"; ++ reg = <0xb0e00000 0x40>, <0xb0e20000 0x200>; ++ clocks = <&clocks CLK_NANDXL>, <&clocks CLK_NFCON>; ++ clock-names = "nandxl", "nand"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ status = "disabled"; ++ }; ++ + chipid@e0000000 { + compatible = "samsung,s5pv210-chipid"; + reg = <0xe0000000 0x1000>; +--- a/drivers/mtd/nand/Kconfig ++++ b/drivers/mtd/nand/Kconfig +@@ -181,6 +181,12 @@ config MTD_NAND_S3C2410_CLKSTOP + when the is NAND chip selected or released, but will save + approximately 5mA of power when there is nothing happening. + ++config MTD_NAND_S5PXX ++ tristate "NAND Flash support for Samsung S5Pxx SoCs" ++ depends on ARCH_S5PV210 ++ help ++ This enables the NAND flash controller on the S5Pxx SoCs ++ + config MTD_NAND_TANGO + tristate "NAND Flash support for Tango chips" + depends on ARCH_TANGO || COMPILE_TEST +--- a/drivers/mtd/nand/Makefile ++++ b/drivers/mtd/nand/Makefile +@@ -16,6 +16,7 @@ obj-$(CONFIG_MTD_NAND_DENALI_DT) += dena + obj-$(CONFIG_MTD_NAND_AU1550) += au1550nd.o + obj-$(CONFIG_MTD_NAND_BF5XX) += bf5xx_nand.o + obj-$(CONFIG_MTD_NAND_S3C2410) += s3c2410.o ++obj-$(CONFIG_MTD_NAND_S5PXX) += s5pxx_nand.o + obj-$(CONFIG_MTD_NAND_TANGO) += tango_nand.o + obj-$(CONFIG_MTD_NAND_DAVINCI) += davinci_nand.o + obj-$(CONFIG_MTD_NAND_DISKONCHIP) += diskonchip.o diff --git a/target/linux/samsung/patches-4.14/002-dm9000-clk.patch b/target/linux/samsung/patches-4.14/002-dm9000-clk.patch new file mode 100644 index 0000000000..1bf2a7ab20 --- /dev/null +++ b/target/linux/samsung/patches-4.14/002-dm9000-clk.patch @@ -0,0 +1,37 @@ +--- a/drivers/net/ethernet/davicom/dm9000.c ++++ b/drivers/net/ethernet/davicom/dm9000.c +@@ -39,6 +39,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -1436,6 +1437,7 @@ dm9000_probe(struct platform_device *pde + enum of_gpio_flags flags; + struct regulator *power; + bool inv_mac_addr = false; ++ const char *clk_name; + + power = devm_regulator_get(dev, "vcc"); + if (IS_ERR(power)) { +@@ -1573,6 +1575,18 @@ dm9000_probe(struct platform_device *pde + goto out; + } + ++ /* Enable clock if specified */ ++ if (!of_property_read_string(dev->of_node, "clock-names", &clk_name)) { ++ struct clk *clk = devm_clk_get(dev, clk_name); ++ if (IS_ERR(clk)) { ++ dev_err(dev, "cannot get clock of %s\n", clk_name); ++ ret = PTR_ERR(clk); ++ goto out; ++ } ++ clk_prepare_enable(clk); ++ dev_info(dev, "enable clock '%s'\n", clk_name); ++ } ++ + /* fill in parameters for net-dev structure */ + ndev->base_addr = (unsigned long)db->io_addr; + diff --git a/target/linux/samsung/s5pv210/config-4.14 b/target/linux/samsung/s5pv210/config-4.14 new file mode 100644 index 0000000000..838d313140 --- /dev/null +++ b/target/linux/samsung/s5pv210/config-4.14 @@ -0,0 +1,414 @@ +CONFIG_ALIGNMENT_TRAP=y +CONFIG_ARCH_CLOCKSOURCE_DATA=y +CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y +CONFIG_ARCH_HAS_SET_MEMORY=y +CONFIG_ARCH_HAS_SG_CHAIN=y +CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y +CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MMAP_RND_BITS_MAX=15 +CONFIG_ARCH_MULTIPLATFORM=y +# CONFIG_ARCH_MULTI_CPU_AUTO is not set +CONFIG_ARCH_MULTI_V6_V7=y +CONFIG_ARCH_MULTI_V7=y +CONFIG_ARCH_NR_GPIO=512 +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y +CONFIG_ARCH_S5PV210=y +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +# CONFIG_ARCH_WANTS_THP_SWAP is not set +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_ARM=y +CONFIG_ARM_AMBA=y +CONFIG_ARM_APPENDED_DTB=y +# CONFIG_ARM_ATAG_DTB_COMPAT is not set +CONFIG_ARM_CPU_SUSPEND=y +CONFIG_ARM_HAS_SG_CHAIN=y +CONFIG_ARM_HEAVY_MB=y +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_L1_CACHE_SHIFT_6=y +# CONFIG_ARM_LPAE is not set +CONFIG_ARM_PATCH_IDIV=y +CONFIG_ARM_PATCH_PHYS_VIRT=y +# CONFIG_ARM_SMMU is not set +CONFIG_ARM_THUMB=y +# CONFIG_ARM_THUMBEE is not set +CONFIG_ARM_UNWIND=y +CONFIG_ARM_VIC=y +CONFIG_ARM_VIC_NR=4 +CONFIG_ARM_VIRT_EXT=y +CONFIG_ATAGS=y +CONFIG_AUTO_ZRELADDR=y +# CONFIG_BLK_DEV is not set +# CONFIG_BPF_SYSCALL is not set +CONFIG_CACHE_L2X0=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CLKSRC_SAMSUNG_PWM=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_COMMON_CLK=y +CONFIG_COMMON_CLK_SAMSUNG=y +CONFIG_COMPACTION=y +CONFIG_COMPAT_BRK=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_COREDUMP=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_CPU_HAS_ASID=y +# CONFIG_CPU_ICACHE_DISABLE is not set +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_PM=y +CONFIG_CPU_S5PV210=y +CONFIG_CPU_THUMB_CAPABLE=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_V7=y +# CONFIG_CRASHLOG is not set +CONFIG_CRC16=y +# CONFIG_CRC32_SARWATE is not set +CONFIG_CRC32_SLICEBY8=y +CONFIG_CRC_CCITT=y +CONFIG_CROSS_MEMORY_ATTACH=y +CONFIG_CRYPTO_ACOMP2=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_WORKQUEUE=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_ALIGN_RODATA=y +CONFIG_DEBUG_ATOMIC_SLEEP=y +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_FS is not set +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_INFO_REDUCED is not set +CONFIG_DEBUG_LL=y +CONFIG_DEBUG_LL_INCLUDE="debug/s5pv210.S" +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_DEBUG_MUTEXES=y +CONFIG_DEBUG_RT_MUTEXES=y +CONFIG_DEBUG_S3C_UART=0 +CONFIG_DEBUG_S3C_UART0=y +# CONFIG_DEBUG_S3C_UART1 is not set +# CONFIG_DEBUG_S3C_UART2 is not set +# CONFIG_DEBUG_S3C_UART3 is not set +CONFIG_DEBUG_S5PV210_UART=y +CONFIG_DEBUG_SPINLOCK=y +# CONFIG_DEBUG_UART_8250 is not set +CONFIG_DEBUG_UNCOMPRESS=y +CONFIG_DEBUG_USER=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_LZ4=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_DECOMPRESS_LZO=y +CONFIG_DECOMPRESS_XZ=y +CONFIG_DEFAULT_IOSCHED="noop" +CONFIG_DEFAULT_NOOP=y +CONFIG_DEVMEM=y +CONFIG_DM9000=y +# CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL is not set +# CONFIG_DMA_NOOP_OPS is not set +# CONFIG_DMA_VIRT_OPS is not set +CONFIG_DNOTIFY=y +# CONFIG_DRM_LIB_RANDOM is not set +CONFIG_DTC=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_EARLY_PRINTK=y +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_EDAC_SUPPORT=y +CONFIG_ELF_CORE=y +# CONFIG_EMBEDDED is not set +# CONFIG_ENABLE_DEFAULT_TRACERS is not set +CONFIG_ENABLE_MUST_CHECK=y +# CONFIG_EXPERT is not set +CONFIG_EXPORTFS=y +# CONFIG_EXYNOS_AUDSS_CLK_CON is not set +CONFIG_FHANDLE=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FREEZER=y +CONFIG_FS_POSIX_ACL=y +CONFIG_FTRACE=y +# CONFIG_FTRACE_SYSCALLS is not set +CONFIG_FUTEX_PI=y +# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IO=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GPIOLIB=y +# CONFIG_GRO_CELLS is not set +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_ARCH_AUDITSYSCALL=y +CONFIG_HAVE_ARCH_BITREVERSE=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_ARM_SMCCC=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_HAVE_CC_STACKPROTECTOR=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y +CONFIG_HAVE_EBPF_JIT=y +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_OPTPROBES=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_SMP=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_UID16=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HW_CONSOLE=y +CONFIG_HW_RANDOM=y +CONFIG_HZ_FIXED=0 +CONFIG_INITRAMFS_SOURCE="" +CONFIG_INPUT=y +# CONFIG_INPUT_MISC is not set +CONFIG_IOMMU_HELPER=y +# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set +# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set +CONFIG_IOMMU_SUPPORT=y +# CONFIG_IOSCHED_DEADLINE is not set +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +# CONFIG_ISDN is not set +# CONFIG_JFFS2_FS is not set +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_MODE_NEON is not set +# CONFIG_KERNEL_XZ is not set +# CONFIG_LBDAF is not set +CONFIG_LIBFDT=y +CONFIG_LOCALVERSION_AUTO=y +CONFIG_LZ4_DECOMPRESS=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_MAGIC_SYSRQ_SERIAL=y +CONFIG_MANDATORY_FILE_LOCKING=y +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +CONFIG_MIGHT_HAVE_PCI=y +CONFIG_MIGRATION=y +CONFIG_MODULES_USE_ELF_REL=y +# CONFIG_MODULE_STRIPPED is not set +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_S5PXX=y +# CONFIG_MTD_ROOTFS_ROOT_DEV is not set +CONFIG_MTD_SPLIT_FIRMWARE=y +# CONFIG_MTD_SPLIT_SQUASHFS_ROOT is not set +CONFIG_MTD_SPLIT_UIMAGE_FW=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_MTD_UBI_BLOCK=y +# CONFIG_MTD_UBI_FASTMAP is not set +# CONFIG_MTD_UBI_GLUEBI is not set +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MULTI_IRQ_HANDLER=y +CONFIG_NAMESPACES=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_PER_CPU_KM=y +CONFIG_NEON=y +# CONFIG_NETWORK_FILESYSTEMS is not set +# CONFIG_NET_CADENCE is not set +CONFIG_NET_NS=y +# CONFIG_NEW_LEDS is not set +CONFIG_NLS=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NO_BOOTMEM=y +CONFIG_NO_HZ=y +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y +CONFIG_NO_IOPORT_MAP=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_NET=y +CONFIG_OF_RESERVED_MEM=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_OUTER_CACHE=y +CONFIG_OUTER_CACHE_SYNC=y +CONFIG_PAGE_OFFSET=0x80000000 +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 +# CONFIG_PARTITION_ADVANCED is not set +# CONFIG_PCI_DOMAINS_GENERIC is not set +# CONFIG_PCI_SYSCALL is not set +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PID_NS=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_EXYNOS=y +CONFIG_PINCTRL_EXYNOS_ARM=y +CONFIG_PINCTRL_SAMSUNG=y +# CONFIG_PINCTRL_SINGLE is not set +# CONFIG_PL310_ERRATA_588369 is not set +# CONFIG_PL310_ERRATA_727915 is not set +# CONFIG_PL310_ERRATA_753970 is not set +# CONFIG_PL310_ERRATA_769419 is not set +CONFIG_PLAT_SAMSUNG=y +CONFIG_PM=y +CONFIG_PM_CLK=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_PREEMPT=y +CONFIG_PREEMPT_COUNT=y +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_RCU=y +# CONFIG_PROBE_EVENTS is not set +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_RATIONAL=y +CONFIG_RCU_CPU_STALL_TIMEOUT=21 +# CONFIG_RCU_EXPERT is not set +CONFIG_RCU_NEED_SEGCBLIST=y +CONFIG_RCU_STALL_COMMON=y +CONFIG_RD_BZIP2=y +CONFIG_RD_GZIP=y +CONFIG_RD_LZ4=y +CONFIG_RD_LZMA=y +CONFIG_RD_LZO=y +CONFIG_RD_XZ=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +# CONFIG_SAMSUNG_ATAGS is not set +# CONFIG_SAMSUNG_PM_CHECK is not set +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHED_INFO is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SERIAL_8250_CONSOLE is not set +CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_AMBA_PL011 is not set +CONFIG_SERIAL_SAMSUNG=y +CONFIG_SERIAL_SAMSUNG_CONSOLE=y +# CONFIG_SERIAL_SAMSUNG_DEBUG is not set +CONFIG_SERIAL_SAMSUNG_UARTS=4 +CONFIG_SERIAL_SAMSUNG_UARTS_4=y +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +CONFIG_SLUB_DEBUG=y +CONFIG_SPARSE_IRQ=y +# CONFIG_SQUASHFS is not set +CONFIG_SRCU=y +# CONFIG_STAGING is not set +# CONFIG_STRIP_ASM_SYMS is not set +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_SWIOTLB=y +# CONFIG_SWP_EMULATE is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +CONFIG_SYSFS_SYSCALL=y +# CONFIG_SYSVIPC is not set +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_TASKS_RCU=y +# CONFIG_TEXTSEARCH is not set +CONFIG_THIN_ARCHIVES=y +# CONFIG_THUMB2_KERNEL is not set +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TRACING_EVENTS_GPIO=y +CONFIG_TREE_SRCU=y +CONFIG_UBIFS_FS=y +# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set +CONFIG_UBIFS_FS_LZO=y +CONFIG_UBIFS_FS_ZLIB=y +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +CONFIG_UNINLINE_SPIN_UNLOCK=y +# CONFIG_USERIO is not set +# CONFIG_USER_NS is not set +CONFIG_USE_OF=y +CONFIG_UTS_NS=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_VMSPLIT_2G=y +# CONFIG_VMSPLIT_3G is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_VT_CONSOLE_SLEEP=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_WATCHDOG is not set +# CONFIG_WIRELESS is not set +# CONFIG_WLAN is not set +# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_XZ_DEC_IA64=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_X86=y +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y diff --git a/target/linux/samsung/s5pv210/profiles/00-default.mk b/target/linux/samsung/s5pv210/profiles/00-default.mk new file mode 100644 index 0000000000..5dd6879760 --- /dev/null +++ b/target/linux/samsung/s5pv210/profiles/00-default.mk @@ -0,0 +1,16 @@ +# +# Copyright (C) 2017 Lede +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Default + NAME:=Default Profile (all drivers) + PRIORITY := 1 +endef + +define Profile/Default/Description + Default profile with package set compatible with most boards. +endef +$(eval $(call Profile,Default)) diff --git a/target/linux/samsung/s5pv210/target.mk b/target/linux/samsung/s5pv210/target.mk new file mode 100644 index 0000000000..a960a537d8 --- /dev/null +++ b/target/linux/samsung/s5pv210/target.mk @@ -0,0 +1,17 @@ +# +# Copyright (C) 2018 Jianhui Zhao +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +SUBTARGET:=s5pv210 +BOARDNAME:=s5pv210 based boards +FEATURES+=fpu +CPU_TYPE:=cortex-a8 +CPU_SUBTYPE:=neon + +define Target/Description + Build firmware images for Samsung s5pv210 based boards. +endef +