Add basic support for Raspberry Pi 4
authorAndre Przywara <andre.przywara@arm.com>
Tue, 9 Jul 2019 10:25:57 +0000 (11:25 +0100)
committerAndre Przywara <andre.przywara@arm.com>
Wed, 25 Sep 2019 10:45:35 +0000 (11:45 +0100)
The Raspberry Pi 4 is a single board computer with four Cortex-A72
cores. From a TF-A perspective it is quite similar to the Raspberry Pi
3, although it comes with more memory (up to 4GB) and has a GIC.

This initial port though differs quite a lot from the existing rpi3
platform port, mainly due to taking a much simpler and more robust
approach to loading the non-secure payload:
The GPU firmware of the SoC, which is responsible for initial platform
setup (including DRAM initialisation), already loads the kernel, device
tree and the "armstub" into DRAM. We take advantage of this, by placing
just a BL31 component into the armstub8.bin component, which will be
executed first, in AArch64 EL3.
The non-secure payload can be a kernel or a boot loader (U-Boot or
EDK-2), disguised as the "kernel" image and loaded by the GPU firmware.

So this is just a BL31-only port, which directly drops into EL2
and executes whatever has been loaded as the "kernel" image, handing
over the DTB address in x0.

Change-Id: I636f4d1f661821566ad9e341d69ba36f6bbfb546
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
plat/rpi/rpi4/aarch64/plat_helpers.S [new file with mode: 0644]
plat/rpi/rpi4/include/plat_macros.S [new file with mode: 0644]
plat/rpi/rpi4/include/platform_def.h [new file with mode: 0644]
plat/rpi/rpi4/include/rpi_hw.h [new file with mode: 0644]
plat/rpi/rpi4/platform.mk [new file with mode: 0644]
plat/rpi/rpi4/rpi4_bl31_setup.c [new file with mode: 0644]

diff --git a/plat/rpi/rpi4/aarch64/plat_helpers.S b/plat/rpi/rpi4/aarch64/plat_helpers.S
new file mode 100644 (file)
index 0000000..46073b7
--- /dev/null
@@ -0,0 +1,187 @@
+/*
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <assert_macros.S>
+#include <platform_def.h>
+#include <cortex_a72.h>
+
+#include "../include/rpi_hw.h"
+
+       .globl  plat_crash_console_flush
+       .globl  plat_crash_console_init
+       .globl  plat_crash_console_putc
+       .globl  platform_mem_init
+       .globl  plat_get_my_entrypoint
+       .globl  plat_is_my_cpu_primary
+       .globl  plat_my_core_pos
+       .globl  plat_reset_handler
+       .globl  plat_rpi3_calc_core_pos
+       .globl  plat_secondary_cold_boot_setup
+
+       /* -----------------------------------------------------
+        *  unsigned int plat_my_core_pos(void)
+        *
+        *  This function uses the plat_rpi3_calc_core_pos()
+        *  definition to get the index of the calling CPU.
+        * -----------------------------------------------------
+        */
+func plat_my_core_pos
+       mrs     x0, mpidr_el1
+       b       plat_rpi3_calc_core_pos
+endfunc plat_my_core_pos
+
+       /* -----------------------------------------------------
+        *  unsigned int plat_rpi3_calc_core_pos(u_register_t mpidr);
+        *
+        *  CorePos = (ClusterId * 4) + CoreId
+        * -----------------------------------------------------
+        */
+func plat_rpi3_calc_core_pos
+       and     x1, x0, #MPIDR_CPU_MASK
+       and     x0, x0, #MPIDR_CLUSTER_MASK
+       add     x0, x1, x0, LSR #6
+       ret
+endfunc plat_rpi3_calc_core_pos
+
+       /* -----------------------------------------------------
+        * unsigned int plat_is_my_cpu_primary (void);
+        *
+        * Find out whether the current cpu is the primary
+        * cpu.
+        * -----------------------------------------------------
+        */
+func plat_is_my_cpu_primary
+       mrs     x0, mpidr_el1
+       and     x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
+       cmp     x0, #RPI4_PRIMARY_CPU
+       cset    w0, eq
+       ret
+endfunc plat_is_my_cpu_primary
+
+       /* -----------------------------------------------------
+        * void plat_secondary_cold_boot_setup (void);
+        *
+        * This function performs any platform specific actions
+        * needed for a secondary cpu after a cold reset e.g
+        * mark the cpu's presence, mechanism to place it in a
+        * holding pen etc.
+        * -----------------------------------------------------
+        */
+func plat_secondary_cold_boot_setup
+       /* Calculate address of our hold entry */
+       bl      plat_my_core_pos
+       lsl     x0, x0, #3
+       mov_imm x2, PLAT_RPI3_TM_HOLD_BASE
+       add     x0, x0, x2
+
+       /*
+        * This code runs way before requesting the warmboot of this core,
+        * so it is possible to clear the mailbox before getting a request
+        * to boot.
+        */
+       mov     x1, PLAT_RPI3_TM_HOLD_STATE_WAIT
+       str     x1,[x0]
+
+       /* Wait until we have a go */
+poll_mailbox:
+       wfe
+       ldr     x1, [x0]
+       cmp     x1, PLAT_RPI3_TM_HOLD_STATE_GO
+       bne     poll_mailbox
+
+       /* Jump to the provided entrypoint */
+       mov_imm x0, PLAT_RPI3_TM_ENTRYPOINT
+       ldr     x1, [x0]
+       br      x1
+endfunc plat_secondary_cold_boot_setup
+
+       /* ---------------------------------------------------------------------
+        * uintptr_t plat_get_my_entrypoint (void);
+        *
+        * Main job of this routine is to distinguish between a cold and a warm
+        * boot.
+        *
+        * This functions returns:
+        *  - 0 for a cold boot.
+        *  - Any other value for a warm boot.
+        * ---------------------------------------------------------------------
+        */
+func plat_get_my_entrypoint
+       /* TODO: support warm boot */
+       mov     x0, #0
+       ret
+endfunc plat_get_my_entrypoint
+
+       /* ---------------------------------------------
+        * void platform_mem_init (void);
+        *
+        * No need to carry out any memory initialization.
+        * ---------------------------------------------
+        */
+func platform_mem_init
+       ret
+endfunc platform_mem_init
+
+       /* ---------------------------------------------
+        * int plat_crash_console_init(void)
+        * Function to initialize the crash console
+        * without a C Runtime to print crash report.
+        * Clobber list : x0 - x3
+        * ---------------------------------------------
+        */
+func plat_crash_console_init
+       mov_imm x0, PLAT_RPI3_UART_BASE
+       mov_imm x1, PLAT_RPI4_VPU_CLK_RATE
+       mov_imm x2, PLAT_RPI3_UART_BAUDRATE
+       b       console_16550_core_init
+endfunc plat_crash_console_init
+
+       /* ---------------------------------------------
+        * int plat_crash_console_putc(int c)
+        * Function to print a character on the crash
+        * console without a C Runtime.
+        * Clobber list : x1, x2
+        * ---------------------------------------------
+        */
+func plat_crash_console_putc
+       mov_imm x1, PLAT_RPI3_UART_BASE
+       b       console_16550_core_putc
+endfunc plat_crash_console_putc
+
+       /* ---------------------------------------------
+        * int plat_crash_console_flush()
+        * Function to force a write of all buffered
+        * data that hasn't been output.
+        * Out : return -1 on error else return 0.
+        * Clobber list : x0, x1
+        * ---------------------------------------------
+        */
+func plat_crash_console_flush
+       mov_imm x0, PLAT_RPI3_UART_BASE
+       b       console_16550_core_flush
+endfunc plat_crash_console_flush
+
+       /* ---------------------------------------------
+        * void plat_reset_handler(void);
+        * ---------------------------------------------
+        */
+func plat_reset_handler
+       /* ------------------------------------------------
+        * Set L2 read/write cache latency:
+        * - L2 Data RAM latency: 3 cycles (0b010)
+        * - L2 Data RAM setup: 1 cycle (bit 5)
+        * ------------------------------------------------
+        */
+       mrs     x0, CORTEX_A72_L2CTLR_EL1
+       mov     x1, #0x22
+       orr     x0, x0, x1
+       msr     CORTEX_A72_L2CTLR_EL1, x0
+       isb
+
+       ret
+endfunc plat_reset_handler
diff --git a/plat/rpi/rpi4/include/plat_macros.S b/plat/rpi/rpi4/include/plat_macros.S
new file mode 100644 (file)
index 0000000..6007d03
--- /dev/null
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef PLAT_MACROS_S
+#define PLAT_MACROS_S
+
+       /* ---------------------------------------------
+        * The below required platform porting macro
+        * prints out relevant platform registers
+        * whenever an unhandled exception is taken in
+        * BL31.
+        * Clobbers: x0 - x10, x16, x17, sp
+        * ---------------------------------------------
+        */
+       .macro plat_crash_print_regs
+       .endm
+
+#endif /* PLAT_MACROS_S */
diff --git a/plat/rpi/rpi4/include/platform_def.h b/plat/rpi/rpi4/include/platform_def.h
new file mode 100644 (file)
index 0000000..831d1c3
--- /dev/null
@@ -0,0 +1,197 @@
+/*
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+#include <arch.h>
+#include <common/tbbr/tbbr_img_def.h>
+#include <lib/utils_def.h>
+#include <plat/common/common_def.h>
+
+#include "rpi_hw.h"
+
+/* Special value used to verify platform parameters from BL2 to BL31 */
+#define RPI3_BL31_PLAT_PARAM_VAL       ULL(0x0F1E2D3C4B5A6978)
+
+#define PLATFORM_STACK_SIZE            ULL(0x1000)
+
+#define PLATFORM_MAX_CPUS_PER_CLUSTER  U(4)
+#define PLATFORM_CLUSTER_COUNT         U(1)
+#define PLATFORM_CLUSTER0_CORE_COUNT   PLATFORM_MAX_CPUS_PER_CLUSTER
+#define PLATFORM_CORE_COUNT            PLATFORM_CLUSTER0_CORE_COUNT
+
+#define RPI4_PRIMARY_CPU               U(0)
+
+#define PLAT_MAX_PWR_LVL               MPIDR_AFFLVL1
+#define PLAT_NUM_PWR_DOMAINS           (PLATFORM_CLUSTER_COUNT + \
+                                        PLATFORM_CORE_COUNT)
+
+#define PLAT_MAX_RET_STATE             U(1)
+#define PLAT_MAX_OFF_STATE             U(2)
+
+/* Local power state for power domains in Run state. */
+#define PLAT_LOCAL_STATE_RUN           U(0)
+/* Local power state for retention. Valid only for CPU power domains */
+#define PLAT_LOCAL_STATE_RET           U(1)
+/*
+ * Local power state for OFF/power-down. Valid for CPU and cluster power
+ * domains.
+ */
+#define PLAT_LOCAL_STATE_OFF           U(2)
+
+/*
+ * Macros used to parse state information from State-ID if it is using the
+ * recommended encoding for State-ID.
+ */
+#define PLAT_LOCAL_PSTATE_WIDTH                U(4)
+#define PLAT_LOCAL_PSTATE_MASK         ((U(1) << PLAT_LOCAL_PSTATE_WIDTH) - 1)
+
+/*
+ * Some data must be aligned on the biggest cache line size in the platform.
+ * This is known only to the platform as it might have a combination of
+ * integrated and external caches.
+ */
+#define CACHE_WRITEBACK_SHIFT          U(6)
+#define CACHE_WRITEBACK_GRANULE                (U(1) << CACHE_WRITEBACK_SHIFT)
+
+/*
+ * Partition memory into secure ROM, non-secure DRAM, secure "SRAM", and
+ * secure DRAM. Note that this is all actually DRAM with different names,
+ * there is no Secure RAM in the Raspberry Pi 4.
+ */
+#if RPI3_USE_UEFI_MAP
+#define SEC_ROM_BASE                   ULL(0x00000000)
+#define SEC_ROM_SIZE                   ULL(0x00010000)
+
+/* FIP placed after ROM to append it to BL1 with very little padding. */
+#define PLAT_RPI3_FIP_BASE             ULL(0x00020000)
+#define PLAT_RPI3_FIP_MAX_SIZE         ULL(0x00010000)
+
+/* Reserve 2M of secure SRAM and DRAM, starting at 2M */
+#define SEC_SRAM_BASE                  ULL(0x00200000)
+#define SEC_SRAM_SIZE                  ULL(0x00100000)
+
+#define SEC_DRAM0_BASE                 ULL(0x00300000)
+#define SEC_DRAM0_SIZE                 ULL(0x00100000)
+
+/* Windows on ARM requires some RAM at 4M */
+#define NS_DRAM0_BASE                  ULL(0x00400000)
+#define NS_DRAM0_SIZE                  ULL(0x00C00000)
+#else
+#define SEC_ROM_BASE                   ULL(0x00000000)
+#define SEC_ROM_SIZE                   ULL(0x00020000)
+
+/* FIP placed after ROM to append it to BL1 with very little padding. */
+#define PLAT_RPI3_FIP_BASE             ULL(0x00020000)
+#define PLAT_RPI3_FIP_MAX_SIZE         ULL(0x001E0000)
+
+/* We have 16M of memory reserved starting at 256M */
+#define SEC_SRAM_BASE                  ULL(0x10000000)
+#define SEC_SRAM_SIZE                  ULL(0x00100000)
+
+#define SEC_DRAM0_BASE                 ULL(0x10100000)
+#define SEC_DRAM0_SIZE                 ULL(0x00F00000)
+/* End of reserved memory */
+
+#define NS_DRAM0_BASE                  ULL(0x11000000)
+#define NS_DRAM0_SIZE                  ULL(0x01000000)
+#endif /* RPI3_USE_UEFI_MAP */
+
+/*
+ * BL33 entrypoint.
+ */
+#define PLAT_RPI3_NS_IMAGE_OFFSET      NS_DRAM0_BASE
+#define PLAT_RPI3_NS_IMAGE_MAX_SIZE    NS_DRAM0_SIZE
+
+/*
+ * I/O registers.
+ */
+#define DEVICE0_BASE                   RPI_IO_BASE
+#define DEVICE0_SIZE                   RPI_IO_SIZE
+
+/*
+ * TF-A lives in SRAM, partition it here
+ */
+#define SHARED_RAM_BASE                        SEC_SRAM_BASE
+#define SHARED_RAM_SIZE                        ULL(0x00001000)
+
+#define BL_RAM_BASE                    (SHARED_RAM_BASE + SHARED_RAM_SIZE)
+#define BL_RAM_SIZE                    (SEC_SRAM_SIZE - SHARED_RAM_SIZE)
+
+/*
+ * Mailbox to control the secondary cores. All secondary cores are held in a
+ * wait loop in cold boot. To release them perform the following steps (plus
+ * any additional barriers that may be needed):
+ *
+ *     uint64_t *entrypoint = (uint64_t *)PLAT_RPI3_TM_ENTRYPOINT;
+ *     *entrypoint = ADDRESS_TO_JUMP_TO;
+ *
+ *     uint64_t *mbox_entry = (uint64_t *)PLAT_RPI3_TM_HOLD_BASE;
+ *     mbox_entry[cpu_id] = PLAT_RPI3_TM_HOLD_STATE_GO;
+ *
+ *     sev();
+ */
+#define PLAT_RPI3_TRUSTED_MAILBOX_BASE SHARED_RAM_BASE
+
+/* The secure entry point to be used on warm reset by all CPUs. */
+#define PLAT_RPI3_TM_ENTRYPOINT                PLAT_RPI3_TRUSTED_MAILBOX_BASE
+#define PLAT_RPI3_TM_ENTRYPOINT_SIZE   ULL(8)
+
+/* Hold entries for each CPU. */
+#define PLAT_RPI3_TM_HOLD_BASE         (PLAT_RPI3_TM_ENTRYPOINT + \
+                                        PLAT_RPI3_TM_ENTRYPOINT_SIZE)
+#define PLAT_RPI3_TM_HOLD_ENTRY_SIZE   ULL(8)
+#define PLAT_RPI3_TM_HOLD_SIZE         (PLAT_RPI3_TM_HOLD_ENTRY_SIZE * \
+                                        PLATFORM_CORE_COUNT)
+
+#define PLAT_RPI3_TRUSTED_MAILBOX_SIZE (PLAT_RPI3_TM_ENTRYPOINT_SIZE + \
+                                        PLAT_RPI3_TM_HOLD_SIZE)
+
+#define PLAT_RPI3_TM_HOLD_STATE_WAIT   ULL(0)
+#define PLAT_RPI3_TM_HOLD_STATE_GO     ULL(1)
+
+/*
+ * BL31 specific defines.
+ *
+ * Put BL31 at the top of the Trusted SRAM. BL31_BASE is calculated using the
+ * current BL31 debug size plus a little space for growth.
+ */
+#define PLAT_MAX_BL31_SIZE             ULL(0x20000)
+
+#define BL31_BASE                      ULL(0x1000)
+#define BL31_LIMIT                     ULL(0x100000)
+#define BL31_PROGBITS_LIMIT            ULL(0x100000)
+
+#define SEC_SRAM_ID                    0
+#define SEC_DRAM_ID                    1
+
+/*
+ * Other memory-related defines.
+ */
+#define PLAT_PHY_ADDR_SPACE_SIZE       (ULL(1) << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE      (ULL(1) << 32)
+
+#define MAX_MMAP_REGIONS               8
+#define MAX_XLAT_TABLES                        4
+
+#define MAX_IO_DEVICES                 U(3)
+#define MAX_IO_HANDLES                 U(4)
+
+#define MAX_IO_BLOCK_DEVICES           U(1)
+
+/*
+ * Serial-related constants.
+ */
+#define PLAT_RPI3_UART_BASE            RPI3_MINI_UART_BASE
+#define PLAT_RPI3_UART_BAUDRATE                ULL(115200)
+
+/*
+ * System counter
+ */
+#define SYS_COUNTER_FREQ_IN_TICKS      ULL(54000000)
+
+#endif /* PLATFORM_DEF_H */
diff --git a/plat/rpi/rpi4/include/rpi_hw.h b/plat/rpi/rpi4/include/rpi_hw.h
new file mode 100644 (file)
index 0000000..ed367ee
--- /dev/null
@@ -0,0 +1,115 @@
+/*
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef RPI_HW_H
+#define RPI_HW_H
+
+#include <lib/utils_def.h>
+
+/*
+ * Peripherals
+ */
+
+#define RPI_IO_BASE                    ULL(0xFE000000)
+#define RPI_IO_SIZE                    ULL(0x02000000)
+
+/*
+ * ARM <-> VideoCore mailboxes
+ */
+#define RPI3_MBOX_OFFSET               ULL(0x0000B880)
+#define RPI3_MBOX_BASE                 (RPI_IO_BASE + RPI3_MBOX_OFFSET)
+/* VideoCore -> ARM */
+#define RPI3_MBOX0_READ_OFFSET         ULL(0x00000000)
+#define RPI3_MBOX0_PEEK_OFFSET         ULL(0x00000010)
+#define RPI3_MBOX0_SENDER_OFFSET       ULL(0x00000014)
+#define RPI3_MBOX0_STATUS_OFFSET       ULL(0x00000018)
+#define RPI3_MBOX0_CONFIG_OFFSET       ULL(0x0000001C)
+/* ARM -> VideoCore */
+#define RPI3_MBOX1_WRITE_OFFSET                ULL(0x00000020)
+#define RPI3_MBOX1_PEEK_OFFSET         ULL(0x00000030)
+#define RPI3_MBOX1_SENDER_OFFSET       ULL(0x00000034)
+#define RPI3_MBOX1_STATUS_OFFSET       ULL(0x00000038)
+#define RPI3_MBOX1_CONFIG_OFFSET       ULL(0x0000003C)
+/* Mailbox status constants */
+#define RPI3_MBOX_STATUS_FULL_MASK     U(0x80000000) /* Set if full */
+#define RPI3_MBOX_STATUS_EMPTY_MASK    U(0x40000000) /* Set if empty */
+
+/*
+ * Power management, reset controller, watchdog.
+ */
+#define RPI3_IO_PM_OFFSET              ULL(0x00100000)
+#define RPI3_PM_BASE                   (RPI_IO_BASE + RPI3_IO_PM_OFFSET)
+/* Registers on top of RPI3_PM_BASE. */
+#define RPI3_PM_RSTC_OFFSET            ULL(0x0000001C)
+#define RPI3_PM_RSTS_OFFSET            ULL(0x00000020)
+#define RPI3_PM_WDOG_OFFSET            ULL(0x00000024)
+/* Watchdog constants */
+#define RPI3_PM_PASSWORD               U(0x5A000000)
+#define RPI3_PM_RSTC_WRCFG_MASK                U(0x00000030)
+#define RPI3_PM_RSTC_WRCFG_FULL_RESET  U(0x00000020)
+/*
+ * The RSTS register is used by the VideoCore firmware when booting the
+ * Raspberry Pi to know which partition to boot from. The partition value is
+ * formed by bits 0, 2, 4, 6, 8 and 10. Partition 63 is used by said firmware
+ * to indicate halt.
+ */
+#define RPI3_PM_RSTS_WRCFG_HALT                U(0x00000555)
+
+/*
+ * Clock controller
+ */
+#define RPI4_IO_CLOCK_OFFSET           ULL(0x00101000)
+#define RPI4_CLOCK_BASE                        (RPI_IO_BASE + RPI4_IO_CLOCK_OFFSET)
+#define RPI4_VPU_CLOCK_DIVIDER         ULL(0x0000000c)
+
+/*
+ * Hardware random number generator.
+ */
+#define RPI3_IO_RNG_OFFSET             ULL(0x00104000)
+#define RPI3_RNG_BASE                  (RPI_IO_BASE + RPI3_IO_RNG_OFFSET)
+#define RPI3_RNG_CTRL_OFFSET           ULL(0x00000000)
+#define RPI3_RNG_STATUS_OFFSET         ULL(0x00000004)
+#define RPI3_RNG_DATA_OFFSET           ULL(0x00000008)
+#define RPI3_RNG_INT_MASK_OFFSET       ULL(0x00000010)
+/* Enable/disable RNG */
+#define RPI3_RNG_CTRL_ENABLE           U(0x1)
+#define RPI3_RNG_CTRL_DISABLE          U(0x0)
+/* Number of currently available words */
+#define RPI3_RNG_STATUS_NUM_WORDS_SHIFT        U(24)
+#define RPI3_RNG_STATUS_NUM_WORDS_MASK U(0xFF)
+/* Value to mask interrupts caused by the RNG */
+#define RPI3_RNG_INT_MASK_DISABLE      U(0x1)
+
+/*
+ * Serial port (called 'Mini UART' in the Broadcom documentation).
+ */
+#define RPI3_IO_MINI_UART_OFFSET       ULL(0x00215040)
+#define RPI3_MINI_UART_BASE            (RPI_IO_BASE + RPI3_IO_MINI_UART_OFFSET)
+#define PLAT_RPI4_VPU_CLK_RATE         ULL(1000000000)
+
+/*
+ * GPIO controller
+ */
+#define RPI3_IO_GPIO_OFFSET            ULL(0x00200000)
+#define RPI3_GPIO_BASE                 (RPI_IO_BASE + RPI3_IO_GPIO_OFFSET)
+
+/*
+ * SDHost controller
+ */
+#define RPI3_IO_SDHOST_OFFSET           ULL(0x00202000)
+#define RPI3_SDHOST_BASE                (RPI_IO_BASE + RPI3_IO_SDHOST_OFFSET)
+
+/*
+ * GIC interrupt controller
+ */
+#define RPI_HAVE_GIC
+#define RPI4_GIC_GICD_BASE             ULL(0xff841000)
+#define RPI4_GIC_GICC_BASE             ULL(0xff842000)
+
+#define        RPI4_LOCAL_CONTROL_BASE_ADDRESS         ULL(0xff800000)
+#define        RPI4_LOCAL_CONTROL_PRESCALER            ULL(0xff800008)
+
+#endif /* RPI_HW_H */
diff --git a/plat/rpi/rpi4/platform.mk b/plat/rpi/rpi4/platform.mk
new file mode 100644 (file)
index 0000000..3ff180e
--- /dev/null
@@ -0,0 +1,108 @@
+#
+# Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+include lib/libfdt/libfdt.mk
+include lib/xlat_tables_v2/xlat_tables.mk
+
+PLAT_INCLUDES          :=      -Iplat/rpi/common/include               \
+                               -Iplat/rpi/rpi4/include
+
+PLAT_BL_COMMON_SOURCES :=      drivers/ti/uart/aarch64/16550_console.S \
+                               plat/rpi/common/rpi3_common.c           \
+                               ${XLAT_TABLES_LIB_SRCS}
+
+BL31_SOURCES           +=      lib/cpus/aarch64/cortex_a72.S           \
+                               plat/rpi/rpi4/aarch64/plat_helpers.S    \
+                               drivers/arm/gic/common/gic_common.c     \
+                               drivers/arm/gic/v2/gicv2_helpers.c      \
+                               drivers/arm/gic/v2/gicv2_main.c         \
+                               plat/common/plat_gicv2.c                \
+                               plat/rpi/rpi4/rpi4_bl31_setup.c         \
+                               plat/rpi/common/rpi3_pm.c               \
+                               plat/common/plat_psci_common.c          \
+                               plat/rpi/common/rpi3_topology.c         \
+                               ${LIBFDT_SRCS}
+
+# For now we only support BL31, using the kernel loaded by the GPU firmware.
+RESET_TO_BL31          :=      1
+
+# All CPUs enter armstub8.bin.
+COLD_BOOT_SINGLE_CPU   :=      0
+
+# Tune compiler for Cortex-A72
+ifeq ($(notdir $(CC)),armclang)
+    TF_CFLAGS_aarch64  +=      -mcpu=cortex-a72
+else ifneq ($(findstring clang,$(notdir $(CC))),)
+    TF_CFLAGS_aarch64  +=      -mcpu=cortex-a72
+else
+    TF_CFLAGS_aarch64  +=      -mtune=cortex-a72
+endif
+
+
+# Enable all errata workarounds for Cortex-A72
+ERRATA_A72_859971              := 1
+
+WORKAROUND_CVE_2017_5715       := 1
+
+# Add new default target when compiling this platform
+all: bl31
+
+# Build config flags
+# ------------------
+
+# Disable stack protector by default
+ENABLE_STACK_PROTECTOR         := 0
+
+# Have different sections for code and rodata
+SEPARATE_CODE_AND_RODATA       := 1
+
+# Use Coherent memory
+USE_COHERENT_MEM               := 1
+
+# Platform build flags
+# --------------------
+
+# Assume that BL33 isn't the Linux kernel by default
+RPI3_DIRECT_LINUX_BOOT         := 0
+
+# BL33 images are in AArch64 by default
+RPI3_BL33_IN_AARCH32           := 0
+
+# UART to use at runtime. -1 means the runtime UART is disabled.
+# Any other value means the default UART will be used.
+RPI3_RUNTIME_UART              := 0
+
+# Use normal memory mapping for ROM, FIP, SRAM and DRAM
+RPI3_USE_UEFI_MAP              := 0
+
+# Process platform flags
+# ----------------------
+
+$(eval $(call add_define,RPI3_BL33_IN_AARCH32))
+$(eval $(call add_define,RPI3_DIRECT_LINUX_BOOT))
+ifdef RPI3_PRELOADED_DTB_BASE
+$(eval $(call add_define,RPI3_PRELOADED_DTB_BASE))
+endif
+$(eval $(call add_define,RPI3_RUNTIME_UART))
+$(eval $(call add_define,RPI3_USE_UEFI_MAP))
+
+# Verify build config
+# -------------------
+#
+ifneq (${RPI3_DIRECT_LINUX_BOOT}, 0)
+  ifndef RPI3_PRELOADED_DTB_BASE
+      $(error Error: RPI3_PRELOADED_DTB_BASE needed if RPI3_DIRECT_LINUX_BOOT=1)
+  endif
+endif
+
+ifeq (${ARCH},aarch32)
+  $(error Error: AArch32 not supported on rpi4)
+endif
+
+ifneq ($(ENABLE_STACK_PROTECTOR), 0)
+PLAT_BL_COMMON_SOURCES +=      drivers/rpi3/rng/rpi3_rng.c             \
+                               plat/rpi/common/rpi3_stack_protector.c
+endif
diff --git a/plat/rpi/rpi4/rpi4_bl31_setup.c b/plat/rpi/rpi4/rpi4_bl31_setup.c
new file mode 100644 (file)
index 0000000..de582b3
--- /dev/null
@@ -0,0 +1,162 @@
+/*
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+
+#include <libfdt.h>
+
+#include <platform_def.h>
+#include <common/bl_common.h>
+#include <lib/mmio.h>
+#include <lib/xlat_tables/xlat_mmu_helpers.h>
+#include <lib/xlat_tables/xlat_tables_defs.h>
+#include <plat/common/platform.h>
+
+#include <drivers/arm/gicv2.h>
+
+#include <rpi_shared.h>
+
+static const gicv2_driver_data_t rpi4_gic_data = {
+       .gicd_base = RPI4_GIC_GICD_BASE,
+       .gicc_base = RPI4_GIC_GICC_BASE,
+};
+
+/*
+ * To be filled by the code below. At the moment BL32 is not supported.
+ * In the future these might be passed down from BL2.
+ */
+static entry_point_info_t bl32_image_ep_info;
+static entry_point_info_t bl33_image_ep_info;
+
+/*******************************************************************************
+ * Return a pointer to the 'entry_point_info' structure of the next image for
+ * the security state specified. BL33 corresponds to the non-secure image type
+ * while BL32 corresponds to the secure image type. A NULL pointer is returned
+ * if the image does not exist.
+ ******************************************************************************/
+entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
+{
+       entry_point_info_t *next_image_info;
+
+       assert(sec_state_is_valid(type) != 0);
+
+       next_image_info = (type == NON_SECURE)
+                       ? &bl33_image_ep_info : &bl32_image_ep_info;
+
+       /* None of the images can have 0x0 as the entrypoint. */
+       if (next_image_info->pc) {
+               return next_image_info;
+       } else {
+               return NULL;
+       }
+}
+
+static void ldelay(register_t delay)
+{
+       __asm__ volatile (
+               "1:\tcbz %0, 2f\n\t"
+               "sub %0, %0, #1\n\t"
+               "b 1b\n"
+               "2:"
+               : "=&r" (delay) : "0" (delay)
+       );
+}
+
+/*******************************************************************************
+ * Perform any BL31 early platform setup. Here is an opportunity to copy
+ * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before
+ * they are lost (potentially). This needs to be done before the MMU is
+ * initialized so that the memory layout can be used while creating page
+ * tables. BL2 has flushed this information to memory, so we are guaranteed
+ * to pick up good data.
+ ******************************************************************************/
+void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
+                               u_register_t arg2, u_register_t arg3)
+
+{
+       uint32_t div_reg;
+
+       /*
+        * LOCAL_CONTROL:
+        * Bit 9 clear: Increment by 1 (vs. 2).
+        * Bit 8 clear: Timer source is 19.2MHz crystal (vs. APB).
+        */
+       mmio_write_32(RPI4_LOCAL_CONTROL_BASE_ADDRESS, 0);
+
+       /* LOCAL_PRESCALER; divide-by (0x80000000 / register_val) == 1 */
+       mmio_write_32(RPI4_LOCAL_CONTROL_PRESCALER, 0x80000000);
+
+       /* Early GPU firmware revisions need a little break here. */
+       ldelay(100000);
+
+       /*
+        * Initialize the console to provide early debug support.
+        * Different GPU firmware revisions set up the VPU divider differently,
+        * so read the actual divider register to learn the UART base clock
+        * rate. The divider is encoded as a 12.12 fixed point number, but we
+        * just care about the integer part of it.
+        */
+       div_reg = mmio_read_32(RPI4_CLOCK_BASE + RPI4_VPU_CLOCK_DIVIDER);
+       div_reg = (div_reg >> 12) & 0xfff;
+       if (div_reg == 0)
+               div_reg = 1;
+       rpi3_console_init(PLAT_RPI4_VPU_CLK_RATE / div_reg);
+
+#if RPI3_DIRECT_LINUX_BOOT
+       bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
+       bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
+                                         DISABLE_ALL_EXCEPTIONS);
+       SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
+
+# if RPI3_BL33_IN_AARCH32
+       /*
+        * According to the file ``Documentation/arm/Booting`` of the Linux
+        * kernel tree, Linux expects:
+        * r0 = 0
+        * r1 = machine type number, optional in DT-only platforms (~0 if so)
+        * r2 = Physical address of the device tree blob
+        */
+       VERBOSE("rpi4: Preparing to boot 32-bit Linux kernel\n");
+       bl33_image_ep_info.args.arg0 = 0U;
+       bl33_image_ep_info.args.arg1 = ~0U;
+       bl33_image_ep_info.args.arg2 = (u_register_t) RPI3_PRELOADED_DTB_BASE;
+# else
+       /*
+        * According to the file ``Documentation/arm64/booting.txt`` of the
+        * Linux kernel tree, Linux expects the physical address of the device
+        * tree blob (DTB) in x0, while x1-x3 are reserved for future use and
+        * must be 0.
+        */
+       VERBOSE("rpi4: Preparing to boot 64-bit Linux kernel\n");
+       bl33_image_ep_info.args.arg0 = (u_register_t) RPI3_PRELOADED_DTB_BASE;
+       bl33_image_ep_info.args.arg1 = 0ULL;
+       bl33_image_ep_info.args.arg2 = 0ULL;
+       bl33_image_ep_info.args.arg3 = 0ULL;
+# endif /* RPI3_BL33_IN_AARCH32 */
+#endif /* RPI3_DIRECT_LINUX_BOOT */
+}
+
+void bl31_plat_arch_setup(void)
+{
+       rpi3_setup_page_tables(BL31_BASE, BL31_END - BL31_BASE,
+                              BL_CODE_BASE, BL_CODE_END,
+                              BL_RO_DATA_BASE, BL_RO_DATA_END
+#if USE_COHERENT_MEM
+                              , BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END
+#endif
+                             );
+
+       enable_mmu_el3(0);
+}
+
+void bl31_platform_setup(void)
+{
+       /* Configure the interrupt controller */
+       gicv2_driver_init(&rpi4_gic_data);
+       gicv2_distif_init();
+       gicv2_pcpu_distif_init();
+       gicv2_cpuif_enable();
+}