ramips: kernel: fix awake-rt305x-dwc2 patch
authorAlexey Dobrovolsky <dobrovolskiy.alexey@gmail.com>
Wed, 6 May 2020 20:48:15 +0000 (23:48 +0300)
committerPetr Štetiar <ynezz@true.cz>
Sat, 11 Jul 2020 11:33:28 +0000 (13:33 +0200)
At this point in v5.4 kernel we cannot use dwc2_readl() and
dwc2_writel() since they rely on the value hsotg->needs_byte_swap
which cannot be obtained before the controller wakes up.
We should use readl() and writel() to wake up the controller before
calling dwc2_check_core_endianness().

Fixes: 6be0da90a165 ("ramips: refresh patches")
Signed-off-by: Alexey Dobrovolsky <dobrovolskiy.alexey@gmail.com>
[fixed Fixes: tag]
Signed-off-by: Petr Štetiar <ynezz@true.cz>
target/linux/ramips/patches-5.4/0069-awake-rt305x-dwc2-controller.patch

index 1ce8fac6821625a7c06ddff92a79fb54778e5813..1ce7102a4e685f3401aa9aac9c2db3adbc1b1689 100644 (file)
@@ -1,15 +1,15 @@
 --- a/drivers/usb/dwc2/platform.c
 +++ b/drivers/usb/dwc2/platform.c
-@@ -432,6 +432,12 @@ static int dwc2_driver_probe(struct plat
-       hsotg->needs_byte_swap = dwc2_check_core_endianness(hsotg);
+@@ -430,6 +430,12 @@ static int dwc2_driver_probe(struct plat
+       if (retval)
+               return retval;
  
 +      /* Enable USB port before any regs access */
-+      if (dwc2_readl(hsotg, PCGCTL) & 0x0f) {
-+              dwc2_writel(0x00, hsotg, PCGCTL);
++      if (readl(hsotg->regs + PCGCTL) & 0x0f) {
++              writel(0x00, hsotg->regs + PCGCTL);
 +              /* TODO: mdelay(25) here? vendor driver don't use it */
 +      }
 +
+       hsotg->needs_byte_swap = dwc2_check_core_endianness(hsotg);
+
        retval = dwc2_get_dr_mode(hsotg);
-       if (retval)
-               goto error;