+++ /dev/null
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_IXP4XX=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_NO_SG_CHAIN=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-# CONFIG_ARCH_PRPMC1100 is not set
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARM=y
-CONFIG_ARM_APPENDED_DTB=y
-CONFIG_ARM_ATAG_DTB_COMPAT=y
-CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
-CONFIG_ARM_L1_CACHE_SHIFT=5
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-CONFIG_ARM_PTDUMP_CORE=y
-CONFIG_ARM_PTDUMP_DEBUGFS=y
-# CONFIG_ARM_THUMB is not set
-CONFIG_ARM_UNWIND=y
-CONFIG_ASN1=y
-CONFIG_ASSOCIATIVE_ARRAY=y
-CONFIG_ASYMMETRIC_KEY_TYPE=y
-CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
-CONFIG_ATAGS=y
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BOUNCE=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CLZ_TAB=y
-CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200"
-CONFIG_CMDLINE_FROM_BOOTLOADER=y
-# CONFIG_COMMON_CLK is not set
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CPU_32v5=y
-CONFIG_CPU_ABRT_EV5T=y
-CONFIG_CPU_BIG_ENDIAN=y
-CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_ENDIAN_BE32=y
-CONFIG_CPU_PABRT_LEGACY=y
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V4WBI=y
-CONFIG_CPU_USE_DOMAINS=y
-CONFIG_CPU_XSCALE=y
-CONFIG_CRYPTO_AEAD=y
-CONFIG_CRYPTO_AEAD2=y
-CONFIG_CRYPTO_AKCIPHER=y
-CONFIG_CRYPTO_AKCIPHER2=y
-CONFIG_CRYPTO_CCM=y
-CONFIG_CRYPTO_CMAC=y
-CONFIG_CRYPTO_CTR=y
-# CONFIG_CRYPTO_DEV_IXP4XX is not set
-CONFIG_CRYPTO_DRBG=y
-CONFIG_CRYPTO_DRBG_HMAC=y
-CONFIG_CRYPTO_DRBG_MENU=y
-CONFIG_CRYPTO_GCM=y
-CONFIG_CRYPTO_GF128MUL=y
-CONFIG_CRYPTO_GHASH=y
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_HASH2=y
-CONFIG_CRYPTO_HASH_INFO=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_JITTERENTROPY=y
-CONFIG_CRYPTO_LIB_SHA256=y
-CONFIG_CRYPTO_MANAGER=y
-CONFIG_CRYPTO_MANAGER2=y
-CONFIG_CRYPTO_NULL=y
-CONFIG_CRYPTO_NULL2=y
-CONFIG_CRYPTO_RNG=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_RNG_DEFAULT=y
-CONFIG_CRYPTO_RSA=y
-CONFIG_CRYPTO_SEQIV=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DEBUG_LL=y
-CONFIG_DEBUG_LL_INCLUDE="debug/8250.S"
-CONFIG_DEBUG_LL_UART_8250=y
-CONFIG_DEBUG_UART_8250=y
-CONFIG_DEBUG_UART_8250_SHIFT=2
-CONFIG_DEBUG_UART_PHYS=0xc8001003
-CONFIG_DEBUG_UART_VIRT=0xfec01003
-CONFIG_DMABOUNCE=y
-CONFIG_DMA_OPS=y
-CONFIG_DMA_REMAP=y
-CONFIG_DNOTIFY=y
-CONFIG_DTC=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EEPROM_AT24=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_GENERIC=y
-CONFIG_GPIO_IXP4XX=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDENED_USERCOPY_FALLBACK=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HWMON=y
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_IXP4XX=y
-CONFIG_HZ_FIXED=0
-CONFIG_HZ_PERIODIC=y
-CONFIG_I2C=y
-CONFIG_I2C_ALGOBIT=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_GPIO=y
-CONFIG_I2C_IOP3XX=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-# CONFIG_IWMMXT is not set
-CONFIG_IXP4XX_ETH=y
-CONFIG_IXP4XX_IRQ=y
-CONFIG_IXP4XX_NPE=y
-# CONFIG_IXP4XX_PCI_LEGACY is not set
-CONFIG_IXP4XX_QMGR=y
-CONFIG_IXP4XX_TIMER=y
-CONFIG_IXP4XX_WATCHDOG=y
-CONFIG_KEYS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-CONFIG_LIBFDT=y
-CONFIG_LLD_VERSION=0
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-# CONFIG_MACH_DEVIXP is not set
-# CONFIG_MACH_GORAMO_MLR is not set
-# CONFIG_MACH_IXDP465 is not set
-CONFIG_MACH_IXP4XX_OF=y
-# CONFIG_MACH_KIXRP435 is not set
-# CONFIG_MACH_MIC256 is not set
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MIGRATION=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MPILIB=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-# CONFIG_MTD_CFI_GEOMETRY is not set
-CONFIG_MTD_IXP4XX=y
-CONFIG_MTD_OTP=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PHYSMAP_IXP4XX=y
-CONFIG_MTD_REDBOOT_PARTS=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_KUSER_HELPERS=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NET_PTP_CLASSIFY=y
-CONFIG_NET_VENDOR_XSCALE=y
-CONFIG_NVMEM=y
-CONFIG_NVMEM_SYSFS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_NET=y
-CONFIG_OID_REGISTRY=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PCI=y
-CONFIG_PCI_DEBUG=y
-CONFIG_PCI_IXP4XX=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PKCS7_MESSAGE_PARSER=y
-# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_DS1672=y
-CONFIG_RTC_DRV_ISL1208=y
-CONFIG_RTC_DRV_PCF8563=y
-CONFIG_RTC_DRV_X1205=y
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RTC_MC146818_LIB=y
-# CONFIG_SECONDARY_TRUSTED_KEYRING is not set
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPLIT_PTLOCK_CPUS=999999
-CONFIG_SRCU=y
-CONFIG_SWPHY=y
-# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set
-CONFIG_SYSTEM_TRUSTED_KEYRING=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TINY_SRCU=y
-CONFIG_UNCOMPRESS_INCLUDE="mach/uncompress.h"
-CONFIG_UNWINDER_ARM=y
-CONFIG_USB_EHCI_BIG_ENDIAN_DESC=y
-CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_OF=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-CONFIG_X509_CERTIFICATE_PARSER=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_ZBOOT_ROM_TEXT=0x0
--- /dev/null
+CONFIG_ALIGNMENT_TRAP=y
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_IXP4XX=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_NO_SG_CHAIN=y
+CONFIG_ARCH_NR_GPIO=0
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARM=y
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ATAG_DTB_COMPAT=y
+CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
+CONFIG_ARM_L1_CACHE_SHIFT=5
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+CONFIG_ARM_PTDUMP_CORE=y
+CONFIG_ARM_PTDUMP_DEBUGFS=y
+# CONFIG_ARM_THUMB is not set
+CONFIG_ARM_UNWIND=y
+CONFIG_ASN1=y
+CONFIG_ASSOCIATIVE_ARRAY=y
+CONFIG_ASYMMETRIC_KEY_TYPE=y
+CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
+CONFIG_ATA=y
+CONFIG_ATAGS=y
+CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CLZ_TAB=y
+CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200"
+CONFIG_CMDLINE_FROM_BOOTLOADER=y
+# CONFIG_COMMON_CLK is not set
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5T=y
+CONFIG_CPU_BIG_ENDIAN=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_CPU_ENDIAN_BE32=y
+CONFIG_CPU_PABRT_LEGACY=y
+CONFIG_CPU_THUMB_CAPABLE=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_USE_DOMAINS=y
+CONFIG_CPU_XSCALE=y
+CONFIG_CRYPTO_CMAC=y
+# CONFIG_CRYPTO_DEV_IXP4XX is not set
+CONFIG_CRYPTO_DRBG=y
+CONFIG_CRYPTO_DRBG_HMAC=y
+CONFIG_CRYPTO_DRBG_MENU=y
+CONFIG_CRYPTO_HASH_INFO=y
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_JITTERENTROPY=y
+CONFIG_CRYPTO_LIB_SHA256=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_RNG_DEFAULT=y
+CONFIG_CRYPTO_RSA=y
+CONFIG_CRYPTO_SEQIV=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_LL=y
+CONFIG_DEBUG_LL_INCLUDE="debug/8250.S"
+CONFIG_DEBUG_LL_UART_8250=y
+CONFIG_DEBUG_UART_8250=y
+CONFIG_DEBUG_UART_8250_SHIFT=2
+CONFIG_DEBUG_UART_PHYS=0xc8001003
+CONFIG_DEBUG_UART_VIRT=0xfec01003
+CONFIG_DMA_OPS=y
+CONFIG_DMA_REMAP=y
+CONFIG_DNOTIFY=y
+CONFIG_DTC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EEPROM_AT24=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GLOB=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_IXP4XX=y
+CONFIG_HANDLE_DOMAIN_IRQ=y
+CONFIG_HARDENED_USERCOPY_FALLBACK=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HWMON=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_IXP4XX=y
+CONFIG_HZ_FIXED=0
+CONFIG_HZ_PERIODIC=y
+CONFIG_I2C=y
+CONFIG_I2C_ALGOBIT=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_GPIO=y
+CONFIG_I2C_IOP3XX=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INTEL_IXP4XX_EB=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+# CONFIG_IWMMXT is not set
+CONFIG_IXP4XX_ETH=y
+CONFIG_IXP4XX_IRQ=y
+CONFIG_IXP4XX_NPE=y
+CONFIG_IXP4XX_QMGR=y
+CONFIG_IXP4XX_TIMER=y
+CONFIG_IXP4XX_WATCHDOG=y
+CONFIG_KEYS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_MACH_IXP4XX_OF=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MEMFD_CREATE=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGRATION=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MPILIB=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+# CONFIG_MTD_CFI_GEOMETRY is not set
+CONFIG_MTD_IXP4XX=y
+CONFIG_MTD_OTP=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_IXP4XX=y
+CONFIG_MTD_REDBOOT_PARTS=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_KUSER_HELPERS=y
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_VENDOR_XSCALE=y
+CONFIG_NLS=y
+CONFIG_NVMEM=y
+CONFIG_NVMEM_SYSFS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OID_REGISTRY=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_PATA_IXP4XX_CF is not set
+CONFIG_PCI=y
+CONFIG_PCI_DEBUG=y
+CONFIG_PCI_IXP4XX=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PKCS7_MESSAGE_PARSER=y
+# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_DS1672=y
+CONFIG_RTC_DRV_ISL1208=y
+CONFIG_RTC_DRV_PCF8563=y
+CONFIG_RTC_DRV_X1205=y
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RTC_MC146818_LIB=y
+CONFIG_SATA_HOST=y
+CONFIG_SATA_VIA=y
+CONFIG_SCSI=y
+CONFIG_SCSI_COMMON=y
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SECONDARY_TRUSTED_KEYRING is not set
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SG_POOL=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPLIT_PTLOCK_CPUS=999999
+CONFIG_SRCU=y
+CONFIG_SWPHY=y
+# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set
+CONFIG_SYSTEM_TRUSTED_KEYRING=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TINY_SRCU=y
+CONFIG_UNCOMPRESS_INCLUDE="mach/uncompress.h"
+CONFIG_UNWINDER_ARM=y
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_EHCI_BIG_ENDIAN_DESC=y
+CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USE_OF=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+CONFIG_X509_CERTIFICATE_PARSER=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ZBOOT_ROM_TEXT=0x0
+++ /dev/null
-From 1454c51d1ec1277a54505159c5de62be0c2a2597 Mon Sep 17 00:00:00 2001
-From: Zheng Yongjun <zhengyongjun3@huawei.com>
-Date: Tue, 29 Dec 2020 21:49:47 +0800
-Subject: net: ixp4xx_eth: Use DEFINE_SPINLOCK() for spinlock
-
-spinlock can be initialized automatically with DEFINE_SPINLOCK()
-rather than explicitly calling spin_lock_init().
-
-Signed-off-by: Zheng Yongjun <zhengyongjun3@huawei.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/ethernet/xscale/ixp4xx_eth.c | 3 +--
- 1 file changed, 1 insertion(+), 2 deletions(-)
-
-(limited to 'drivers/net/ethernet/xscale/ixp4xx_eth.c')
-
-diff --git a/drivers/net/ethernet/xscale/ixp4xx_eth.c b/drivers/net/ethernet/xscale/ixp4xx_eth.c
-index 2e52029235104..0152f1e707834 100644
---- a/drivers/net/ethernet/xscale/ixp4xx_eth.c
-+++ b/drivers/net/ethernet/xscale/ixp4xx_eth.c
-@@ -247,7 +247,7 @@ static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
- }
- #endif
-
--static spinlock_t mdio_lock;
-+static DEFINE_SPINLOCK(mdio_lock);
- static struct eth_regs __iomem *mdio_regs; /* mdio command and status only */
- static struct mii_bus *mdio_bus;
- static int ports_open;
-@@ -528,7 +528,6 @@ static int ixp4xx_mdio_register(struct eth_regs __iomem *regs)
-
- mdio_regs = regs;
- __raw_writel(DEFAULT_CORE_CNTRL, &mdio_regs->core_control);
-- spin_lock_init(&mdio_lock);
- mdio_bus->name = "IXP4xx MII Bus";
- mdio_bus->read = &ixp4xx_mdio_read;
- mdio_bus->write = &ixp4xx_mdio_write;
---
-cgit 1.2.3-1.el7
-
+++ /dev/null
-From 3e8047a98553e234a751f4f7f42d687ba98c0822 Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Sun, 25 Apr 2021 02:30:37 +0200
-Subject: net: ethernet: ixp4xx: Retire ancient phy retrieveal
-
-This driver was using a really dated way of obtaining the
-phy by printing a string and using it with phy_connect().
-Switch to using more reasonable modern interfaces.
-
-Suggested-by: Andrew Lunn <andrew@lunn.ch>
-Reviewed-by: Andrew Lunn <andrew@lunn.ch>
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/ethernet/xscale/ixp4xx_eth.c | 10 +++++-----
- 1 file changed, 5 insertions(+), 5 deletions(-)
-
-diff --git a/drivers/net/ethernet/xscale/ixp4xx_eth.c b/drivers/net/ethernet/xscale/ixp4xx_eth.c
-index 0152f1e707834..9d323e8595e2b 100644
---- a/drivers/net/ethernet/xscale/ixp4xx_eth.c
-+++ b/drivers/net/ethernet/xscale/ixp4xx_eth.c
-@@ -1360,7 +1360,6 @@ static const struct net_device_ops ixp4xx_netdev_ops = {
-
- static int ixp4xx_eth_probe(struct platform_device *pdev)
- {
-- char phy_id[MII_BUS_ID_SIZE + 3];
- struct phy_device *phydev = NULL;
- struct device *dev = &pdev->dev;
- struct eth_plat_info *plat;
-@@ -1459,14 +1458,15 @@ static int ixp4xx_eth_probe(struct platform_device *pdev)
- __raw_writel(DEFAULT_CORE_CNTRL, &port->regs->core_control);
- udelay(50);
-
-- snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT,
-- mdio_bus->id, plat->phy);
-- phydev = phy_connect(ndev, phy_id, &ixp4xx_adjust_link,
-- PHY_INTERFACE_MODE_MII);
-+ phydev = mdiobus_get_phy(mdio_bus, plat->phy);
- if (IS_ERR(phydev)) {
- err = PTR_ERR(phydev);
- goto err_free_mem;
- }
-+ err = phy_connect_direct(ndev, phydev, ixp4xx_adjust_link,
-+ PHY_INTERFACE_MODE_MII);
-+ if (err)
-+ goto err_free_mem;
-
- phydev->irq = PHY_POLL;
-
---
-cgit 1.2.3-1.el7
-
+++ /dev/null
-From 95aafe911db602d19b00d2a88c3d54a84119f5dc Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Sun, 25 Apr 2021 02:30:38 +0200
-Subject: net: ethernet: ixp4xx: Support device tree probing
-
-This adds device tree probing to the IXP4xx ethernet
-driver.
-
-Add a platform data bool to tell us whether to
-register an MDIO bus for the device or not, as well
-as the corresponding NPE.
-
-We need to drop the memory region request as part of
-this since the OF core will request the memory for the
-device.
-
-Cc: Zoltan HERPAI <wigyori@uid0.hu>
-Cc: Raylynn Knight <rayknight@me.com>
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/ethernet/xscale/Kconfig | 1 +
- drivers/net/ethernet/xscale/ixp4xx_eth.c | 210 +++++++++++++++++++++----------
- include/linux/platform_data/eth_ixp4xx.h | 2 +
- 3 files changed, 150 insertions(+), 63 deletions(-)
-
-diff --git a/drivers/net/ethernet/xscale/Kconfig b/drivers/net/ethernet/xscale/Kconfig
-index 7b83a6e5d894d..468ffe3d17075 100644
---- a/drivers/net/ethernet/xscale/Kconfig
-+++ b/drivers/net/ethernet/xscale/Kconfig
-@@ -22,6 +22,7 @@ config IXP4XX_ETH
- tristate "Intel IXP4xx Ethernet support"
- depends on ARM && ARCH_IXP4XX && IXP4XX_NPE && IXP4XX_QMGR
- select PHYLIB
-+ select OF_MDIO if OF
- select NET_PTP_CLASSIFY
- help
- Say Y here if you want to use built-in Ethernet ports
-diff --git a/drivers/net/ethernet/xscale/ixp4xx_eth.c b/drivers/net/ethernet/xscale/ixp4xx_eth.c
-index 9d323e8595e2b..1149e88e64546 100644
---- a/drivers/net/ethernet/xscale/ixp4xx_eth.c
-+++ b/drivers/net/ethernet/xscale/ixp4xx_eth.c
-@@ -28,6 +28,7 @@
- #include <linux/kernel.h>
- #include <linux/net_tstamp.h>
- #include <linux/of.h>
-+#include <linux/of_mdio.h>
- #include <linux/phy.h>
- #include <linux/platform_data/eth_ixp4xx.h>
- #include <linux/platform_device.h>
-@@ -165,7 +166,6 @@ struct eth_regs {
- };
-
- struct port {
-- struct resource *mem_res;
- struct eth_regs __iomem *regs;
- struct npe *npe;
- struct net_device *netdev;
-@@ -250,6 +250,7 @@ static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
- static DEFINE_SPINLOCK(mdio_lock);
- static struct eth_regs __iomem *mdio_regs; /* mdio command and status only */
- static struct mii_bus *mdio_bus;
-+static struct device_node *mdio_bus_np;
- static int ports_open;
- static struct port *npe_port_tab[MAX_NPES];
- static struct dma_pool *dma_pool;
-@@ -533,7 +534,8 @@ static int ixp4xx_mdio_register(struct eth_regs __iomem *regs)
- mdio_bus->write = &ixp4xx_mdio_write;
- snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "ixp4xx-eth-0");
-
-- if ((err = mdiobus_register(mdio_bus)))
-+ err = of_mdiobus_register(mdio_bus, mdio_bus_np);
-+ if (err)
- mdiobus_free(mdio_bus);
- return err;
- }
-@@ -1358,18 +1360,118 @@ static const struct net_device_ops ixp4xx_netdev_ops = {
- .ndo_validate_addr = eth_validate_addr,
- };
-
-+#ifdef CONFIG_OF
-+static struct eth_plat_info *ixp4xx_of_get_platdata(struct device *dev)
-+{
-+ struct device_node *np = dev->of_node;
-+ struct of_phandle_args queue_spec;
-+ struct of_phandle_args npe_spec;
-+ struct device_node *mdio_np;
-+ struct eth_plat_info *plat;
-+ int ret;
-+
-+ plat = devm_kzalloc(dev, sizeof(*plat), GFP_KERNEL);
-+ if (!plat)
-+ return NULL;
-+
-+ ret = of_parse_phandle_with_fixed_args(np, "intel,npe-handle", 1, 0,
-+ &npe_spec);
-+ if (ret) {
-+ dev_err(dev, "no NPE engine specified\n");
-+ return NULL;
-+ }
-+ /* NPE ID 0x00, 0x10, 0x20... */
-+ plat->npe = (npe_spec.args[0] << 4);
-+
-+ /* Check if this device has an MDIO bus */
-+ mdio_np = of_get_child_by_name(np, "mdio");
-+ if (mdio_np) {
-+ plat->has_mdio = true;
-+ mdio_bus_np = mdio_np;
-+ /* DO NOT put the mdio_np, it will be used */
-+ }
-+
-+ /* Get the rx queue as a resource from queue manager */
-+ ret = of_parse_phandle_with_fixed_args(np, "queue-rx", 1, 0,
-+ &queue_spec);
-+ if (ret) {
-+ dev_err(dev, "no rx queue phandle\n");
-+ return NULL;
-+ }
-+ plat->rxq = queue_spec.args[0];
-+
-+ /* Get the txready queue as resource from queue manager */
-+ ret = of_parse_phandle_with_fixed_args(np, "queue-txready", 1, 0,
-+ &queue_spec);
-+ if (ret) {
-+ dev_err(dev, "no txready queue phandle\n");
-+ return NULL;
-+ }
-+ plat->txreadyq = queue_spec.args[0];
-+
-+ return plat;
-+}
-+#else
-+static struct eth_plat_info *ixp4xx_of_get_platdata(struct device *dev)
-+{
-+ return NULL;
-+}
-+#endif
-+
- static int ixp4xx_eth_probe(struct platform_device *pdev)
- {
- struct phy_device *phydev = NULL;
- struct device *dev = &pdev->dev;
-+ struct device_node *np = dev->of_node;
- struct eth_plat_info *plat;
-- resource_size_t regs_phys;
- struct net_device *ndev;
- struct resource *res;
- struct port *port;
- int err;
-
-- plat = dev_get_platdata(dev);
-+ if (np) {
-+ plat = ixp4xx_of_get_platdata(dev);
-+ if (!plat)
-+ return -ENODEV;
-+ } else {
-+ plat = dev_get_platdata(dev);
-+ if (!plat)
-+ return -ENODEV;
-+ plat->npe = pdev->id;
-+ switch (plat->npe) {
-+ case IXP4XX_ETH_NPEA:
-+ /* If the MDIO bus is not up yet, defer probe */
-+ break;
-+ case IXP4XX_ETH_NPEB:
-+ /* On all except IXP43x, NPE-B is used for the MDIO bus.
-+ * If there is no NPE-B in the feature set, bail out,
-+ * else we have the MDIO bus here.
-+ */
-+ if (!cpu_is_ixp43x()) {
-+ if (!(ixp4xx_read_feature_bits() &
-+ IXP4XX_FEATURE_NPEB_ETH0))
-+ return -ENODEV;
-+ /* Else register the MDIO bus on NPE-B */
-+ plat->has_mdio = true;
-+ }
-+ break;
-+ case IXP4XX_ETH_NPEC:
-+ /* IXP43x lacks NPE-B and uses NPE-C for the MDIO bus
-+ * access, if there is no NPE-C, no bus, nothing works,
-+ * so bail out.
-+ */
-+ if (cpu_is_ixp43x()) {
-+ if (!(ixp4xx_read_feature_bits() &
-+ IXP4XX_FEATURE_NPEC_ETH))
-+ return -ENODEV;
-+ /* Else register the MDIO bus on NPE-B */
-+ plat->has_mdio = true;
-+ }
-+ break;
-+ default:
-+ return -ENODEV;
-+ }
-+ }
-
- if (!(ndev = devm_alloc_etherdev(dev, sizeof(struct port))))
- return -ENOMEM;
-@@ -1377,59 +1479,29 @@ static int ixp4xx_eth_probe(struct platform_device *pdev)
- SET_NETDEV_DEV(ndev, dev);
- port = netdev_priv(ndev);
- port->netdev = ndev;
-- port->id = pdev->id;
-+ port->id = plat->npe;
-
- /* Get the port resource and remap */
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (!res)
- return -ENODEV;
-- regs_phys = res->start;
- port->regs = devm_ioremap_resource(dev, res);
- if (IS_ERR(port->regs))
- return PTR_ERR(port->regs);
-
-- switch (port->id) {
-- case IXP4XX_ETH_NPEA:
-- /* If the MDIO bus is not up yet, defer probe */
-- if (!mdio_bus)
-- return -EPROBE_DEFER;
-- break;
-- case IXP4XX_ETH_NPEB:
-- /*
-- * On all except IXP43x, NPE-B is used for the MDIO bus.
-- * If there is no NPE-B in the feature set, bail out, else
-- * register the MDIO bus.
-- */
-- if (!cpu_is_ixp43x()) {
-- if (!(ixp4xx_read_feature_bits() &
-- IXP4XX_FEATURE_NPEB_ETH0))
-- return -ENODEV;
-- /* Else register the MDIO bus on NPE-B */
-- if ((err = ixp4xx_mdio_register(port->regs)))
-- return err;
-- }
-- if (!mdio_bus)
-- return -EPROBE_DEFER;
-- break;
-- case IXP4XX_ETH_NPEC:
-- /*
-- * IXP43x lacks NPE-B and uses NPE-C for the MDIO bus access,
-- * of there is no NPE-C, no bus, nothing works, so bail out.
-- */
-- if (cpu_is_ixp43x()) {
-- if (!(ixp4xx_read_feature_bits() &
-- IXP4XX_FEATURE_NPEC_ETH))
-- return -ENODEV;
-- /* Else register the MDIO bus on NPE-C */
-- if ((err = ixp4xx_mdio_register(port->regs)))
-- return err;
-+ /* Register the MDIO bus if we have it */
-+ if (plat->has_mdio) {
-+ err = ixp4xx_mdio_register(port->regs);
-+ if (err) {
-+ dev_err(dev, "failed to register MDIO bus\n");
-+ return err;
- }
-- if (!mdio_bus)
-- return -EPROBE_DEFER;
-- break;
-- default:
-- return -ENODEV;
- }
-+ /* If the instance with the MDIO bus has not yet appeared,
-+ * defer probing until it gets probed.
-+ */
-+ if (!mdio_bus)
-+ return -EPROBE_DEFER;
-
- ndev->netdev_ops = &ixp4xx_netdev_ops;
- ndev->ethtool_ops = &ixp4xx_ethtool_ops;
-@@ -1440,12 +1512,6 @@ static int ixp4xx_eth_probe(struct platform_device *pdev)
- if (!(port->npe = npe_request(NPE_ID(port->id))))
- return -EIO;
-
-- port->mem_res = request_mem_region(regs_phys, REGS_SIZE, ndev->name);
-- if (!port->mem_res) {
-- err = -EBUSY;
-- goto err_npe_rel;
-- }
--
- port->plat = plat;
- npe_port_tab[NPE_ID(port->id)] = port;
- memcpy(ndev->dev_addr, plat->hwaddr, ETH_ALEN);
-@@ -1458,15 +1524,26 @@ static int ixp4xx_eth_probe(struct platform_device *pdev)
- __raw_writel(DEFAULT_CORE_CNTRL, &port->regs->core_control);
- udelay(50);
-
-- phydev = mdiobus_get_phy(mdio_bus, plat->phy);
-- if (IS_ERR(phydev)) {
-- err = PTR_ERR(phydev);
-- goto err_free_mem;
-+ if (np) {
-+ phydev = of_phy_get_and_connect(ndev, np, ixp4xx_adjust_link);
-+ } else {
-+ phydev = mdiobus_get_phy(mdio_bus, plat->phy);
-+ if (IS_ERR(phydev)) {
-+ err = PTR_ERR(phydev);
-+ dev_err(dev, "could not connect phydev (%d)\n", err);
-+ goto err_free_mem;
-+ }
-+ err = phy_connect_direct(ndev, phydev, ixp4xx_adjust_link,
-+ PHY_INTERFACE_MODE_MII);
-+ if (err)
-+ goto err_free_mem;
-+
- }
-- err = phy_connect_direct(ndev, phydev, ixp4xx_adjust_link,
-- PHY_INTERFACE_MODE_MII);
-- if (err)
-+ if (!phydev) {
-+ err = -ENODEV;
-+ dev_err(dev, "no phydev\n");
- goto err_free_mem;
-+ }
-
- phydev->irq = PHY_POLL;
-
-@@ -1482,8 +1559,6 @@ err_phy_dis:
- phy_disconnect(phydev);
- err_free_mem:
- npe_port_tab[NPE_ID(port->id)] = NULL;
-- release_resource(port->mem_res);
--err_npe_rel:
- npe_release(port->npe);
- return err;
- }
-@@ -1499,12 +1574,21 @@ static int ixp4xx_eth_remove(struct platform_device *pdev)
- ixp4xx_mdio_remove();
- npe_port_tab[NPE_ID(port->id)] = NULL;
- npe_release(port->npe);
-- release_resource(port->mem_res);
- return 0;
- }
-
-+static const struct of_device_id ixp4xx_eth_of_match[] = {
-+ {
-+ .compatible = "intel,ixp4xx-ethernet",
-+ },
-+ { },
-+};
-+
- static struct platform_driver ixp4xx_eth_driver = {
-- .driver.name = DRV_NAME,
-+ .driver = {
-+ .name = DRV_NAME,
-+ .of_match_table = of_match_ptr(ixp4xx_eth_of_match),
-+ },
- .probe = ixp4xx_eth_probe,
- .remove = ixp4xx_eth_remove,
- };
-diff --git a/include/linux/platform_data/eth_ixp4xx.h b/include/linux/platform_data/eth_ixp4xx.h
-index 6f652ea0c6ae2..114b0940729f5 100644
---- a/include/linux/platform_data/eth_ixp4xx.h
-+++ b/include/linux/platform_data/eth_ixp4xx.h
-@@ -14,6 +14,8 @@ struct eth_plat_info {
- u8 rxq; /* configurable, currently 0 - 31 only */
- u8 txreadyq;
- u8 hwaddr[6];
-+ u8 npe; /* NPE instance used by this interface */
-+ bool has_mdio; /* If this instance has an MDIO bus */
- };
-
- #endif
---
-cgit 1.2.3-1.el7
-
+++ /dev/null
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-From: Linus Walleij <linus.walleij@linaro.org>
-To: linux-arm-kernel@lists.infradead.org, Imre Kaloz <kaloz@openwrt.org>,
- Krzysztof Halasa <khalasa@piap.pl>
-Cc: Linus Walleij <linus.walleij@linaro.org>, Zoltan HERPAI <wigyori@uid0.hu>,
- Raylynn Knight <rayknight@me.com>
-Subject: [PATCH] ARM: dts: ixp4xx: Add ethernet
-Date: Mon, 10 May 2021 12:49:06 +0200
-Message-Id: <20210510104906.439171-1-linus.walleij@linaro.org>
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-
-This adds ethernet to the IXP4xx device trees.
-
-Cc: Zoltan HERPAI <wigyori@uid0.hu>
-Cc: Raylynn Knight <rayknight@me.com>
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
-ChangeLog v1->v2:
-- Adapt to the changes adding the proper MDIO bus and
- phy references in the nodes.
-- Use phandle for reference the NPE
----
- .../boot/dts/intel-ixp42x-linksys-nslu2.dts | 19 ++++++++
- .../dts/intel-ixp43x-gateworks-gw2358.dts | 19 ++++++++
- arch/arm/boot/dts/intel-ixp45x-ixp46x.dtsi | 44 +++++++++++++++++++
- arch/arm/boot/dts/intel-ixp4xx.dtsi | 24 +++++++++-
- 4 files changed, 105 insertions(+), 1 deletion(-)
-
-diff --git a/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts b/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts
-index 8fcd95805ff4..8cacf035dc32 100644
---- a/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts
-+++ b/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts
-@@ -106,4 +106,23 @@ partitions {
- fis-index-block = <0x3f>;
- };
- };
-+
-+ soc {
-+ ethernet@c8009000 {
-+ status = "ok";
-+ queue-rx = <&qmgr 3>;
-+ queue-txready = <&qmgr 20>;
-+ phy-mode = "rgmii";
-+ phy-handle = <&phy1>;
-+
-+ mdio {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ phy1: ethernet-phy@1 {
-+ reg = <1>;
-+ };
-+ };
-+ };
-+ };
- };
-diff --git a/arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts b/arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts
-index ba1163a1e1e7..f89d41b496ab 100644
---- a/arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts
-+++ b/arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts
-@@ -91,4 +91,23 @@ partitions {
- fis-index-block = <0xff>;
- };
- };
-+
-+ soc {
-+ ethernet@c800a000 {
-+ status = "ok";
-+ queue-rx = <&qmgr 4>;
-+ queue-txready = <&qmgr 21>;
-+ phy-mode = "rgmii";
-+ phy-handle = <&phy1>;
-+
-+ mdio {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ phy1: ethernet-phy@1 {
-+ reg = <1>;
-+ };
-+ };
-+ };
-+ };
- };
-diff --git a/arch/arm/boot/dts/intel-ixp45x-ixp46x.dtsi b/arch/arm/boot/dts/intel-ixp45x-ixp46x.dtsi
-index f8cd506659dc..ef3696e369b8 100644
---- a/arch/arm/boot/dts/intel-ixp45x-ixp46x.dtsi
-+++ b/arch/arm/boot/dts/intel-ixp45x-ixp46x.dtsi
-@@ -30,5 +30,49 @@ i2c@c8011000 {
- interrupts = <33 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-+
-+ /* This is known as EthA */
-+ ethernet@c800c000 {
-+ compatible = "intel,ixp4xx-ethernet";
-+ reg = <0xc800c000 0x1000>;
-+ status = "disabled";
-+ intel,npe = <0>;
-+ /* Dummy values that depend on firmware */
-+ queue-rx = <&qmgr 0>;
-+ queue-txready = <&qmgr 0>;
-+ };
-+
-+ /* This is known as EthB1 */
-+ ethernet@c800d000 {
-+ compatible = "intel,ixp4xx-ethernet";
-+ reg = <0xc800d000 0x1000>;
-+ status = "disabled";
-+ intel,npe = <1>;
-+ /* Dummy values that depend on firmware */
-+ queue-rx = <&qmgr 0>;
-+ queue-txready = <&qmgr 0>;
-+ };
-+
-+ /* This is known as EthB2 */
-+ ethernet@c800e000 {
-+ compatible = "intel,ixp4xx-ethernet";
-+ reg = <0xc800e000 0x1000>;
-+ status = "disabled";
-+ intel,npe = <2>;
-+ /* Dummy values that depend on firmware */
-+ queue-rx = <&qmgr 0>;
-+ queue-txready = <&qmgr 0>;
-+ };
-+
-+ /* This is known as EthB3 */
-+ ethernet@c800f000 {
-+ compatible = "intel,ixp4xx-ethernet";
-+ reg = <0xc800f000 0x1000>;
-+ status = "disabled";
-+ intel,npe = <3>;
-+ /* Dummy values that depend on firmware */
-+ queue-rx = <&qmgr 0>;
-+ queue-txready = <&qmgr 0>;
-+ };
- };
- };
-diff --git a/arch/arm/boot/dts/intel-ixp4xx.dtsi b/arch/arm/boot/dts/intel-ixp4xx.dtsi
-index d4a09584f417..b3de0501cf6f 100644
---- a/arch/arm/boot/dts/intel-ixp4xx.dtsi
-+++ b/arch/arm/boot/dts/intel-ixp4xx.dtsi
-@@ -61,9 +61,31 @@ timer@c8005000 {
- interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
- };
-
-- npe@c8006000 {
-+ npe: npe@c8006000 {
- compatible = "intel,ixp4xx-network-processing-engine";
- reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>;
- };
-+
-+ /* This is known as EthB */
-+ ethernet@c8009000 {
-+ compatible = "intel,ixp4xx-ethernet";
-+ reg = <0xc8009000 0x1000>;
-+ status = "disabled";
-+ /* Dummy values that depend on firmware */
-+ queue-rx = <&qmgr 3>;
-+ queue-txready = <&qmgr 20>;
-+ intel,npe-handle = <&npe 1>;
-+ };
-+
-+ /* This is known as EthC */
-+ ethernet@c800a000 {
-+ compatible = "intel,ixp4xx-ethernet";
-+ reg = <0xc800a000 0x1000>;
-+ status = "disabled";
-+ /* Dummy values that depend on firmware */
-+ queue-rx = <&qmgr 0>;
-+ queue-txready = <&qmgr 0>;
-+ intel,npe-handle = <&npe 2>;
-+ };
- };
- };
+++ /dev/null
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- Mon, 10 May 2021 14:40:32 -0700 (PDT)
-From: Linus Walleij <linus.walleij@linaro.org>
-To: linux-arm-kernel@lists.infradead.org, Imre Kaloz <kaloz@openwrt.org>,
- Krzysztof Halasa <khalasa@piap.pl>
-Cc: Linus Walleij <linus.walleij@linaro.org>, Zoltan HERPAI <wigyori@uid0.hu>,
- Raylynn Knight <rayknight@me.com>
-Subject: [PATCH] ARM: dts: ixp4xx: Add PCI hosts
-Date: Mon, 10 May 2021 23:40:18 +0200
-Message-Id: <20210510214018.601580-1-linus.walleij@linaro.org>
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-
-This adds a basic PCI host definition to the base device
-tree for IXP4xx and then further details it in the 42x
-and 43x device tree include, also the specific target
-devices NSLU2 and GW2358 get proper PCI swizzling
-defined.
-
-Cc: Zoltan HERPAI <wigyori@uid0.hu>
-Cc: Raylynn Knight <rayknight@me.com>
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- .../boot/dts/intel-ixp42x-linksys-nslu2.dts | 27 +++++++++++
- arch/arm/boot/dts/intel-ixp42x.dtsi | 4 ++
- .../dts/intel-ixp43x-gateworks-gw2358.dts | 46 +++++++++++++++++++
- arch/arm/boot/dts/intel-ixp43x.dtsi | 4 ++
- arch/arm/boot/dts/intel-ixp4xx.dtsi | 36 +++++++++++++++
- 5 files changed, 117 insertions(+)
-
-diff --git a/arch/arm/boot/dts/intel-ixp42x.dtsi b/arch/arm/boot/dts/intel-ixp42x.dtsi
-index a9622ca850cc..5fa063ed396c 100644
---- a/arch/arm/boot/dts/intel-ixp42x.dtsi
-+++ b/arch/arm/boot/dts/intel-ixp42x.dtsi
-@@ -7,6 +7,10 @@
-
- / {
- soc {
-+ pci@c0000000 {
-+ compatible = "intel,ixp42x-pci";
-+ };
-+
- interrupt-controller@c8003000 {
- compatible = "intel,ixp42x-interrupt";
- };
-diff --git a/arch/arm/boot/dts/intel-ixp43x.dtsi b/arch/arm/boot/dts/intel-ixp43x.dtsi
-index 494fb2ff57a0..1d0817c6e3f9 100644
---- a/arch/arm/boot/dts/intel-ixp43x.dtsi
-+++ b/arch/arm/boot/dts/intel-ixp43x.dtsi
-@@ -8,6 +8,10 @@
-
- / {
- soc {
-+ pci@c0000000 {
-+ compatible = "intel,ixp43x-pci";
-+ };
-+
- interrupt-controller@c8003000 {
- compatible = "intel,ixp43x-interrupt";
- };
-diff --git a/arch/arm/boot/dts/intel-ixp4xx.dtsi b/arch/arm/boot/dts/intel-ixp4xx.dtsi
-index d4a09584f417..52ba8e4a49cc 100644
---- a/arch/arm/boot/dts/intel-ixp4xx.dtsi
-+++ b/arch/arm/boot/dts/intel-ixp4xx.dtsi
-@@ -20,6 +20,42 @@ qmgr: queue-manager@60000000 {
- interrupts = <3 IRQ_TYPE_LEVEL_HIGH>, <4 IRQ_TYPE_LEVEL_HIGH>;
- };
-
-+ pci@c0000000 {
-+ compatible = "intel,ixp43x-pci";
-+ reg = <0xc0000000 0x1000>;
-+ interrupts = <8 IRQ_TYPE_LEVEL_HIGH>,
-+ <9 IRQ_TYPE_LEVEL_HIGH>,
-+ <10 IRQ_TYPE_LEVEL_HIGH>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ device_type = "pci";
-+ bus-range = <0x00 0xff>;
-+ status = "disabled";
-+
-+ ranges =
-+ /*
-+ * 64MB 32bit non-prefetchable memory 0x48000000-0x4bffffff
-+ * done in 4 chunks of 16MB each.
-+ */
-+ <0x02000000 0 0x48000000 0x48000000 0 0x04000000>,
-+ /* 64KB I/O space at 0x4c000000 */
-+ <0x01000000 0 0x00000000 0x4c000000 0 0x00010000>;
-+
-+ /*
-+ * This needs to map to the start of physical memory so
-+ * PCI devices can see all (hopefully) memory. This is done
-+ * using 4 1:1 16MB windows, so the RAM should not be more than
-+ * 64 MB for this to work. If your memory is anywhere else
-+ * than at 0x0 you need to alter this.
-+ */
-+ dma-ranges =
-+ <0x02000000 0 0x00000000 0x00000000 0 0x04000000>;
-+
-+ #interrupt-cells = <1>;
-+ interrupt-map-mask = <0xf800 0 0 7>;
-+ /* Each unique DTS using PCI must specify the swizzling */
-+ };
-+
- uart0: serial@c8000000 {
- compatible = "intel,xscale-uart";
- reg = <0xc8000000 0x1000>;
+++ /dev/null
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- Sun, 09 May 2021 15:21:01 -0700 (PDT)
-From: Linus Walleij <linus.walleij@linaro.org>
-To: Bjorn Helgaas <bhelgaas@google.com>
-Cc: linux-pci@vger.kernel.org, Arnd Bergmann <arnd@arndb.de>,
- Imre Kaloz <kaloz@openwrt.org>,
- Krzysztof Halasa <khalasa@piap.pl>,
- Zoltan HERPAI <wigyori@uid0.hu>,
- Raylynn Knight <rayknight@me.com>,
- Linus Walleij <linus.walleij@linaro.org>
-Subject: [PATCH 1/4 v3] ARM/ixp4xx: Move the virtual IObases
-Date: Mon, 10 May 2021 00:20:52 +0200
-Message-Id: <20210509222055.341945-2-linus.walleij@linaro.org>
-X-Mailer: git-send-email 2.30.2
-In-Reply-To: <20210509222055.341945-1-linus.walleij@linaro.org>
-References: <20210509222055.341945-1-linus.walleij@linaro.org>
-MIME-Version: 1.0
-Precedence: bulk
-List-ID: <linux-pci.vger.kernel.org>
-X-Mailing-List: linux-pci@vger.kernel.org
-
-UART1, UART2 and the expansion bus config registers
-are the only registers mapped in a fixed location
-when using device tree.
-
-For device tree we also want to get rid of the custom
-<mach/io.h> for IXP4xx. So we need to undefine
-CONFIG_NEED_MACH_IO_H. Doing that activates the fixed
-mapping of the PCI IO space to PCI_IO_VIRT_BASE which
-is hardcoded to 0xFEE00000 and this would collide with
-the old fixed mappings.
-
-Move the fixed virtual IO base address from 0xFEF00000
-to 0xFEC00000 in order to avoid the collision.
-
-For the OF-only boot path let's even cut the reliance
-on <mach/io.h> and just hardcode the one single virtbase
-we need apart from the UART, which is hardcoded in
-Kconfig.debug.
-
-Cc: Arnd Bergmann <arnd@arndb.de>
-Cc: Imre Kaloz <kaloz@openwrt.org>
-Cc: Krzysztof Halasa <khalasa@piap.pl>
-Cc: Zoltan HERPAI <wigyori@uid0.hu>
-Cc: Raylynn Knight <rayknight@me.com>
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
-ChangeLog v2->v3:
-- No changes, resend with the rest of the patches.
-ChangeLog v1->v2:
-- Instead of handling the UART and expansion ports
- separately just move all peripherals from 0xfef00000
- to 0xfec00000.
-- Stay out of the fixmap area, that area has special
- uses.
-
-PCI maintainers: this patch is mostly FYI, will be
-merged through ARM SoC
----
- arch/arm/Kconfig.debug | 4 ++--
- arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h | 7 ++++---
- arch/arm/mach-ixp4xx/ixp4xx-of.c | 8 ++++++--
- 3 files changed, 12 insertions(+), 7 deletions(-)
-
-diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
-index 9e0b5e7f12af..f672b23301e6 100644
---- a/arch/arm/Kconfig.debug
-+++ b/arch/arm/Kconfig.debug
-@@ -1803,8 +1803,8 @@ config DEBUG_UART_VIRT
- default 0xfedc0000 if DEBUG_EP93XX
- default 0xfee003f8 if DEBUG_FOOTBRIDGE_COM1
- default 0xfee20000 if DEBUG_NSPIRE_CLASSIC_UART || DEBUG_NSPIRE_CX_UART
-- default 0xfef00000 if ARCH_IXP4XX && !CPU_BIG_ENDIAN
-- default 0xfef00003 if ARCH_IXP4XX && CPU_BIG_ENDIAN
-+ default 0xfec00000 if ARCH_IXP4XX && !CPU_BIG_ENDIAN
-+ default 0xfec00003 if ARCH_IXP4XX && CPU_BIG_ENDIAN
- default 0xfef36000 if DEBUG_HIGHBANK_UART
- default 0xfefb0000 if DEBUG_OMAP1UART1 || DEBUG_OMAP7XXUART1
- default 0xfefb0800 if DEBUG_OMAP1UART2 || DEBUG_OMAP7XXUART2
-diff --git a/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h b/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
-index 708d085ce39f..f375c1c005d4 100644
---- a/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
-+++ b/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
-@@ -45,21 +45,21 @@
- * it can be used with the low-level debug code.
- */
- #define IXP4XX_PERIPHERAL_BASE_PHYS 0xC8000000
--#define IXP4XX_PERIPHERAL_BASE_VIRT IOMEM(0xFEF00000)
-+#define IXP4XX_PERIPHERAL_BASE_VIRT IOMEM(0xFEC00000)
- #define IXP4XX_PERIPHERAL_REGION_SIZE 0x00013000
-
- /*
- * PCI Config registers
- */
- #define IXP4XX_PCI_CFG_BASE_PHYS 0xC0000000
--#define IXP4XX_PCI_CFG_BASE_VIRT IOMEM(0xFEF13000)
-+#define IXP4XX_PCI_CFG_BASE_VIRT IOMEM(0xFEC13000)
- #define IXP4XX_PCI_CFG_REGION_SIZE 0x00001000
-
- /*
- * Expansion BUS Configuration registers
- */
- #define IXP4XX_EXP_CFG_BASE_PHYS 0xC4000000
--#define IXP4XX_EXP_CFG_BASE_VIRT 0xFEF14000
-+#define IXP4XX_EXP_CFG_BASE_VIRT 0xFEC14000
- #define IXP4XX_EXP_CFG_REGION_SIZE 0x00001000
-
- #define IXP4XX_EXP_CS0_OFFSET 0x00
-@@ -120,6 +120,7 @@
- #define IXP4XX_SSP_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x12000)
-
-
-+/* The UART is explicitly put in the beginning of fixmap */
- #define IXP4XX_UART1_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x0000)
- #define IXP4XX_UART2_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x1000)
- #define IXP4XX_PMU_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x2000)
-diff --git a/arch/arm/mach-ixp4xx/ixp4xx-of.c b/arch/arm/mach-ixp4xx/ixp4xx-of.c
-index 7449b8319c8a..f9904716ec7f 100644
---- a/arch/arm/mach-ixp4xx/ixp4xx-of.c
-+++ b/arch/arm/mach-ixp4xx/ixp4xx-of.c
-@@ -9,8 +9,12 @@
- #include <asm/mach/arch.h>
- #include <asm/mach/map.h>
-
--#include <mach/hardware.h>
--#include <mach/ixp4xx-regs.h>
-+/*
-+ * These are the only fixed phys to virt mappings we ever need
-+ * we put it right after the UART mapping at 0xffc80000-0xffc81fff
-+ */
-+#define IXP4XX_EXP_CFG_BASE_PHYS 0xC4000000
-+#define IXP4XX_EXP_CFG_BASE_VIRT 0xFEC14000
-
- static struct map_desc ixp4xx_of_io_desc[] __initdata = {
- /*
-
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-From: Linus Walleij <linus.walleij@linaro.org>
-To: Bjorn Helgaas <bhelgaas@google.com>
-Cc: linux-pci@vger.kernel.org, Arnd Bergmann <arnd@arndb.de>,
- Imre Kaloz <kaloz@openwrt.org>,
- Krzysztof Halasa <khalasa@piap.pl>,
- Zoltan HERPAI <wigyori@uid0.hu>,
- Raylynn Knight <rayknight@me.com>,
- Linus Walleij <linus.walleij@linaro.org>
-Subject: [PATCH 2/4 v3] ARM/ixp4xx: Make NEED_MACH_IO_H optional
-Date: Mon, 10 May 2021 00:20:53 +0200
-Message-Id: <20210509222055.341945-3-linus.walleij@linaro.org>
-X-Mailer: git-send-email 2.30.2
-In-Reply-To: <20210509222055.341945-1-linus.walleij@linaro.org>
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-MIME-Version: 1.0
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-List-ID: <linux-pci.vger.kernel.org>
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-
-In order to create a proper PCI driver for the IXP4xx
-we need to make the old PCI driver and its reliance
-on <mach/io.h> optional.
-
-Create a new Kconfig symbol for the legacy PCI driver
-IXP4XX_PCI_LEGACY and only activate NEED_MACH_IO_H
-for this driver.
-
-A few files need to be adjusted to explicitly include
-the <mach/hardware.h> and <mach/cpu.h> headers that
-they previously obtained implicitly using <linux/io.h>
-that would include <mach/io.h> and in turn include
-these two headers.
-
-This breaks our reliance on the old PCI and indirect
-PCI support so we can reimplement a proper purely
-DT-based driver in the PCI subsystem.
-
-Cc: Arnd Bergmann <arnd@arndb.de>
-Cc: Imre Kaloz <kaloz@openwrt.org>
-Cc: Krzysztof Halasa <khalasa@piap.pl>
-Cc: Zoltan HERPAI <wigyori@uid0.hu>
-Cc: Raylynn Knight <rayknight@me.com>
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
-ChangeLog v2->v3:
-- No changes, resend with the rest of the patches.
-
-PCI maintainers: this patch is mostly FYI, will be
-merged through ARM SoC
----
- arch/arm/Kconfig | 3 ++-
- arch/arm/mach-ixp4xx/Kconfig | 33 +++++++++++++++---------
- arch/arm/mach-ixp4xx/common.c | 1 -
- arch/arm/mach-ixp4xx/fsg-setup.c | 1 +
- arch/arm/mach-ixp4xx/nas100d-setup.c | 1 +
- arch/arm/mach-ixp4xx/nslu2-setup.c | 1 +
- drivers/ata/pata_ixp4xx_cf.c | 1 +
- drivers/net/ethernet/xscale/ixp4xx_eth.c | 1 +
- drivers/soc/ixp4xx/ixp4xx-npe.c | 2 ++
- drivers/soc/ixp4xx/ixp4xx-qmgr.c | 2 ++
- 10 files changed, 32 insertions(+), 14 deletions(-)
-
-diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
-index 853aab5ab327..4ca2ab19d265 100644
---- a/arch/arm/Kconfig
-+++ b/arch/arm/Kconfig
-@@ -394,7 +394,8 @@ config ARCH_IXP4XX
- select HAVE_PCI
- select IXP4XX_IRQ
- select IXP4XX_TIMER
-- select NEED_MACH_IO_H
-+ # With the new PCI driver this is not needed
-+ select NEED_MACH_IO_H if PCI_IXP4XX_LEGACY
- select USB_EHCI_BIG_ENDIAN_DESC
- select USB_EHCI_BIG_ENDIAN_MMIO
- help
-diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig
-index 165c184801e1..cabb37232704 100644
---- a/arch/arm/mach-ixp4xx/Kconfig
-+++ b/arch/arm/mach-ixp4xx/Kconfig
-@@ -20,7 +20,7 @@ config MACH_IXP4XX_OF
- config MACH_NSLU2
- bool
- prompt "Linksys NSLU2"
-- select FORCE_PCI
-+ depends on IXP4XX_PCI_LEGACY
- help
- Say 'Y' here if you want your kernel to support Linksys's
- NSLU2 NAS device. For more information on this platform,
-@@ -28,7 +28,7 @@ config MACH_NSLU2
-
- config MACH_AVILA
- bool "Avila"
-- select FORCE_PCI
-+ depends on IXP4XX_PCI_LEGACY
- help
- Say 'Y' here if you want your kernel to support the Gateworks
- Avila Network Platform. For more information on this platform,
-@@ -44,7 +44,7 @@ config MACH_LOFT
-
- config ARCH_ADI_COYOTE
- bool "Coyote"
-- select FORCE_PCI
-+ depends on IXP4XX_PCI_LEGACY
- help
- Say 'Y' here if you want your kernel to support the ADI
- Engineering Coyote Gateway Reference Platform. For more
-@@ -52,7 +52,7 @@ config ARCH_ADI_COYOTE
-
- config MACH_GATEWAY7001
- bool "Gateway 7001"
-- select FORCE_PCI
-+ depends on IXP4XX_PCI_LEGACY
- help
- Say 'Y' here if you want your kernel to support Gateway's
- 7001 Access Point. For more information on this platform,
-@@ -60,7 +60,7 @@ config MACH_GATEWAY7001
-
- config MACH_WG302V2
- bool "Netgear WG302 v2 / WAG302 v2"
-- select FORCE_PCI
-+ depends on IXP4XX_PCI_LEGACY
- help
- Say 'Y' here if you want your kernel to support Netgear's
- WG302 v2 or WAG302 v2 Access Points. For more information
-@@ -68,6 +68,7 @@ config MACH_WG302V2
-
- config ARCH_IXDP425
- bool "IXDP425"
-+ depends on IXP4XX_PCI_LEGACY
- help
- Say 'Y' here if you want your kernel to support Intel's
- IXDP425 Development Platform (Also known as Richfield).
-@@ -75,6 +76,7 @@ config ARCH_IXDP425
-
- config MACH_IXDPG425
- bool "IXDPG425"
-+ depends on IXP4XX_PCI_LEGACY
- help
- Say 'Y' here if you want your kernel to support Intel's
- IXDPG425 Development Platform (Also known as Montajade).
-@@ -120,7 +122,7 @@ config ARCH_PRPMC1100
- config MACH_NAS100D
- bool
- prompt "NAS100D"
-- select FORCE_PCI
-+ depends on IXP4XX_PCI_LEGACY
- help
- Say 'Y' here if you want your kernel to support Iomega's
- NAS 100d device. For more information on this platform,
-@@ -129,7 +131,7 @@ config MACH_NAS100D
- config MACH_DSMG600
- bool
- prompt "D-Link DSM-G600 RevA"
-- select FORCE_PCI
-+ depends on IXP4XX_PCI_LEGACY
- help
- Say 'Y' here if you want your kernel to support D-Link's
- DSM-G600 RevA device. For more information on this platform,
-@@ -143,7 +145,7 @@ config ARCH_IXDP4XX
- config MACH_FSG
- bool
- prompt "Freecom FSG-3"
-- select FORCE_PCI
-+ depends on IXP4XX_PCI_LEGACY
- help
- Say 'Y' here if you want your kernel to support Freecom's
- FSG-3 device. For more information on this platform,
-@@ -152,7 +154,7 @@ config MACH_FSG
- config MACH_ARCOM_VULCAN
- bool
- prompt "Arcom/Eurotech Vulcan"
-- select FORCE_PCI
-+ depends on IXP4XX_PCI_LEGACY
- help
- Say 'Y' here if you want your kernel to support Arcom's
- Vulcan board.
-@@ -173,7 +175,7 @@ config CPU_IXP43X
- config MACH_GTWX5715
- bool "Gemtek WX5715 (Linksys WRV54G)"
- depends on ARCH_IXP4XX
-- select FORCE_PCI
-+ depends on IXP4XX_PCI_LEGACY
- help
- This board is currently inside the Linksys WRV54G Gateways.
-
-@@ -196,7 +198,7 @@ config MACH_DEVIXP
-
- config MACH_MICCPT
- bool "Omicron MICCPT"
-- select FORCE_PCI
-+ depends on IXP4XX_PCI_LEGACY
- help
- Say 'Y' here if you want your kernel to support the MICCPT
- board from OMICRON electronics GmbH.
-@@ -209,9 +211,16 @@ config MACH_MIC256
-
- comment "IXP4xx Options"
-
-+config IXP4XX_PCI_LEGACY
-+ bool "IXP4xx legacy PCI driver support"
-+ depends on PCI
-+ help
-+ Selects legacy PCI driver.
-+ Not recommended for new development.
-+
- config IXP4XX_INDIRECT_PCI
- bool "Use indirect PCI memory access"
-- depends on PCI
-+ depends on IXP4XX_PCI_LEGACY
- help
- IXP4xx provides two methods of accessing PCI memory space:
-
-diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
-index 000f672a94c9..431da1b4f6bd 100644
---- a/arch/arm/mach-ixp4xx/common.c
-+++ b/arch/arm/mach-ixp4xx/common.c
-@@ -32,7 +32,6 @@
- #include <linux/dma-map-ops.h>
- #include <mach/udc.h>
- #include <mach/hardware.h>
--#include <mach/io.h>
- #include <linux/uaccess.h>
- #include <asm/page.h>
- #include <asm/exception.h>
-diff --git a/arch/arm/mach-ixp4xx/fsg-setup.c b/arch/arm/mach-ixp4xx/fsg-setup.c
-index 507ee3878769..844329c5610d 100644
---- a/arch/arm/mach-ixp4xx/fsg-setup.c
-+++ b/arch/arm/mach-ixp4xx/fsg-setup.c
-@@ -28,6 +28,7 @@
- #include <asm/mach-types.h>
- #include <asm/mach/arch.h>
- #include <asm/mach/flash.h>
-+#include <mach/hardware.h>
-
- #include "irqs.h"
-
-diff --git a/arch/arm/mach-ixp4xx/nas100d-setup.c b/arch/arm/mach-ixp4xx/nas100d-setup.c
-index 6959ad2e3aec..6133cf01cbe4 100644
---- a/arch/arm/mach-ixp4xx/nas100d-setup.c
-+++ b/arch/arm/mach-ixp4xx/nas100d-setup.c
-@@ -33,6 +33,7 @@
- #include <asm/mach-types.h>
- #include <asm/mach/arch.h>
- #include <asm/mach/flash.h>
-+#include <mach/hardware.h>
-
- #include "irqs.h"
-
-diff --git a/arch/arm/mach-ixp4xx/nslu2-setup.c b/arch/arm/mach-ixp4xx/nslu2-setup.c
-index a428bb918703..8526a70e401b 100644
---- a/arch/arm/mach-ixp4xx/nslu2-setup.c
-+++ b/arch/arm/mach-ixp4xx/nslu2-setup.c
-@@ -31,6 +31,7 @@
- #include <asm/mach/arch.h>
- #include <asm/mach/flash.h>
- #include <asm/mach/time.h>
-+#include <mach/hardware.h>
-
- #include "irqs.h"
-
-diff --git a/drivers/ata/pata_ixp4xx_cf.c b/drivers/ata/pata_ixp4xx_cf.c
-index d1644a8ef9fa..9929d0150141 100644
---- a/drivers/ata/pata_ixp4xx_cf.c
-+++ b/drivers/ata/pata_ixp4xx_cf.c
-@@ -18,6 +18,7 @@
- #include <linux/irq.h>
- #include <linux/platform_device.h>
- #include <scsi/scsi_host.h>
-+#include <mach/hardware.h>
-
- #define DRV_NAME "pata_ixp4xx_cf"
- #define DRV_VERSION "0.2"
-diff --git a/drivers/net/ethernet/xscale/ixp4xx_eth.c b/drivers/net/ethernet/xscale/ixp4xx_eth.c
-index 0152f1e70783..88ad1639a7da 100644
---- a/drivers/net/ethernet/xscale/ixp4xx_eth.c
-+++ b/drivers/net/ethernet/xscale/ixp4xx_eth.c
-@@ -36,6 +36,7 @@
- #include <linux/module.h>
- #include <linux/soc/ixp4xx/npe.h>
- #include <linux/soc/ixp4xx/qmgr.h>
-+#include <mach/hardware.h>
-
- #include "ixp46x_ts.h"
-
-diff --git a/drivers/soc/ixp4xx/ixp4xx-npe.c b/drivers/soc/ixp4xx/ixp4xx-npe.c
-index ec90b44fa0cd..0a16ac46ab59 100644
---- a/drivers/soc/ixp4xx/ixp4xx-npe.c
-+++ b/drivers/soc/ixp4xx/ixp4xx-npe.c
-@@ -20,6 +20,8 @@
- #include <linux/of.h>
- #include <linux/platform_device.h>
- #include <linux/soc/ixp4xx/npe.h>
-+#include <mach/hardware.h>
-+#include <mach/cpu.h>
-
- #define DEBUG_MSG 0
- #define DEBUG_FW 0
-diff --git a/drivers/soc/ixp4xx/ixp4xx-qmgr.c b/drivers/soc/ixp4xx/ixp4xx-qmgr.c
-index 8c968382cea7..1b1631ac0438 100644
---- a/drivers/soc/ixp4xx/ixp4xx-qmgr.c
-+++ b/drivers/soc/ixp4xx/ixp4xx-qmgr.c
-@@ -12,6 +12,8 @@
- #include <linux/of.h>
- #include <linux/platform_device.h>
- #include <linux/soc/ixp4xx/qmgr.h>
-+#include <mach/hardware.h>
-+#include <mach/cpu.h>
-
- static struct qmgr_regs __iomem *qmgr_regs;
- static int qmgr_irq_1;
-
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-From: Linus Walleij <linus.walleij@linaro.org>
-To: Bjorn Helgaas <bhelgaas@google.com>
-Cc: linux-pci@vger.kernel.org, Arnd Bergmann <arnd@arndb.de>,
- Imre Kaloz <kaloz@openwrt.org>,
- Krzysztof Halasa <khalasa@piap.pl>,
- Zoltan HERPAI <wigyori@uid0.hu>,
- Raylynn Knight <rayknight@me.com>,
- Linus Walleij <linus.walleij@linaro.org>,
- devicetree@vger.kernel.org
-Subject: [PATCH 3/4 v3] PCI: ixp4xx: Add device tree bindings for IXP4xx
-Date: Mon, 10 May 2021 00:20:54 +0200
-Message-Id: <20210509222055.341945-4-linus.walleij@linaro.org>
-X-Mailer: git-send-email 2.30.2
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-MIME-Version: 1.0
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-List-ID: <linux-pci.vger.kernel.org>
-X-Mailing-List: linux-pci@vger.kernel.org
-
-This adds device tree bindings for the Intel IXP4xx
-PCI controller which can be used as both host and
-option.
-
-Cc: devicetree@vger.kernel.org
-Cc: Arnd Bergmann <arnd@arndb.de>
-Cc: Imre Kaloz <kaloz@openwrt.org>
-Cc: Krzysztof Halasa <khalasa@piap.pl>
-Cc: Zoltan HERPAI <wigyori@uid0.hu>
-Cc: Raylynn Knight <rayknight@me.com>
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-Reviewed-by: Rob Herring <robh@kernel.org>
----
-ChangeLog v2->v3:
-- Drop ranges, these are part of pci-bus.yaml
-- Drop status = "disabled" on the node
-ChangeLog v1->v2:
-- Add the three controller interrupts to the binding.
-
-PCI maintainers: mainly looking for a review and ACK (if
-you care about DT bindings) the patch will be merged
-through ARM SoC.
----
- .../bindings/pci/intel,ixp4xx-pci.yaml | 100 ++++++++++++++++++
- 1 file changed, 100 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/pci/intel,ixp4xx-pci.yaml
-
-diff --git a/Documentation/devicetree/bindings/pci/intel,ixp4xx-pci.yaml b/Documentation/devicetree/bindings/pci/intel,ixp4xx-pci.yaml
-new file mode 100644
-index 000000000000..debfb54a8042
---- /dev/null
-+++ b/Documentation/devicetree/bindings/pci/intel,ixp4xx-pci.yaml
-@@ -0,0 +1,100 @@
-+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/pci/intel,ixp4xx-pci.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: Intel IXP4xx PCI controller
-+
-+maintainers:
-+ - Linus Walleij <linus.walleij@linaro.org>
-+
-+description: PCI host controller found in the Intel IXP4xx SoC series.
-+
-+allOf:
-+ - $ref: /schemas/pci/pci-bus.yaml#
-+
-+properties:
-+ compatible:
-+ items:
-+ - enum:
-+ - intel,ixp42x-pci
-+ - intel,ixp43x-pci
-+ description: The two supported variants are ixp42x and ixp43x,
-+ though more variants may exist.
-+
-+ reg:
-+ items:
-+ - description: IXP4xx-specific registers
-+
-+ interrupts:
-+ items:
-+ - description: Main PCI interrupt
-+ - description: PCI DMA interrupt 1
-+ - description: PCI DMA interrupt 2
-+
-+ ranges:
-+ maxItems: 2
-+ description: Typically one memory range of 64MB and one IO
-+ space range of 64KB.
-+
-+ dma-ranges:
-+ maxItems: 1
-+ description: The DMA range tells the PCI host which addresses
-+ the RAM is at. It can map only 64MB so if the RAM is bigger
-+ than 64MB the DMA access has to be restricted to these
-+ addresses.
-+
-+ "#interrupt-cells": true
-+
-+ interrupt-map: true
-+
-+ interrupt-map-mask:
-+ items:
-+ - const: 0xf800
-+ - const: 0
-+ - const: 0
-+ - const: 7
-+
-+required:
-+ - compatible
-+ - reg
-+ - dma-ranges
-+ - "#interrupt-cells"
-+ - interrupt-map
-+ - interrupt-map-mask
-+
-+unevaluatedProperties: false
-+
-+examples:
-+ - |
-+ pci@c0000000 {
-+ compatible = "intel,ixp43x-pci";
-+ reg = <0xc0000000 0x1000>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ device_type = "pci";
-+ bus-range = <0x00 0xff>;
-+
-+ ranges =
-+ <0x02000000 0 0x48000000 0x48000000 0 0x04000000>,
-+ <0x01000000 0 0x00000000 0x4c000000 0 0x00010000>;
-+ dma-ranges =
-+ <0x02000000 0 0x00000000 0x00000000 0 0x04000000>;
-+
-+ #interrupt-cells = <1>;
-+ interrupt-map-mask = <0xf800 0 0 7>;
-+ interrupt-map =
-+ <0x0800 0 0 1 &gpio0 11 3>, /* INT A on slot 1 is irq 11 */
-+ <0x0800 0 0 2 &gpio0 10 3>, /* INT B on slot 1 is irq 10 */
-+ <0x0800 0 0 3 &gpio0 9 3>, /* INT C on slot 1 is irq 9 */
-+ <0x0800 0 0 4 &gpio0 8 3>, /* INT D on slot 1 is irq 8 */
-+ <0x1000 0 0 1 &gpio0 10 3>, /* INT A on slot 2 is irq 10 */
-+ <0x1000 0 0 2 &gpio0 9 3>, /* INT B on slot 2 is irq 9 */
-+ <0x1000 0 0 3 &gpio0 8 3>, /* INT C on slot 2 is irq 8 */
-+ <0x1000 0 0 4 &gpio0 11 3>, /* INT D on slot 2 is irq 11 */
-+ <0x1800 0 0 1 &gpio0 9 3>, /* INT A on slot 3 is irq 9 */
-+ <0x1800 0 0 2 &gpio0 8 3>, /* INT B on slot 3 is irq 8 */
-+ <0x1800 0 0 3 &gpio0 11 3>, /* INT C on slot 3 is irq 11 */
-+ <0x1800 0 0 4 &gpio0 10 3>; /* INT D on slot 3 is irq 10 */
-+ };
-
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- Sun, 09 May 2021 15:21:06 -0700 (PDT)
-From: Linus Walleij <linus.walleij@linaro.org>
-To: Bjorn Helgaas <bhelgaas@google.com>
-Cc: linux-pci@vger.kernel.org, Arnd Bergmann <arnd@arndb.de>,
- Imre Kaloz <kaloz@openwrt.org>,
- Krzysztof Halasa <khalasa@piap.pl>,
- Zoltan HERPAI <wigyori@uid0.hu>,
- Raylynn Knight <rayknight@me.com>,
- Linus Walleij <linus.walleij@linaro.org>
-Subject: [PATCH 4/4 v3] PCI: ixp4xx: Add a new driver for IXP4xx
-Date: Mon, 10 May 2021 00:20:55 +0200
-Message-Id: <20210509222055.341945-5-linus.walleij@linaro.org>
-X-Mailer: git-send-email 2.30.2
-In-Reply-To: <20210509222055.341945-1-linus.walleij@linaro.org>
-References: <20210509222055.341945-1-linus.walleij@linaro.org>
-MIME-Version: 1.0
-Precedence: bulk
-List-ID: <linux-pci.vger.kernel.org>
-X-Mailing-List: linux-pci@vger.kernel.org
-
-This adds a new PCI controller driver for the Intel IXP4xx
-(IX425, IXP435 etc), based on the XScale microarchitecture.
-
-This replaces the old driver in arch/arm/mach-ixp4xx/common-pci.c
-which utilized the ARM-specific BIOS32 PCI framework,
-and all parameterization for such things as memory and
-IO space as well as interrupt swizzling is done from the
-device tree.
-
-The __raw_writel() and __raw_readl() are used for accessing
-the PCI controller for the same reason that these accessors
-are used in the timer, IRQ and GPIO drivers: the platform
-will alter its address bus pattern based on whether the
-system is booted in big- or little-endian mode. For this
-reason all register on IXP4xx must always be accessed in
-native (CPU) endianness.
-
-This driver supports 64MB of PCI memory space, but not the
-indirect access of 1GB that is available in the old driver.
-We can address that later if and only if there are users
-that need all 1GB of PCI address space.
-
-Tested by booting the NSLU2, attaching a USB stick, mounting
-and browsing the drive.
-
-Cc: Arnd Bergmann <arnd@arndb.de>
-Cc: Imre Kaloz <kaloz@openwrt.org>
-Cc: Krzysztof Halasa <khalasa@piap.pl>
-Cc: Zoltan HERPAI <wigyori@uid0.hu>
-Cc: Raylynn Knight <rayknight@me.com>
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
-ChangeLog v2->v3:
-- Fix a double assignment of .suppress_bind_attrs
-ChangeLog v1->v2:
-- Add dependencies on ARM to Kconfig since we are regisering
- and ARM only abort handler.
-- Create ixp4xx_readl() and ixp4xx_writel() static inline
- wrappers around the __raw_readl() and __raw_writel() calls
- with a big comment block explaining what is going on.
-- Drop bus pointer from state container, it is only used in
- probe()
-- Use pci_host_probe() and get rid of a lot of boilerplate.
-- Use builtin_driver_probe() and explain why this is
- necessary with comments in the code.
-
-PCI maintainers: looking for review or ACK to take this
-driver throght ARM SoC since it is dependent on the first
-patches in the series in order not to cause build
-problems.
----
- MAINTAINERS | 6 +
- drivers/pci/controller/Kconfig | 8 +
- drivers/pci/controller/Makefile | 1 +
- drivers/pci/controller/pci-ixp4xx.c | 705 ++++++++++++++++++++++++++++
- 4 files changed, 720 insertions(+)
- create mode 100644 drivers/pci/controller/pci-ixp4xx.c
-
-diff --git a/MAINTAINERS b/MAINTAINERS
-index d92f85ca831d..ae220d52a6d7 100644
---- a/MAINTAINERS
-+++ b/MAINTAINERS
-@@ -13692,6 +13692,12 @@ S: Maintained
- F: Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
- F: drivers/pci/controller/dwc/*imx6*
-
-+PCI DRIVER FOR INTEL IXP4XX
-+M: Linus Walleij <linus.walleij@linaro.org>
-+S: Maintained
-+F: Documentation/devicetree/bindings/pci/intel,ixp4xx-pci.yaml
-+F: drivers/pci/controller/pci-ixp4xx.c
-+
- PCI DRIVER FOR INTEL VOLUME MANAGEMENT DEVICE (VMD)
- M: Jonathan Derrick <jonathan.derrick@intel.com>
- L: linux-pci@vger.kernel.org
-diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
-index 5aa8977d7b0f..b9a9a05be0e7 100644
---- a/drivers/pci/controller/Kconfig
-+++ b/drivers/pci/controller/Kconfig
-@@ -37,6 +37,14 @@ config PCI_FTPCI100
- depends on OF
- default ARCH_GEMINI
-
-+config PCI_IXP4XX
-+ bool "Intel IXP4xx PCI controller"
-+ depends on ARM && OF
-+ default ARCH_IXP4XX
-+ help
-+ Say Y here if you want support for the PCI host controller found
-+ in the Intel IXP4xx XScale-based network processor SoC.
-+
- config PCI_TEGRA
- bool "NVIDIA Tegra PCIe controller"
- depends on ARCH_TEGRA || COMPILE_TEST
-diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
-index e4559f2182f2..f81f3fd7a9e0 100644
---- a/drivers/pci/controller/Makefile
-+++ b/drivers/pci/controller/Makefile
-@@ -1,6 +1,7 @@
- # SPDX-License-Identifier: GPL-2.0
- obj-$(CONFIG_PCIE_CADENCE) += cadence/
- obj-$(CONFIG_PCI_FTPCI100) += pci-ftpci100.o
-+obj-$(CONFIG_PCI_IXP4XX) += pci-ixp4xx.o
- obj-$(CONFIG_PCI_HYPERV) += pci-hyperv.o
- obj-$(CONFIG_PCI_HYPERV_INTERFACE) += pci-hyperv-intf.o
- obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
-diff --git a/drivers/pci/controller/pci-ixp4xx.c b/drivers/pci/controller/pci-ixp4xx.c
-new file mode 100644
-index 000000000000..c6912fd630b4
---- /dev/null
-+++ b/drivers/pci/controller/pci-ixp4xx.c
-@@ -0,0 +1,705 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Support for Intel IXP4xx PCI host controller
-+ *
-+ * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
-+ *
-+ * Based on the IXP4xx arch/arm/mach-ixp4xx/common-pci.c driver
-+ * Copyright (C) 2002 Intel Corporation
-+ * Copyright (C) 2003 Greg Ungerer <gerg@linux-m68k.org>
-+ * Copyright (C) 2003-2004 MontaVista Software, Inc.
-+ * Copyright (C) 2005 Deepak Saxena <dsaxena@plexity.net>
-+ * Copyright (C) 2005 Alessandro Zummo <a.zummo@towertech.it>
-+ *
-+ * TODO:
-+ * - Test IO-space access
-+ * - DMA support
-+ */
-+
-+#include <linux/init.h>
-+#include <linux/io.h>
-+#include <linux/kernel.h>
-+#include <linux/of_address.h>
-+#include <linux/of_device.h>
-+#include <linux/of_pci.h>
-+#include <linux/pci.h>
-+#include <linux/platform_device.h>
-+#include <linux/slab.h>
-+#include <linux/bits.h>
-+
-+/* Register offsets */
-+#define IXP4XX_PCI_NP_AD 0x00
-+#define IXP4XX_PCI_NP_CBE 0x04
-+#define IXP4XX_PCI_NP_WDATA 0x08
-+#define IXP4XX_PCI_NP_RDATA 0x0c
-+#define IXP4XX_PCI_CRP_AD_CBE 0x10
-+#define IXP4XX_PCI_CRP_WDATA 0x14
-+#define IXP4XX_PCI_CRP_RDATA 0x18
-+#define IXP4XX_PCI_CSR 0x1c
-+#define IXP4XX_PCI_ISR 0x20
-+#define IXP4XX_PCI_INTEN 0x24
-+#define IXP4XX_PCI_DMACTRL 0x28
-+#define IXP4XX_PCI_AHBMEMBASE 0x2c
-+#define IXP4XX_PCI_AHBIOBASE 0x30
-+#define IXP4XX_PCI_PCIMEMBASE 0x34
-+#define IXP4XX_PCI_AHBDOORBELL 0x38
-+#define IXP4XX_PCI_PCIDOORBELL 0x3C
-+#define IXP4XX_PCI_ATPDMA0_AHBADDR 0x40
-+#define IXP4XX_PCI_ATPDMA0_PCIADDR 0x44
-+#define IXP4XX_PCI_ATPDMA0_LENADDR 0x48
-+#define IXP4XX_PCI_ATPDMA1_AHBADDR 0x4C
-+#define IXP4XX_PCI_ATPDMA1_PCIADDR 0x50
-+#define IXP4XX_PCI_ATPDMA1_LENADDR 0x54
-+
-+/* CSR bit definitions */
-+#define IXP4XX_PCI_CSR_HOST BIT(0)
-+#define IXP4XX_PCI_CSR_ARBEN BIT(1)
-+#define IXP4XX_PCI_CSR_ADS BIT(2)
-+#define IXP4XX_PCI_CSR_PDS BIT(3)
-+#define IXP4XX_PCI_CSR_ABE BIT(4)
-+#define IXP4XX_PCI_CSR_DBT BIT(5)
-+#define IXP4XX_PCI_CSR_ASE BIT(8)
-+#define IXP4XX_PCI_CSR_IC BIT(15)
-+#define IXP4XX_PCI_CSR_PRST BIT(16)
-+
-+/* ISR (Interrupt status) Register bit definitions */
-+#define IXP4XX_PCI_ISR_PSE BIT(0)
-+#define IXP4XX_PCI_ISR_PFE BIT(1)
-+#define IXP4XX_PCI_ISR_PPE BIT(2)
-+#define IXP4XX_PCI_ISR_AHBE BIT(3)
-+#define IXP4XX_PCI_ISR_APDC BIT(4)
-+#define IXP4XX_PCI_ISR_PADC BIT(5)
-+#define IXP4XX_PCI_ISR_ADB BIT(6)
-+#define IXP4XX_PCI_ISR_PDB BIT(7)
-+
-+/* INTEN (Interrupt Enable) Register bit definitions */
-+#define IXP4XX_PCI_INTEN_PSE BIT(0)
-+#define IXP4XX_PCI_INTEN_PFE BIT(1)
-+#define IXP4XX_PCI_INTEN_PPE BIT(2)
-+#define IXP4XX_PCI_INTEN_AHBE BIT(3)
-+#define IXP4XX_PCI_INTEN_APDC BIT(4)
-+#define IXP4XX_PCI_INTEN_PADC BIT(5)
-+#define IXP4XX_PCI_INTEN_ADB BIT(6)
-+#define IXP4XX_PCI_INTEN_PDB BIT(7)
-+
-+/* Shift value for byte enable on NP cmd/byte enable register */
-+#define IXP4XX_PCI_NP_CBE_BESL 4
-+
-+/* PCI commands supported by NP access unit */
-+#define NP_CMD_IOREAD 0x2
-+#define NP_CMD_IOWRITE 0x3
-+#define NP_CMD_CONFIGREAD 0xa
-+#define NP_CMD_CONFIGWRITE 0xb
-+#define NP_CMD_MEMREAD 0x6
-+#define NP_CMD_MEMWRITE 0x7
-+
-+/* Constants for CRP access into local config space */
-+#define CRP_AD_CBE_BESL 20
-+#define CRP_AD_CBE_WRITE 0x00010000
-+
-+/* Special PCI configuration space registers for this controller */
-+#define IXP4XX_PCI_RTOTTO 0x40
-+
-+struct ixp4xx_pci {
-+ struct device *dev;
-+ void __iomem *base;
-+ raw_spinlock_t lock; /* Protects bus writes */
-+ bool errata_hammer;
-+ bool host_mode;
-+};
-+
-+/*
-+ * The IXP4xx has a peculiar address bus that will change the
-+ * byte order on SoC peripherals depending on whether the device
-+ * operates in big endian or little endian mode. That means that
-+ * readl() and writel() that always use little-endian access
-+ * will not work for SoC peripherals such as the PCI controller
-+ * when used in big endian mode. The accesses to the individual
-+ * PCI devices on the other hand, are always little-endian and
-+ * can use readl() and writel().
-+ *
-+ * For local AHB bus access we need to use __raw_[readl|writel]()
-+ * to make sure that we access the SoC devices in the CPU native
-+ * endianness.
-+ */
-+static inline u32 ixp4xx_readl(struct ixp4xx_pci *p, u32 reg)
-+{
-+ return __raw_readl(p->base + reg);
-+}
-+
-+static inline void ixp4xx_writel(struct ixp4xx_pci *p, u32 reg, u32 val)
-+{
-+ __raw_writel(val, p->base + reg);
-+}
-+
-+static int ixp4xx_pci_check_master_abort(struct ixp4xx_pci *p)
-+{
-+ u32 isr = ixp4xx_readl(p, IXP4XX_PCI_ISR);
-+
-+ if (isr & IXP4XX_PCI_ISR_PFE) {
-+ /* Make sure the master abort bit is reset */
-+ ixp4xx_writel(p, IXP4XX_PCI_ISR, IXP4XX_PCI_ISR_PFE);
-+ dev_dbg(p->dev, "master abort detected\n");
-+ return -EINVAL;
-+ }
-+
-+ return 0;
-+}
-+
-+static int ixp4xx_pci_read(struct ixp4xx_pci *p, u32 addr, u32 cmd, u32 *data)
-+{
-+ unsigned long flags;
-+ int ret;
-+
-+ raw_spin_lock_irqsave(&p->lock, flags);
-+
-+ ixp4xx_writel(p, IXP4XX_PCI_NP_AD, addr);
-+
-+ if (p->errata_hammer) {
-+ int i;
-+
-+ /*
-+ * PCI workaround - only works if NP PCI space reads have
-+ * no side effects. Hammer the register and read twice 8
-+ * times. last one will be good.
-+ */
-+ for (i = 0; i < 8; i++) {
-+ ixp4xx_writel(p, IXP4XX_PCI_NP_CBE, cmd);
-+ *data = ixp4xx_readl(p, IXP4XX_PCI_NP_RDATA);
-+ *data = ixp4xx_readl(p, IXP4XX_PCI_NP_RDATA);
-+ }
-+ } else {
-+ ixp4xx_writel(p, IXP4XX_PCI_NP_CBE, cmd);
-+ *data = ixp4xx_readl(p, IXP4XX_PCI_NP_RDATA);
-+ }
-+
-+ /* Check for master abort */
-+ ret = ixp4xx_pci_check_master_abort(p);
-+
-+ raw_spin_unlock_irqrestore(&p->lock, flags);
-+ return ret;
-+}
-+
-+static int ixp4xx_pci_write(struct ixp4xx_pci *p, u32 addr, u32 cmd, u32 data)
-+{
-+ unsigned long flags;
-+ int ret;
-+
-+ raw_spin_lock_irqsave(&p->lock, flags);
-+
-+ ixp4xx_writel(p, IXP4XX_PCI_NP_AD, addr);
-+
-+ /* Set up the write */
-+ ixp4xx_writel(p, IXP4XX_PCI_NP_CBE, cmd);
-+
-+ /* Execute the write by writing to NP_WDATA */
-+ ixp4xx_writel(p, IXP4XX_PCI_NP_WDATA, data);
-+
-+ /* Check for master abort */
-+ ret = ixp4xx_pci_check_master_abort(p);
-+
-+ raw_spin_unlock_irqrestore(&p->lock, flags);
-+ return ret;
-+}
-+
-+static u32 ixp4xx_config_addr(u8 bus_num, u16 devfn, int where)
-+{
-+ u32 addr;
-+
-+ if (!bus_num) {
-+ /* type 0 */
-+ addr = BIT(32-PCI_SLOT(devfn)) | ((PCI_FUNC(devfn)) << 8) |
-+ (where & ~3);
-+ } else {
-+ /* type 1 */
-+ addr = (bus_num << 16) | ((PCI_SLOT(devfn)) << 11) |
-+ ((PCI_FUNC(devfn)) << 8) | (where & ~3) | 1;
-+ }
-+ return addr;
-+}
-+
-+/*
-+ * CRP functions are "Controller Configuration Port" accesses
-+ * initiated from within this driver itself to read/write PCI
-+ * control information in the config space.
-+ */
-+static u32 ixp4xx_crp_byte_lane_enable_bits(u32 n, int size)
-+{
-+ if (size == 1)
-+ return (0xf & ~BIT(n)) << CRP_AD_CBE_BESL;
-+ if (size == 2)
-+ return (0xf & ~(BIT(n) | BIT(n+1))) << CRP_AD_CBE_BESL;
-+ if (size == 4)
-+ return 0;
-+ return 0xffffffff;
-+}
-+
-+static int ixp4xx_crp_read_config(struct ixp4xx_pci *p, int where, int size,
-+ u32 *value)
-+{
-+ unsigned long flags;
-+ u32 n, cmd, val;
-+
-+ n = where % 4;
-+ cmd = where & ~3;
-+
-+ dev_dbg(p->dev, "%s from %d size %d cmd %08x\n",
-+ __func__, where, size, cmd);
-+
-+ raw_spin_lock_irqsave(&p->lock, flags);
-+ ixp4xx_writel(p, IXP4XX_PCI_CRP_AD_CBE, cmd);
-+ val = ixp4xx_readl(p, IXP4XX_PCI_CRP_RDATA);
-+ raw_spin_unlock_irqrestore(&p->lock, flags);
-+
-+ val >>= (8*n);
-+ switch (size) {
-+ case 1:
-+ val &= U8_MAX;
-+ dev_dbg(p->dev, "%s read byte %02x\n", __func__, val);
-+ break;
-+ case 2:
-+ val &= U16_MAX;
-+ dev_dbg(p->dev, "%s read word %04x\n", __func__, val);
-+ break;
-+ case 4:
-+ val &= U32_MAX;
-+ dev_dbg(p->dev, "%s read long %08x\n", __func__, val);
-+ break;
-+ default:
-+ /* Should not happen */
-+ dev_err(p->dev, "%s illegal size\n", __func__);
-+ return PCIBIOS_DEVICE_NOT_FOUND;
-+ }
-+ *value = val;
-+
-+ return PCIBIOS_SUCCESSFUL;
-+}
-+
-+static int ixp4xx_crp_write_config(struct ixp4xx_pci *p, int where, int size,
-+ u32 value)
-+{
-+ unsigned long flags;
-+ u32 n, cmd, val;
-+
-+ n = where % 4;
-+ cmd = ixp4xx_crp_byte_lane_enable_bits(n, size);
-+ if (cmd == 0xffffffff)
-+ return PCIBIOS_BAD_REGISTER_NUMBER;
-+ cmd |= where & ~3;
-+ cmd |= CRP_AD_CBE_WRITE;
-+
-+ val = value << (8*n);
-+
-+ dev_dbg(p->dev, "%s to %d size %d cmd %08x val %08x\n",
-+ __func__, where, size, cmd, val);
-+
-+ raw_spin_lock_irqsave(&p->lock, flags);
-+ ixp4xx_writel(p, IXP4XX_PCI_CRP_AD_CBE, cmd);
-+ ixp4xx_writel(p, IXP4XX_PCI_CRP_WDATA, val);
-+ raw_spin_unlock_irqrestore(&p->lock, flags);
-+
-+ return PCIBIOS_SUCCESSFUL;
-+}
-+
-+/*
-+ * Then follows the functions that read and write from the common
-+ * PCI configuration space.
-+ */
-+
-+static u32 ixp4xx_byte_lane_enable_bits(u32 n, int size)
-+{
-+ if (size == 1)
-+ return (0xf & ~BIT(n)) << 4;
-+ if (size == 2)
-+ return (0xf & ~(BIT(n) | BIT(n+1))) << 4;
-+ if (size == 4)
-+ return 0;
-+ return 0xffffffff;
-+}
-+
-+static int ixp4xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
-+ int where, int size, u32 *value)
-+{
-+ struct ixp4xx_pci *p = bus->sysdata;
-+ u32 n, addr, val, cmd;
-+ u8 bus_num = bus->number;
-+ int ret;
-+
-+ *value = 0xffffffff;
-+ n = where % 4;
-+ cmd = ixp4xx_byte_lane_enable_bits(n, size);
-+ if (cmd == 0xffffffff)
-+ return PCIBIOS_BAD_REGISTER_NUMBER;
-+
-+ addr = ixp4xx_config_addr(bus_num, devfn, where);
-+ cmd |= NP_CMD_CONFIGREAD;
-+ dev_dbg(p->dev, "read_config from %d size %d dev %d:%d:%d address: %08x cmd: %08x\n",
-+ where, size, bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn), addr, cmd);
-+
-+ ret = ixp4xx_pci_read(p, addr, cmd, &val);
-+ if (ret)
-+ return PCIBIOS_DEVICE_NOT_FOUND;
-+
-+ val >>= (8*n);
-+ switch (size) {
-+ case 1:
-+ val &= U8_MAX;
-+ dev_dbg(p->dev, "%s read byte %02x\n", __func__, val);
-+ break;
-+ case 2:
-+ val &= U16_MAX;
-+ dev_dbg(p->dev, "%s read word %04x\n", __func__, val);
-+ break;
-+ case 4:
-+ val &= U32_MAX;
-+ dev_dbg(p->dev, "%s read long %08x\n", __func__, val);
-+ break;
-+ default:
-+ /* Should not happen */
-+ dev_err(p->dev, "%s illegal size\n", __func__);
-+ return PCIBIOS_DEVICE_NOT_FOUND;
-+ }
-+ *value = val;
-+
-+ return PCIBIOS_SUCCESSFUL;
-+}
-+
-+static int ixp4xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
-+ int where, int size, u32 value)
-+{
-+ struct ixp4xx_pci *p = bus->sysdata;
-+ u32 n, addr, val, cmd;
-+ u8 bus_num = bus->number;
-+ int ret;
-+
-+ n = where % 4;
-+ cmd = ixp4xx_byte_lane_enable_bits(n, size);
-+ if (cmd == 0xffffffff)
-+ return PCIBIOS_BAD_REGISTER_NUMBER;
-+
-+ addr = ixp4xx_config_addr(bus_num, devfn, where);
-+ cmd |= NP_CMD_CONFIGWRITE;
-+ val = value << (8*n);
-+
-+ dev_dbg(p->dev, "write_config_byte %#x to %d size %d dev %d:%d:%d addr: %08x cmd %08x\n",
-+ value, where, size, bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn), addr, cmd);
-+
-+ ret = ixp4xx_pci_write(p, addr, cmd, val);
-+ if (ret)
-+ return PCIBIOS_DEVICE_NOT_FOUND;
-+
-+ return PCIBIOS_SUCCESSFUL;
-+}
-+
-+static struct pci_ops ixp4xx_pci_ops = {
-+ .read = ixp4xx_pci_read_config,
-+ .write = ixp4xx_pci_write_config,
-+};
-+
-+static u32 ixp4xx_pci_addr_to_64mconf(phys_addr_t addr)
-+{
-+ u8 base;
-+
-+ base = ((addr & 0xff000000) >> 24);
-+ return (base << 24) | ((base + 1) << 16)
-+ | ((base + 2) << 8) | (base + 3);
-+}
-+
-+static int ixp4xx_pci_parse_map_ranges(struct ixp4xx_pci *p)
-+{
-+ struct device *dev = p->dev;
-+ struct pci_host_bridge *bridge = pci_host_bridge_from_priv(p);
-+ struct resource_entry *win;
-+ struct resource *res;
-+ phys_addr_t addr;
-+
-+ win = resource_list_first_type(&bridge->windows, IORESOURCE_MEM);
-+ if (win) {
-+ u32 pcimembase;
-+
-+ res = win->res;
-+ addr = res->start - win->offset;
-+
-+ if (res->flags & IORESOURCE_PREFETCH)
-+ res->name = "IXP4xx PCI PRE-MEM";
-+ else
-+ res->name = "IXP4xx PCI NON-PRE-MEM";
-+
-+ dev_dbg(dev, "%s window %pR, bus addr %pa\n",
-+ res->name, res, &addr);
-+ if (resource_size(res) != SZ_64M) {
-+ dev_err(dev, "memory range is not 64MB\n");
-+ return -EINVAL;
-+ }
-+
-+ pcimembase = ixp4xx_pci_addr_to_64mconf(addr);
-+ /* Commit configuration */
-+ ixp4xx_writel(p, IXP4XX_PCI_PCIMEMBASE, pcimembase);
-+ } else {
-+ dev_err(dev, "no AHB memory mapping defined\n");
-+ }
-+
-+ win = resource_list_first_type(&bridge->windows, IORESOURCE_IO);
-+ if (win) {
-+ res = win->res;
-+
-+ addr = pci_pio_to_address(res->start);
-+ if (addr & 0xff) {
-+ dev_err(dev, "IO mem at uneven address: %pa\n", &addr);
-+ return -EINVAL;
-+ }
-+
-+ res->name = "IXP4xx PCI IO MEM";
-+ /*
-+ * Setup I/O space location for PCI->AHB access, the
-+ * upper 24 bits of the address goes into the lower
-+ * 24 bits of this register.
-+ */
-+ ixp4xx_writel(p, IXP4XX_PCI_AHBIOBASE, (addr >> 8));
-+ } else {
-+ dev_info(dev, "no IO space AHB memory mapping defined\n");
-+ }
-+
-+ return 0;
-+}
-+
-+static int ixp4xx_pci_parse_map_dma_ranges(struct ixp4xx_pci *p)
-+{
-+ struct device *dev = p->dev;
-+ struct pci_host_bridge *bridge = pci_host_bridge_from_priv(p);
-+ struct resource_entry *win;
-+ struct resource *res;
-+ phys_addr_t addr;
-+ u32 ahbmembase;
-+
-+ win = resource_list_first_type(&bridge->dma_ranges, IORESOURCE_MEM);
-+ if (win) {
-+ res = win->res;
-+ addr = res->start - win->offset;
-+
-+ if (resource_size(res) != SZ_64M) {
-+ dev_err(dev, "DMA memory range is not 64MB\n");
-+ return -EINVAL;
-+ }
-+
-+ dev_dbg(dev, "DMA MEM BASE: %pa\n", &addr);
-+ /*
-+ * 4 PCI-to-AHB windows of 16 MB each, write the 8 high bits
-+ * into each byte of the PCI_AHBMEMBASE register.
-+ */
-+ ahbmembase = ixp4xx_pci_addr_to_64mconf(addr);
-+ /* Commit AHB membase */
-+ ixp4xx_writel(p, IXP4XX_PCI_AHBMEMBASE, ahbmembase);
-+ } else {
-+ dev_err(dev, "no DMA memory range defined\n");
-+ }
-+
-+ return 0;
-+}
-+
-+/* Only used to get context for abort handling */
-+static struct ixp4xx_pci *ixp4xx_pci_abort_singleton;
-+
-+static int ixp4xx_pci_abort_handler(unsigned long addr, unsigned int fsr,
-+ struct pt_regs *regs)
-+{
-+ struct ixp4xx_pci *p = ixp4xx_pci_abort_singleton;
-+ u32 isr, status;
-+ int ret;
-+
-+ isr = ixp4xx_readl(p, IXP4XX_PCI_ISR);
-+ ret = ixp4xx_crp_read_config(p, PCI_STATUS, 2, &status);
-+ if (ret) {
-+ dev_err(p->dev, "unable to read abort status\n");
-+ return -EINVAL;
-+ }
-+
-+ dev_err(p->dev,
-+ "PCI: abort_handler addr = %#lx, isr = %#x, status = %#x\n",
-+ addr, isr, status);
-+
-+ /* Make sure the Master Abort bit is reset */
-+ ixp4xx_writel(p, IXP4XX_PCI_ISR, IXP4XX_PCI_ISR_PFE);
-+ status |= PCI_STATUS_REC_MASTER_ABORT;
-+ ret = ixp4xx_crp_write_config(p, PCI_STATUS, 2, status);
-+ if (ret)
-+ dev_err(p->dev, "unable to clear abort status bit\n");
-+
-+ /*
-+ * If it was an imprecise abort, then we need to correct the
-+ * return address to be _after_ the instruction.
-+ */
-+ if (fsr & (1 << 10)) {
-+ dev_err(p->dev, "imprecise abort\n");
-+ regs->ARM_pc += 4;
-+ }
-+
-+ return 0;
-+}
-+
-+static int __init ixp4xx_pci_probe(struct platform_device *pdev)
-+{
-+ struct device *dev = &pdev->dev;
-+ struct device_node *np = dev->of_node;
-+ struct ixp4xx_pci *p;
-+ struct pci_host_bridge *host;
-+ int ret;
-+ u32 val;
-+ phys_addr_t addr;
-+ u32 basereg[4] = {
-+ PCI_BASE_ADDRESS_0,
-+ PCI_BASE_ADDRESS_1,
-+ PCI_BASE_ADDRESS_2,
-+ PCI_BASE_ADDRESS_3,
-+ };
-+ int i;
-+
-+ host = devm_pci_alloc_host_bridge(dev, sizeof(*p));
-+ if (!host)
-+ return -ENOMEM;
-+
-+ host->ops = &ixp4xx_pci_ops;
-+ p = pci_host_bridge_priv(host);
-+ host->sysdata = p;
-+ p->dev = dev;
-+ raw_spin_lock_init(&p->lock);
-+ dev_set_drvdata(dev, p);
-+
-+ /*
-+ * Set up quirk for erratic behaviour in the 42x variant
-+ * when accessing config space.
-+ */
-+ if (of_device_is_compatible(np, "intel,ixp42x-pci")) {
-+ p->errata_hammer = true;
-+ dev_info(dev, "activate hammering errata\n");
-+ }
-+
-+ p->base = devm_platform_ioremap_resource(pdev, 0);
-+ if (IS_ERR(p->base))
-+ return PTR_ERR(p->base);
-+
-+ val = ixp4xx_readl(p, IXP4XX_PCI_CSR);
-+ p->host_mode = !!(val & IXP4XX_PCI_CSR_HOST);
-+ dev_info(dev, "controller is in %s mode\n",
-+ p->host_mode ? "host" : "option");
-+
-+ /* Hook in our fault handler for PCI errors */
-+ ixp4xx_pci_abort_singleton = p;
-+ hook_fault_code(16+6, ixp4xx_pci_abort_handler, SIGBUS, 0,
-+ "imprecise external abort");
-+
-+ ret = ixp4xx_pci_parse_map_ranges(p);
-+ if (ret)
-+ return ret;
-+
-+ ret = ixp4xx_pci_parse_map_dma_ranges(p);
-+ if (ret)
-+ return ret;
-+
-+ /* This is only configured in host mode */
-+ if (p->host_mode) {
-+ addr = __pa(PAGE_OFFSET);
-+ /* This is a noop (0x00) but explains what is going on */
-+ addr |= PCI_BASE_ADDRESS_SPACE_MEMORY;
-+
-+ for (i = 0; i < 4; i++) {
-+ /* Write this directly into the config space */
-+ ret = ixp4xx_crp_write_config(p, basereg[i], 4, addr);
-+ if (ret)
-+ dev_err(dev, "failed to set up PCI_BASE_ADDRESS_%d\n", i);
-+ else
-+ dev_info(dev, "set PCI_BASE_ADDR_%d to %pa\n", i, &addr);
-+ addr += SZ_16M;
-+ }
-+
-+ /*
-+ * Enable CSR window at 64 MiB to allow PCI masters to continue
-+ * prefetching past the 64 MiB boundary, if all AHB to PCI windows
-+ * are consecutive.
-+ */
-+ ret = ixp4xx_crp_write_config(p, PCI_BASE_ADDRESS_4, 4, addr);
-+ if (ret)
-+ dev_err(dev, "failed to set up PCI_BASE_ADDRESS_4\n");
-+ else
-+ dev_info(dev, "set PCI_BASE_ADDR_4 to %pa\n", &addr);
-+
-+ /*
-+ * Put the IO memory at the very end of physical memory at
-+ * 0xfffffc00. This is when the PCI is trying to access IO
-+ * memory over AHB.
-+ */
-+ addr = 0xfffffc00;
-+ addr |= PCI_BASE_ADDRESS_SPACE_IO;
-+ ret = ixp4xx_crp_write_config(p, PCI_BASE_ADDRESS_5, 4, addr);
-+ if (ret)
-+ dev_err(dev, "failed to set up PCI_BASE_ADDRESS_5\n");
-+ else
-+ dev_info(dev, "set PCI_BASE_ADDR_5 to %pa\n", &addr);
-+
-+ /*
-+ * Retry timeout to 0x80
-+ * Transfer ready timeout to 0xff
-+ */
-+ ret = ixp4xx_crp_write_config(p, IXP4XX_PCI_RTOTTO, 4,
-+ 0x000080ff);
-+ if (ret)
-+ dev_err(dev, "failed to set up TRDY limit\n");
-+ else
-+ dev_info(dev, "set TRDY limit to 0x80ff\n");
-+ }
-+
-+ /* Clear interrupts */
-+ val = IXP4XX_PCI_ISR_PSE | IXP4XX_PCI_ISR_PFE | IXP4XX_PCI_ISR_PPE | IXP4XX_PCI_ISR_AHBE;
-+ ixp4xx_writel(p, IXP4XX_PCI_ISR, val);
-+
-+ /*
-+ * Set Initialize Complete in PCI Control Register: allow IXP4XX to
-+ * respond to PCI configuration cycles. Specify that the AHB bus is
-+ * operating in big endian mode. Set up byte lane swapping between
-+ * little-endian PCI and the big-endian AHB bus.
-+ */
-+ val = IXP4XX_PCI_CSR_IC | IXP4XX_PCI_CSR_ABE;
-+#ifdef __ARMEB__
-+ val |= (IXP4XX_PCI_CSR_PDS | IXP4XX_PCI_CSR_ADS);
-+#endif
-+ ixp4xx_writel(p, IXP4XX_PCI_CSR, val);
-+
-+ ret = ixp4xx_crp_write_config(p, PCI_COMMAND, 2, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
-+ if (ret)
-+ dev_err(dev, "unable to initialize master and command memory\n");
-+ else
-+ dev_info(dev, "initialized as master\n");
-+
-+ pci_host_probe(host);
-+
-+ return 0;
-+}
-+
-+static const struct of_device_id ixp4xx_pci_of_match[] = {
-+ {
-+ .compatible = "intel,ixp42x-pci",
-+ },
-+ {
-+ .compatible = "intel,ixp43x-pci",
-+ },
-+ {},
-+};
-+
-+/*
-+ * This driver needs to be a builtin module with suppressed bind
-+ * attributes since the probe() is initializing a hard exception
-+ * handler and this can only be done from __init-tagged code
-+ * sections. This module cannot be removed and inserted at all.
-+ */
-+static struct platform_driver ixp4xx_pci_driver = {
-+ .driver = {
-+ .name = "ixp4xx-pci",
-+ .suppress_bind_attrs = true,
-+ .of_match_table = of_match_ptr(ixp4xx_pci_of_match),
-+ },
-+};
-+/*
-+ * This is the only way to have an __init tagged probe that does
-+ * not cause link errors.
-+ */
-+builtin_platform_driver_probe(ixp4xx_pci_driver, ixp4xx_pci_probe);
+++ /dev/null
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- Tue, 11 May 2021 00:48:16 -0700 (PDT)
-From: Linus Walleij <linus.walleij@linaro.org>
-To: linux-arm-kernel@lists.infradead.org, Imre Kaloz <kaloz@openwrt.org>,
- Krzysztof Halasa <khalasa@piap.pl>
-Cc: Linus Walleij <linus.walleij@linaro.org>, Zoltan HERPAI <wigyori@uid0.hu>,
- Raylynn Knight <rayknight@me.com>
-Subject: [PATCH] ARM: dts: ixp4xx: Create a proper expansion bus
-Date: Tue, 11 May 2021 09:48:12 +0200
-Message-Id: <20210511074812.686159-1-linus.walleij@linaro.org>
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-
-The IXP4xx expansion bus is 24 bits (256 MB) that is memory
-mapped between 0x50000000-0x5fffffff usin a set of chip
-selects. The size of the windows is 16 or 32MB defined by
-the boot loader system configuration at runtime.
-
-Create a rudimentary simple-bus and move the flash memories
-to the expansion bus, inside the SoC.
-
-Cc: Zoltan HERPAI <wigyori@uid0.hu>
-Cc: Raylynn Knight <rayknight@me.com>
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- .../boot/dts/intel-ixp42x-linksys-nslu2.dts | 34 +++++++++++--------
- .../dts/intel-ixp43x-gateworks-gw2358.dts | 30 ++++++++--------
- arch/arm/boot/dts/intel-ixp4xx.dtsi | 13 +++++++
- 3 files changed, 49 insertions(+), 28 deletions(-)
-
-diff --git a/arch/arm/boot/dts/intel-ixp4xx.dtsi b/arch/arm/boot/dts/intel-ixp4xx.dtsi
-index 17a712e9d582..2848f8c543af 100644
---- a/arch/arm/boot/dts/intel-ixp4xx.dtsi
-+++ b/arch/arm/boot/dts/intel-ixp4xx.dtsi
-@@ -14,6 +14,19 @@ soc {
- compatible = "simple-bus";
- interrupt-parent = <&intcon>;
-
-+ /*
-+ * The IXP4xx expansion bus is a set of 16 or 32MB
-+ * windows in the 256MB space from 0x50000000 to
-+ * 0x5fffffff.
-+ */
-+ bus@50000000 {
-+ compatible = "simple-bus";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ ranges = <0x00000000 0x50000000 0x10000000>;
-+ dma-ranges = <0x00000000 0x50000000 0x10000000>;
-+ };
-+
- qmgr: queue-manager@60000000 {
- compatible = "intel,ixp4xx-ahb-queue-manager";
- reg = <0x60000000 0x4000>;
+++ /dev/null
-diff -ruN a/arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts b/arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts
-diff -ruN a/arch/arm/boot/dts/intel-ixp4xx.dtsi b/arch/arm/boot/dts/intel-ixp4xx.dtsi
---- a/arch/arm/boot/dts/intel-ixp4xx.dtsi 2021-05-19 16:16:30.448864696 +0200
-+++ b/arch/arm/boot/dts/intel-ixp4xx.dtsi 2021-05-19 14:50:52.447176661 +0200
-@@ -70,6 +70,20 @@
- no-loopback-test;
- };
-
-+ uart1: serial@c8001000 {
-+ compatible = "intel,xscale-uart";
-+ reg = <0xc8001000 0x1000>;
-+ /*
-+ * The reg-offset and reg-shift is a side effect
-+ * of running the platform in big endian mode.
-+ */
-+ reg-offset = <3>;
-+ reg-shift = <2>;
-+ interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
-+ clock-frequency = <14745600>;
-+ no-loopback-test;
-+ };
-+
- gpio0: gpio@c8004000 {
- compatible = "intel,ixp4xx-gpio";
- reg = <0xc8004000 0x1000>;
-diff -ruN a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
+++ /dev/null
-diff -ruN a/arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts b/arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts
---- a/arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts 1970-01-01 01:00:00.000000000 +0100
-+++ b/arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts 2021-05-19 15:37:54.621241935 +0200
-@@ -0,0 +1,152 @@
-+// SPDX-License-Identifier: ISC
-+/*
-+ * Device Tree file for Gateway 7001 AP
-+ * Copyright (c) 2021 Zoltan HERPAI <wigyori@uid0.hu>
-+ */
-+
-+/dts-v1/;
-+
-+#include "intel-ixp42x.dtsi"
-+#include <dt-bindings/input/input.h>
-+
-+/ {
-+ model = "Gateway 7001 AP";
-+ compatible = "gateway,7001", "intel,ixp42x";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ memory@0 {
-+ /* 32 MB SDRAM */
-+ device_type = "memory";
-+ reg = <0x00000000 0x2000000>;
-+ };
-+
-+ chosen {
-+ bootargs = "console=ttyS0,115200n8 root=/dev/mtdblock2 rw rootfstype=squashfs,jffs2 rootwait";
-+ stdout-path = "uart1:115200n8";
-+ };
-+
-+ aliases {
-+ serial0 = &uart1;
-+ };
-+
-+ gpio_keys {
-+ compatible = "gpio-keys";
-+
-+ button-power {
-+ wakeup-source;
-+ linux,code = <KEY_POWER>;
-+ label = "power";
-+ gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
-+ };
-+ button-reset {
-+ wakeup-source;
-+ linux,code = <KEY_ESC>;
-+ label = "reset";
-+ gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
-+ };
-+ };
-+
-+ i2c {
-+ compatible = "i2c-gpio";
-+ sda-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
-+ scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ rtc@6f {
-+ compatible = "xicor,x1205";
-+ reg = <0x6f>;
-+ };
-+ };
-+
-+ gpio-poweroff {
-+ compatible = "gpio-poweroff";
-+ gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
-+ timeout-ms = <5000>;
-+ };
-+
-+ /* The first 16MB region on the expansion bus */
-+ flash@50000000 {
-+ compatible = "intel,ixp4xx-flash", "cfi-flash";
-+ bank-width = <2>;
-+ /*
-+ * 8 MB of Flash in 0x20000 byte blocks
-+ * mapped in at 0x50000000
-+ */
-+ reg = <0x50000000 0x800000>;
-+
-+ partitions {
-+ compatible = "redboot-fis";
-+ /* Eraseblock at 0x7e0000 */
-+ fis-index-block = <0x3f>;
-+ };
-+ };
-+
-+ soc {
-+ pci@c0000000 {
-+ status = "ok";
-+
-+ /*
-+ * Taken from NSLU2 PCI boardfile, INT A, B, C swizzled D constant
-+ * We have slots (IDSEL) 1, 2 and 3.
-+ */
-+ interrupt-map =
-+ /* IDSEL 1 */
-+ <0x0800 0 0 1 &gpio0 11 3>, /* INT A on slot 1 is irq 11 */
-+ <0x0800 0 0 2 &gpio0 10 3>, /* INT B on slot 1 is irq 10 */
-+ <0x0800 0 0 3 &gpio0 9 3>, /* INT C on slot 1 is irq 9 */
-+ <0x0800 0 0 4 &gpio0 8 3>, /* INT D on slot 1 is irq 8 */
-+ /* IDSEL 2 */
-+ <0x1000 0 0 1 &gpio0 10 3>, /* INT A on slot 2 is irq 10 */
-+ <0x1000 0 0 2 &gpio0 9 3>, /* INT B on slot 2 is irq 9 */
-+ <0x1000 0 0 3 &gpio0 11 3>, /* INT C on slot 2 is irq 11 */
-+ <0x1000 0 0 4 &gpio0 8 3>, /* INT D on slot 2 is irq 8 */
-+ /* IDSEL 3 */
-+ <0x1800 0 0 1 &gpio0 9 3>, /* INT A on slot 3 is irq 9 */
-+ <0x1800 0 0 2 &gpio0 11 3>, /* INT B on slot 3 is irq 11 */
-+ <0x1800 0 0 3 &gpio0 10 3>, /* INT C on slot 3 is irq 10 */
-+ <0x1800 0 0 4 &gpio0 8 3>; /* INT D on slot 3 is irq 8 */
-+ };
-+ };
-+
-+ soc {
-+ ethernet@c8009000 {
-+ status = "ok";
-+ queue-rx = <&qmgr 3>;
-+ queue-txready = <&qmgr 20>;
-+ phy-mode = "rgmii";
-+ phy-handle = <&phy1>;
-+
-+ mdio {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ phy1: ethernet-phy@1 {
-+ reg = <1>;
-+ };
-+ };
-+ };
-+
-+ ethernet@c800a000 {
-+ status = "ok";
-+ queue-rx = <&qmgr 4>;
-+ queue-txready = <&qmgr 21>;
-+ phy-mode = "rgmii";
-+ phy-handle = <&phy2>;
-+
-+ mdio {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ phy2: ethernet-phy@2 {
-+ reg = <2>;
-+ };
-+ };
-+ };
-+ };
-+};
-+
-+&uart0 {
-+ status = "disabled";
-+};
-diff -ruN a/arch/arm/boot/dts/intel-ixp4xx.dtsi b/arch/arm/boot/dts/intel-ixp4xx.dtsi
-diff -ruN a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
---- a/arch/arm/boot/dts/Makefile 2021-05-17 13:36:56.001312909 +0200
-+++ b/arch/arm/boot/dts/Makefile 2021-05-17 13:36:14.141559230 +0200
-@@ -244,6 +244,7 @@
- integratorap-im-pd1.dtb \
- integratorcp.dtb
- dtb-$(CONFIG_ARCH_IXP4XX) += \
-+ intel-ixp42x-gateway-7001.dtb \
- intel-ixp42x-linksys-nslu2.dtb \
- intel-ixp43x-gateworks-gw2358.dtb
- dtb-$(CONFIG_ARCH_KEYSTONE) += \
+++ /dev/null
-diff -ruN a/arch/arm/boot/dts/intel-ixp42x-adi-pronghorn-metro.dts b/arch/arm/boot/dts/intel-ixp42x-adi-pronghorn-metro.dts
---- a/arch/arm/boot/dts/intel-ixp42x-adi-pronghorn-metro.dts 1970-01-01 01:00:00.000000000 +0100
-+++ b/arch/arm/boot/dts/intel-ixp42x-adi-pronghorn-metro.dts 2021-05-17 17:33:40.427244073 +0200
-@@ -0,0 +1,175 @@
-+// SPDX-License-Identifier: ISC
-+/*
-+ * Device Tree file for ADI Engineering Pronghorn Metro
-+ * Copyright (c) 2021 Zoltan HERPAI <wigyori@uid0.hu>
-+ */
-+
-+/dts-v1/;
-+
-+#include "intel-ixp42x.dtsi"
-+#include <dt-bindings/input/input.h>
-+
-+/ {
-+ model = "ADI Engineering Pronghorn Metro";
-+ compatible = "adi,pronghornmetro", "intel,ixp42x";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ memory@0 {
-+ /* 64 MB SDRAM */
-+ device_type = "memory";
-+ reg = <0x00000000 0x4000000>;
-+ };
-+
-+ chosen {
-+ bootargs = "console=ttyS0,115200n8 root=/dev/mtdblock2 rw rootfstype=squashfs,jffs2 rootwait";
-+ stdout-path = "uart1:115200n8";
-+ };
-+
-+ aliases {
-+ serial0 = &uart1;
-+ serial1 = &uart0;
-+ };
-+
-+ leds {
-+ compatible = "gpio-leds";
-+ led-status {
-+ label = "nslu2:red:status";
-+ gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
-+ default-state = "on";
-+ linux,default-trigger = "heartbeat";
-+ };
-+ led-ready {
-+ label = "nslu2:green:ready";
-+ gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
-+ default-state = "on";
-+ };
-+ led-disk-1 {
-+ label = "nslu2:green:disk-1";
-+ gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
-+ default-state = "off";
-+ };
-+ led-disk-2 {
-+ label = "nslu2:green:disk-2";
-+ gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
-+ default-state = "off";
-+ };
-+ };
-+
-+ gpio_keys {
-+ compatible = "gpio-keys";
-+
-+ button-power {
-+ wakeup-source;
-+ linux,code = <KEY_POWER>;
-+ label = "power";
-+ gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
-+ };
-+ button-reset {
-+ wakeup-source;
-+ linux,code = <KEY_ESC>;
-+ label = "reset";
-+ gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
-+ };
-+ };
-+
-+ i2c {
-+ compatible = "i2c-gpio";
-+ sda-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
-+ scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ rtc@6f {
-+ compatible = "xicor,x1205";
-+ reg = <0x6f>;
-+ };
-+ };
-+
-+ gpio-poweroff {
-+ compatible = "gpio-poweroff";
-+ gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
-+ timeout-ms = <5000>;
-+ };
-+
-+ /* The first 16MB region on the expansion bus */
-+ flash@50000000 {
-+ compatible = "intel,ixp4xx-flash", "cfi-flash";
-+ bank-width = <2>;
-+ /*
-+ * 8 MB of Flash in 0x20000 byte blocks
-+ * mapped in at 0x50000000
-+ */
-+ reg = <0x50000000 0x800000>;
-+
-+ partitions {
-+ compatible = "redboot-fis";
-+ /* Eraseblock at 0x7e0000 */
-+ fis-index-block = <0x3f>;
-+ };
-+ };
-+
-+ soc {
-+ pci@c0000000 {
-+ status = "ok";
-+
-+ /*
-+ * Taken from NSLU2 PCI boardfile, INT A, B, C swizzled D constant
-+ * We have slots (IDSEL) 1, 2 and 3.
-+ */
-+ interrupt-map =
-+ /* IDSEL 1 */
-+ <0x0800 0 0 1 &gpio0 11 3>, /* INT A on slot 1 is irq 11 */
-+ <0x0800 0 0 2 &gpio0 10 3>, /* INT B on slot 1 is irq 10 */
-+ <0x0800 0 0 3 &gpio0 9 3>, /* INT C on slot 1 is irq 9 */
-+ <0x0800 0 0 4 &gpio0 8 3>, /* INT D on slot 1 is irq 8 */
-+ /* IDSEL 2 */
-+ <0x1000 0 0 1 &gpio0 10 3>, /* INT A on slot 2 is irq 10 */
-+ <0x1000 0 0 2 &gpio0 9 3>, /* INT B on slot 2 is irq 9 */
-+ <0x1000 0 0 3 &gpio0 11 3>, /* INT C on slot 2 is irq 11 */
-+ <0x1000 0 0 4 &gpio0 8 3>, /* INT D on slot 2 is irq 8 */
-+ /* IDSEL 3 */
-+ <0x1800 0 0 1 &gpio0 9 3>, /* INT A on slot 3 is irq 9 */
-+ <0x1800 0 0 2 &gpio0 11 3>, /* INT B on slot 3 is irq 11 */
-+ <0x1800 0 0 3 &gpio0 10 3>, /* INT C on slot 3 is irq 10 */
-+ <0x1800 0 0 4 &gpio0 8 3>; /* INT D on slot 3 is irq 8 */
-+ };
-+ };
-+
-+ soc {
-+ ethernet@c8009000 {
-+ status = "ok";
-+ queue-rx = <&qmgr 3>;
-+ queue-txready = <&qmgr 20>;
-+ phy-mode = "rgmii";
-+ phy-handle = <&phy1>;
-+
-+ mdio {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ phy1: ethernet-phy@1 {
-+ reg = <1>;
-+ };
-+ };
-+ };
-+
-+ ethernet@c800a000 {
-+ status = "ok";
-+ queue-rx = <&qmgr 4>;
-+ queue-txready = <&qmgr 21>;
-+ phy-mode = "rgmii";
-+ phy-handle = <&phy2>;
-+
-+ mdio {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ phy2: ethernet-phy@2 {
-+ reg = <2>;
-+ };
-+ };
-+ };
-+
-+ };
-+};
-diff -ruN a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
---- a/arch/arm/boot/dts/Makefile 2021-05-17 17:34:23.627055651 +0200
-+++ b/arch/arm/boot/dts/Makefile 2021-05-17 17:33:51.703194925 +0200
-@@ -244,6 +244,7 @@
- integratorap-im-pd1.dtb \
- integratorcp.dtb
- dtb-$(CONFIG_ARCH_IXP4XX) += \
-+ intel-ixp42x-adi-pronghorn-metro.dtb \
- intel-ixp42x-gateway-7001.dtb \
- intel-ixp42x-linksys-nslu2.dtb \
- intel-ixp43x-gateworks-gw2358.dtb
+++ /dev/null
-diff -ruN a/arch/arm/boot/dts/intel-ixp42x-titanwireless-tw2662.dts b/arch/arm/boot/dts/intel-ixp42x-titanwireless-tw2662.dts
---- a/arch/arm/boot/dts/intel-ixp42x-titanwireless-tw2662.dts 1970-01-01 01:00:00.000000000 +0100
-+++ b/arch/arm/boot/dts/intel-ixp42x-titanwireless-tw2662.dts 2021-05-20 23:48:13.602479932 +0200
-@@ -0,0 +1,101 @@
-+// SPDX-License-Identifier: ISC
-+/*
-+ * Device Tree file for Titan Wireless TW266-2
-+ * Copyright (c) 2021 Zoltan HERPAI <wigyori@uid0.hu>
-+ */
-+
-+/dts-v1/;
-+
-+#include "intel-ixp42x.dtsi"
-+#include <dt-bindings/input/input.h>
-+
-+/ {
-+ model = "Titan Wireless 266-2";
-+ compatible = "titanwireless,tw266", "intel,ixp42x";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ memory@0 {
-+ /* 64 MB SDRAM */
-+ device_type = "memory";
-+ reg = <0x00000000 0x4000000>;
-+ };
-+
-+ chosen {
-+ /* mem=64M taken from the tw2662-setup.c boardfile */
-+ bootargs = "console=ttyS0,115200n8";
-+ stdout-path = "uart0:115200n8";
-+ };
-+
-+/* i2c {
-+ compatible = "i2c-gpio";
-+ sda-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
-+ scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+*/
-+ aliases {
-+ serial0 = &uart0;
-+ };
-+
-+ soc {
-+ bus@50000000 {
-+ /* The first 16MB region at CS0 on the expansion bus */
-+ flash@0 {
-+ compatible = "intel,ixp4xx-flash", "cfi-flash";
-+ bank-width = <2>;
-+ /*
-+ * 16 MB of Flash in 0x20000 byte blocks
-+ * mapped in at CS0.
-+ */
-+ reg = <0x00000000 0x1000000>;
-+
-+ partitions {
-+ compatible = "redboot-fis";
-+ /* Eraseblock at 0x7e0000 */
-+ fis-index-block = <0x7f>;
-+ };
-+ };
-+ };
-+
-+ pci@c0000000 {
-+ status = "ok";
-+
-+ interrupt-map =
-+ /* IDSEL 1 */
-+ <0x0800 0 0 1 &gpio0 11 3>, /* INT A on slot 1 is irq 11 */
-+ /* IDSEL 3 */
-+ <0x1800 0 0 1 &gpio0 9 3>; /* INT A on slot 3 is irq 9 */
-+ };
-+
-+ ethernet@c8009000 {
-+ status = "ok";
-+ queue-rx = <&qmgr 3>;
-+ queue-txready = <&qmgr 20>;
-+ phy-mode = "rgmii";
-+ phy-handle = <&phy3>;
-+
-+ mdio {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ phy1: ethernet-phy@1 {
-+ reg = <1>;
-+ };
-+
-+ phy3: ethernet-phy@3 {
-+ reg = <3>;
-+ };
-+ };
-+ };
-+
-+ ethernet@c800a000 {
-+ status = "ok";
-+ queue-rx = <&qmgr 4>;
-+ queue-txready = <&qmgr 21>;
-+ phy-mode = "rgmii";
-+ phy-handle = <&phy1>;
-+ };
-+ };
-+};
-diff -ruN a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
---- a/arch/arm/boot/dts/Makefile 2021-05-19 17:41:15.911243339 +0200
-+++ b/arch/arm/boot/dts/Makefile 2021-05-20 17:27:15.111961454 +0200
-@@ -247,6 +247,7 @@
- intel-ixp42x-adi-pronghorn-metro.dtb \
- intel-ixp42x-gateway-7001.dtb \
- intel-ixp42x-linksys-nslu2.dtb \
-+ intel-ixp42x-titanwireless-tw2662.dtb \
- intel-ixp43x-gateworks-gw2358.dtb
- dtb-$(CONFIG_ARCH_KEYSTONE) += \
- keystone-k2hk-evm.dtb \
+++ /dev/null
---- a/net/core/skbuff.c
-+++ b/net/core/skbuff.c
-@@ -215,6 +215,9 @@ struct sk_buff *__alloc_skb(unsigned int
-
- if (sk_memalloc_socks() && (flags & SKB_ALLOC_RX))
- gfp_mask |= __GFP_MEMALLOC;
-+#ifdef CONFIG_ARCH_IXP4XX
-+ gfp_mask |= GFP_DMA;
-+#endif
-
- /* Get the HEAD */
- skb = kmem_cache_alloc_node(cache, gfp_mask & ~__GFP_DMA, node);
-@@ -1223,6 +1226,10 @@ int pskb_expand_head(struct sk_buff *skb
- if (skb_shared(skb))
- BUG();
-
-+#ifdef CONFIG_ARCH_IXP4XX
-+ gfp_mask |= GFP_DMA;
-+#endif
-+
- size = SKB_DATA_ALIGN(size);
-
- if (skb_pfmemalloc(skb))
+++ /dev/null
-diff -ruN a/scripts/Makefile b/scripts/Makefile
---- a/scripts/Makefile 2021-05-21 17:43:33.989097196 +0200
-+++ b/scripts/Makefile 2021-05-21 11:41:14.174017561 +0200
-@@ -20,7 +20,7 @@
- HOSTCFLAGS_sign-file.o = $(CRYPTO_CFLAGS)
- HOSTLDLIBS_sign-file = $(CRYPTO_LIBS)
- HOSTCFLAGS_extract-cert.o = $(CRYPTO_CFLAGS)
--HOSTLDLIBS_extract-cert = $(CRYPTO_LIBS)
-+HOSTLDLIBS_extract-cert = $(CRYPTO_LIBS) -lpthread
-
- ifdef CONFIG_UNWINDER_ORC
- ifeq ($(ARCH),x86_64)
--- /dev/null
+From 7a4d10a17c7a080cd46f782f4318492af32ad972 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Sun, 1 Aug 2021 01:46:40 +0200
+Subject: [PATCH 1/2] ARM: dts: Add PTP timesource to the IXP456x
+
+This adds the PTP timesource to the IXP45x and IXP46x
+platforms.
+
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ arch/arm/boot/dts/intel-ixp45x-ixp46x.dtsi | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/arch/arm/boot/dts/intel-ixp45x-ixp46x.dtsi b/arch/arm/boot/dts/intel-ixp45x-ixp46x.dtsi
+index b6ff614dadc6..1dd4a65cb7a6 100644
+--- a/arch/arm/boot/dts/intel-ixp45x-ixp46x.dtsi
++++ b/arch/arm/boot/dts/intel-ixp45x-ixp46x.dtsi
+@@ -74,5 +74,13 @@
+ queue-rx = <&qmgr 0>;
+ queue-txready = <&qmgr 0>;
+ };
++
++ ptp-timer@c8010000 {
++ compatible = "intel,ixp46x-ptp-timer";
++ reg = <0xc8010000 0x1000>;
++ interrupt-parent = <&gpio0>;
++ interrupts = <8 IRQ_TYPE_EDGE_FALLING>, <7 IRQ_TYPE_EDGE_FALLING>;
++ interrupt-names = "master", "slave";
++ };
+ };
+ };
+--
+2.20.1
+
--- /dev/null
+From 3e70cee46cbcdf3dc5b89c525a4632f051f8abd9 Mon Sep 17 00:00:00 2001
+From: Rob Herring <robh@kernel.org>
+Date: Tue, 28 Sep 2021 14:21:22 -0500
+Subject: [PATCH 2/2] ARM: dts: ixp4xx: Group PCI interrupt properties together
+
+Move the PCI 'interrupt-map-mask' and '#interrupt-cells' properties
+alongside the 'interrupt-map' property in each board dts. This avoids
+having incomplete set of interrupt properties which may fail validation.
+
+Cc: Linus Walleij <linus.walleij@linaro.org>
+Signed-off-by: Rob Herring <robh@kernel.org>
+---
+ arch/arm/boot/dts/intel-ixp42x-adi-coyote.dts | 2 ++
+ arch/arm/boot/dts/intel-ixp42x-arcom-vulcan.dts | 2 ++
+ arch/arm/boot/dts/intel-ixp42x-dlink-dsm-g600.dts | 2 ++
+ arch/arm/boot/dts/intel-ixp42x-freecom-fsg-3.dts | 2 ++
+ arch/arm/boot/dts/intel-ixp42x-gateworks-gw2348.dts | 2 ++
+ arch/arm/boot/dts/intel-ixp42x-iomega-nas100d.dts | 2 ++
+ arch/arm/boot/dts/intel-ixp42x-ixdpg425.dts | 2 ++
+ arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts | 2 ++
+ arch/arm/boot/dts/intel-ixp42x-linksys-wrv54g.dts | 2 ++
+ arch/arm/boot/dts/intel-ixp42x-netgear-wg302v2.dts | 2 ++
+ arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts | 2 ++
+ arch/arm/boot/dts/intel-ixp4xx-reference-design.dtsi | 2 ++
+ arch/arm/boot/dts/intel-ixp4xx.dtsi | 2 --
+ 13 files changed, 24 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/boot/dts/intel-ixp42x-adi-coyote.dts b/arch/arm/boot/dts/intel-ixp42x-adi-coyote.dts
+index 44c017b78008..bd4230d7dac9 100644
+--- a/arch/arm/boot/dts/intel-ixp42x-adi-coyote.dts
++++ b/arch/arm/boot/dts/intel-ixp42x-adi-coyote.dts
+@@ -63,6 +63,8 @@
+ * We have slots (IDSEL) 1 and 2 with one assigned IRQ
+ * each handling all IRQs.
+ */
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map =
+ /* IDSEL 1 */
+ <0x0800 0 0 1 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 6 */
+diff --git a/arch/arm/boot/dts/intel-ixp42x-arcom-vulcan.dts b/arch/arm/boot/dts/intel-ixp42x-arcom-vulcan.dts
+index 7200126cb3b5..92b987bc3f99 100644
+--- a/arch/arm/boot/dts/intel-ixp42x-arcom-vulcan.dts
++++ b/arch/arm/boot/dts/intel-ixp42x-arcom-vulcan.dts
+@@ -120,6 +120,8 @@
+ * We have 2 slots (IDSEL) 1 and 2 with one dedicated interrupt
+ * per slot. This interrupt is shared (OR:ed) by all four pins.
+ */
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map =
+ /* IDSEL 1 */
+ <0x0800 0 0 1 &gpio0 2 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 2 */
+diff --git a/arch/arm/boot/dts/intel-ixp42x-dlink-dsm-g600.dts b/arch/arm/boot/dts/intel-ixp42x-dlink-dsm-g600.dts
+index 8b32e9f22d81..5ab09fb10dae 100644
+--- a/arch/arm/boot/dts/intel-ixp42x-dlink-dsm-g600.dts
++++ b/arch/arm/boot/dts/intel-ixp42x-dlink-dsm-g600.dts
+@@ -129,6 +129,8 @@
+ * We have slots (IDSEL) 1, 2, 3, 4 and pins 1, 2 and 3.
+ * Only slot 3 have three IRQs.
+ */
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map =
+ /* IDSEL 1 */
+ <0x0800 0 0 1 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT E on slot 1 is irq 7 */
+diff --git a/arch/arm/boot/dts/intel-ixp42x-freecom-fsg-3.dts b/arch/arm/boot/dts/intel-ixp42x-freecom-fsg-3.dts
+index 77e78c6dc2cd..598586fc0862 100644
+--- a/arch/arm/boot/dts/intel-ixp42x-freecom-fsg-3.dts
++++ b/arch/arm/boot/dts/intel-ixp42x-freecom-fsg-3.dts
+@@ -106,6 +106,8 @@
+ * Written based on the FSG-3 PCI boardfile.
+ * We have slots 12, 13 & 14 (IDSEL) with one IRQ each.
+ */
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map =
+ /* IDSEL 12 */
+ <0x6000 0 0 1 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 12 is irq 5 */
+diff --git a/arch/arm/boot/dts/intel-ixp42x-gateworks-gw2348.dts b/arch/arm/boot/dts/intel-ixp42x-gateworks-gw2348.dts
+index a20277ff0420..a5943f51e8c2 100644
+--- a/arch/arm/boot/dts/intel-ixp42x-gateworks-gw2348.dts
++++ b/arch/arm/boot/dts/intel-ixp42x-gateworks-gw2348.dts
+@@ -115,6 +115,8 @@
+ *
+ * We have up to 4 slots (IDSEL) with 4 swizzled IRQs.
+ */
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map =
+ /* IDSEL 1 */
+ <0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
+diff --git a/arch/arm/boot/dts/intel-ixp42x-iomega-nas100d.dts b/arch/arm/boot/dts/intel-ixp42x-iomega-nas100d.dts
+index 8c18d802c849..cbc87b344f6a 100644
+--- a/arch/arm/boot/dts/intel-ixp42x-iomega-nas100d.dts
++++ b/arch/arm/boot/dts/intel-ixp42x-iomega-nas100d.dts
+@@ -115,6 +115,8 @@
+ * Taken from NAS 100D PCI boardfile (nas100d-pci.c)
+ * We have slots (IDSEL) 1, 2 and 3 and pins 1, 2 and 3.
+ */
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map =
+ /* IDSEL 1 */
+ <0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
+diff --git a/arch/arm/boot/dts/intel-ixp42x-ixdpg425.dts b/arch/arm/boot/dts/intel-ixp42x-ixdpg425.dts
+index 002a8705abc9..f17cab12a64b 100644
+--- a/arch/arm/boot/dts/intel-ixp42x-ixdpg425.dts
++++ b/arch/arm/boot/dts/intel-ixp42x-ixdpg425.dts
+@@ -68,6 +68,8 @@
+ * We have slots (IDSEL) 12, 13 and 14 with one assigned IRQ
+ * for 12 & 13 and one for 14.
+ */
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map =
+ /* IDSEL 12 */
+ <0x6000 0 0 1 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 12 is irq 7 */
+diff --git a/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts b/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts
+index e3a32b08d167..0edc5928e00b 100644
+--- a/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts
++++ b/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts
+@@ -122,6 +122,8 @@
+ * Taken from NSLU2 PCI boardfile, INT A, B, C swizzled D constant
+ * We have slots (IDSEL) 1, 2 and 3.
+ */
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map =
+ /* IDSEL 1 */
+ <0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
+diff --git a/arch/arm/boot/dts/intel-ixp42x-linksys-wrv54g.dts b/arch/arm/boot/dts/intel-ixp42x-linksys-wrv54g.dts
+index 6b28dda747fd..5e7e31b74b04 100644
+--- a/arch/arm/boot/dts/intel-ixp42x-linksys-wrv54g.dts
++++ b/arch/arm/boot/dts/intel-ixp42x-linksys-wrv54g.dts
+@@ -123,6 +123,8 @@
+ * We have up to 2 slots (IDSEL) with 2 swizzled IRQs.
+ * Derived from the GTWX5715 PCI boardfile.
+ */
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map =
+ /* IDSEL 0 */
+ <0x0000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 0 is irq 10 */
+diff --git a/arch/arm/boot/dts/intel-ixp42x-netgear-wg302v2.dts b/arch/arm/boot/dts/intel-ixp42x-netgear-wg302v2.dts
+index 04a0f7138967..a57009436ed8 100644
+--- a/arch/arm/boot/dts/intel-ixp42x-netgear-wg302v2.dts
++++ b/arch/arm/boot/dts/intel-ixp42x-netgear-wg302v2.dts
+@@ -62,6 +62,8 @@
+ * We have slots (IDSEL) 1 and 2 with one assigned IRQ
+ * each handling all IRQs.
+ */
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map =
+ /* IDSEL 1 */
+ <0x0800 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 8 */
+diff --git a/arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts b/arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts
+index 84e6aec8e665..cf4010d60187 100644
+--- a/arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts
++++ b/arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts
+@@ -131,6 +131,8 @@
+ * have instead assumed that they are rotated (swizzled) like
+ * this with 11, 10, 9, 8 for the 4 pins on IDSEL 1 etc.
+ */
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map =
+ /* IDSEL 1 */
+ <0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
+diff --git a/arch/arm/boot/dts/intel-ixp4xx-reference-design.dtsi b/arch/arm/boot/dts/intel-ixp4xx-reference-design.dtsi
+index c1d9c49982b3..146352ba848b 100644
+--- a/arch/arm/boot/dts/intel-ixp4xx-reference-design.dtsi
++++ b/arch/arm/boot/dts/intel-ixp4xx-reference-design.dtsi
+@@ -106,6 +106,8 @@
+ * PCI slots on the BIXMB425BD base card.
+ * We have up to 4 slots (IDSEL) with 4 swizzled IRQs.
+ */
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map =
+ /* IDSEL 1 */
+ <0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
+diff --git a/arch/arm/boot/dts/intel-ixp4xx.dtsi b/arch/arm/boot/dts/intel-ixp4xx.dtsi
+index e5af2d463074..46fede021476 100644
+--- a/arch/arm/boot/dts/intel-ixp4xx.dtsi
++++ b/arch/arm/boot/dts/intel-ixp4xx.dtsi
+@@ -78,8 +78,6 @@
+ dma-ranges =
+ <0x02000000 0 0x00000000 0x00000000 0 0x04000000>;
+
+- #interrupt-cells = <1>;
+- interrupt-map-mask = <0xf800 0 0 7>;
+ /* Each unique DTS using PCI must specify the swizzling */
+ };
+
+--
+2.20.1
+
--- /dev/null
+From 65248dde81528d7f6cdd091e397d2d6e0b49dae1 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Thu, 29 Jul 2021 01:34:39 +0200
+Subject: [PATCH 2/3] ARM: dts: Add Goramo MultiLink device tree
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This adds a device tree for the Goramo MultiLink IXP425-based
+WAN router.
+
+Cc: Krzysztof Hałasa <khalasa@piap.pl>
+Cc: openwrt-devel@lists.openwrt.org
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ arch/arm/boot/dts/Makefile | 1 +
+ .../dts/intel-ixp42x-goramo-multilink.dts | 180 ++++++++++++++++++
+ arch/arm/boot/dts/intel-ixp4xx.dtsi | 17 ++
+ 3 files changed, 198 insertions(+)
+ create mode 100644 arch/arm/boot/dts/intel-ixp42x-goramo-multilink.dts
+
+diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
+index 0de64f237cd8..4084535c6489 100644
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -263,6 +263,7 @@ dtb-$(CONFIG_ARCH_IXP4XX) += \
+ intel-ixp46x-ixdp465.dtb \
+ intel-ixp42x-adi-coyote.dtb \
+ intel-ixp42x-ixdpg425.dtb \
++ intel-ixp42x-goramo-multilink.dtb \
+ intel-ixp42x-iomega-nas100d.dtb \
+ intel-ixp42x-dlink-dsm-g600.dtb \
+ intel-ixp42x-gateworks-gw2348.dtb \
+diff --git a/arch/arm/boot/dts/intel-ixp42x-goramo-multilink.dts b/arch/arm/boot/dts/intel-ixp42x-goramo-multilink.dts
+new file mode 100644
+index 000000000000..f80388b17a9e
+--- /dev/null
++++ b/arch/arm/boot/dts/intel-ixp42x-goramo-multilink.dts
+@@ -0,0 +1,180 @@
++// SPDX-License-Identifier: ISC
++/*
++ * Device Tree file for the Goramo MultiLink Router
++ * There are two variants:
++ * - MultiLink Basic (a box)
++ * - MultiLink Max (19" rack mount)
++ * This device tree supports MultiLink Basic.
++ * This machine is based on IXP425.
++ * This is one of the few devices supporting the IXP4xx High-Speed Serial
++ * (HSS) link for a V.35 WAN interface.
++ * The hardware originates in Poland.
++ */
++
++/dts-v1/;
++
++#include "intel-ixp42x.dtsi"
++#include <dt-bindings/input/input.h>
++
++/ {
++ model = "Goramo MultiLink Router";
++ compatible = "goramo,multilink-router", "intel,ixp42x";
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ memory@0 {
++ /*
++ * 64 MB of RAM according to the manual. The MultiLink
++ * Max has 128 MB.
++ */
++ device_type = "memory";
++ reg = <0x00000000 0x4000000>;
++ };
++
++ chosen {
++ bootargs = "console=ttyS0,115200n8";
++ stdout-path = "uart0:115200n8";
++ };
++
++ aliases {
++ serial0 = &uart0;
++ serial1 = &uart1;
++ };
++
++ /*
++ * 74HC4094 which is used as a rudimentary GPIO expander
++ * FIXME:
++ * - Create device tree bindings for this as GPIO expander
++ * - Write a pure DT GPIO driver using these bindings
++ * - Support cascading in the style of gpio-74x164.c (cannot be reused, very different)
++ */
++ gpio_74: gpio-74hc4094 {
++ compatible = "nxp,74hc4094";
++ cp-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
++ d-gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
++ str-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
++ /* oe-gpios is optional */
++ gpio-controller;
++ #gpio-cells = <2>;
++ /* We are not cascaded */
++ registers-number = <1>;
++ gpio-line-names = "CONTROL_HSS0_CLK_INT", "CONTROL_HSS1_CLK_INT", "CONTROL_HSS0_DTR_N",
++ "CONTROL_HSS1_DTR_N", "CONTROL_EXT", "CONTROL_AUTO_RESET",
++ "CONTROL_PCI_RESET_N", "CONTROL_EEPROM_WC_N";
++ };
++
++ soc {
++ bus@c4000000 {
++ flash@0,0 {
++ compatible = "intel,ixp4xx-flash", "cfi-flash";
++ bank-width = <2>;
++ /* Enable writes on the expansion bus */
++ intel,ixp4xx-eb-write-enable = <1>;
++ /* 16 MB of Flash mapped in at CS0 */
++ reg = <0 0x00000000 0x1000000>;
++
++ partitions {
++ compatible = "redboot-fis";
++ /* Eraseblock at 0x0fe0000 */
++ fis-index-block = <0x7f>;
++ };
++ };
++ };
++
++ pci@c0000000 {
++ status = "ok";
++
++ /*
++ * The device has 4 slots (IDSEL) with one dedicated IRQ per slot.
++ * The slots have Ethernet, Ethernet, NEC and MPCI.
++ * The IDSELs are 11, 12, 13, 14.
++ */
++ interrupt-map =
++ /* IDSEL 11 - Ethernet A */
++ <0x5800 0 0 1 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 11 is irq 4 */
++ <0x5800 0 0 2 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 11 is irq 4 */
++ <0x5800 0 0 3 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 11 is irq 4 */
++ <0x5800 0 0 4 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 11 is irq 4 */
++ /* IDSEL 12 - Ethernet B */
++ <0x6000 0 0 1 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 12 is irq 5 */
++ <0x6000 0 0 2 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 12 is irq 5 */
++ <0x6000 0 0 3 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 12 is irq 5 */
++ <0x6000 0 0 4 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 12 is irq 5 */
++ /* IDSEL 13 - MPCI */
++ <0x6800 0 0 1 &gpio0 12 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 13 is irq 12 */
++ <0x6800 0 0 2 &gpio0 12 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 13 is irq 12 */
++ <0x6800 0 0 3 &gpio0 12 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 13 is irq 12 */
++ <0x6800 0 0 4 &gpio0 12 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 13 is irq 12 */
++ /* IDSEL 14 - NEC */
++ <0x7000 0 0 1 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 14 is irq 3 */
++ <0x7000 0 0 2 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 14 is irq 3 */
++ <0x7000 0 0 3 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 14 is irq 3 */
++ <0x7000 0 0 4 &gpio0 3 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 14 is irq 3 */
++ };
++
++ /* HSS links */
++ npe@c8006000 {
++ hss@0 {
++ status = "okay";
++ intel,queue-chl-rxtrig = <&qmgr 12>;
++ intel,queue-chl-txready = <&qmgr 34>;
++ intel,queue-pkt-rx = <&qmgr 13>;
++ intel,queue-pkt-tx = <&qmgr 14>, <&qmgr 15>, <&qmgr 16>, <&qmgr 17>;
++ intel,queue-pkt-rxfree = <&qmgr 18>, <&qmgr 19>, <&qmgr 20>, <&qmgr 21>;
++ intel,queue-pkt-txdone = <&qmgr 22>;
++ /* The Goramo GPIO-based clock etc control */
++ cts-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
++ rts-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
++ dcd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
++ dtr-gpios = <&gpio_74 2 GPIO_ACTIVE_LOW>;
++ clk-internal-gpios = <&gpio_74 0 GPIO_ACTIVE_HIGH>;
++ };
++ hss@1 {
++ status = "okay";
++ intel,queue-chl-rxtrig = <&qmgr 10>;
++ intel,queue-chl-txready = <&qmgr 35>;
++ intel,queue-pkt-rx = <&qmgr 0>;
++ intel,queue-pkt-tx = <&qmgr 5>, <&qmgr 6>, <&qmgr 7>, <&qmgr 8>;
++ intel,queue-pkt-rxfree = <&qmgr 1>, <&qmgr 2>, <&qmgr 3>, <&qmgr 4>;
++ intel,queue-pkt-txdone = <&qmgr 9>;
++ /* The Goramo GPIO-based clock etc control */
++ cts-gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
++ rts-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
++ dcd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
++ dtr-gpios = <&gpio_74 3 GPIO_ACTIVE_LOW>;
++ clk-internal-gpios = <&gpio_74 1 GPIO_ACTIVE_HIGH>;
++ };
++ };
++
++ /* EthB */
++ ethernet@c8009000 {
++ status = "ok";
++ queue-rx = <&qmgr 3>;
++ queue-txready = <&qmgr 32>;
++ phy-mode = "rgmii";
++ phy-handle = <&phy0>;
++
++ mdio {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ phy0: ethernet-phy@0 {
++ reg = <0>;
++ };
++
++ phy1: ethernet-phy@1 {
++ reg = <1>;
++ };
++ };
++ };
++
++ /* EthC */
++ ethernet@c800a000 {
++ status = "ok";
++ queue-rx = <&qmgr 4>;
++ queue-txready = <&qmgr 33>;
++ phy-mode = "rgmii";
++ phy-handle = <&phy1>;
++ };
++ };
++};
+diff --git a/arch/arm/boot/dts/intel-ixp4xx.dtsi b/arch/arm/boot/dts/intel-ixp4xx.dtsi
+index 46fede021476..51a716c59669 100644
+--- a/arch/arm/boot/dts/intel-ixp4xx.dtsi
++++ b/arch/arm/boot/dts/intel-ixp4xx.dtsi
+@@ -139,6 +139,23 @@
+ npe: npe@c8006000 {
+ compatible = "intel,ixp4xx-network-processing-engine";
+ reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ /* NPE-A contains two high-speed serial links */
++ hss@0 {
++ compatible = "intel,ixp4xx-hss";
++ reg = <0>;
++ intel,npe-handle = <&npe 0>;
++ status = "disabled";
++ };
++
++ hss@1 {
++ compatible = "intel,ixp4xx-hss";
++ reg = <1>;
++ intel,npe-handle = <&npe 0>;
++ status = "disabled";
++ };
+
+ /* NPE-C contains a crypto accelerator */
+ crypto {
+--
+2.20.1
+
--- /dev/null
+From c25b80c560b8a2bb9ca60155553abff6223c73a8 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Mon, 22 Nov 2021 11:22:28 +0100
+Subject: [PATCH 1/3] ARM: dts: Add FSG3 system controller and LEDs
+
+This adds the system controller on CS2 and the LEDs on it.
+
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ .../boot/dts/intel-ixp42x-freecom-fsg-3.dts | 59 +++++++++++++++++++
+ 1 file changed, 59 insertions(+)
+
+diff --git a/arch/arm/boot/dts/intel-ixp42x-freecom-fsg-3.dts b/arch/arm/boot/dts/intel-ixp42x-freecom-fsg-3.dts
+index 598586fc0862..b740403b05a9 100644
+--- a/arch/arm/boot/dts/intel-ixp42x-freecom-fsg-3.dts
++++ b/arch/arm/boot/dts/intel-ixp42x-freecom-fsg-3.dts
+@@ -97,6 +97,65 @@
+ fis-index-block = <0x1f>;
+ };
+ };
++
++ /* Small syscon with some LEDs at CS2 */
++ syscon@2,0 {
++ compatible = "freecom,fsg-cs2-system-controller", "syscon";
++ reg = <2 0x0 0x200>;
++ reg-io-width = <2>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges = <2 0x0 0x0 0x200>;
++
++ led@0,0 {
++ compatible = "register-bit-led";
++ reg = <0x00 0x02>;
++ mask = <0x01>;
++ label = "fsg:blue:wlan";
++ linux,default-trigger = "wlan";
++ default-state = "on";
++ };
++ led@0,1 {
++ compatible = "register-bit-led";
++ reg = <0x00 0x02>;
++ mask = <0x02>;
++ label = "fsg:blue:wan";
++ linux,default-trigger = "";
++ default-state = "on";
++ };
++ led@0,2 {
++ compatible = "register-bit-led";
++ reg = <0x00 0x02>;
++ mask = <0x04>;
++ label = "fsg:blue:sata";
++ linux,default-trigger = "";
++ default-state = "on";
++ };
++ led@0,3 {
++ compatible = "register-bit-led";
++ reg = <0x00 0x02>;
++ mask = <0x04>;
++ label = "fsg:blue:usb";
++ linux,default-trigger = "";
++ default-state = "on";
++ };
++ led@0,4 {
++ compatible = "register-bit-led";
++ reg = <0x00 0x02>;
++ mask = <0x08>;
++ label = "fsg:blue:sync";
++ linux,default-trigger = "";
++ default-state = "on";
++ };
++ led@0,5 {
++ compatible = "register-bit-led";
++ reg = <0x00 0x02>;
++ mask = <0x10>;
++ label = "fsg:blue:ring";
++ linux,default-trigger = "";
++ default-state = "on";
++ };
++ };
+ };
+
+ pci@c0000000 {
+--
+2.20.1
+
--- /dev/null
+From 7b9eb6cfdb784ad713024a3f8f202620ad40ba70 Mon Sep 17 00:00:00 2001
+From: Zoltan HERPAI <wigyori@uid0.hu>
+Date: Sun, 12 Dec 2021 18:49:40 +0100
+Subject: [PATCH 3/3] ARM: dts: ixp4xx: Add devicetree for Gateway 7001
+
+This adds a device tree for the Gateway 7001 AP, based on
+Intel IXP422.
+
+Cc: Imre Kaloz <kaloz@openwrt.org>
+Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ arch/arm/boot/dts/Makefile | 3 +-
+ .../boot/dts/intel-ixp42x-gateway-7001.dts | 111 ++++++++++++++++++
+ 2 files changed, 113 insertions(+), 1 deletion(-)
+ create mode 100644 arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts
+
+diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
+index 4084535c6489..7dfda6be2916 100644
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -269,7 +269,8 @@ dtb-$(CONFIG_ARCH_IXP4XX) += \
+ intel-ixp42x-gateworks-gw2348.dtb \
+ intel-ixp43x-gateworks-gw2358.dtb \
+ intel-ixp42x-netgear-wg302v2.dtb \
+- intel-ixp42x-arcom-vulcan.dtb
++ intel-ixp42x-arcom-vulcan.dtb \
++ intel-ixp42x-gateway-7001.dtb
+ dtb-$(CONFIG_ARCH_KEYSTONE) += \
+ keystone-k2hk-evm.dtb \
+ keystone-k2l-evm.dtb \
+diff --git a/arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts b/arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts
+new file mode 100644
+index 000000000000..a1c03c965f17
+--- /dev/null
++++ b/arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts
+@@ -0,0 +1,111 @@
++// SPDX-License-Identifier: ISC
++/*
++ * Device Tree file for Gateway 7001 AP
++ * Derived from boardfiles written by Imre Kaloz
++ */
++
++/dts-v1/;
++
++#include "intel-ixp42x.dtsi"
++#include <dt-bindings/input/input.h>
++
++/ {
++ model = "Gateway 7001 AP";
++ compatible = "gateway,7001", "intel,ixp42x";
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ memory@0 {
++ /* 32 MB SDRAM */
++ device_type = "memory";
++ reg = <0x00000000 0x2000000>;
++ };
++
++ chosen {
++ bootargs = "console=ttyS0,115200n8";
++ stdout-path = "uart1:115200n8";
++ };
++
++ aliases {
++ /* second UART is the primary console */
++ serial0 = &uart1;
++ serial1 = &uart0;
++ };
++
++ soc {
++ bus@c4000000 {
++ flash@0,0 {
++ compatible = "intel,ixp4xx-flash", "cfi-flash";
++ bank-width = <2>;
++ /*
++ * 8 MB of flash
++ */
++ reg = <0 0x00000000 0x800000>;
++
++ /* Configure expansion bus to allow writes */
++ intel,ixp4xx-eb-write-enable = <1>;
++
++ partitions {
++ compatible = "redboot-fis";
++ /* Eraseblock at 0x7e0000 */
++ fis-index-block = <0x3f>;
++ };
++ };
++ };
++
++ pci@c0000000 {
++ status = "ok";
++
++ /*
++ * Taken from Gateway 7001 PCI boardfile (gateway7001-pci.c)
++ * We have slots (IDSEL) 1 and 2 with one assigned IRQ
++ * each handling all IRQs.
++ */
++ interrupt-map =
++ /* IDSEL 1 */
++ <0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
++ <0x0800 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 11 */
++ <0x0800 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 11 */
++ <0x0800 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 11 */
++ /* IDSEL 2 */
++ <0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */
++ <0x1000 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 10 */
++ <0x1000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 10 */
++ <0x1000 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 10 */
++ };
++
++ ethernet@c8009000 {
++ status = "ok";
++ queue-rx = <&qmgr 3>;
++ queue-txready = <&qmgr 20>;
++ phy-mode = "rgmii";
++ phy-handle = <&phy1>;
++
++ mdio {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ phy1: ethernet-phy@1 {
++ reg = <1>;
++ };
++ };
++ };
++
++ ethernet@c800a000 {
++ status = "ok";
++ queue-rx = <&qmgr 4>;
++ queue-txready = <&qmgr 21>;
++ phy-mode = "rgmii";
++ phy-handle = <&phy2>;
++
++ mdio {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ phy2: ethernet-phy@2 {
++ reg = <2>;
++ };
++ };
++ };
++ };
++};
+--
+2.20.1
+
--- /dev/null
+From 6786e78d6b7a7236df7ded9ae0e09fa1cba950fb Mon Sep 17 00:00:00 2001
+From: Lukas Bulwahn <lukas.bulwahn@gmail.com>
+Date: Thu, 28 Oct 2021 16:19:31 +0200
+Subject: [PATCH 1/2] ARM: ixp4xx: remove dead configs CPU_IXP43X and
+ CPU_IXP46X
+
+Commit 73d04ca5f4ac ("ARM: ixp4xx: Delete Intel reference design
+boardfiles") removes the definition of the configs MACH_IXDP465 and
+MACH_KIXRP435, but misses to remove the configs CPU_IXP43X and CPU_IXP46X
+that depend on those removed configs, and hence are dead now.
+
+Fortunately, ./scripts/checkkconfigsymbols.py warns:
+
+MACH_IXDP465
+Referencing files: arch/arm/mach-ixp4xx/Kconfig
+
+MACH_KIXRP435
+Referencing files: arch/arm/mach-ixp4xx/Kconfig
+
+Remove the dead configs CPU_IXP43X and CPU_IXP46X.
+
+A further quick grep for the name of those two symbols did not show any
+use of the two config symbols; so, there are no further clean-up activities
+beyond this config removal needed.
+
+Signed-off-by: Lukas Bulwahn <lukas.bulwahn@gmail.com>
+Reviewed-by: Arnd Bergmann <arnd@arndb.de>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ arch/arm/mach-ixp4xx/Kconfig | 13 -------------
+ 1 file changed, 13 deletions(-)
+
+diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig
+index 365a5853d310..4c787b4be62b 100644
+--- a/arch/arm/mach-ixp4xx/Kconfig
++++ b/arch/arm/mach-ixp4xx/Kconfig
+@@ -39,19 +39,6 @@ config ARCH_PRPMC1100
+ PrPCM1100 Processor Mezanine Module. For more information on
+ this platform, see <file:Documentation/arm/ixp4xx.rst>.
+
+-#
+-# Certain registers and IRQs are only enabled if supporting IXP465 CPUs
+-#
+-config CPU_IXP46X
+- bool
+- depends on MACH_IXDP465
+- default y
+-
+-config CPU_IXP43X
+- bool
+- depends on MACH_KIXRP435
+- default y
+-
+ comment "IXP4xx Options"
+
+ config IXP4XX_PCI_LEGACY
+--
+2.20.1
+
--- /dev/null
+From 019cd8a9e3bcbbf6bac8036a9ae545f7858e0c08 Mon Sep 17 00:00:00 2001
+From: Jonathan Corbet <corbet@lwn.net>
+Date: Tue, 2 Nov 2021 16:02:01 -0600
+Subject: [PATCH 2/2] ARM: ixp4xx: remove unused header file pata_ixp4xx_cf.h
+
+Commit b00ced38e317 ("ARM: ixp4xx: Delete Avila boardfiles") removed the
+last use of <linux/platform_data/pata_ixp4xx_cf.h> but left the header file
+in place. Nothing uses this file, delete it now.
+
+Cc: Linus Walleij <linus.walleij@linaro.org>
+Cc: Arnd Bergmann <arnd@arndb.de>
+Signed-off-by: Jonathan Corbet <corbet@lwn.net>
+Acked-by: Arnd Bergmann <arnd@arndb.de>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ include/linux/platform_data/pata_ixp4xx_cf.h | 21 --------------------
+ 1 file changed, 21 deletions(-)
+ delete mode 100644 include/linux/platform_data/pata_ixp4xx_cf.h
+
+diff --git a/include/linux/platform_data/pata_ixp4xx_cf.h b/include/linux/platform_data/pata_ixp4xx_cf.h
+deleted file mode 100644
+index e60fa41da4a5..000000000000
+--- a/include/linux/platform_data/pata_ixp4xx_cf.h
++++ /dev/null
+@@ -1,21 +0,0 @@
+-/* SPDX-License-Identifier: GPL-2.0 */
+-#ifndef __PLATFORM_DATA_PATA_IXP4XX_H
+-#define __PLATFORM_DATA_PATA_IXP4XX_H
+-
+-#include <linux/types.h>
+-
+-/*
+- * This structure provide a means for the board setup code
+- * to give information to th pata_ixp4xx driver. It is
+- * passed as platform_data.
+- */
+-struct ixp4xx_pata_data {
+- volatile u32 *cs0_cfg;
+- volatile u32 *cs1_cfg;
+- unsigned long cs0_bits;
+- unsigned long cs1_bits;
+- void __iomem *cmd;
+- void __iomem *ctl;
+-};
+-
+-#endif
+--
+2.20.1
+
--- /dev/null
+From 35aefaad326bb267ef254e64ef65a374bd99c98f Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Mon, 22 Nov 2021 23:35:30 +0100
+Subject: [PATCH] net: ixp4xx_hss: Convert to use DT probing
+
+IXP4xx is being migrated to device tree only. Convert this
+driver to use device tree probing.
+
+Pull in all the boardfile code from the one boardfile and
+make it local, pull all the boardfile parameters from the
+device tree instead of the board file.
+
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/wan/ixp4xx_hss.c | 260 +++++++++++++++++++++++++----------
+ 1 file changed, 185 insertions(+), 75 deletions(-)
+
+diff --git a/drivers/net/wan/ixp4xx_hss.c b/drivers/net/wan/ixp4xx_hss.c
+index 88a36a06931120..d02d8a2eb99dd9 100644
+--- a/drivers/net/wan/ixp4xx_hss.c
++++ b/drivers/net/wan/ixp4xx_hss.c
+@@ -17,13 +17,19 @@
+ #include <linux/io.h>
+ #include <linux/kernel.h>
+ #include <linux/platform_device.h>
+-#include <linux/platform_data/wan_ixp4xx_hss.h>
+ #include <linux/poll.h>
+ #include <linux/slab.h>
++#include <linux/gpio/consumer.h>
++#include <linux/of.h>
+ #include <linux/soc/ixp4xx/npe.h>
+ #include <linux/soc/ixp4xx/qmgr.h>
+ #include <linux/soc/ixp4xx/cpu.h>
+
++/* This is what all IXP4xx platforms we know uses, if more frequencies
++ * are needed, we need to migrate to the clock framework.
++ */
++#define IXP4XX_TIMER_FREQ 66666000
++
+ #define DEBUG_DESC 0
+ #define DEBUG_RX 0
+ #define DEBUG_TX 0
+@@ -50,7 +56,6 @@
+ #define NAPI_WEIGHT 16
+
+ /* Queue IDs */
+-#define HSS0_CHL_RXTRIG_QUEUE 12 /* orig size = 32 dwords */
+ #define HSS0_PKT_RX_QUEUE 13 /* orig size = 32 dwords */
+ #define HSS0_PKT_TX0_QUEUE 14 /* orig size = 16 dwords */
+ #define HSS0_PKT_TX1_QUEUE 15
+@@ -62,7 +67,6 @@
+ #define HSS0_PKT_RXFREE3_QUEUE 21
+ #define HSS0_PKT_TXDONE_QUEUE 22 /* orig size = 64 dwords */
+
+-#define HSS1_CHL_RXTRIG_QUEUE 10
+ #define HSS1_PKT_RX_QUEUE 0
+ #define HSS1_PKT_TX0_QUEUE 5
+ #define HSS1_PKT_TX1_QUEUE 6
+@@ -252,9 +256,19 @@ typedef void buffer_t;
+ struct port {
+ struct device *dev;
+ struct npe *npe;
++ unsigned int txreadyq;
++ unsigned int rxtrigq;
++ unsigned int rxfreeq;
++ unsigned int rxq;
++ unsigned int txq;
++ unsigned int txdoneq;
++ struct gpio_desc *cts;
++ struct gpio_desc *rts;
++ struct gpio_desc *dcd;
++ struct gpio_desc *dtr;
++ struct gpio_desc *clk_internal;
+ struct net_device *netdev;
+ struct napi_struct napi;
+- struct hss_plat_info *plat;
+ buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];
+ struct desc *desc_tab; /* coherent */
+ dma_addr_t desc_tab_phys;
+@@ -322,14 +336,6 @@ static int ports_open;
+ static struct dma_pool *dma_pool;
+ static DEFINE_SPINLOCK(npe_lock);
+
+-static const struct {
+- int tx, txdone, rx, rxfree;
+-} queue_ids[2] = {{HSS0_PKT_TX0_QUEUE, HSS0_PKT_TXDONE_QUEUE, HSS0_PKT_RX_QUEUE,
+- HSS0_PKT_RXFREE0_QUEUE},
+- {HSS1_PKT_TX0_QUEUE, HSS1_PKT_TXDONE_QUEUE, HSS1_PKT_RX_QUEUE,
+- HSS1_PKT_RXFREE0_QUEUE},
+-};
+-
+ /*****************************************************************************
+ * utility functions
+ ****************************************************************************/
+@@ -645,7 +651,7 @@ static void hss_hdlc_rx_irq(void *pdev)
+ #if DEBUG_RX
+ printk(KERN_DEBUG "%s: hss_hdlc_rx_irq\n", dev->name);
+ #endif
+- qmgr_disable_irq(queue_ids[port->id].rx);
++ qmgr_disable_irq(port->rxq);
+ napi_schedule(&port->napi);
+ }
+
+@@ -653,8 +659,8 @@ static int hss_hdlc_poll(struct napi_struct *napi, int budget)
+ {
+ struct port *port = container_of(napi, struct port, napi);
+ struct net_device *dev = port->netdev;
+- unsigned int rxq = queue_ids[port->id].rx;
+- unsigned int rxfreeq = queue_ids[port->id].rxfree;
++ unsigned int rxq = port->rxq;
++ unsigned int rxfreeq = port->rxfreeq;
+ int received = 0;
+
+ #if DEBUG_RX
+@@ -795,7 +801,7 @@ static void hss_hdlc_txdone_irq(void *pdev)
+ #if DEBUG_TX
+ printk(KERN_DEBUG DRV_NAME ": hss_hdlc_txdone_irq\n");
+ #endif
+- while ((n_desc = queue_get_desc(queue_ids[port->id].txdone,
++ while ((n_desc = queue_get_desc(port->txdoneq,
+ port, 1)) >= 0) {
+ struct desc *desc;
+ int start;
+@@ -813,8 +819,8 @@ static void hss_hdlc_txdone_irq(void *pdev)
+ free_buffer_irq(port->tx_buff_tab[n_desc]);
+ port->tx_buff_tab[n_desc] = NULL;
+
+- start = qmgr_stat_below_low_watermark(port->plat->txreadyq);
+- queue_put_desc(port->plat->txreadyq,
++ start = qmgr_stat_below_low_watermark(port->txreadyq);
++ queue_put_desc(port->txreadyq,
+ tx_desc_phys(port, n_desc), desc);
+ if (start) { /* TX-ready queue was empty */
+ #if DEBUG_TX
+@@ -829,7 +835,7 @@ static void hss_hdlc_txdone_irq(void *pdev)
+ static int hss_hdlc_xmit(struct sk_buff *skb, struct net_device *dev)
+ {
+ struct port *port = dev_to_port(dev);
+- unsigned int txreadyq = port->plat->txreadyq;
++ unsigned int txreadyq = port->txreadyq;
+ int len, offset, bytes, n;
+ void *mem;
+ u32 phys;
+@@ -889,7 +895,7 @@ static int hss_hdlc_xmit(struct sk_buff *skb, struct net_device *dev)
+ desc->buf_len = desc->pkt_len = len;
+
+ wmb();
+- queue_put_desc(queue_ids[port->id].tx, tx_desc_phys(port, n), desc);
++ queue_put_desc(port->txq, tx_desc_phys(port, n), desc);
+
+ if (qmgr_stat_below_low_watermark(txreadyq)) { /* empty */
+ #if DEBUG_TX
+@@ -916,40 +922,40 @@ static int request_hdlc_queues(struct port *port)
+ {
+ int err;
+
+- err = qmgr_request_queue(queue_ids[port->id].rxfree, RX_DESCS, 0, 0,
++ err = qmgr_request_queue(port->rxfreeq, RX_DESCS, 0, 0,
+ "%s:RX-free", port->netdev->name);
+ if (err)
+ return err;
+
+- err = qmgr_request_queue(queue_ids[port->id].rx, RX_DESCS, 0, 0,
++ err = qmgr_request_queue(port->rxq, RX_DESCS, 0, 0,
+ "%s:RX", port->netdev->name);
+ if (err)
+ goto rel_rxfree;
+
+- err = qmgr_request_queue(queue_ids[port->id].tx, TX_DESCS, 0, 0,
++ err = qmgr_request_queue(port->txq, TX_DESCS, 0, 0,
+ "%s:TX", port->netdev->name);
+ if (err)
+ goto rel_rx;
+
+- err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0,
++ err = qmgr_request_queue(port->txreadyq, TX_DESCS, 0, 0,
+ "%s:TX-ready", port->netdev->name);
+ if (err)
+ goto rel_tx;
+
+- err = qmgr_request_queue(queue_ids[port->id].txdone, TX_DESCS, 0, 0,
++ err = qmgr_request_queue(port->txdoneq, TX_DESCS, 0, 0,
+ "%s:TX-done", port->netdev->name);
+ if (err)
+ goto rel_txready;
+ return 0;
+
+ rel_txready:
+- qmgr_release_queue(port->plat->txreadyq);
++ qmgr_release_queue(port->txreadyq);
+ rel_tx:
+- qmgr_release_queue(queue_ids[port->id].tx);
++ qmgr_release_queue(port->txq);
+ rel_rx:
+- qmgr_release_queue(queue_ids[port->id].rx);
++ qmgr_release_queue(port->rxq);
+ rel_rxfree:
+- qmgr_release_queue(queue_ids[port->id].rxfree);
++ qmgr_release_queue(port->rxfreeq);
+ printk(KERN_DEBUG "%s: unable to request hardware queues\n",
+ port->netdev->name);
+ return err;
+@@ -957,11 +963,11 @@ static int request_hdlc_queues(struct port *port)
+
+ static void release_hdlc_queues(struct port *port)
+ {
+- qmgr_release_queue(queue_ids[port->id].rxfree);
+- qmgr_release_queue(queue_ids[port->id].rx);
+- qmgr_release_queue(queue_ids[port->id].txdone);
+- qmgr_release_queue(queue_ids[port->id].tx);
+- qmgr_release_queue(port->plat->txreadyq);
++ qmgr_release_queue(port->rxfreeq);
++ qmgr_release_queue(port->rxq);
++ qmgr_release_queue(port->txdoneq);
++ qmgr_release_queue(port->txq);
++ qmgr_release_queue(port->txreadyq);
+ }
+
+ static int init_hdlc_queues(struct port *port)
+@@ -1046,11 +1052,24 @@ static void destroy_hdlc_queues(struct port *port)
+ }
+ }
+
++static irqreturn_t hss_hdlc_dcd_irq(int irq, void *data)
++{
++ struct net_device *dev = data;
++ struct port *port = dev_to_port(dev);
++ int val;
++
++ val = gpiod_get_value(port->dcd);
++ hss_hdlc_set_carrier(dev, val);
++
++ return IRQ_HANDLED;
++}
++
+ static int hss_hdlc_open(struct net_device *dev)
+ {
+ struct port *port = dev_to_port(dev);
+ unsigned long flags;
+ int i, err = 0;
++ int val;
+
+ err = hdlc_open(dev);
+ if (err)
+@@ -1069,32 +1088,44 @@ static int hss_hdlc_open(struct net_device *dev)
+ goto err_destroy_queues;
+
+ spin_lock_irqsave(&npe_lock, flags);
+- if (port->plat->open) {
+- err = port->plat->open(port->id, dev, hss_hdlc_set_carrier);
+- if (err)
+- goto err_unlock;
++
++ /* Set the carrier, the GPIO is flagged active low so this will return
++ * 1 if DCD is asserted.
++ */
++ val = gpiod_get_value(port->dcd);
++ hss_hdlc_set_carrier(dev, val);
++
++ /* Set up an IRQ for DCD */
++ err = request_irq(gpiod_to_irq(port->dcd), hss_hdlc_dcd_irq, 0, "IXP4xx HSS", dev);
++ if (err) {
++ dev_err(&dev->dev, "ixp4xx_hss: failed to request DCD IRQ (%i)\n", err);
++ goto err_unlock;
+ }
+
++ /* GPIOs are flagged active low so this asserts DTR and RTS */
++ gpiod_set_value(port->dtr, 1);
++ gpiod_set_value(port->rts, 1);
++
+ spin_unlock_irqrestore(&npe_lock, flags);
+
+ /* Populate queues with buffers, no failure after this point */
+ for (i = 0; i < TX_DESCS; i++)
+- queue_put_desc(port->plat->txreadyq,
++ queue_put_desc(port->txreadyq,
+ tx_desc_phys(port, i), tx_desc_ptr(port, i));
+
+ for (i = 0; i < RX_DESCS; i++)
+- queue_put_desc(queue_ids[port->id].rxfree,
++ queue_put_desc(port->rxfreeq,
+ rx_desc_phys(port, i), rx_desc_ptr(port, i));
+
+ napi_enable(&port->napi);
+ netif_start_queue(dev);
+
+- qmgr_set_irq(queue_ids[port->id].rx, QUEUE_IRQ_SRC_NOT_EMPTY,
++ qmgr_set_irq(port->rxq, QUEUE_IRQ_SRC_NOT_EMPTY,
+ hss_hdlc_rx_irq, dev);
+
+- qmgr_set_irq(queue_ids[port->id].txdone, QUEUE_IRQ_SRC_NOT_EMPTY,
++ qmgr_set_irq(port->txdoneq, QUEUE_IRQ_SRC_NOT_EMPTY,
+ hss_hdlc_txdone_irq, dev);
+- qmgr_enable_irq(queue_ids[port->id].txdone);
++ qmgr_enable_irq(port->txdoneq);
+
+ ports_open++;
+
+@@ -1125,15 +1156,15 @@ static int hss_hdlc_close(struct net_device *dev)
+
+ spin_lock_irqsave(&npe_lock, flags);
+ ports_open--;
+- qmgr_disable_irq(queue_ids[port->id].rx);
++ qmgr_disable_irq(port->rxq);
+ netif_stop_queue(dev);
+ napi_disable(&port->napi);
+
+ hss_stop_hdlc(port);
+
+- while (queue_get_desc(queue_ids[port->id].rxfree, port, 0) >= 0)
++ while (queue_get_desc(port->rxfreeq, port, 0) >= 0)
+ buffs--;
+- while (queue_get_desc(queue_ids[port->id].rx, port, 0) >= 0)
++ while (queue_get_desc(port->rxq, port, 0) >= 0)
+ buffs--;
+
+ if (buffs)
+@@ -1141,12 +1172,12 @@ static int hss_hdlc_close(struct net_device *dev)
+ buffs);
+
+ buffs = TX_DESCS;
+- while (queue_get_desc(queue_ids[port->id].tx, port, 1) >= 0)
++ while (queue_get_desc(port->txq, port, 1) >= 0)
+ buffs--; /* cancel TX */
+
+ i = 0;
+ do {
+- while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0)
++ while (queue_get_desc(port->txreadyq, port, 1) >= 0)
+ buffs--;
+ if (!buffs)
+ break;
+@@ -1159,10 +1190,12 @@ static int hss_hdlc_close(struct net_device *dev)
+ if (!buffs)
+ printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i);
+ #endif
+- qmgr_disable_irq(queue_ids[port->id].txdone);
++ qmgr_disable_irq(port->txdoneq);
+
+- if (port->plat->close)
+- port->plat->close(port->id, dev);
++ free_irq(gpiod_to_irq(port->dcd), dev);
++ /* GPIOs are flagged active low so this de-asserts DTR and RTS */
++ gpiod_set_value(port->dtr, 0);
++ gpiod_set_value(port->rts, 0);
+ spin_unlock_irqrestore(&npe_lock, flags);
+
+ destroy_hdlc_queues(port);
+@@ -1254,6 +1287,21 @@ static void find_best_clock(u32 timer_freq, u32 rate, u32 *best, u32 *reg)
+ }
+ }
+
++static int hss_hdlc_set_clock(struct port *port, unsigned int clock_type)
++{
++ switch (clock_type) {
++ case CLOCK_DEFAULT:
++ case CLOCK_EXT:
++ gpiod_set_value(port->clk_internal, 0);
++ return CLOCK_EXT;
++ case CLOCK_INT:
++ gpiod_set_value(port->clk_internal, 1);
++ return CLOCK_INT;
++ default:
++ return -EINVAL;
++ }
++}
++
+ static int hss_hdlc_ioctl(struct net_device *dev, struct if_settings *ifs)
+ {
+ const size_t size = sizeof(sync_serial_settings);
+@@ -1286,8 +1334,7 @@ static int hss_hdlc_ioctl(struct net_device *dev, struct if_settings *ifs)
+ return -EFAULT;
+
+ clk = new_line.clock_type;
+- if (port->plat->set_clock)
+- clk = port->plat->set_clock(port->id, clk);
++ hss_hdlc_set_clock(port, clk);
+
+ if (clk != CLOCK_EXT && clk != CLOCK_INT)
+ return -EINVAL; /* No such clock setting */
+@@ -1297,7 +1344,7 @@ static int hss_hdlc_ioctl(struct net_device *dev, struct if_settings *ifs)
+
+ port->clock_type = clk; /* Update settings */
+ if (clk == CLOCK_INT) {
+- find_best_clock(port->plat->timer_freq,
++ find_best_clock(IXP4XX_TIMER_FREQ,
+ new_line.clock_rate,
+ &port->clock_rate, &port->clock_reg);
+ } else {
+@@ -1335,63 +1382,126 @@ static const struct net_device_ops hss_hdlc_ops = {
+ .ndo_siocwandev = hss_hdlc_ioctl,
+ };
+
+-static int hss_init_one(struct platform_device *pdev)
++static int ixp4xx_hss_probe(struct platform_device *pdev)
+ {
++ struct of_phandle_args queue_spec;
++ struct of_phandle_args npe_spec;
++ struct device *dev = &pdev->dev;
++ struct net_device *ndev;
++ struct device_node *np;
+ struct port *port;
+- struct net_device *dev;
+ hdlc_device *hdlc;
+ int err;
+
+- port = kzalloc(sizeof(*port), GFP_KERNEL);
++ np = dev->of_node;
++
++ port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
+ if (!port)
+ return -ENOMEM;
+
+- port->npe = npe_request(0);
++ err = of_parse_phandle_with_fixed_args(np, "intel,npe-handle", 1, 0,
++ &npe_spec);
++ if (err)
++ return dev_err_probe(dev, err, "no NPE engine specified\n");
++ /* NPE ID 0x00, 0x10, 0x20... */
++ port->npe = npe_request(npe_spec.args[0] << 4);
+ if (!port->npe) {
+- err = -ENODEV;
+- goto err_free;
++ dev_err(dev, "unable to obtain NPE instance\n");
++ return -ENODEV;
+ }
+
+- dev = alloc_hdlcdev(port);
++ /* Get the TX ready queue as resource from queue manager */
++ err = of_parse_phandle_with_fixed_args(np, "intek,queue-chl-txready", 1, 0,
++ &queue_spec);
++ if (err)
++ return dev_err_probe(dev, err, "no txready queue phandle\n");
++ port->txreadyq = queue_spec.args[0];
++ /* Get the RX trig queue as resource from queue manager */
++ err = of_parse_phandle_with_fixed_args(np, "intek,queue-chl-rxtrig", 1, 0,
++ &queue_spec);
++ if (err)
++ return dev_err_probe(dev, err, "no rxtrig queue phandle\n");
++ port->rxtrigq = queue_spec.args[0];
++ /* Get the RX queue as resource from queue manager */
++ err = of_parse_phandle_with_fixed_args(np, "intek,queue-pkt-rx", 1, 0,
++ &queue_spec);
++ if (err)
++ return dev_err_probe(dev, err, "no RX queue phandle\n");
++ port->rxq = queue_spec.args[0];
++ /* Get the TX queue as resource from queue manager */
++ err = of_parse_phandle_with_fixed_args(np, "intek,queue-pkt-tx", 1, 0,
++ &queue_spec);
++ if (err)
++ return dev_err_probe(dev, err, "no RX queue phandle\n");
++ port->txq = queue_spec.args[0];
++ /* Get the RX free queue as resource from queue manager */
++ err = of_parse_phandle_with_fixed_args(np, "intek,queue-pkt-rxfree", 1, 0,
++ &queue_spec);
++ if (err)
++ return dev_err_probe(dev, err, "no RX free queue phandle\n");
++ port->rxfreeq = queue_spec.args[0];
++ /* Get the TX done queue as resource from queue manager */
++ err = of_parse_phandle_with_fixed_args(np, "intek,queue-pkt-txdone", 1, 0,
++ &queue_spec);
++ if (err)
++ return dev_err_probe(dev, err, "no TX done queue phandle\n");
++ port->txdoneq = queue_spec.args[0];
++
++ /* Obtain all the line control GPIOs */
++ port->cts = devm_gpiod_get(dev, "cts", GPIOD_OUT_LOW);
++ if (IS_ERR(port->cts))
++ return dev_err_probe(dev, PTR_ERR(port->cts), "unable to get CTS GPIO\n");
++ port->rts = devm_gpiod_get(dev, "rts", GPIOD_OUT_LOW);
++ if (IS_ERR(port->rts))
++ return dev_err_probe(dev, PTR_ERR(port->rts), "unable to get RTS GPIO\n");
++ port->dcd = devm_gpiod_get(dev, "dcd", GPIOD_IN);
++ if (IS_ERR(port->dcd))
++ return dev_err_probe(dev, PTR_ERR(port->dcd), "unable to get DCD GPIO\n");
++ port->dtr = devm_gpiod_get(dev, "dtr", GPIOD_OUT_LOW);
++ if (IS_ERR(port->dtr))
++ return dev_err_probe(dev, PTR_ERR(port->dtr), "unable to get DTR GPIO\n");
++ port->clk_internal = devm_gpiod_get(dev, "clk-internal", GPIOD_OUT_LOW);
++ if (IS_ERR(port->clk_internal))
++ return dev_err_probe(dev, PTR_ERR(port->clk_internal),
++ "unable to get CLK internal GPIO\n");
++
++ ndev = alloc_hdlcdev(port);
+ port->netdev = alloc_hdlcdev(port);
+ if (!port->netdev) {
+ err = -ENOMEM;
+ goto err_plat;
+ }
+
+- SET_NETDEV_DEV(dev, &pdev->dev);
+- hdlc = dev_to_hdlc(dev);
++ SET_NETDEV_DEV(ndev, &pdev->dev);
++ hdlc = dev_to_hdlc(ndev);
+ hdlc->attach = hss_hdlc_attach;
+ hdlc->xmit = hss_hdlc_xmit;
+- dev->netdev_ops = &hss_hdlc_ops;
+- dev->tx_queue_len = 100;
++ ndev->netdev_ops = &hss_hdlc_ops;
++ ndev->tx_queue_len = 100;
+ port->clock_type = CLOCK_EXT;
+ port->clock_rate = 0;
+ port->clock_reg = CLK42X_SPEED_2048KHZ;
+ port->id = pdev->id;
+ port->dev = &pdev->dev;
+- port->plat = pdev->dev.platform_data;
+- netif_napi_add(dev, &port->napi, hss_hdlc_poll, NAPI_WEIGHT);
++ netif_napi_add(ndev, &port->napi, hss_hdlc_poll, NAPI_WEIGHT);
+
+- err = register_hdlc_device(dev);
++ err = register_hdlc_device(ndev);
+ if (err)
+ goto err_free_netdev;
+
+ platform_set_drvdata(pdev, port);
+
+- netdev_info(dev, "initialized\n");
++ netdev_info(ndev, "initialized\n");
+ return 0;
+
+ err_free_netdev:
+- free_netdev(dev);
++ free_netdev(ndev);
+ err_plat:
+ npe_release(port->npe);
+-err_free:
+- kfree(port);
+ return err;
+ }
+
+-static int hss_remove_one(struct platform_device *pdev)
++static int ixp4xx_hss_remove(struct platform_device *pdev)
+ {
+ struct port *port = platform_get_drvdata(pdev);
+
+@@ -1404,8 +1514,8 @@ static int hss_remove_one(struct platform_device *pdev)
+
+ static struct platform_driver ixp4xx_hss_driver = {
+ .driver.name = DRV_NAME,
+- .probe = hss_init_one,
+- .remove = hss_remove_one,
++ .probe = ixp4xx_hss_probe,
++ .remove = ixp4xx_hss_remove,
+ };
+
+ static int __init hss_init_module(void)
--- /dev/null
+From f960b33f6d53f6f21f9c73a74b3700e724dc0fed Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Tue, 28 Dec 2021 01:08:39 +0100
+Subject: [PATCH 1/3] ARM: dts: ixp4xx: Fix up the Netgear WG302 device tree
+
+The version we can support (because of access to the hardware)
+is WG302v1, so rename the file and make the following
+modifications:
+
+- We have 32MB memory not 16MB
+- The default console speed is 9600 baud so use this
+- The device has no ATA disk nor USB so drop the /dev/sda1
+ default mount, this needs to mount ramdisk or NFS
+- Both serial0 and serial1 cannot be assigned with aliases,
+ just assign serial0
+- The Flash is just 8MB so augment the size
+- The Flash FIS index is at eraseblock 0x3f
+- The PHY is at MDIO address 30
+
+Tested by bringing the Netgear WG302v1 up to userspace using
+initramfs appended to the kernel and downloaded over TFTP,
+then ifconfig to bring up eth0 and pinging the host. All
+works fine including SSH into the device from the host.
+
+Cc: Zoltan HERPAI <wigyori@uid0.hu>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ arch/arm/boot/dts/Makefile | 2 +-
+ ...2.dts => intel-ixp42x-netgear-wg302v1.dts} | 29 +++++++++----------
+ 2 files changed, 15 insertions(+), 16 deletions(-)
+ rename arch/arm/boot/dts/{intel-ixp42x-netgear-wg302v2.dts => intel-ixp42x-netgear-wg302v1.dts} (77%)
+
+diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
+index 235ad559acb2..dea29395c9a4 100644
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -269,7 +269,7 @@ dtb-$(CONFIG_ARCH_IXP4XX) += \
+ intel-ixp42x-dlink-dsm-g600.dtb \
+ intel-ixp42x-gateworks-gw2348.dtb \
+ intel-ixp43x-gateworks-gw2358.dtb \
+- intel-ixp42x-netgear-wg302v2.dtb \
++ intel-ixp42x-netgear-wg302v1.dtb \
+ intel-ixp42x-arcom-vulcan.dtb \
+ intel-ixp42x-gateway-7001.dtb
+ dtb-$(CONFIG_ARCH_KEYSTONE) += \
+diff --git a/arch/arm/boot/dts/intel-ixp42x-netgear-wg302v2.dts b/arch/arm/boot/dts/intel-ixp42x-netgear-wg302v1.dts
+similarity index 77%
+rename from arch/arm/boot/dts/intel-ixp42x-netgear-wg302v2.dts
+rename to arch/arm/boot/dts/intel-ixp42x-netgear-wg302v1.dts
+index a57009436ed8..df2ca6d95ee5 100644
+--- a/arch/arm/boot/dts/intel-ixp42x-netgear-wg302v2.dts
++++ b/arch/arm/boot/dts/intel-ixp42x-netgear-wg302v1.dts
+@@ -10,26 +10,26 @@
+ #include <dt-bindings/input/input.h>
+
+ / {
+- model = "Netgear WG302 v2";
+- compatible = "netgear,wg302v2", "intel,ixp42x";
++ model = "Netgear WG302 v1";
++ compatible = "netgear,wg302v1", "intel,ixp42x";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ memory@0 {
+- /* 16 MB SDRAM according to OpenWrt database */
++ /* 32 MB SDRAM according to boot arguments */
+ device_type = "memory";
+- reg = <0x00000000 0x01000000>;
++ reg = <0x00000000 0x02000000>;
+ };
+
+ chosen {
+- bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootwait";
+- stdout-path = "uart1:115200n8";
++ /* The RedBoot comes up in 9600 baud so let's keep this */
++ bootargs = "console=ttyS0,9600n8";
++ stdout-path = "uart1:9600n8";
+ };
+
+ aliases {
+ /* These are switched around */
+ serial0 = &uart1;
+- serial1 = &uart0;
+ };
+
+ soc {
+@@ -38,18 +38,17 @@
+ compatible = "intel,ixp4xx-flash", "cfi-flash";
+ bank-width = <2>;
+ /*
+- * 32 MB of Flash in 128 0x20000 sized blocks
+- * mapped in at CS0 and CS1
++ * 8 MB of Flash in 64 0x20000 sized blocks
++ * mapped in at CS0.
+ */
+- reg = <0 0x00000000 0x2000000>;
++ reg = <0 0x00000000 0x800000>;
+
+ /* Configure expansion bus to allow writes */
+ intel,ixp4xx-eb-write-enable = <1>;
+
+ partitions {
+ compatible = "redboot-fis";
+- /* CHECKME: guess this is Redboot FIS */
+- fis-index-block = <0xff>;
++ fis-index-block = <0x3f>;
+ };
+ };
+ };
+@@ -82,14 +81,14 @@
+ queue-rx = <&qmgr 3>;
+ queue-txready = <&qmgr 20>;
+ phy-mode = "rgmii";
+- phy-handle = <&phy8>;
++ phy-handle = <&phy30>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+- phy8: ethernet-phy@8 {
+- reg = <8>;
++ phy30: ethernet-phy@30 {
++ reg = <30>;
+ };
+ };
+ };
+--
+2.20.1
+
--- /dev/null
+From 0b6a849bb75d4330366f48a0b17bcb118f86a8dc Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Wed, 26 Jan 2022 01:26:01 +0100
+Subject: [PATCH 2/3] ARM: dts: ixp42x: Expand syscon register range
+
+We have at least 0x30 registers in the IXP42x syscon as
+register 0x2c is actively used to read platform features.
+
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ arch/arm/boot/dts/intel-ixp42x.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/intel-ixp42x.dtsi b/arch/arm/boot/dts/intel-ixp42x.dtsi
+index d0e0f8afb7c9..84cee8ec3ab8 100644
+--- a/arch/arm/boot/dts/intel-ixp42x.dtsi
++++ b/arch/arm/boot/dts/intel-ixp42x.dtsi
+@@ -9,7 +9,7 @@
+ soc {
+ bus@c4000000 {
+ compatible = "intel,ixp42x-expansion-bus-controller", "syscon";
+- reg = <0xc4000000 0x28>;
++ reg = <0xc4000000 0x30>;
+ };
+
+ pci@c0000000 {
+--
+2.20.1
+
--- /dev/null
+From 8d3ca344bb6aefd8dbf554db18b18611e01d3ab6 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Tue, 1 Feb 2022 01:05:54 +0100
+Subject: [PATCH 3/3] ARM: dts: Drop serial 1 alias on GW7001
+
+The Gateaway 7001 has a serial port alias for serial1, this has
+proven detrimental on the WG302 so remove it on this machine
+as well.
+
+Drop in a small comment that this machine is based on IXP422.
+
+Cc: Zoltan HERPAI <wigyori@uid0.hu>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts b/arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts
+index a1c03c965f17..b7cbc90e1c18 100644
+--- a/arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts
++++ b/arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts
+@@ -1,6 +1,6 @@
+ // SPDX-License-Identifier: ISC
+ /*
+- * Device Tree file for Gateway 7001 AP
++ * Device Tree file for Gateway 7001 AP based on IXP422
+ * Derived from boardfiles written by Imre Kaloz
+ */
+
+@@ -29,7 +29,6 @@
+ aliases {
+ /* second UART is the primary console */
+ serial0 = &uart1;
+- serial1 = &uart0;
+ };
+
+ soc {
+--
+2.20.1
+
--- /dev/null
+From c8f59a1f0f4846848ee8cee4d2199a0cb7d04f53 Mon Sep 17 00:00:00 2001
+From: Zoltan HERPAI <wigyori@uid0.hu>
+Date: Fri, 11 Feb 2022 23:32:26 +0100
+Subject: [PATCH 02/14] ARM: ixp4xx: Delete Gateway 7001 boardfiles
+
+This board is replaced with the corresponding device tree.
+
+Cc: Imre Kaloz <kaloz@openwrt.org>
+Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Link: https://lore.kernel.org/r/20220211223238.648934-2-linus.walleij@linaro.org
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ arch/arm/mach-ixp4xx/Kconfig | 8 --
+ arch/arm/mach-ixp4xx/Makefile | 3 -
+ arch/arm/mach-ixp4xx/gateway7001-pci.c | 61 ------------
+ arch/arm/mach-ixp4xx/gateway7001-setup.c | 113 -----------------------
+ 4 files changed, 185 deletions(-)
+ delete mode 100644 arch/arm/mach-ixp4xx/gateway7001-pci.c
+ delete mode 100644 arch/arm/mach-ixp4xx/gateway7001-setup.c
+
+diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig
+index 4c787b4be62b..e6b23c3ce50c 100644
+--- a/arch/arm/mach-ixp4xx/Kconfig
++++ b/arch/arm/mach-ixp4xx/Kconfig
+@@ -17,14 +17,6 @@ config MACH_IXP4XX_OF
+ help
+ Say 'Y' here to support Device Tree-based IXP4xx platforms.
+
+-config MACH_GATEWAY7001
+- bool "Gateway 7001"
+- depends on IXP4XX_PCI_LEGACY
+- help
+- Say 'Y' here if you want your kernel to support Gateway's
+- 7001 Access Point. For more information on this platform,
+- see http://openwrt.org
+-
+ config MACH_GORAMO_MLR
+ bool "GORAMO Multi Link Router"
+ depends on IXP4XX_PCI_LEGACY
+diff --git a/arch/arm/mach-ixp4xx/Makefile b/arch/arm/mach-ixp4xx/Makefile
+index b241094c9649..0a92f8c40e1c 100644
+--- a/arch/arm/mach-ixp4xx/Makefile
++++ b/arch/arm/mach-ixp4xx/Makefile
+@@ -9,11 +9,8 @@ obj-pci-n :=
+ # Device tree platform
+ obj-pci-$(CONFIG_MACH_IXP4XX_OF) += ixp4xx-of.o
+
+-obj-pci-$(CONFIG_MACH_GATEWAY7001) += gateway7001-pci.o
+-
+ obj-y += common.o
+
+-obj-$(CONFIG_MACH_GATEWAY7001) += gateway7001-setup.o
+ obj-$(CONFIG_MACH_GORAMO_MLR) += goramo_mlr.o
+
+ obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o
+diff --git a/arch/arm/mach-ixp4xx/gateway7001-pci.c b/arch/arm/mach-ixp4xx/gateway7001-pci.c
+deleted file mode 100644
+index 3c3ee9dad6d8..000000000000
+--- a/arch/arm/mach-ixp4xx/gateway7001-pci.c
++++ /dev/null
+@@ -1,61 +0,0 @@
+-// SPDX-License-Identifier: GPL-2.0-only
+-/*
+- * arch/arch/mach-ixp4xx/gateway7001-pci.c
+- *
+- * PCI setup routines for Gateway 7001
+- *
+- * Copyright (C) 2007 Imre Kaloz <kaloz@openwrt.org>
+- *
+- * based on coyote-pci.c:
+- * Copyright (C) 2002 Jungo Software Technologies.
+- * Copyright (C) 2003 MontaVista Softwrae, Inc.
+- *
+- * Maintainer: Imre Kaloz <kaloz@openwrt.org>
+- */
+-
+-#include <linux/kernel.h>
+-#include <linux/pci.h>
+-#include <linux/init.h>
+-#include <linux/irq.h>
+-
+-#include <asm/mach-types.h>
+-#include <mach/hardware.h>
+-
+-#include <asm/mach/pci.h>
+-
+-#include "irqs.h"
+-
+-void __init gateway7001_pci_preinit(void)
+-{
+- irq_set_irq_type(IRQ_IXP4XX_GPIO10, IRQ_TYPE_LEVEL_LOW);
+- irq_set_irq_type(IRQ_IXP4XX_GPIO11, IRQ_TYPE_LEVEL_LOW);
+-
+- ixp4xx_pci_preinit();
+-}
+-
+-static int __init gateway7001_map_irq(const struct pci_dev *dev, u8 slot,
+- u8 pin)
+-{
+- if (slot == 1)
+- return IRQ_IXP4XX_GPIO11;
+- else if (slot == 2)
+- return IRQ_IXP4XX_GPIO10;
+- else return -1;
+-}
+-
+-struct hw_pci gateway7001_pci __initdata = {
+- .nr_controllers = 1,
+- .ops = &ixp4xx_ops,
+- .preinit = gateway7001_pci_preinit,
+- .setup = ixp4xx_setup,
+- .map_irq = gateway7001_map_irq,
+-};
+-
+-int __init gateway7001_pci_init(void)
+-{
+- if (machine_is_gateway7001())
+- pci_common_init(&gateway7001_pci);
+- return 0;
+-}
+-
+-subsys_initcall(gateway7001_pci_init);
+diff --git a/arch/arm/mach-ixp4xx/gateway7001-setup.c b/arch/arm/mach-ixp4xx/gateway7001-setup.c
+deleted file mode 100644
+index 678e7dfff0e5..000000000000
+--- a/arch/arm/mach-ixp4xx/gateway7001-setup.c
++++ /dev/null
+@@ -1,113 +0,0 @@
+-// SPDX-License-Identifier: GPL-2.0
+-/*
+- * arch/arm/mach-ixp4xx/gateway7001-setup.c
+- *
+- * Board setup for the Gateway 7001 board
+- *
+- * Copyright (C) 2007 Imre Kaloz <kaloz@openwrt.org>
+- *
+- * based on coyote-setup.c:
+- * Copyright (C) 2003-2005 MontaVista Software, Inc.
+- *
+- * Author: Imre Kaloz <Kaloz@openwrt.org>
+- */
+-
+-#include <linux/kernel.h>
+-#include <linux/init.h>
+-#include <linux/device.h>
+-#include <linux/serial.h>
+-#include <linux/tty.h>
+-#include <linux/serial_8250.h>
+-
+-#include <asm/types.h>
+-#include <asm/setup.h>
+-#include <asm/memory.h>
+-#include <mach/hardware.h>
+-#include <asm/irq.h>
+-#include <asm/mach-types.h>
+-#include <asm/mach/arch.h>
+-#include <asm/mach/flash.h>
+-
+-#include "irqs.h"
+-
+-static struct flash_platform_data gateway7001_flash_data = {
+- .map_name = "cfi_probe",
+- .width = 2,
+-};
+-
+-static struct resource gateway7001_flash_resource = {
+- .flags = IORESOURCE_MEM,
+-};
+-
+-static struct platform_device gateway7001_flash = {
+- .name = "IXP4XX-Flash",
+- .id = 0,
+- .dev = {
+- .platform_data = &gateway7001_flash_data,
+- },
+- .num_resources = 1,
+- .resource = &gateway7001_flash_resource,
+-};
+-
+-static struct resource gateway7001_uart_resource = {
+- .start = IXP4XX_UART2_BASE_PHYS,
+- .end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
+- .flags = IORESOURCE_MEM,
+-};
+-
+-static struct plat_serial8250_port gateway7001_uart_data[] = {
+- {
+- .mapbase = IXP4XX_UART2_BASE_PHYS,
+- .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
+- .irq = IRQ_IXP4XX_UART2,
+- .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+- .iotype = UPIO_MEM,
+- .regshift = 2,
+- .uartclk = IXP4XX_UART_XTAL,
+- },
+- { },
+-};
+-
+-static struct platform_device gateway7001_uart = {
+- .name = "serial8250",
+- .id = PLAT8250_DEV_PLATFORM,
+- .dev = {
+- .platform_data = gateway7001_uart_data,
+- },
+- .num_resources = 1,
+- .resource = &gateway7001_uart_resource,
+-};
+-
+-static struct platform_device *gateway7001_devices[] __initdata = {
+- &gateway7001_flash,
+- &gateway7001_uart
+-};
+-
+-static void __init gateway7001_init(void)
+-{
+- ixp4xx_sys_init();
+-
+- gateway7001_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
+- gateway7001_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1;
+-
+- *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE;
+- *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
+-
+- platform_add_devices(gateway7001_devices, ARRAY_SIZE(gateway7001_devices));
+-}
+-
+-#ifdef CONFIG_MACH_GATEWAY7001
+-MACHINE_START(GATEWAY7001, "Gateway 7001 AP")
+- /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
+- .map_io = ixp4xx_map_io,
+- .init_early = ixp4xx_init_early,
+- .init_irq = ixp4xx_init_irq,
+- .init_time = ixp4xx_timer_init,
+- .atag_offset = 0x100,
+- .init_machine = gateway7001_init,
+-#if defined(CONFIG_PCI)
+- .dma_zone_size = SZ_64M,
+-#endif
+- .restart = ixp4xx_restart,
+-MACHINE_END
+-#endif
+--
+2.20.1
+
--- /dev/null
+From 3e96dcfb96e80d2f7f1edb6a1ac81b12de996fa8 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Fri, 11 Feb 2022 23:32:27 +0100
+Subject: [PATCH 03/14] ARM: ixp4xx: Delete the Goramo MLR boardfile
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This board is replaced with the corresponding device tree.
+
+Also delete dangling platform data file only used by this
+boardfile and nothing else.
+
+Cc: Krzysztof Hałasa <khalasa@piap.pl>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Link: https://lore.kernel.org/r/20220211223238.648934-3-linus.walleij@linaro.org
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ arch/arm/mach-ixp4xx/Kconfig | 7 -
+ arch/arm/mach-ixp4xx/Makefile | 2 -
+ arch/arm/mach-ixp4xx/goramo_mlr.c | 532 -------------------
+ include/linux/platform_data/wan_ixp4xx_hss.h | 17 -
+ 4 files changed, 558 deletions(-)
+ delete mode 100644 arch/arm/mach-ixp4xx/goramo_mlr.c
+ delete mode 100644 include/linux/platform_data/wan_ixp4xx_hss.h
+
+diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig
+index e6b23c3ce50c..0fac12cb31a6 100644
+--- a/arch/arm/mach-ixp4xx/Kconfig
++++ b/arch/arm/mach-ixp4xx/Kconfig
+@@ -17,13 +17,6 @@ config MACH_IXP4XX_OF
+ help
+ Say 'Y' here to support Device Tree-based IXP4xx platforms.
+
+-config MACH_GORAMO_MLR
+- bool "GORAMO Multi Link Router"
+- depends on IXP4XX_PCI_LEGACY
+- help
+- Say 'Y' here if you want your kernel to support GORAMO
+- MultiLink router.
+-
+ config ARCH_PRPMC1100
+ bool "PrPMC1100"
+ help
+diff --git a/arch/arm/mach-ixp4xx/Makefile b/arch/arm/mach-ixp4xx/Makefile
+index 0a92f8c40e1c..83719704a626 100644
+--- a/arch/arm/mach-ixp4xx/Makefile
++++ b/arch/arm/mach-ixp4xx/Makefile
+@@ -11,6 +11,4 @@ obj-pci-$(CONFIG_MACH_IXP4XX_OF) += ixp4xx-of.o
+
+ obj-y += common.o
+
+-obj-$(CONFIG_MACH_GORAMO_MLR) += goramo_mlr.o
+-
+ obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o
+diff --git a/arch/arm/mach-ixp4xx/goramo_mlr.c b/arch/arm/mach-ixp4xx/goramo_mlr.c
+deleted file mode 100644
+index 07b50dfcc489..000000000000
+--- a/arch/arm/mach-ixp4xx/goramo_mlr.c
++++ /dev/null
+@@ -1,532 +0,0 @@
+-// SPDX-License-Identifier: GPL-2.0
+-/*
+- * Goramo MultiLink router platform code
+- * Copyright (C) 2006-2009 Krzysztof Halasa <khc@pm.waw.pl>
+- */
+-
+-#include <linux/delay.h>
+-#include <linux/gpio.h>
+-#include <linux/hdlc.h>
+-#include <linux/io.h>
+-#include <linux/irq.h>
+-#include <linux/kernel.h>
+-#include <linux/pci.h>
+-#include <linux/platform_data/wan_ixp4xx_hss.h>
+-#include <linux/serial_8250.h>
+-#include <asm/mach-types.h>
+-#include <asm/mach/arch.h>
+-#include <asm/mach/flash.h>
+-#include <asm/mach/pci.h>
+-#include <asm/system_info.h>
+-
+-#include "irqs.h"
+-
+-#define SLOT_ETHA 0x0B /* IDSEL = AD21 */
+-#define SLOT_ETHB 0x0C /* IDSEL = AD20 */
+-#define SLOT_MPCI 0x0D /* IDSEL = AD19 */
+-#define SLOT_NEC 0x0E /* IDSEL = AD18 */
+-
+-/* GPIO lines */
+-#define GPIO_SCL 0
+-#define GPIO_SDA 1
+-#define GPIO_STR 2
+-#define GPIO_IRQ_NEC 3
+-#define GPIO_IRQ_ETHA 4
+-#define GPIO_IRQ_ETHB 5
+-#define GPIO_HSS0_DCD_N 6
+-#define GPIO_HSS1_DCD_N 7
+-#define GPIO_UART0_DCD 8
+-#define GPIO_UART1_DCD 9
+-#define GPIO_HSS0_CTS_N 10
+-#define GPIO_HSS1_CTS_N 11
+-#define GPIO_IRQ_MPCI 12
+-#define GPIO_HSS1_RTS_N 13
+-#define GPIO_HSS0_RTS_N 14
+-/* GPIO15 is not connected */
+-
+-/* Control outputs from 74HC4094 */
+-#define CONTROL_HSS0_CLK_INT 0
+-#define CONTROL_HSS1_CLK_INT 1
+-#define CONTROL_HSS0_DTR_N 2
+-#define CONTROL_HSS1_DTR_N 3
+-#define CONTROL_EXT 4
+-#define CONTROL_AUTO_RESET 5
+-#define CONTROL_PCI_RESET_N 6
+-#define CONTROL_EEPROM_WC_N 7
+-
+-/* offsets from start of flash ROM = 0x50000000 */
+-#define CFG_ETH0_ADDRESS 0x40 /* 6 bytes */
+-#define CFG_ETH1_ADDRESS 0x46 /* 6 bytes */
+-#define CFG_REV 0x4C /* u32 */
+-#define CFG_SDRAM_SIZE 0x50 /* u32 */
+-#define CFG_SDRAM_CONF 0x54 /* u32 */
+-#define CFG_SDRAM_MODE 0x58 /* u32 */
+-#define CFG_SDRAM_REFRESH 0x5C /* u32 */
+-
+-#define CFG_HW_BITS 0x60 /* u32 */
+-#define CFG_HW_USB_PORTS 0x00000007 /* 0 = no NEC chip, 1-5 = ports # */
+-#define CFG_HW_HAS_PCI_SLOT 0x00000008
+-#define CFG_HW_HAS_ETH0 0x00000010
+-#define CFG_HW_HAS_ETH1 0x00000020
+-#define CFG_HW_HAS_HSS0 0x00000040
+-#define CFG_HW_HAS_HSS1 0x00000080
+-#define CFG_HW_HAS_UART0 0x00000100
+-#define CFG_HW_HAS_UART1 0x00000200
+-#define CFG_HW_HAS_EEPROM 0x00000400
+-
+-#define FLASH_CMD_READ_ARRAY 0xFF
+-#define FLASH_CMD_READ_ID 0x90
+-#define FLASH_SER_OFF 0x102 /* 0x81 in 16-bit mode */
+-
+-static u32 hw_bits = 0xFFFFFFFD; /* assume all hardware present */;
+-static u8 control_value;
+-
+-/*
+- * FIXME: this is reimplementing I2C bit-bangining. Move this
+- * over to using driver/i2c/busses/i2c-gpio.c like all other boards
+- * and register proper I2C device(s) on the bus for this. (See
+- * other IXP4xx boards for examples.)
+- */
+-static void set_scl(u8 value)
+-{
+- gpio_set_value(GPIO_SCL, !!value);
+- udelay(3);
+-}
+-
+-static void set_sda(u8 value)
+-{
+- gpio_set_value(GPIO_SDA, !!value);
+- udelay(3);
+-}
+-
+-static void set_str(u8 value)
+-{
+- gpio_set_value(GPIO_STR, !!value);
+- udelay(3);
+-}
+-
+-static inline void set_control(int line, int value)
+-{
+- if (value)
+- control_value |= (1 << line);
+- else
+- control_value &= ~(1 << line);
+-}
+-
+-
+-static void output_control(void)
+-{
+- int i;
+-
+- gpio_direction_output(GPIO_SCL, 1);
+- gpio_direction_output(GPIO_SDA, 1);
+-
+- for (i = 0; i < 8; i++) {
+- set_scl(0);
+- set_sda(control_value & (0x80 >> i)); /* MSB first */
+- set_scl(1); /* active edge */
+- }
+-
+- set_str(1);
+- set_str(0);
+-
+- set_scl(0);
+- set_sda(1); /* Be ready for START */
+- set_scl(1);
+-}
+-
+-
+-static void (*set_carrier_cb_tab[2])(void *pdev, int carrier);
+-
+-static int hss_set_clock(int port, unsigned int clock_type)
+-{
+- int ctrl_int = port ? CONTROL_HSS1_CLK_INT : CONTROL_HSS0_CLK_INT;
+-
+- switch (clock_type) {
+- case CLOCK_DEFAULT:
+- case CLOCK_EXT:
+- set_control(ctrl_int, 0);
+- output_control();
+- return CLOCK_EXT;
+-
+- case CLOCK_INT:
+- set_control(ctrl_int, 1);
+- output_control();
+- return CLOCK_INT;
+-
+- default:
+- return -EINVAL;
+- }
+-}
+-
+-static irqreturn_t hss_dcd_irq(int irq, void *pdev)
+-{
+- int port = (irq == IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N));
+- int i = gpio_get_value(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N);
+- set_carrier_cb_tab[port](pdev, !i);
+- return IRQ_HANDLED;
+-}
+-
+-
+-static int hss_open(int port, void *pdev,
+- void (*set_carrier_cb)(void *pdev, int carrier))
+-{
+- int i, irq;
+-
+- if (!port)
+- irq = IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N);
+- else
+- irq = IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N);
+-
+- i = gpio_get_value(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N);
+- set_carrier_cb(pdev, !i);
+-
+- set_carrier_cb_tab[!!port] = set_carrier_cb;
+-
+- if ((i = request_irq(irq, hss_dcd_irq, 0, "IXP4xx HSS", pdev)) != 0) {
+- printk(KERN_ERR "ixp4xx_hss: failed to request IRQ%i (%i)\n",
+- irq, i);
+- return i;
+- }
+-
+- set_control(port ? CONTROL_HSS1_DTR_N : CONTROL_HSS0_DTR_N, 0);
+- output_control();
+- gpio_set_value(port ? GPIO_HSS1_RTS_N : GPIO_HSS0_RTS_N, 0);
+- return 0;
+-}
+-
+-static void hss_close(int port, void *pdev)
+-{
+- free_irq(port ? IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N) :
+- IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), pdev);
+- set_carrier_cb_tab[!!port] = NULL; /* catch bugs */
+-
+- set_control(port ? CONTROL_HSS1_DTR_N : CONTROL_HSS0_DTR_N, 1);
+- output_control();
+- gpio_set_value(port ? GPIO_HSS1_RTS_N : GPIO_HSS0_RTS_N, 1);
+-}
+-
+-
+-/* Flash memory */
+-static struct flash_platform_data flash_data = {
+- .map_name = "cfi_probe",
+- .width = 2,
+-};
+-
+-static struct resource flash_resource = {
+- .flags = IORESOURCE_MEM,
+-};
+-
+-static struct platform_device device_flash = {
+- .name = "IXP4XX-Flash",
+- .id = 0,
+- .dev = { .platform_data = &flash_data },
+- .num_resources = 1,
+- .resource = &flash_resource,
+-};
+-
+-/* IXP425 2 UART ports */
+-static struct resource uart_resources[] = {
+- {
+- .start = IXP4XX_UART1_BASE_PHYS,
+- .end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
+- .flags = IORESOURCE_MEM,
+- },
+- {
+- .start = IXP4XX_UART2_BASE_PHYS,
+- .end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
+- .flags = IORESOURCE_MEM,
+- }
+-};
+-
+-static struct plat_serial8250_port uart_data[] = {
+- {
+- .mapbase = IXP4XX_UART1_BASE_PHYS,
+- .membase = (char __iomem *)IXP4XX_UART1_BASE_VIRT +
+- REG_OFFSET,
+- .irq = IRQ_IXP4XX_UART1,
+- .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+- .iotype = UPIO_MEM,
+- .regshift = 2,
+- .uartclk = IXP4XX_UART_XTAL,
+- },
+- {
+- .mapbase = IXP4XX_UART2_BASE_PHYS,
+- .membase = (char __iomem *)IXP4XX_UART2_BASE_VIRT +
+- REG_OFFSET,
+- .irq = IRQ_IXP4XX_UART2,
+- .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+- .iotype = UPIO_MEM,
+- .regshift = 2,
+- .uartclk = IXP4XX_UART_XTAL,
+- },
+- { },
+-};
+-
+-static struct platform_device device_uarts = {
+- .name = "serial8250",
+- .id = PLAT8250_DEV_PLATFORM,
+- .dev.platform_data = uart_data,
+- .num_resources = 2,
+- .resource = uart_resources,
+-};
+-
+-
+-/* Built-in 10/100 Ethernet MAC interfaces */
+-static struct resource eth_npeb_resources[] = {
+- {
+- .start = IXP4XX_EthB_BASE_PHYS,
+- .end = IXP4XX_EthB_BASE_PHYS + 0x0fff,
+- .flags = IORESOURCE_MEM,
+- },
+-};
+-
+-static struct resource eth_npec_resources[] = {
+- {
+- .start = IXP4XX_EthC_BASE_PHYS,
+- .end = IXP4XX_EthC_BASE_PHYS + 0x0fff,
+- .flags = IORESOURCE_MEM,
+- },
+-};
+-
+-static struct eth_plat_info eth_plat[] = {
+- {
+- .phy = 0,
+- .rxq = 3,
+- .txreadyq = 32,
+- }, {
+- .phy = 1,
+- .rxq = 4,
+- .txreadyq = 33,
+- }
+-};
+-
+-static struct platform_device device_eth_tab[] = {
+- {
+- .name = "ixp4xx_eth",
+- .id = IXP4XX_ETH_NPEB,
+- .dev.platform_data = eth_plat,
+- .num_resources = ARRAY_SIZE(eth_npeb_resources),
+- .resource = eth_npeb_resources,
+- }, {
+- .name = "ixp4xx_eth",
+- .id = IXP4XX_ETH_NPEC,
+- .dev.platform_data = eth_plat + 1,
+- .num_resources = ARRAY_SIZE(eth_npec_resources),
+- .resource = eth_npec_resources,
+- }
+-};
+-
+-
+-/* IXP425 2 synchronous serial ports */
+-static struct hss_plat_info hss_plat[] = {
+- {
+- .set_clock = hss_set_clock,
+- .open = hss_open,
+- .close = hss_close,
+- .txreadyq = 34,
+- }, {
+- .set_clock = hss_set_clock,
+- .open = hss_open,
+- .close = hss_close,
+- .txreadyq = 35,
+- }
+-};
+-
+-static struct platform_device device_hss_tab[] = {
+- {
+- .name = "ixp4xx_hss",
+- .id = 0,
+- .dev.platform_data = hss_plat,
+- }, {
+- .name = "ixp4xx_hss",
+- .id = 1,
+- .dev.platform_data = hss_plat + 1,
+- }
+-};
+-
+-
+-static struct platform_device *device_tab[7] __initdata = {
+- &device_flash, /* index 0 */
+-};
+-
+-static inline u8 __init flash_readb(u8 __iomem *flash, u32 addr)
+-{
+-#ifdef __ARMEB__
+- return __raw_readb(flash + addr);
+-#else
+- return __raw_readb(flash + (addr ^ 3));
+-#endif
+-}
+-
+-static inline u16 __init flash_readw(u8 __iomem *flash, u32 addr)
+-{
+-#ifdef __ARMEB__
+- return __raw_readw(flash + addr);
+-#else
+- return __raw_readw(flash + (addr ^ 2));
+-#endif
+-}
+-
+-static void __init gmlr_init(void)
+-{
+- u8 __iomem *flash;
+- int i, devices = 1; /* flash */
+-
+- ixp4xx_sys_init();
+-
+- if ((flash = ioremap(IXP4XX_EXP_BUS_BASE_PHYS, 0x80)) == NULL)
+- printk(KERN_ERR "goramo-mlr: unable to access system"
+- " configuration data\n");
+- else {
+- system_rev = __raw_readl(flash + CFG_REV);
+- hw_bits = __raw_readl(flash + CFG_HW_BITS);
+-
+- for (i = 0; i < ETH_ALEN; i++) {
+- eth_plat[0].hwaddr[i] =
+- flash_readb(flash, CFG_ETH0_ADDRESS + i);
+- eth_plat[1].hwaddr[i] =
+- flash_readb(flash, CFG_ETH1_ADDRESS + i);
+- }
+-
+- __raw_writew(FLASH_CMD_READ_ID, flash);
+- system_serial_high = flash_readw(flash, FLASH_SER_OFF);
+- system_serial_high <<= 16;
+- system_serial_high |= flash_readw(flash, FLASH_SER_OFF + 2);
+- system_serial_low = flash_readw(flash, FLASH_SER_OFF + 4);
+- system_serial_low <<= 16;
+- system_serial_low |= flash_readw(flash, FLASH_SER_OFF + 6);
+- __raw_writew(FLASH_CMD_READ_ARRAY, flash);
+-
+- iounmap(flash);
+- }
+-
+- switch (hw_bits & (CFG_HW_HAS_UART0 | CFG_HW_HAS_UART1)) {
+- case CFG_HW_HAS_UART0:
+- memset(&uart_data[1], 0, sizeof(uart_data[1]));
+- device_uarts.num_resources = 1;
+- break;
+-
+- case CFG_HW_HAS_UART1:
+- device_uarts.dev.platform_data = &uart_data[1];
+- device_uarts.resource = &uart_resources[1];
+- device_uarts.num_resources = 1;
+- break;
+- }
+- if (hw_bits & (CFG_HW_HAS_UART0 | CFG_HW_HAS_UART1))
+- device_tab[devices++] = &device_uarts; /* max index 1 */
+-
+- if (hw_bits & CFG_HW_HAS_ETH0)
+- device_tab[devices++] = &device_eth_tab[0]; /* max index 2 */
+- if (hw_bits & CFG_HW_HAS_ETH1)
+- device_tab[devices++] = &device_eth_tab[1]; /* max index 3 */
+-
+- if (hw_bits & CFG_HW_HAS_HSS0)
+- device_tab[devices++] = &device_hss_tab[0]; /* max index 4 */
+- if (hw_bits & CFG_HW_HAS_HSS1)
+- device_tab[devices++] = &device_hss_tab[1]; /* max index 5 */
+-
+- hss_plat[0].timer_freq = ixp4xx_timer_freq;
+- hss_plat[1].timer_freq = ixp4xx_timer_freq;
+-
+- gpio_request(GPIO_SCL, "SCL/clock");
+- gpio_request(GPIO_SDA, "SDA/data");
+- gpio_request(GPIO_STR, "strobe");
+- gpio_request(GPIO_HSS0_RTS_N, "HSS0 RTS");
+- gpio_request(GPIO_HSS1_RTS_N, "HSS1 RTS");
+- gpio_request(GPIO_HSS0_DCD_N, "HSS0 DCD");
+- gpio_request(GPIO_HSS1_DCD_N, "HSS1 DCD");
+-
+- gpio_direction_output(GPIO_SCL, 1);
+- gpio_direction_output(GPIO_SDA, 1);
+- gpio_direction_output(GPIO_STR, 0);
+- gpio_direction_output(GPIO_HSS0_RTS_N, 1);
+- gpio_direction_output(GPIO_HSS1_RTS_N, 1);
+- gpio_direction_input(GPIO_HSS0_DCD_N);
+- gpio_direction_input(GPIO_HSS1_DCD_N);
+- irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), IRQ_TYPE_EDGE_BOTH);
+- irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N), IRQ_TYPE_EDGE_BOTH);
+-
+- set_control(CONTROL_HSS0_DTR_N, 1);
+- set_control(CONTROL_HSS1_DTR_N, 1);
+- set_control(CONTROL_EEPROM_WC_N, 1);
+- set_control(CONTROL_PCI_RESET_N, 1);
+- output_control();
+-
+- msleep(1); /* Wait for PCI devices to initialize */
+-
+- flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
+- flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
+-
+- platform_add_devices(device_tab, devices);
+-}
+-
+-
+-#ifdef CONFIG_PCI
+-static void __init gmlr_pci_preinit(void)
+-{
+- irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA), IRQ_TYPE_LEVEL_LOW);
+- irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB), IRQ_TYPE_LEVEL_LOW);
+- irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC), IRQ_TYPE_LEVEL_LOW);
+- irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI), IRQ_TYPE_LEVEL_LOW);
+- ixp4xx_pci_preinit();
+-}
+-
+-static void __init gmlr_pci_postinit(void)
+-{
+- if ((hw_bits & CFG_HW_USB_PORTS) >= 2 &&
+- (hw_bits & CFG_HW_USB_PORTS) < 5) {
+- /* need to adjust number of USB ports on NEC chip */
+- u32 value, addr = BIT(32 - SLOT_NEC) | 0xE0;
+- if (!ixp4xx_pci_read(addr, NP_CMD_CONFIGREAD, &value)) {
+- value &= ~7;
+- value |= (hw_bits & CFG_HW_USB_PORTS);
+- ixp4xx_pci_write(addr, NP_CMD_CONFIGWRITE, value);
+- }
+- }
+-}
+-
+-static int __init gmlr_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+-{
+- switch(slot) {
+- case SLOT_ETHA: return IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA);
+- case SLOT_ETHB: return IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB);
+- case SLOT_NEC: return IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC);
+- default: return IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI);
+- }
+-}
+-
+-static struct hw_pci gmlr_hw_pci __initdata = {
+- .nr_controllers = 1,
+- .ops = &ixp4xx_ops,
+- .preinit = gmlr_pci_preinit,
+- .postinit = gmlr_pci_postinit,
+- .setup = ixp4xx_setup,
+- .map_irq = gmlr_map_irq,
+-};
+-
+-static int __init gmlr_pci_init(void)
+-{
+- if (machine_is_goramo_mlr() &&
+- (hw_bits & (CFG_HW_USB_PORTS | CFG_HW_HAS_PCI_SLOT)))
+- pci_common_init(&gmlr_hw_pci);
+- return 0;
+-}
+-
+-subsys_initcall(gmlr_pci_init);
+-#endif /* CONFIG_PCI */
+-
+-
+-MACHINE_START(GORAMO_MLR, "MultiLink")
+- /* Maintainer: Krzysztof Halasa */
+- .map_io = ixp4xx_map_io,
+- .init_early = ixp4xx_init_early,
+- .init_irq = ixp4xx_init_irq,
+- .init_time = ixp4xx_timer_init,
+- .atag_offset = 0x100,
+- .init_machine = gmlr_init,
+-#if defined(CONFIG_PCI)
+- .dma_zone_size = SZ_64M,
+-#endif
+- .restart = ixp4xx_restart,
+-MACHINE_END
+diff --git a/include/linux/platform_data/wan_ixp4xx_hss.h b/include/linux/platform_data/wan_ixp4xx_hss.h
+deleted file mode 100644
+index d525a0feb9e1..000000000000
+--- a/include/linux/platform_data/wan_ixp4xx_hss.h
++++ /dev/null
+@@ -1,17 +0,0 @@
+-/* SPDX-License-Identifier: GPL-2.0 */
+-#ifndef __PLATFORM_DATA_WAN_IXP4XX_HSS_H
+-#define __PLATFORM_DATA_WAN_IXP4XX_HSS_H
+-
+-#include <linux/types.h>
+-
+-/* Information about built-in HSS (synchronous serial) interfaces */
+-struct hss_plat_info {
+- int (*set_clock)(int port, unsigned int clock_type);
+- int (*open)(int port, void *pdev,
+- void (*set_carrier_cb)(void *pdev, int carrier));
+- void (*close)(int port, void *pdev);
+- u8 txreadyq;
+- u32 timer_freq;
+-};
+-
+-#endif
+--
+2.20.1
+
--- /dev/null
+From 0ac230e413c8e5cada53320c063b9d84b336cd62 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Fri, 11 Feb 2022 23:32:28 +0100
+Subject: [PATCH 04/14] ARM: ixp4xx: Delete old PCI driver
+
+We are just using the new PCI driver in the proper PCI host
+drivers folder: drivers/pci/controller/pci-ixp4xx.c.
+
+The new driver does not support indirect PCI but it has
+turned out noone is using this. If the feature is desired
+we have ways to implement it, suggested by John Linville.
+
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Link: https://lore.kernel.org/r/20220211223238.648934-4-linus.walleij@linaro.org
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ arch/arm/Kconfig | 2 -
+ arch/arm/mach-ixp4xx/Kconfig | 35 --
+ arch/arm/mach-ixp4xx/Makefile | 14 +-
+ arch/arm/mach-ixp4xx/common-pci.c | 451 ---------------
+ arch/arm/mach-ixp4xx/common.c | 28 -
+ arch/arm/mach-ixp4xx/include/mach/hardware.h | 6 -
+ arch/arm/mach-ixp4xx/include/mach/io.h | 545 -------------------
+ arch/arm/mach-ixp4xx/include/mach/platform.h | 4 -
+ 8 files changed, 1 insertion(+), 1084 deletions(-)
+ delete mode 100644 arch/arm/mach-ixp4xx/common-pci.c
+ delete mode 100644 arch/arm/mach-ixp4xx/include/mach/io.h
+
+diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
+index fabe39169b12..3a95203236d2 100644
+--- a/arch/arm/Kconfig
++++ b/arch/arm/Kconfig
+@@ -391,8 +391,6 @@ config ARCH_IXP4XX
+ select HAVE_PCI
+ select IXP4XX_IRQ
+ select IXP4XX_TIMER
+- # With the new PCI driver this is not needed
+- select NEED_MACH_IO_H if IXP4XX_PCI_LEGACY
+ select USB_EHCI_BIG_ENDIAN_DESC
+ select USB_EHCI_BIG_ENDIAN_MMIO
+ help
+diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig
+index 0fac12cb31a6..495cbfd2358d 100644
+--- a/arch/arm/mach-ixp4xx/Kconfig
++++ b/arch/arm/mach-ixp4xx/Kconfig
+@@ -24,41 +24,6 @@ config ARCH_PRPMC1100
+ PrPCM1100 Processor Mezanine Module. For more information on
+ this platform, see <file:Documentation/arm/ixp4xx.rst>.
+
+-comment "IXP4xx Options"
+-
+-config IXP4XX_PCI_LEGACY
+- bool "IXP4xx legacy PCI driver support"
+- depends on PCI
+- help
+- Selects legacy PCI driver.
+- Not recommended for new development.
+-
+-config IXP4XX_INDIRECT_PCI
+- bool "Use indirect PCI memory access"
+- depends on IXP4XX_PCI_LEGACY
+- help
+- IXP4xx provides two methods of accessing PCI memory space:
+-
+- 1) A direct mapped window from 0x48000000 to 0x4BFFFFFF (64MB).
+- To access PCI via this space, we simply ioremap() the BAR
+- into the kernel and we can use the standard read[bwl]/write[bwl]
+- macros. This is the preferred method due to speed but it
+- limits the system to just 64MB of PCI memory. This can be
+- problematic if using video cards and other memory-heavy devices.
+-
+- 2) If > 64MB of memory space is required, the IXP4xx can be
+- configured to use indirect registers to access the whole PCI
+- memory space. This currently allows for up to 1 GB (0x10000000
+- to 0x4FFFFFFF) of memory on the bus. The disadvantage of this
+- is that every PCI access requires three local register accesses
+- plus a spinlock, but in some cases the performance hit is
+- acceptable. In addition, you cannot mmap() PCI devices in this
+- case due to the indirect nature of the PCI window.
+-
+- By default, the direct method is used. Choose this option if you
+- need to use the indirect method instead. If you don't know
+- what you need, leave this option unselected.
+-
+ endmenu
+
+ endif
+diff --git a/arch/arm/mach-ixp4xx/Makefile b/arch/arm/mach-ixp4xx/Makefile
+index 83719704a626..4ebe35227bf6 100644
+--- a/arch/arm/mach-ixp4xx/Makefile
++++ b/arch/arm/mach-ixp4xx/Makefile
+@@ -1,14 +1,2 @@
+ # SPDX-License-Identifier: GPL-2.0
+-#
+-# Makefile for the linux kernel.
+-#
+-
+-obj-pci-y :=
+-obj-pci-n :=
+-
+-# Device tree platform
+-obj-pci-$(CONFIG_MACH_IXP4XX_OF) += ixp4xx-of.o
+-
+-obj-y += common.o
+-
+-obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o
++obj-y += ixp4xx-of.o common.o
+diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c
+deleted file mode 100644
+index 893c19c254e3..000000000000
+--- a/arch/arm/mach-ixp4xx/common-pci.c
++++ /dev/null
+@@ -1,451 +0,0 @@
+-// SPDX-License-Identifier: GPL-2.0-only
+-/*
+- * arch/arm/mach-ixp4xx/common-pci.c
+- *
+- * IXP4XX PCI routines for all platforms
+- *
+- * Maintainer: Deepak Saxena <dsaxena@plexity.net>
+- *
+- * Copyright (C) 2002 Intel Corporation.
+- * Copyright (C) 2003 Greg Ungerer <gerg@snapgear.com>
+- * Copyright (C) 2003-2004 MontaVista Software, Inc.
+- */
+-
+-#include <linux/sched.h>
+-#include <linux/kernel.h>
+-#include <linux/pci.h>
+-#include <linux/interrupt.h>
+-#include <linux/mm.h>
+-#include <linux/init.h>
+-#include <linux/ioport.h>
+-#include <linux/slab.h>
+-#include <linux/delay.h>
+-#include <linux/device.h>
+-#include <linux/io.h>
+-#include <linux/export.h>
+-#include <asm/dma-mapping.h>
+-
+-#include <asm/cputype.h>
+-#include <asm/irq.h>
+-#include <linux/sizes.h>
+-#include <asm/mach/pci.h>
+-#include <mach/hardware.h>
+-
+-
+-/*
+- * IXP4xx PCI read function is dependent on whether we are
+- * running A0 or B0 (AppleGate) silicon.
+- */
+-int (*ixp4xx_pci_read)(u32 addr, u32 cmd, u32* data);
+-
+-/*
+- * Base address for PCI register region
+- */
+-unsigned long ixp4xx_pci_reg_base = 0;
+-
+-/*
+- * PCI cfg an I/O routines are done by programming a
+- * command/byte enable register, and then read/writing
+- * the data from a data register. We need to ensure
+- * these transactions are atomic or we will end up
+- * with corrupt data on the bus or in a driver.
+- */
+-static DEFINE_RAW_SPINLOCK(ixp4xx_pci_lock);
+-
+-/*
+- * Read from PCI config space
+- */
+-static void crp_read(u32 ad_cbe, u32 *data)
+-{
+- unsigned long flags;
+- raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags);
+- *PCI_CRP_AD_CBE = ad_cbe;
+- *data = *PCI_CRP_RDATA;
+- raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
+-}
+-
+-/*
+- * Write to PCI config space
+- */
+-static void crp_write(u32 ad_cbe, u32 data)
+-{
+- unsigned long flags;
+- raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags);
+- *PCI_CRP_AD_CBE = CRP_AD_CBE_WRITE | ad_cbe;
+- *PCI_CRP_WDATA = data;
+- raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
+-}
+-
+-static inline int check_master_abort(void)
+-{
+- /* check Master Abort bit after access */
+- unsigned long isr = *PCI_ISR;
+-
+- if (isr & PCI_ISR_PFE) {
+- /* make sure the Master Abort bit is reset */
+- *PCI_ISR = PCI_ISR_PFE;
+- pr_debug("%s failed\n", __func__);
+- return 1;
+- }
+-
+- return 0;
+-}
+-
+-int ixp4xx_pci_read_errata(u32 addr, u32 cmd, u32* data)
+-{
+- unsigned long flags;
+- int retval = 0;
+- int i;
+-
+- raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags);
+-
+- *PCI_NP_AD = addr;
+-
+- /*
+- * PCI workaround - only works if NP PCI space reads have
+- * no side effects!!! Read 8 times. last one will be good.
+- */
+- for (i = 0; i < 8; i++) {
+- *PCI_NP_CBE = cmd;
+- *data = *PCI_NP_RDATA;
+- *data = *PCI_NP_RDATA;
+- }
+-
+- if(check_master_abort())
+- retval = 1;
+-
+- raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
+- return retval;
+-}
+-
+-int ixp4xx_pci_read_no_errata(u32 addr, u32 cmd, u32* data)
+-{
+- unsigned long flags;
+- int retval = 0;
+-
+- raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags);
+-
+- *PCI_NP_AD = addr;
+-
+- /* set up and execute the read */
+- *PCI_NP_CBE = cmd;
+-
+- /* the result of the read is now in NP_RDATA */
+- *data = *PCI_NP_RDATA;
+-
+- if(check_master_abort())
+- retval = 1;
+-
+- raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
+- return retval;
+-}
+-
+-int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data)
+-{
+- unsigned long flags;
+- int retval = 0;
+-
+- raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags);
+-
+- *PCI_NP_AD = addr;
+-
+- /* set up the write */
+- *PCI_NP_CBE = cmd;
+-
+- /* execute the write by writing to NP_WDATA */
+- *PCI_NP_WDATA = data;
+-
+- if(check_master_abort())
+- retval = 1;
+-
+- raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
+- return retval;
+-}
+-
+-static u32 ixp4xx_config_addr(u8 bus_num, u16 devfn, int where)
+-{
+- u32 addr;
+- if (!bus_num) {
+- /* type 0 */
+- addr = BIT(32-PCI_SLOT(devfn)) | ((PCI_FUNC(devfn)) << 8) |
+- (where & ~3);
+- } else {
+- /* type 1 */
+- addr = (bus_num << 16) | ((PCI_SLOT(devfn)) << 11) |
+- ((PCI_FUNC(devfn)) << 8) | (where & ~3) | 1;
+- }
+- return addr;
+-}
+-
+-/*
+- * Mask table, bits to mask for quantity of size 1, 2 or 4 bytes.
+- * 0 and 3 are not valid indexes...
+- */
+-static u32 bytemask[] = {
+- /*0*/ 0,
+- /*1*/ 0xff,
+- /*2*/ 0xffff,
+- /*3*/ 0,
+- /*4*/ 0xffffffff,
+-};
+-
+-static u32 local_byte_lane_enable_bits(u32 n, int size)
+-{
+- if (size == 1)
+- return (0xf & ~BIT(n)) << CRP_AD_CBE_BESL;
+- if (size == 2)
+- return (0xf & ~(BIT(n) | BIT(n+1))) << CRP_AD_CBE_BESL;
+- if (size == 4)
+- return 0;
+- return 0xffffffff;
+-}
+-
+-static int local_read_config(int where, int size, u32 *value)
+-{
+- u32 n, data;
+- pr_debug("local_read_config from %d size %d\n", where, size);
+- n = where % 4;
+- crp_read(where & ~3, &data);
+- *value = (data >> (8*n)) & bytemask[size];
+- pr_debug("local_read_config read %#x\n", *value);
+- return PCIBIOS_SUCCESSFUL;
+-}
+-
+-static int local_write_config(int where, int size, u32 value)
+-{
+- u32 n, byte_enables, data;
+- pr_debug("local_write_config %#x to %d size %d\n", value, where, size);
+- n = where % 4;
+- byte_enables = local_byte_lane_enable_bits(n, size);
+- if (byte_enables == 0xffffffff)
+- return PCIBIOS_BAD_REGISTER_NUMBER;
+- data = value << (8*n);
+- crp_write((where & ~3) | byte_enables, data);
+- return PCIBIOS_SUCCESSFUL;
+-}
+-
+-static u32 byte_lane_enable_bits(u32 n, int size)
+-{
+- if (size == 1)
+- return (0xf & ~BIT(n)) << 4;
+- if (size == 2)
+- return (0xf & ~(BIT(n) | BIT(n+1))) << 4;
+- if (size == 4)
+- return 0;
+- return 0xffffffff;
+-}
+-
+-static int ixp4xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
+-{
+- u32 n, byte_enables, addr, data;
+- u8 bus_num = bus->number;
+-
+- pr_debug("read_config from %d size %d dev %d:%d:%d\n", where, size,
+- bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn));
+-
+- *value = 0xffffffff;
+- n = where % 4;
+- byte_enables = byte_lane_enable_bits(n, size);
+- if (byte_enables == 0xffffffff)
+- return PCIBIOS_BAD_REGISTER_NUMBER;
+-
+- addr = ixp4xx_config_addr(bus_num, devfn, where);
+- if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_CONFIGREAD, &data))
+- return PCIBIOS_DEVICE_NOT_FOUND;
+-
+- *value = (data >> (8*n)) & bytemask[size];
+- pr_debug("read_config_byte read %#x\n", *value);
+- return PCIBIOS_SUCCESSFUL;
+-}
+-
+-static int ixp4xx_pci_write_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
+-{
+- u32 n, byte_enables, addr, data;
+- u8 bus_num = bus->number;
+-
+- pr_debug("write_config_byte %#x to %d size %d dev %d:%d:%d\n", value, where,
+- size, bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn));
+-
+- n = where % 4;
+- byte_enables = byte_lane_enable_bits(n, size);
+- if (byte_enables == 0xffffffff)
+- return PCIBIOS_BAD_REGISTER_NUMBER;
+-
+- addr = ixp4xx_config_addr(bus_num, devfn, where);
+- data = value << (8*n);
+- if (ixp4xx_pci_write(addr, byte_enables | NP_CMD_CONFIGWRITE, data))
+- return PCIBIOS_DEVICE_NOT_FOUND;
+-
+- return PCIBIOS_SUCCESSFUL;
+-}
+-
+-struct pci_ops ixp4xx_ops = {
+- .read = ixp4xx_pci_read_config,
+- .write = ixp4xx_pci_write_config,
+-};
+-
+-/*
+- * PCI abort handler
+- */
+-static int abort_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
+-{
+- u32 isr, status;
+-
+- isr = *PCI_ISR;
+- local_read_config(PCI_STATUS, 2, &status);
+- pr_debug("PCI: abort_handler addr = %#lx, isr = %#x, "
+- "status = %#x\n", addr, isr, status);
+-
+- /* make sure the Master Abort bit is reset */
+- *PCI_ISR = PCI_ISR_PFE;
+- status |= PCI_STATUS_REC_MASTER_ABORT;
+- local_write_config(PCI_STATUS, 2, status);
+-
+- /*
+- * If it was an imprecise abort, then we need to correct the
+- * return address to be _after_ the instruction.
+- */
+- if (fsr & (1 << 10))
+- regs->ARM_pc += 4;
+-
+- return 0;
+-}
+-
+-void __init ixp4xx_pci_preinit(void)
+-{
+- unsigned long cpuid = read_cpuid_id();
+-
+-#ifdef CONFIG_IXP4XX_INDIRECT_PCI
+- pcibios_min_mem = 0x10000000; /* 1 GB of indirect PCI MMIO space */
+-#else
+- pcibios_min_mem = 0x48000000; /* 64 MB of PCI MMIO space */
+-#endif
+- /*
+- * Determine which PCI read method to use.
+- * Rev 0 IXP425 requires workaround.
+- */
+- if (!(cpuid & 0xf) && cpu_is_ixp42x()) {
+- printk("PCI: IXP42x A0 silicon detected - "
+- "PCI Non-Prefetch Workaround Enabled\n");
+- ixp4xx_pci_read = ixp4xx_pci_read_errata;
+- } else
+- ixp4xx_pci_read = ixp4xx_pci_read_no_errata;
+-
+-
+- /* hook in our fault handler for PCI errors */
+- hook_fault_code(16+6, abort_handler, SIGBUS, 0,
+- "imprecise external abort");
+-
+- pr_debug("setup PCI-AHB(inbound) and AHB-PCI(outbound) address mappings\n");
+-
+- /*
+- * We use identity AHB->PCI address translation
+- * in the 0x48000000 to 0x4bffffff address space
+- */
+- *PCI_PCIMEMBASE = 0x48494A4B;
+-
+- /*
+- * We also use identity PCI->AHB address translation
+- * in 4 16MB BARs that begin at the physical memory start
+- */
+- *PCI_AHBMEMBASE = (PHYS_OFFSET & 0xFF000000) +
+- ((PHYS_OFFSET & 0xFF000000) >> 8) +
+- ((PHYS_OFFSET & 0xFF000000) >> 16) +
+- ((PHYS_OFFSET & 0xFF000000) >> 24) +
+- 0x00010203;
+-
+- if (*PCI_CSR & PCI_CSR_HOST) {
+- printk("PCI: IXP4xx is host\n");
+-
+- pr_debug("setup BARs in controller\n");
+-
+- /*
+- * We configure the PCI inbound memory windows to be
+- * 1:1 mapped to SDRAM
+- */
+- local_write_config(PCI_BASE_ADDRESS_0, 4, PHYS_OFFSET);
+- local_write_config(PCI_BASE_ADDRESS_1, 4, PHYS_OFFSET + SZ_16M);
+- local_write_config(PCI_BASE_ADDRESS_2, 4, PHYS_OFFSET + SZ_32M);
+- local_write_config(PCI_BASE_ADDRESS_3, 4,
+- PHYS_OFFSET + SZ_32M + SZ_16M);
+-
+- /*
+- * Enable CSR window at 64 MiB to allow PCI masters
+- * to continue prefetching past 64 MiB boundary.
+- */
+- local_write_config(PCI_BASE_ADDRESS_4, 4, PHYS_OFFSET + SZ_64M);
+-
+- /*
+- * Enable the IO window to be way up high, at 0xfffffc00
+- */
+- local_write_config(PCI_BASE_ADDRESS_5, 4, 0xfffffc01);
+- local_write_config(0x40, 4, 0x000080FF); /* No TRDY time limit */
+- } else {
+- printk("PCI: IXP4xx is target - No bus scan performed\n");
+- }
+-
+- printk("PCI: IXP4xx Using %s access for memory space\n",
+-#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+- "direct"
+-#else
+- "indirect"
+-#endif
+- );
+-
+- pr_debug("clear error bits in ISR\n");
+- *PCI_ISR = PCI_ISR_PSE | PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE;
+-
+- /*
+- * Set Initialize Complete in PCI Control Register: allow IXP4XX to
+- * respond to PCI configuration cycles. Specify that the AHB bus is
+- * operating in big endian mode. Set up byte lane swapping between
+- * little-endian PCI and the big-endian AHB bus
+- */
+-#ifdef __ARMEB__
+- *PCI_CSR = PCI_CSR_IC | PCI_CSR_ABE | PCI_CSR_PDS | PCI_CSR_ADS;
+-#else
+- *PCI_CSR = PCI_CSR_IC | PCI_CSR_ABE;
+-#endif
+-
+- pr_debug("DONE\n");
+-}
+-
+-int ixp4xx_setup(int nr, struct pci_sys_data *sys)
+-{
+- struct resource *res;
+-
+- if (nr >= 1)
+- return 0;
+-
+- res = kcalloc(2, sizeof(*res), GFP_KERNEL);
+- if (res == NULL) {
+- /*
+- * If we're out of memory this early, something is wrong,
+- * so we might as well catch it here.
+- */
+- panic("PCI: unable to allocate resources?\n");
+- }
+-
+- local_write_config(PCI_COMMAND, 2, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+-
+- res[0].name = "PCI I/O Space";
+- res[0].start = 0x00000000;
+- res[0].end = 0x0000ffff;
+- res[0].flags = IORESOURCE_IO;
+-
+- res[1].name = "PCI Memory Space";
+- res[1].start = PCIBIOS_MIN_MEM;
+- res[1].end = PCIBIOS_MAX_MEM;
+- res[1].flags = IORESOURCE_MEM;
+-
+- request_resource(&ioport_resource, &res[0]);
+- request_resource(&iomem_resource, &res[1]);
+-
+- pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset);
+- pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset);
+-
+- return 1;
+-}
+-
+-EXPORT_SYMBOL(ixp4xx_pci_read);
+-EXPORT_SYMBOL(ixp4xx_pci_write);
+diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
+index cdc720f54daa..1116bd2df687 100644
+--- a/arch/arm/mach-ixp4xx/common.c
++++ b/arch/arm/mach-ixp4xx/common.c
+@@ -411,38 +411,10 @@ int dma_set_coherent_mask(struct device *dev, u64 mask)
+ }
+ EXPORT_SYMBOL(dma_set_coherent_mask);
+
+-#ifdef CONFIG_IXP4XX_INDIRECT_PCI
+-/*
+- * In the case of using indirect PCI, we simply return the actual PCI
+- * address and our read/write implementation use that to drive the
+- * access registers. If something outside of PCI is ioremap'd, we
+- * fallback to the default.
+- */
+-
+-static void __iomem *ixp4xx_ioremap_caller(phys_addr_t addr, size_t size,
+- unsigned int mtype, void *caller)
+-{
+- if (!is_pci_memory(addr))
+- return __arm_ioremap_caller(addr, size, mtype, caller);
+-
+- return (void __iomem *)addr;
+-}
+-
+-static void ixp4xx_iounmap(volatile void __iomem *addr)
+-{
+- if (!is_pci_memory((__force u32)addr))
+- __iounmap(addr);
+-}
+-#endif
+-
+ void __init ixp4xx_init_early(void)
+ {
+ platform_notify = ixp4xx_platform_notify;
+ #ifdef CONFIG_PCI
+ platform_notify_remove = ixp4xx_platform_notify_remove;
+ #endif
+-#ifdef CONFIG_IXP4XX_INDIRECT_PCI
+- arch_ioremap_caller = ixp4xx_ioremap_caller;
+- arch_iounmap = ixp4xx_iounmap;
+-#endif
+ }
+diff --git a/arch/arm/mach-ixp4xx/include/mach/hardware.h b/arch/arm/mach-ixp4xx/include/mach/hardware.h
+index b2b7301ce503..41f28fb8e63f 100644
+--- a/arch/arm/mach-ixp4xx/include/mach/hardware.h
++++ b/arch/arm/mach-ixp4xx/include/mach/hardware.h
+@@ -13,12 +13,6 @@
+ #ifndef __ASM_ARCH_HARDWARE_H__
+ #define __ASM_ARCH_HARDWARE_H__
+
+-#ifdef CONFIG_IXP4XX_INDIRECT_PCI
+-#define PCIBIOS_MAX_MEM 0x4FFFFFFF
+-#else
+-#define PCIBIOS_MAX_MEM 0x4BFFFFFF
+-#endif
+-
+ /* Register locations and bits */
+ #include "ixp4xx-regs.h"
+
+diff --git a/arch/arm/mach-ixp4xx/include/mach/io.h b/arch/arm/mach-ixp4xx/include/mach/io.h
+deleted file mode 100644
+index 014cf6dcaf8b..000000000000
+--- a/arch/arm/mach-ixp4xx/include/mach/io.h
++++ /dev/null
+@@ -1,545 +0,0 @@
+-/* SPDX-License-Identifier: GPL-2.0-only */
+-/*
+- * arch/arm/mach-ixp4xx/include/mach/io.h
+- *
+- * Author: Deepak Saxena <dsaxena@plexity.net>
+- *
+- * Copyright (C) 2002-2005 MontaVista Software, Inc.
+- */
+-
+-#ifndef __ASM_ARM_ARCH_IO_H
+-#define __ASM_ARM_ARCH_IO_H
+-
+-#include <linux/bitops.h>
+-
+-#include <mach/hardware.h>
+-
+-extern int (*ixp4xx_pci_read)(u32 addr, u32 cmd, u32* data);
+-extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data);
+-
+-
+-/*
+- * IXP4xx provides two methods of accessing PCI memory space:
+- *
+- * 1) A direct mapped window from 0x48000000 to 0x4BFFFFFF (64MB).
+- * To access PCI via this space, we simply ioremap() the BAR
+- * into the kernel and we can use the standard read[bwl]/write[bwl]
+- * macros. This is the preffered method due to speed but it
+- * limits the system to just 64MB of PCI memory. This can be
+- * problematic if using video cards and other memory-heavy targets.
+- *
+- * 2) If > 64MB of memory space is required, the IXP4xx can use indirect
+- * registers to access the whole 4 GB of PCI memory space (as we do below
+- * for I/O transactions). This allows currently for up to 1 GB (0x10000000
+- * to 0x4FFFFFFF) of memory on the bus. The disadvantage of this is that
+- * every PCI access requires three local register accesses plus a spinlock,
+- * but in some cases the performance hit is acceptable. In addition, you
+- * cannot mmap() PCI devices in this case.
+- */
+-#ifdef CONFIG_IXP4XX_INDIRECT_PCI
+-
+-/*
+- * In the case of using indirect PCI, we simply return the actual PCI
+- * address and our read/write implementation use that to drive the
+- * access registers. If something outside of PCI is ioremap'd, we
+- * fallback to the default.
+- */
+-
+-extern unsigned long pcibios_min_mem;
+-static inline int is_pci_memory(u32 addr)
+-{
+- return (addr >= pcibios_min_mem) && (addr <= 0x4FFFFFFF);
+-}
+-
+-#define writeb(v, p) __indirect_writeb(v, p)
+-#define writew(v, p) __indirect_writew(v, p)
+-#define writel(v, p) __indirect_writel(v, p)
+-
+-#define writeb_relaxed(v, p) __indirect_writeb(v, p)
+-#define writew_relaxed(v, p) __indirect_writew(v, p)
+-#define writel_relaxed(v, p) __indirect_writel(v, p)
+-
+-#define writesb(p, v, l) __indirect_writesb(p, v, l)
+-#define writesw(p, v, l) __indirect_writesw(p, v, l)
+-#define writesl(p, v, l) __indirect_writesl(p, v, l)
+-
+-#define readb(p) __indirect_readb(p)
+-#define readw(p) __indirect_readw(p)
+-#define readl(p) __indirect_readl(p)
+-
+-#define readb_relaxed(p) __indirect_readb(p)
+-#define readw_relaxed(p) __indirect_readw(p)
+-#define readl_relaxed(p) __indirect_readl(p)
+-
+-#define readsb(p, v, l) __indirect_readsb(p, v, l)
+-#define readsw(p, v, l) __indirect_readsw(p, v, l)
+-#define readsl(p, v, l) __indirect_readsl(p, v, l)
+-
+-static inline void __indirect_writeb(u8 value, volatile void __iomem *p)
+-{
+- u32 addr = (u32)p;
+- u32 n, byte_enables, data;
+-
+- if (!is_pci_memory(addr)) {
+- __raw_writeb(value, p);
+- return;
+- }
+-
+- n = addr % 4;
+- byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
+- data = value << (8*n);
+- ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data);
+-}
+-
+-static inline void __indirect_writesb(volatile void __iomem *bus_addr,
+- const void *p, int count)
+-{
+- const u8 *vaddr = p;
+-
+- while (count--)
+- writeb(*vaddr++, bus_addr);
+-}
+-
+-static inline void __indirect_writew(u16 value, volatile void __iomem *p)
+-{
+- u32 addr = (u32)p;
+- u32 n, byte_enables, data;
+-
+- if (!is_pci_memory(addr)) {
+- __raw_writew(value, p);
+- return;
+- }
+-
+- n = addr % 4;
+- byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
+- data = value << (8*n);
+- ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data);
+-}
+-
+-static inline void __indirect_writesw(volatile void __iomem *bus_addr,
+- const void *p, int count)
+-{
+- const u16 *vaddr = p;
+-
+- while (count--)
+- writew(*vaddr++, bus_addr);
+-}
+-
+-static inline void __indirect_writel(u32 value, volatile void __iomem *p)
+-{
+- u32 addr = (__force u32)p;
+-
+- if (!is_pci_memory(addr)) {
+- __raw_writel(value, p);
+- return;
+- }
+-
+- ixp4xx_pci_write(addr, NP_CMD_MEMWRITE, value);
+-}
+-
+-static inline void __indirect_writesl(volatile void __iomem *bus_addr,
+- const void *p, int count)
+-{
+- const u32 *vaddr = p;
+- while (count--)
+- writel(*vaddr++, bus_addr);
+-}
+-
+-static inline u8 __indirect_readb(const volatile void __iomem *p)
+-{
+- u32 addr = (u32)p;
+- u32 n, byte_enables, data;
+-
+- if (!is_pci_memory(addr))
+- return __raw_readb(p);
+-
+- n = addr % 4;
+- byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
+- if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_MEMREAD, &data))
+- return 0xff;
+-
+- return data >> (8*n);
+-}
+-
+-static inline void __indirect_readsb(const volatile void __iomem *bus_addr,
+- void *p, u32 count)
+-{
+- u8 *vaddr = p;
+-
+- while (count--)
+- *vaddr++ = readb(bus_addr);
+-}
+-
+-static inline u16 __indirect_readw(const volatile void __iomem *p)
+-{
+- u32 addr = (u32)p;
+- u32 n, byte_enables, data;
+-
+- if (!is_pci_memory(addr))
+- return __raw_readw(p);
+-
+- n = addr % 4;
+- byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
+- if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_MEMREAD, &data))
+- return 0xffff;
+-
+- return data>>(8*n);
+-}
+-
+-static inline void __indirect_readsw(const volatile void __iomem *bus_addr,
+- void *p, u32 count)
+-{
+- u16 *vaddr = p;
+-
+- while (count--)
+- *vaddr++ = readw(bus_addr);
+-}
+-
+-static inline u32 __indirect_readl(const volatile void __iomem *p)
+-{
+- u32 addr = (__force u32)p;
+- u32 data;
+-
+- if (!is_pci_memory(addr))
+- return __raw_readl(p);
+-
+- if (ixp4xx_pci_read(addr, NP_CMD_MEMREAD, &data))
+- return 0xffffffff;
+-
+- return data;
+-}
+-
+-static inline void __indirect_readsl(const volatile void __iomem *bus_addr,
+- void *p, u32 count)
+-{
+- u32 *vaddr = p;
+-
+- while (count--)
+- *vaddr++ = readl(bus_addr);
+-}
+-
+-
+-/*
+- * We can use the built-in functions b/c they end up calling writeb/readb
+- */
+-#define memset_io(c,v,l) _memset_io((c),(v),(l))
+-#define memcpy_fromio(a,c,l) _memcpy_fromio((a),(c),(l))
+-#define memcpy_toio(c,a,l) _memcpy_toio((c),(a),(l))
+-
+-#endif /* CONFIG_IXP4XX_INDIRECT_PCI */
+-
+-#ifndef CONFIG_PCI
+-
+-#define __io(v) __typesafe_io(v)
+-
+-#else
+-
+-/*
+- * IXP4xx does not have a transparent cpu -> PCI I/O translation
+- * window. Instead, it has a set of registers that must be tweaked
+- * with the proper byte lanes, command types, and address for the
+- * transaction. This means that we need to override the default
+- * I/O functions.
+- */
+-
+-#define outb outb
+-static inline void outb(u8 value, u32 addr)
+-{
+- u32 n, byte_enables, data;
+- n = addr % 4;
+- byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
+- data = value << (8*n);
+- ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data);
+-}
+-
+-#define outsb outsb
+-static inline void outsb(u32 io_addr, const void *p, u32 count)
+-{
+- const u8 *vaddr = p;
+-
+- while (count--)
+- outb(*vaddr++, io_addr);
+-}
+-
+-#define outw outw
+-static inline void outw(u16 value, u32 addr)
+-{
+- u32 n, byte_enables, data;
+- n = addr % 4;
+- byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
+- data = value << (8*n);
+- ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data);
+-}
+-
+-#define outsw outsw
+-static inline void outsw(u32 io_addr, const void *p, u32 count)
+-{
+- const u16 *vaddr = p;
+- while (count--)
+- outw(cpu_to_le16(*vaddr++), io_addr);
+-}
+-
+-#define outl outl
+-static inline void outl(u32 value, u32 addr)
+-{
+- ixp4xx_pci_write(addr, NP_CMD_IOWRITE, value);
+-}
+-
+-#define outsl outsl
+-static inline void outsl(u32 io_addr, const void *p, u32 count)
+-{
+- const u32 *vaddr = p;
+- while (count--)
+- outl(cpu_to_le32(*vaddr++), io_addr);
+-}
+-
+-#define inb inb
+-static inline u8 inb(u32 addr)
+-{
+- u32 n, byte_enables, data;
+- n = addr % 4;
+- byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
+- if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_IOREAD, &data))
+- return 0xff;
+-
+- return data >> (8*n);
+-}
+-
+-#define insb insb
+-static inline void insb(u32 io_addr, void *p, u32 count)
+-{
+- u8 *vaddr = p;
+- while (count--)
+- *vaddr++ = inb(io_addr);
+-}
+-
+-#define inw inw
+-static inline u16 inw(u32 addr)
+-{
+- u32 n, byte_enables, data;
+- n = addr % 4;
+- byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
+- if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_IOREAD, &data))
+- return 0xffff;
+-
+- return data>>(8*n);
+-}
+-
+-#define insw insw
+-static inline void insw(u32 io_addr, void *p, u32 count)
+-{
+- u16 *vaddr = p;
+- while (count--)
+- *vaddr++ = le16_to_cpu(inw(io_addr));
+-}
+-
+-#define inl inl
+-static inline u32 inl(u32 addr)
+-{
+- u32 data;
+- if (ixp4xx_pci_read(addr, NP_CMD_IOREAD, &data))
+- return 0xffffffff;
+-
+- return data;
+-}
+-
+-#define insl insl
+-static inline void insl(u32 io_addr, void *p, u32 count)
+-{
+- u32 *vaddr = p;
+- while (count--)
+- *vaddr++ = le32_to_cpu(inl(io_addr));
+-}
+-
+-#define PIO_OFFSET 0x10000UL
+-#define PIO_MASK 0x0ffffUL
+-
+-#define __is_io_address(p) (((unsigned long)p >= PIO_OFFSET) && \
+- ((unsigned long)p <= (PIO_MASK + PIO_OFFSET)))
+-
+-#define ioread8(p) ioread8(p)
+-static inline u8 ioread8(const void __iomem *addr)
+-{
+- unsigned long port = (unsigned long __force)addr;
+- if (__is_io_address(port))
+- return (unsigned int)inb(port & PIO_MASK);
+- else
+-#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+- return (unsigned int)__raw_readb(addr);
+-#else
+- return (unsigned int)__indirect_readb(addr);
+-#endif
+-}
+-
+-#define ioread8_rep(p, v, c) ioread8_rep(p, v, c)
+-static inline void ioread8_rep(const void __iomem *addr, void *vaddr, u32 count)
+-{
+- unsigned long port = (unsigned long __force)addr;
+- if (__is_io_address(port))
+- insb(port & PIO_MASK, vaddr, count);
+- else
+-#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+- __raw_readsb(addr, vaddr, count);
+-#else
+- __indirect_readsb(addr, vaddr, count);
+-#endif
+-}
+-
+-#define ioread16(p) ioread16(p)
+-static inline u16 ioread16(const void __iomem *addr)
+-{
+- unsigned long port = (unsigned long __force)addr;
+- if (__is_io_address(port))
+- return (unsigned int)inw(port & PIO_MASK);
+- else
+-#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+- return le16_to_cpu((__force __le16)__raw_readw(addr));
+-#else
+- return (unsigned int)__indirect_readw(addr);
+-#endif
+-}
+-
+-#define ioread16_rep(p, v, c) ioread16_rep(p, v, c)
+-static inline void ioread16_rep(const void __iomem *addr, void *vaddr,
+- u32 count)
+-{
+- unsigned long port = (unsigned long __force)addr;
+- if (__is_io_address(port))
+- insw(port & PIO_MASK, vaddr, count);
+- else
+-#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+- __raw_readsw(addr, vaddr, count);
+-#else
+- __indirect_readsw(addr, vaddr, count);
+-#endif
+-}
+-
+-#define ioread32(p) ioread32(p)
+-static inline u32 ioread32(const void __iomem *addr)
+-{
+- unsigned long port = (unsigned long __force)addr;
+- if (__is_io_address(port))
+- return (unsigned int)inl(port & PIO_MASK);
+- else {
+-#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+- return le32_to_cpu((__force __le32)__raw_readl(addr));
+-#else
+- return (unsigned int)__indirect_readl(addr);
+-#endif
+- }
+-}
+-
+-#define ioread32_rep(p, v, c) ioread32_rep(p, v, c)
+-static inline void ioread32_rep(const void __iomem *addr, void *vaddr,
+- u32 count)
+-{
+- unsigned long port = (unsigned long __force)addr;
+- if (__is_io_address(port))
+- insl(port & PIO_MASK, vaddr, count);
+- else
+-#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+- __raw_readsl(addr, vaddr, count);
+-#else
+- __indirect_readsl(addr, vaddr, count);
+-#endif
+-}
+-
+-#define iowrite8(v, p) iowrite8(v, p)
+-static inline void iowrite8(u8 value, void __iomem *addr)
+-{
+- unsigned long port = (unsigned long __force)addr;
+- if (__is_io_address(port))
+- outb(value, port & PIO_MASK);
+- else
+-#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+- __raw_writeb(value, addr);
+-#else
+- __indirect_writeb(value, addr);
+-#endif
+-}
+-
+-#define iowrite8_rep(p, v, c) iowrite8_rep(p, v, c)
+-static inline void iowrite8_rep(void __iomem *addr, const void *vaddr,
+- u32 count)
+-{
+- unsigned long port = (unsigned long __force)addr;
+- if (__is_io_address(port))
+- outsb(port & PIO_MASK, vaddr, count);
+- else
+-#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+- __raw_writesb(addr, vaddr, count);
+-#else
+- __indirect_writesb(addr, vaddr, count);
+-#endif
+-}
+-
+-#define iowrite16(v, p) iowrite16(v, p)
+-static inline void iowrite16(u16 value, void __iomem *addr)
+-{
+- unsigned long port = (unsigned long __force)addr;
+- if (__is_io_address(port))
+- outw(value, port & PIO_MASK);
+- else
+-#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+- __raw_writew(cpu_to_le16(value), addr);
+-#else
+- __indirect_writew(value, addr);
+-#endif
+-}
+-
+-#define iowrite16_rep(p, v, c) iowrite16_rep(p, v, c)
+-static inline void iowrite16_rep(void __iomem *addr, const void *vaddr,
+- u32 count)
+-{
+- unsigned long port = (unsigned long __force)addr;
+- if (__is_io_address(port))
+- outsw(port & PIO_MASK, vaddr, count);
+- else
+-#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+- __raw_writesw(addr, vaddr, count);
+-#else
+- __indirect_writesw(addr, vaddr, count);
+-#endif
+-}
+-
+-#define iowrite32(v, p) iowrite32(v, p)
+-static inline void iowrite32(u32 value, void __iomem *addr)
+-{
+- unsigned long port = (unsigned long __force)addr;
+- if (__is_io_address(port))
+- outl(value, port & PIO_MASK);
+- else
+-#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+- __raw_writel((u32 __force)cpu_to_le32(value), addr);
+-#else
+- __indirect_writel(value, addr);
+-#endif
+-}
+-
+-#define iowrite32_rep(p, v, c) iowrite32_rep(p, v, c)
+-static inline void iowrite32_rep(void __iomem *addr, const void *vaddr,
+- u32 count)
+-{
+- unsigned long port = (unsigned long __force)addr;
+- if (__is_io_address(port))
+- outsl(port & PIO_MASK, vaddr, count);
+- else
+-#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+- __raw_writesl(addr, vaddr, count);
+-#else
+- __indirect_writesl(addr, vaddr, count);
+-#endif
+-}
+-
+-#define ioport_map(port, nr) ioport_map(port, nr)
+-static inline void __iomem *ioport_map(unsigned long port, unsigned int nr)
+-{
+- return ((void __iomem*)((port) + PIO_OFFSET));
+-}
+-#define ioport_unmap(addr) ioport_unmap(addr)
+-static inline void ioport_unmap(void __iomem *addr)
+-{
+-}
+-#endif /* CONFIG_PCI */
+-
+-#endif /* __ASM_ARM_ARCH_IO_H */
+diff --git a/arch/arm/mach-ixp4xx/include/mach/platform.h b/arch/arm/mach-ixp4xx/include/mach/platform.h
+index d8b4df96db08..f9ec07f00be0 100644
+--- a/arch/arm/mach-ixp4xx/include/mach/platform.h
++++ b/arch/arm/mach-ixp4xx/include/mach/platform.h
+@@ -93,10 +93,6 @@ extern void ixp4xx_init_irq(void);
+ extern void ixp4xx_sys_init(void);
+ extern void ixp4xx_timer_init(void);
+ extern void ixp4xx_restart(enum reboot_mode, const char *);
+-extern void ixp4xx_pci_preinit(void);
+-struct pci_sys_data;
+-extern int ixp4xx_setup(int nr, struct pci_sys_data *sys);
+-extern struct pci_ops ixp4xx_ops;
+
+ #endif // __ASSEMBLY__
+
+--
+2.20.1
+
--- /dev/null
+From 0b78be6f432d99f30b9e30588a9173a965ebdd8a Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Fri, 11 Feb 2022 23:32:29 +0100
+Subject: [PATCH 05/14] ARM: ixp4xx: Drop stale Kconfig entry
+
+The Kconfig entry for the Motorola PrPMC1100 was added to the
+kernel in the very first git import for v2.6.12-rc2 in 2005.
+But it was never used for anything since it was not accompanied
+by any boardfile.
+
+It is easy to support with a device tree if someone needs it,
+delete this stray Kconfig.
+
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Link: https://lore.kernel.org/r/20220211223238.648934-5-linus.walleij@linaro.org
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ arch/arm/mach-ixp4xx/Kconfig | 7 -------
+ 1 file changed, 7 deletions(-)
+
+diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig
+index 495cbfd2358d..f41ba3f42fc8 100644
+--- a/arch/arm/mach-ixp4xx/Kconfig
++++ b/arch/arm/mach-ixp4xx/Kconfig
+@@ -17,13 +17,6 @@ config MACH_IXP4XX_OF
+ help
+ Say 'Y' here to support Device Tree-based IXP4xx platforms.
+
+-config ARCH_PRPMC1100
+- bool "PrPMC1100"
+- help
+- Say 'Y' here if you want your kernel to support the Motorola
+- PrPCM1100 Processor Mezanine Module. For more information on
+- this platform, see <file:Documentation/arm/ixp4xx.rst>.
+-
+ endmenu
+
+ endif
+--
+2.20.1
+
--- /dev/null
+From bb3f6e55a9018271ca99f85abebaff66db3c2b8b Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Fri, 11 Feb 2022 23:32:30 +0100
+Subject: [PATCH 06/14] ARM: ixp4xx: Drop UDC info setting function
+
+The IXP4xx has a callback to "set UDC info" for the USB but
+nothing in the kernel is using it. Delete it.
+
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Link: https://lore.kernel.org/r/20220211223238.648934-6-linus.walleij@linaro.org
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ arch/arm/mach-ixp4xx/common.c | 11 -----------
+ arch/arm/mach-ixp4xx/include/mach/udc.h | 8 --------
+ 2 files changed, 19 deletions(-)
+ delete mode 100644 arch/arm/mach-ixp4xx/include/mach/udc.h
+
+diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
+index 1116bd2df687..5192cf621f5b 100644
+--- a/arch/arm/mach-ixp4xx/common.c
++++ b/arch/arm/mach-ixp4xx/common.c
+@@ -31,7 +31,6 @@
+ #include <linux/irqchip/irq-ixp4xx.h>
+ #include <linux/platform_data/timer-ixp4xx.h>
+ #include <linux/dma-map-ops.h>
+-#include <mach/udc.h>
+ #include <mach/hardware.h>
+ #include <linux/uaccess.h>
+ #include <asm/page.h>
+@@ -113,13 +112,6 @@ void __init ixp4xx_timer_init(void)
+ IXP4XX_TIMER_FREQ);
+ }
+
+-static struct pxa2xx_udc_mach_info ixp4xx_udc_info;
+-
+-void __init ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info)
+-{
+- memcpy(&ixp4xx_udc_info, info, sizeof *info);
+-}
+-
+ static struct resource ixp4xx_udc_resources[] = {
+ [0] = {
+ .start = 0xc800b000,
+@@ -160,9 +152,6 @@ static struct platform_device ixp4xx_udc_device = {
+ .id = -1,
+ .num_resources = 2,
+ .resource = ixp4xx_udc_resources,
+- .dev = {
+- .platform_data = &ixp4xx_udc_info,
+- },
+ };
+
+ static struct resource ixp4xx_npe_resources[] = {
+diff --git a/arch/arm/mach-ixp4xx/include/mach/udc.h b/arch/arm/mach-ixp4xx/include/mach/udc.h
+deleted file mode 100644
+index 7bd8b96c8843..000000000000
+--- a/arch/arm/mach-ixp4xx/include/mach/udc.h
++++ /dev/null
+@@ -1,8 +0,0 @@
+-/*
+- * arch/arm/mach-ixp4xx/include/mach/udc.h
+- *
+- */
+-#include <linux/platform_data/pxa2xx_udc.h>
+-
+-extern void ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info);
+-
+--
+2.20.1
+
--- /dev/null
+From b50113cbdd1340c31e85e4cfc5f5e81ce9cbb2aa Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Fri, 11 Feb 2022 23:32:31 +0100
+Subject: [PATCH 07/14] soc: ixp4xx: Add features from regmap helper
+
+If we want to read the CFG2 register on the expansion bus and
+apply the inversion and check for some hardcoded versions this
+helper comes in handy.
+
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Link: https://lore.kernel.org/r/20220211223238.648934-7-linus.walleij@linaro.org
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ include/linux/soc/ixp4xx/cpu.h | 24 ++++++++++++++++++++++++
+ 1 file changed, 24 insertions(+)
+
+diff --git a/include/linux/soc/ixp4xx/cpu.h b/include/linux/soc/ixp4xx/cpu.h
+index 88bd8de0e803..48c2e241ac83 100644
+--- a/include/linux/soc/ixp4xx/cpu.h
++++ b/include/linux/soc/ixp4xx/cpu.h
+@@ -9,6 +9,7 @@
+ #define __SOC_IXP4XX_CPU_H__
+
+ #include <linux/io.h>
++#include <linux/regmap.h>
+ #ifdef CONFIG_ARM
+ #include <asm/cputype.h>
+ #endif
+@@ -23,6 +24,9 @@
+ #define IXP46X_PROCESSOR_ID_VALUE 0x69054200 /* including IXP455 */
+ #define IXP46X_PROCESSOR_ID_MASK 0xfffffff0
+
++/* Feature register in the expansion bus controller */
++#define IXP4XX_EXP_CNFG2 0x2c
++
+ /* "fuse" bits of IXP_EXP_CFG2 */
+ /* All IXP4xx CPUs */
+ #define IXP4XX_FEATURE_RCOMP (1 << 0)
+@@ -89,6 +93,22 @@
+
+ u32 ixp4xx_read_feature_bits(void);
+ void ixp4xx_write_feature_bits(u32 value);
++static inline u32 cpu_ixp4xx_features(struct regmap *rmap)
++{
++ u32 val;
++
++ regmap_read(rmap, IXP4XX_EXP_CNFG2, &val);
++ /* For some reason this register is inverted */
++ val = ~val;
++ if (cpu_is_ixp42x_rev_a0())
++ return IXP42X_FEATURE_MASK & ~(IXP4XX_FEATURE_RCOMP |
++ IXP4XX_FEATURE_AES);
++ if (cpu_is_ixp42x())
++ return val & IXP42X_FEATURE_MASK;
++ if (cpu_is_ixp43x())
++ return val & IXP43X_FEATURE_MASK;
++ return val & IXP46X_FEATURE_MASK;
++}
+ #else
+ #define cpu_is_ixp42x_rev_a0() 0
+ #define cpu_is_ixp42x() 0
+@@ -101,6 +121,10 @@ static inline u32 ixp4xx_read_feature_bits(void)
+ static inline void ixp4xx_write_feature_bits(u32 value)
+ {
+ }
++static inline u32 cpu_ixp4xx_features(struct regmap *rmap)
++{
++ return 0;
++}
+ #endif
+
+ #endif /* _ASM_ARCH_CPU_H */
+--
+2.20.1
+
--- /dev/null
+From 8754a7e61c766fbc533c627b56ff181550dca00e Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Fri, 11 Feb 2022 23:32:32 +0100
+Subject: [PATCH 08/14] soc: ixp4xx-npe: Access syscon regs using regmap
+
+If we access the syscon (expansion bus config registers) using the
+syscon regmap instead of relying on direct accessor functions,
+we do not need to call this static code in the machine
+(arch/arm/mach-ixp4xx/common.c) which makes things less dependent
+on custom machine-dependent code.
+
+Look up the syscon regmap and handle the error: this will make
+deferred probe work with relation to the syscon.
+
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Link: https://lore.kernel.org/r/20220211223238.648934-8-linus.walleij@linaro.org
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/soc/ixp4xx/Kconfig | 1 +
+ drivers/soc/ixp4xx/ixp4xx-npe.c | 33 ++++++++++++++++++++++++---------
+ include/linux/soc/ixp4xx/npe.h | 2 ++
+ 3 files changed, 27 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/soc/ixp4xx/Kconfig b/drivers/soc/ixp4xx/Kconfig
+index e3eb19b85fa4..c55f0c9ae513 100644
+--- a/drivers/soc/ixp4xx/Kconfig
++++ b/drivers/soc/ixp4xx/Kconfig
+@@ -12,6 +12,7 @@ config IXP4XX_QMGR
+ config IXP4XX_NPE
+ tristate "IXP4xx Network Processor Engine support"
+ select FW_LOADER
++ select MFD_SYSCON
+ help
+ This driver supports IXP4xx built-in network coprocessors
+ and is automatically selected by Ethernet and HSS drivers.
+diff --git a/drivers/soc/ixp4xx/ixp4xx-npe.c b/drivers/soc/ixp4xx/ixp4xx-npe.c
+index f490c4ca51f5..613935cb6a48 100644
+--- a/drivers/soc/ixp4xx/ixp4xx-npe.c
++++ b/drivers/soc/ixp4xx/ixp4xx-npe.c
+@@ -16,6 +16,7 @@
+ #include <linux/firmware.h>
+ #include <linux/io.h>
+ #include <linux/kernel.h>
++#include <linux/mfd/syscon.h>
+ #include <linux/module.h>
+ #include <linux/of.h>
+ #include <linux/of_platform.h>
+@@ -284,6 +285,7 @@ static int __must_check npe_logical_reg_write32(struct npe *npe, u32 addr,
+
+ static int npe_reset(struct npe *npe)
+ {
++ u32 reset_bit = (IXP4XX_FEATURE_RESET_NPEA << npe->id);
+ u32 val, ctl, exec_count, ctx_reg2;
+ int i;
+
+@@ -380,16 +382,19 @@ static int npe_reset(struct npe *npe)
+ __raw_writel(0, &npe->regs->action_points[3]);
+ __raw_writel(0, &npe->regs->watch_count);
+
+- val = ixp4xx_read_feature_bits();
++ /*
++ * We need to work on cached values here because the register
++ * will read inverted but needs to be written non-inverted.
++ */
++ val = cpu_ixp4xx_features(npe->rmap);
+ /* reset the NPE */
+- ixp4xx_write_feature_bits(val &
+- ~(IXP4XX_FEATURE_RESET_NPEA << npe->id));
++ regmap_write(npe->rmap, IXP4XX_EXP_CNFG2, val & ~reset_bit);
+ /* deassert reset */
+- ixp4xx_write_feature_bits(val |
+- (IXP4XX_FEATURE_RESET_NPEA << npe->id));
++ regmap_write(npe->rmap, IXP4XX_EXP_CNFG2, val | reset_bit);
++
+ for (i = 0; i < MAX_RETRIES; i++) {
+- if (ixp4xx_read_feature_bits() &
+- (IXP4XX_FEATURE_RESET_NPEA << npe->id))
++ val = cpu_ixp4xx_features(npe->rmap);
++ if (val & reset_bit)
+ break; /* NPE is back alive */
+ udelay(1);
+ }
+@@ -683,6 +688,14 @@ static int ixp4xx_npe_probe(struct platform_device *pdev)
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct resource *res;
++ struct regmap *rmap;
++ u32 val;
++
++ /* This system has only one syscon, so fetch it */
++ rmap = syscon_regmap_lookup_by_compatible("syscon");
++ if (IS_ERR(rmap))
++ return dev_err_probe(dev, PTR_ERR(rmap),
++ "failed to look up syscon\n");
+
+ for (i = 0; i < NPE_COUNT; i++) {
+ struct npe *npe = &npe_tab[i];
+@@ -691,8 +704,9 @@ static int ixp4xx_npe_probe(struct platform_device *pdev)
+ if (!res)
+ return -ENODEV;
+
+- if (!(ixp4xx_read_feature_bits() &
+- (IXP4XX_FEATURE_RESET_NPEA << i))) {
++ val = cpu_ixp4xx_features(rmap);
++
++ if (!(val & (IXP4XX_FEATURE_RESET_NPEA << i))) {
+ dev_info(dev, "NPE%d at %pR not available\n",
+ i, res);
+ continue; /* NPE already disabled or not present */
+@@ -700,6 +714,7 @@ static int ixp4xx_npe_probe(struct platform_device *pdev)
+ npe->regs = devm_ioremap_resource(dev, res);
+ if (IS_ERR(npe->regs))
+ return PTR_ERR(npe->regs);
++ npe->rmap = rmap;
+
+ if (npe_reset(npe)) {
+ dev_info(dev, "NPE%d at %pR does not reset\n",
+diff --git a/include/linux/soc/ixp4xx/npe.h b/include/linux/soc/ixp4xx/npe.h
+index 2a91f465d456..9efeac777da1 100644
+--- a/include/linux/soc/ixp4xx/npe.h
++++ b/include/linux/soc/ixp4xx/npe.h
+@@ -3,6 +3,7 @@
+ #define __IXP4XX_NPE_H
+
+ #include <linux/kernel.h>
++#include <linux/regmap.h>
+
+ extern const char *npe_names[];
+
+@@ -17,6 +18,7 @@ struct npe_regs {
+
+ struct npe {
+ struct npe_regs __iomem *regs;
++ struct regmap *rmap;
+ int id;
+ int valid;
+ };
+--
+2.20.1
+
--- /dev/null
+From c8200f4e7267545a384fb86a4630f76958ab9df6 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Fri, 11 Feb 2022 23:32:33 +0100
+Subject: [PATCH 09/14] net: ixp4xx_eth: Drop platform data support
+
+All IXP4xx platforms are converted to device tree, the platform
+data path is no longer used. Drop the code and custom include,
+confine the driver in its own file.
+
+Depend on OF and remove ifdefs around this, as we are all probing
+from OF now.
+
+Cc: David S. Miller <davem@davemloft.net>
+Cc: Jakub Kicinski <kuba@kernel.org>
+Cc: netdev@vger.kernel.org
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Acked-by: Jakub Kicinski <kuba@kernel.org>
+Link: https://lore.kernel.org/r/20220211223238.648934-9-linus.walleij@linaro.org
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/net/ethernet/xscale/Kconfig | 4 +-
+ drivers/net/ethernet/xscale/ixp4xx_eth.c | 85 ++++++------------------
+ include/linux/platform_data/eth_ixp4xx.h | 21 ------
+ 3 files changed, 21 insertions(+), 89 deletions(-)
+ delete mode 100644 include/linux/platform_data/eth_ixp4xx.h
+
+diff --git a/drivers/net/ethernet/xscale/Kconfig b/drivers/net/ethernet/xscale/Kconfig
+index 0e878fa6e322..b33f64c54b0e 100644
+--- a/drivers/net/ethernet/xscale/Kconfig
++++ b/drivers/net/ethernet/xscale/Kconfig
+@@ -20,9 +20,9 @@ if NET_VENDOR_XSCALE
+
+ config IXP4XX_ETH
+ tristate "Intel IXP4xx Ethernet support"
+- depends on ARM && ARCH_IXP4XX && IXP4XX_NPE && IXP4XX_QMGR
++ depends on ARM && ARCH_IXP4XX && IXP4XX_NPE && IXP4XX_QMGR && OF
+ select PHYLIB
+- select OF_MDIO if OF
++ select OF_MDIO
+ select NET_PTP_CLASSIFY
+ help
+ Say Y here if you want to use built-in Ethernet ports
+diff --git a/drivers/net/ethernet/xscale/ixp4xx_eth.c b/drivers/net/ethernet/xscale/ixp4xx_eth.c
+index df77a22d1b81..d947955621ee 100644
+--- a/drivers/net/ethernet/xscale/ixp4xx_eth.c
++++ b/drivers/net/ethernet/xscale/ixp4xx_eth.c
+@@ -30,7 +30,6 @@
+ #include <linux/of.h>
+ #include <linux/of_mdio.h>
+ #include <linux/phy.h>
+-#include <linux/platform_data/eth_ixp4xx.h>
+ #include <linux/platform_device.h>
+ #include <linux/ptp_classify.h>
+ #include <linux/slab.h>
+@@ -38,6 +37,11 @@
+ #include <linux/soc/ixp4xx/npe.h>
+ #include <linux/soc/ixp4xx/qmgr.h>
+ #include <linux/soc/ixp4xx/cpu.h>
++#include <linux/types.h>
++
++#define IXP4XX_ETH_NPEA 0x00
++#define IXP4XX_ETH_NPEB 0x10
++#define IXP4XX_ETH_NPEC 0x20
+
+ #include "ixp46x_ts.h"
+
+@@ -147,6 +151,16 @@ typedef void buffer_t;
+ #define free_buffer_irq kfree
+ #endif
+
++/* Information about built-in Ethernet MAC interfaces */
++struct eth_plat_info {
++ u8 phy; /* MII PHY ID, 0 - 31 */
++ u8 rxq; /* configurable, currently 0 - 31 only */
++ u8 txreadyq;
++ u8 hwaddr[6];
++ u8 npe; /* NPE instance used by this interface */
++ bool has_mdio; /* If this instance has an MDIO bus */
++};
++
+ struct eth_regs {
+ u32 tx_control[2], __res1[2]; /* 000 */
+ u32 rx_control[2], __res2[2]; /* 010 */
+@@ -1366,7 +1380,6 @@ static const struct net_device_ops ixp4xx_netdev_ops = {
+ .ndo_validate_addr = eth_validate_addr,
+ };
+
+-#ifdef CONFIG_OF
+ static struct eth_plat_info *ixp4xx_of_get_platdata(struct device *dev)
+ {
+ struct device_node *np = dev->of_node;
+@@ -1417,12 +1430,6 @@ static struct eth_plat_info *ixp4xx_of_get_platdata(struct device *dev)
+
+ return plat;
+ }
+-#else
+-static struct eth_plat_info *ixp4xx_of_get_platdata(struct device *dev)
+-{
+- return NULL;
+-}
+-#endif
+
+ static int ixp4xx_eth_probe(struct platform_device *pdev)
+ {
+@@ -1434,49 +1441,9 @@ static int ixp4xx_eth_probe(struct platform_device *pdev)
+ struct port *port;
+ int err;
+
+- if (np) {
+- plat = ixp4xx_of_get_platdata(dev);
+- if (!plat)
+- return -ENODEV;
+- } else {
+- plat = dev_get_platdata(dev);
+- if (!plat)
+- return -ENODEV;
+- plat->npe = pdev->id;
+- switch (plat->npe) {
+- case IXP4XX_ETH_NPEA:
+- /* If the MDIO bus is not up yet, defer probe */
+- break;
+- case IXP4XX_ETH_NPEB:
+- /* On all except IXP43x, NPE-B is used for the MDIO bus.
+- * If there is no NPE-B in the feature set, bail out,
+- * else we have the MDIO bus here.
+- */
+- if (!cpu_is_ixp43x()) {
+- if (!(ixp4xx_read_feature_bits() &
+- IXP4XX_FEATURE_NPEB_ETH0))
+- return -ENODEV;
+- /* Else register the MDIO bus on NPE-B */
+- plat->has_mdio = true;
+- }
+- break;
+- case IXP4XX_ETH_NPEC:
+- /* IXP43x lacks NPE-B and uses NPE-C for the MDIO bus
+- * access, if there is no NPE-C, no bus, nothing works,
+- * so bail out.
+- */
+- if (cpu_is_ixp43x()) {
+- if (!(ixp4xx_read_feature_bits() &
+- IXP4XX_FEATURE_NPEC_ETH))
+- return -ENODEV;
+- /* Else register the MDIO bus on NPE-B */
+- plat->has_mdio = true;
+- }
+- break;
+- default:
+- return -ENODEV;
+- }
+- }
++ plat = ixp4xx_of_get_platdata(dev);
++ if (!plat)
++ return -ENODEV;
+
+ if (!(ndev = devm_alloc_etherdev(dev, sizeof(struct port))))
+ return -ENOMEM;
+@@ -1530,21 +1497,7 @@ static int ixp4xx_eth_probe(struct platform_device *pdev)
+ __raw_writel(DEFAULT_CORE_CNTRL, &port->regs->core_control);
+ udelay(50);
+
+- if (np) {
+- phydev = of_phy_get_and_connect(ndev, np, ixp4xx_adjust_link);
+- } else {
+- phydev = mdiobus_get_phy(mdio_bus, plat->phy);
+- if (!phydev) {
+- err = -ENODEV;
+- dev_err(dev, "could not connect phydev (%d)\n", err);
+- goto err_free_mem;
+- }
+- err = phy_connect_direct(ndev, phydev, ixp4xx_adjust_link,
+- PHY_INTERFACE_MODE_MII);
+- if (err)
+- goto err_free_mem;
+-
+- }
++ phydev = of_phy_get_and_connect(ndev, np, ixp4xx_adjust_link);
+ if (!phydev) {
+ err = -ENODEV;
+ dev_err(dev, "no phydev\n");
+diff --git a/include/linux/platform_data/eth_ixp4xx.h b/include/linux/platform_data/eth_ixp4xx.h
+deleted file mode 100644
+index 114b0940729f..000000000000
+--- a/include/linux/platform_data/eth_ixp4xx.h
++++ /dev/null
+@@ -1,21 +0,0 @@
+-/* SPDX-License-Identifier: GPL-2.0 */
+-#ifndef __PLATFORM_DATA_ETH_IXP4XX
+-#define __PLATFORM_DATA_ETH_IXP4XX
+-
+-#include <linux/types.h>
+-
+-#define IXP4XX_ETH_NPEA 0x00
+-#define IXP4XX_ETH_NPEB 0x10
+-#define IXP4XX_ETH_NPEC 0x20
+-
+-/* Information about built-in Ethernet MAC interfaces */
+-struct eth_plat_info {
+- u8 phy; /* MII PHY ID, 0 - 31 */
+- u8 rxq; /* configurable, currently 0 - 31 only */
+- u8 txreadyq;
+- u8 hwaddr[6];
+- u8 npe; /* NPE instance used by this interface */
+- bool has_mdio; /* If this instance has an MDIO bus */
+-};
+-
+-#endif
+--
+2.20.1
+
--- /dev/null
+From e1721881ab51821fffe4b76364faf33e1cd7b95a Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Fri, 11 Feb 2022 23:32:34 +0100
+Subject: [PATCH 10/14] net: ixp4xx_hss: Check features using syscon
+
+If we access the syscon (expansion bus config registers) using the
+syscon regmap instead of relying on direct accessor functions,
+we do not need to call this static code in the machine
+(arch/arm/mach-ixp4xx/common.c) which makes things less dependent
+on custom machine-dependent code.
+
+Look up the syscon regmap and handle the error: this will make
+deferred probe work with relation to the syscon.
+
+Select the syscon in Kconfig and depend on OF so we know that
+all we need will be available.
+
+Cc: David S. Miller <davem@davemloft.net>
+Cc: Jakub Kicinski <kuba@kernel.org>
+Cc: netdev@vger.kernel.org
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Acked-by: Jakub Kicinski <kuba@kernel.org>
+Link: https://lore.kernel.org/r/20220211223238.648934-10-linus.walleij@linaro.org
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/net/wan/Kconfig | 3 ++-
+ drivers/net/wan/ixp4xx_hss.c | 39 ++++++++++++++++++++----------------
+ 2 files changed, 24 insertions(+), 18 deletions(-)
+
+diff --git a/drivers/net/wan/Kconfig b/drivers/net/wan/Kconfig
+index 592a8389fc5a..140780ac1745 100644
+--- a/drivers/net/wan/Kconfig
++++ b/drivers/net/wan/Kconfig
+@@ -293,7 +293,8 @@ config SLIC_DS26522
+ config IXP4XX_HSS
+ tristate "Intel IXP4xx HSS (synchronous serial port) support"
+ depends on HDLC && IXP4XX_NPE && IXP4XX_QMGR
+- depends on ARCH_IXP4XX
++ depends on ARCH_IXP4XX && OF
++ select MFD_SYSCON
+ help
+ Say Y here if you want to use built-in HSS ports
+ on IXP4xx processor.
+diff --git a/drivers/net/wan/ixp4xx_hss.c b/drivers/net/wan/ixp4xx_hss.c
+index 0b7d9f2f2b8b..863c3e34e136 100644
+--- a/drivers/net/wan/ixp4xx_hss.c
++++ b/drivers/net/wan/ixp4xx_hss.c
+@@ -16,8 +16,10 @@
+ #include <linux/hdlc.h>
+ #include <linux/io.h>
+ #include <linux/kernel.h>
++#include <linux/mfd/syscon.h>
+ #include <linux/platform_device.h>
+ #include <linux/poll.h>
++#include <linux/regmap.h>
+ #include <linux/slab.h>
+ #include <linux/gpio/consumer.h>
+ #include <linux/of.h>
+@@ -1389,9 +1391,28 @@ static int ixp4xx_hss_probe(struct platform_device *pdev)
+ struct device *dev = &pdev->dev;
+ struct net_device *ndev;
+ struct device_node *np;
++ struct regmap *rmap;
+ struct port *port;
+ hdlc_device *hdlc;
+ int err;
++ u32 val;
++
++ /*
++ * Go into the syscon and check if we have the HSS and HDLC
++ * features available, else this will not work.
++ */
++ rmap = syscon_regmap_lookup_by_compatible("syscon");
++ if (IS_ERR(rmap))
++ return dev_err_probe(dev, PTR_ERR(rmap),
++ "failed to look up syscon\n");
++
++ val = cpu_ixp4xx_features(rmap);
++
++ if ((val & (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS)) !=
++ (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS)) {
++ dev_err(dev, "HDLC and HSS feature unavailable in platform\n");
++ return -ENODEV;
++ }
+
+ np = dev->of_node;
+
+@@ -1516,25 +1537,9 @@ static struct platform_driver ixp4xx_hss_driver = {
+ .probe = ixp4xx_hss_probe,
+ .remove = ixp4xx_hss_remove,
+ };
+-
+-static int __init hss_init_module(void)
+-{
+- if ((ixp4xx_read_feature_bits() &
+- (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS)) !=
+- (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS))
+- return -ENODEV;
+-
+- return platform_driver_register(&ixp4xx_hss_driver);
+-}
+-
+-static void __exit hss_cleanup_module(void)
+-{
+- platform_driver_unregister(&ixp4xx_hss_driver);
+-}
++module_platform_driver(ixp4xx_hss_driver);
+
+ MODULE_AUTHOR("Krzysztof Halasa");
+ MODULE_DESCRIPTION("Intel IXP4xx HSS driver");
+ MODULE_LICENSE("GPL v2");
+ MODULE_ALIAS("platform:ixp4xx_hss");
+-module_init(hss_init_module);
+-module_exit(hss_cleanup_module);
+--
+2.20.1
+
--- /dev/null
+From 3059dfa52c07a9b6d770e87dc21b68f4295239c5 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Fri, 11 Feb 2022 23:32:35 +0100
+Subject: [PATCH 11/14] ARM: ixp4xx: Remove feature bit accessors
+
+We switched users of the accessors over to using syscon to inspect
+the bits, or removed the need for checking them. Delete these
+accessors.
+
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Link: https://lore.kernel.org/r/20220211223238.648934-11-linus.walleij@linaro.org
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ arch/arm/mach-ixp4xx/common.c | 21 ---------------------
+ include/linux/soc/ixp4xx/cpu.h | 10 ----------
+ 2 files changed, 31 deletions(-)
+
+diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
+index 5192cf621f5b..4e51514ace6d 100644
+--- a/arch/arm/mach-ixp4xx/common.c
++++ b/arch/arm/mach-ixp4xx/common.c
+@@ -43,27 +43,6 @@
+
+ #include "irqs.h"
+
+-u32 ixp4xx_read_feature_bits(void)
+-{
+- u32 val = ~__raw_readl(IXP4XX_EXP_CFG2);
+-
+- if (cpu_is_ixp42x_rev_a0())
+- return IXP42X_FEATURE_MASK & ~(IXP4XX_FEATURE_RCOMP |
+- IXP4XX_FEATURE_AES);
+- if (cpu_is_ixp42x())
+- return val & IXP42X_FEATURE_MASK;
+- if (cpu_is_ixp43x())
+- return val & IXP43X_FEATURE_MASK;
+- return val & IXP46X_FEATURE_MASK;
+-}
+-EXPORT_SYMBOL(ixp4xx_read_feature_bits);
+-
+-void ixp4xx_write_feature_bits(u32 value)
+-{
+- __raw_writel(~value, IXP4XX_EXP_CFG2);
+-}
+-EXPORT_SYMBOL(ixp4xx_write_feature_bits);
+-
+ #define IXP4XX_TIMER_FREQ 66666000
+
+ /*************************************************************************
+diff --git a/include/linux/soc/ixp4xx/cpu.h b/include/linux/soc/ixp4xx/cpu.h
+index 48c2e241ac83..f526ac33afea 100644
+--- a/include/linux/soc/ixp4xx/cpu.h
++++ b/include/linux/soc/ixp4xx/cpu.h
+@@ -90,9 +90,6 @@
+ IXP43X_PROCESSOR_ID_VALUE)
+ #define cpu_is_ixp46x() ((read_cpuid_id() & IXP46X_PROCESSOR_ID_MASK) == \
+ IXP46X_PROCESSOR_ID_VALUE)
+-
+-u32 ixp4xx_read_feature_bits(void);
+-void ixp4xx_write_feature_bits(u32 value);
+ static inline u32 cpu_ixp4xx_features(struct regmap *rmap)
+ {
+ u32 val;
+@@ -114,13 +111,6 @@ static inline u32 cpu_ixp4xx_features(struct regmap *rmap)
+ #define cpu_is_ixp42x() 0
+ #define cpu_is_ixp43x() 0
+ #define cpu_is_ixp46x() 0
+-static inline u32 ixp4xx_read_feature_bits(void)
+-{
+- return 0;
+-}
+-static inline void ixp4xx_write_feature_bits(u32 value)
+-{
+-}
+ static inline u32 cpu_ixp4xx_features(struct regmap *rmap)
+ {
+ return 0;
+--
+2.20.1
+
--- /dev/null
+From 00ba9357d18947859b7ef03a82c7f4185567ff0b Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Fri, 11 Feb 2022 23:32:36 +0100
+Subject: [PATCH 12/14] ARM: ixp4xx: Drop custom DMA coherency and bouncing
+
+The new PCI driver does not need any of this stuff, so just
+drop it.
+
+Cc: iommu@lists.linux-foundation.org
+Reviewed-by: Christoph Hellwig <hch@lst.de>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Link: https://lore.kernel.org/r/20220211223238.648934-12-linus.walleij@linaro.org
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ arch/arm/Kconfig | 5 ---
+ arch/arm/mach-ixp4xx/common.c | 57 -----------------------------------
+ kernel/dma/mapping.c | 2 --
+ 3 files changed, 64 deletions(-)
+
+diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
+index 3a95203236d2..ec0dbaf73a81 100644
+--- a/arch/arm/Kconfig
++++ b/arch/arm/Kconfig
+@@ -217,9 +217,6 @@ config ARCH_MAY_HAVE_PC_FDC
+ config ARCH_SUPPORTS_UPROBES
+ def_bool y
+
+-config ARCH_HAS_DMA_SET_COHERENT_MASK
+- bool
+-
+ config GENERIC_ISA_DMA
+ bool
+
+@@ -381,10 +378,8 @@ config ARCH_IOP32X
+ config ARCH_IXP4XX
+ bool "IXP4xx-based"
+ depends on MMU
+- select ARCH_HAS_DMA_SET_COHERENT_MASK
+ select ARCH_SUPPORTS_BIG_ENDIAN
+ select CPU_XSCALE
+- select DMABOUNCE if PCI
+ select GENERIC_IRQ_MULTI_HANDLER
+ select GPIO_IXP4XX
+ select GPIOLIB
+diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
+index 4e51514ace6d..310e1602fbfc 100644
+--- a/arch/arm/mach-ixp4xx/common.c
++++ b/arch/arm/mach-ixp4xx/common.c
+@@ -30,7 +30,6 @@
+ #include <linux/soc/ixp4xx/cpu.h>
+ #include <linux/irqchip/irq-ixp4xx.h>
+ #include <linux/platform_data/timer-ixp4xx.h>
+-#include <linux/dma-map-ops.h>
+ #include <mach/hardware.h>
+ #include <linux/uaccess.h>
+ #include <asm/page.h>
+@@ -330,59 +329,3 @@ void ixp4xx_restart(enum reboot_mode mode, const char *cmd)
+ *IXP4XX_OSWE = IXP4XX_WDT_RESET_ENABLE | IXP4XX_WDT_COUNT_ENABLE;
+ }
+ }
+-
+-#ifdef CONFIG_PCI
+-static int ixp4xx_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
+-{
+- return (dma_addr + size) > SZ_64M;
+-}
+-
+-static int ixp4xx_platform_notify_remove(struct device *dev)
+-{
+- if (dev_is_pci(dev))
+- dmabounce_unregister_dev(dev);
+-
+- return 0;
+-}
+-#endif
+-
+-/*
+- * Setup DMA mask to 64MB on PCI devices and 4 GB on all other things.
+- */
+-static int ixp4xx_platform_notify(struct device *dev)
+-{
+- dev->dma_mask = &dev->coherent_dma_mask;
+-
+-#ifdef CONFIG_PCI
+- if (dev_is_pci(dev)) {
+- dev->coherent_dma_mask = DMA_BIT_MASK(28); /* 64 MB */
+- dmabounce_register_dev(dev, 2048, 4096, ixp4xx_needs_bounce);
+- return 0;
+- }
+-#endif
+-
+- dev->coherent_dma_mask = DMA_BIT_MASK(32);
+- return 0;
+-}
+-
+-int dma_set_coherent_mask(struct device *dev, u64 mask)
+-{
+- if (dev_is_pci(dev))
+- mask &= DMA_BIT_MASK(28); /* 64 MB */
+-
+- if ((mask & DMA_BIT_MASK(28)) == DMA_BIT_MASK(28)) {
+- dev->coherent_dma_mask = mask;
+- return 0;
+- }
+-
+- return -EIO; /* device wanted sub-64MB mask */
+-}
+-EXPORT_SYMBOL(dma_set_coherent_mask);
+-
+-void __init ixp4xx_init_early(void)
+-{
+- platform_notify = ixp4xx_platform_notify;
+-#ifdef CONFIG_PCI
+- platform_notify_remove = ixp4xx_platform_notify_remove;
+-#endif
+-}
+diff --git a/kernel/dma/mapping.c b/kernel/dma/mapping.c
+index 9478eccd1c8e..559461a826ba 100644
+--- a/kernel/dma/mapping.c
++++ b/kernel/dma/mapping.c
+@@ -745,7 +745,6 @@ int dma_set_mask(struct device *dev, u64 mask)
+ }
+ EXPORT_SYMBOL(dma_set_mask);
+
+-#ifndef CONFIG_ARCH_HAS_DMA_SET_COHERENT_MASK
+ int dma_set_coherent_mask(struct device *dev, u64 mask)
+ {
+ /*
+@@ -761,7 +760,6 @@ int dma_set_coherent_mask(struct device *dev, u64 mask)
+ return 0;
+ }
+ EXPORT_SYMBOL(dma_set_coherent_mask);
+-#endif
+
+ size_t dma_max_mapping_size(struct device *dev)
+ {
+--
+2.20.1
+
--- /dev/null
+From 18b3b7b323196c11bc7e6cd28655b46482b2d33c Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Fri, 11 Feb 2022 23:32:37 +0100
+Subject: [PATCH 13/14] ARM: ixp4xx: Drop all common code
+
+After moving away from all the code we depend on in common we can
+get a clean device tree boot and delete the common code in
+arch/arm/mach-ixp4xx/common.c altogether.
+
+Two physical register addresses remain in use, just copy these
+verbatim into uncompress.h.
+
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Link: https://lore.kernel.org/r/20220211223238.648934-13-linus.walleij@linaro.org
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ arch/arm/mach-ixp4xx/Makefile | 2 +-
+ arch/arm/mach-ixp4xx/common.c | 331 ------------------
+ arch/arm/mach-ixp4xx/include/mach/hardware.h | 26 --
+ .../mach-ixp4xx/include/mach/ixp4xx-regs.h | 303 ----------------
+ arch/arm/mach-ixp4xx/include/mach/platform.h | 98 ------
+ .../arm/mach-ixp4xx/include/mach/uncompress.h | 4 +-
+ arch/arm/mach-ixp4xx/irqs.h | 64 ----
+ drivers/crypto/ixp4xx_crypto.c | 1 -
+ drivers/net/ethernet/xscale/ptp_ixp46x.c | 1 -
+ 9 files changed, 4 insertions(+), 826 deletions(-)
+ delete mode 100644 arch/arm/mach-ixp4xx/common.c
+ delete mode 100644 arch/arm/mach-ixp4xx/include/mach/hardware.h
+ delete mode 100644 arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
+ delete mode 100644 arch/arm/mach-ixp4xx/include/mach/platform.h
+ delete mode 100644 arch/arm/mach-ixp4xx/irqs.h
+
+diff --git a/arch/arm/mach-ixp4xx/Makefile b/arch/arm/mach-ixp4xx/Makefile
+index 4ebe35227bf6..3d1c9d854c7f 100644
+--- a/arch/arm/mach-ixp4xx/Makefile
++++ b/arch/arm/mach-ixp4xx/Makefile
+@@ -1,2 +1,2 @@
+ # SPDX-License-Identifier: GPL-2.0
+-obj-y += ixp4xx-of.o common.o
++obj-y += ixp4xx-of.o
+diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
+deleted file mode 100644
+index 310e1602fbfc..000000000000
+--- a/arch/arm/mach-ixp4xx/common.c
++++ /dev/null
+@@ -1,331 +0,0 @@
+-/*
+- * arch/arm/mach-ixp4xx/common.c
+- *
+- * Generic code shared across all IXP4XX platforms
+- *
+- * Maintainer: Deepak Saxena <dsaxena@plexity.net>
+- *
+- * Copyright 2002 (c) Intel Corporation
+- * Copyright 2003-2004 (c) MontaVista, Software, Inc.
+- *
+- * This file is licensed under the terms of the GNU General Public
+- * License version 2. This program is licensed "as is" without any
+- * warranty of any kind, whether express or implied.
+- */
+-
+-#include <linux/kernel.h>
+-#include <linux/mm.h>
+-#include <linux/init.h>
+-#include <linux/serial.h>
+-#include <linux/tty.h>
+-#include <linux/platform_device.h>
+-#include <linux/serial_core.h>
+-#include <linux/interrupt.h>
+-#include <linux/bitops.h>
+-#include <linux/io.h>
+-#include <linux/export.h>
+-#include <linux/cpu.h>
+-#include <linux/pci.h>
+-#include <linux/sched_clock.h>
+-#include <linux/soc/ixp4xx/cpu.h>
+-#include <linux/irqchip/irq-ixp4xx.h>
+-#include <linux/platform_data/timer-ixp4xx.h>
+-#include <mach/hardware.h>
+-#include <linux/uaccess.h>
+-#include <asm/page.h>
+-#include <asm/exception.h>
+-#include <asm/irq.h>
+-#include <asm/system_misc.h>
+-#include <asm/mach/map.h>
+-#include <asm/mach/irq.h>
+-#include <asm/mach/time.h>
+-
+-#include "irqs.h"
+-
+-#define IXP4XX_TIMER_FREQ 66666000
+-
+-/*************************************************************************
+- * IXP4xx chipset I/O mapping
+- *************************************************************************/
+-static struct map_desc ixp4xx_io_desc[] __initdata = {
+- { /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */
+- .virtual = (unsigned long)IXP4XX_PERIPHERAL_BASE_VIRT,
+- .pfn = __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS),
+- .length = IXP4XX_PERIPHERAL_REGION_SIZE,
+- .type = MT_DEVICE
+- }, { /* Expansion Bus Config Registers */
+- .virtual = (unsigned long)IXP4XX_EXP_CFG_BASE_VIRT,
+- .pfn = __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS),
+- .length = IXP4XX_EXP_CFG_REGION_SIZE,
+- .type = MT_DEVICE
+- }, { /* PCI Registers */
+- .virtual = (unsigned long)IXP4XX_PCI_CFG_BASE_VIRT,
+- .pfn = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS),
+- .length = IXP4XX_PCI_CFG_REGION_SIZE,
+- .type = MT_DEVICE
+- },
+-};
+-
+-void __init ixp4xx_map_io(void)
+-{
+- iotable_init(ixp4xx_io_desc, ARRAY_SIZE(ixp4xx_io_desc));
+-}
+-
+-void __init ixp4xx_init_irq(void)
+-{
+- /*
+- * ixp4xx does not implement the XScale PWRMODE register
+- * so it must not call cpu_do_idle().
+- */
+- cpu_idle_poll_ctrl(true);
+-
+- ixp4xx_irq_init(IXP4XX_INTC_BASE_PHYS,
+- (cpu_is_ixp46x() || cpu_is_ixp43x()));
+-}
+-
+-void __init ixp4xx_timer_init(void)
+-{
+- return ixp4xx_timer_setup(IXP4XX_TIMER_BASE_PHYS,
+- IRQ_IXP4XX_TIMER1,
+- IXP4XX_TIMER_FREQ);
+-}
+-
+-static struct resource ixp4xx_udc_resources[] = {
+- [0] = {
+- .start = 0xc800b000,
+- .end = 0xc800bfff,
+- .flags = IORESOURCE_MEM,
+- },
+- [1] = {
+- .start = IRQ_IXP4XX_USB,
+- .end = IRQ_IXP4XX_USB,
+- .flags = IORESOURCE_IRQ,
+- },
+-};
+-
+-static struct resource ixp4xx_gpio_resource[] = {
+- {
+- .start = IXP4XX_GPIO_BASE_PHYS,
+- .end = IXP4XX_GPIO_BASE_PHYS + 0xfff,
+- .flags = IORESOURCE_MEM,
+- },
+-};
+-
+-static struct platform_device ixp4xx_gpio_device = {
+- .name = "ixp4xx-gpio",
+- .id = -1,
+- .dev = {
+- .coherent_dma_mask = DMA_BIT_MASK(32),
+- },
+- .resource = ixp4xx_gpio_resource,
+- .num_resources = ARRAY_SIZE(ixp4xx_gpio_resource),
+-};
+-
+-/*
+- * USB device controller. The IXP4xx uses the same controller as PXA25X,
+- * so we just use the same device.
+- */
+-static struct platform_device ixp4xx_udc_device = {
+- .name = "pxa25x-udc",
+- .id = -1,
+- .num_resources = 2,
+- .resource = ixp4xx_udc_resources,
+-};
+-
+-static struct resource ixp4xx_npe_resources[] = {
+- {
+- .start = IXP4XX_NPEA_BASE_PHYS,
+- .end = IXP4XX_NPEA_BASE_PHYS + 0xfff,
+- .flags = IORESOURCE_MEM,
+- },
+- {
+- .start = IXP4XX_NPEB_BASE_PHYS,
+- .end = IXP4XX_NPEB_BASE_PHYS + 0xfff,
+- .flags = IORESOURCE_MEM,
+- },
+- {
+- .start = IXP4XX_NPEC_BASE_PHYS,
+- .end = IXP4XX_NPEC_BASE_PHYS + 0xfff,
+- .flags = IORESOURCE_MEM,
+- },
+-
+-};
+-
+-static struct platform_device ixp4xx_npe_device = {
+- .name = "ixp4xx-npe",
+- .id = -1,
+- .num_resources = ARRAY_SIZE(ixp4xx_npe_resources),
+- .resource = ixp4xx_npe_resources,
+-};
+-
+-static struct resource ixp4xx_qmgr_resources[] = {
+- {
+- .start = IXP4XX_QMGR_BASE_PHYS,
+- .end = IXP4XX_QMGR_BASE_PHYS + 0x3fff,
+- .flags = IORESOURCE_MEM,
+- },
+- {
+- .start = IRQ_IXP4XX_QM1,
+- .end = IRQ_IXP4XX_QM1,
+- .flags = IORESOURCE_IRQ,
+- },
+- {
+- .start = IRQ_IXP4XX_QM2,
+- .end = IRQ_IXP4XX_QM2,
+- .flags = IORESOURCE_IRQ,
+- },
+-};
+-
+-static struct platform_device ixp4xx_qmgr_device = {
+- .name = "ixp4xx-qmgr",
+- .id = -1,
+- .num_resources = ARRAY_SIZE(ixp4xx_qmgr_resources),
+- .resource = ixp4xx_qmgr_resources,
+-};
+-
+-static struct platform_device *ixp4xx_devices[] __initdata = {
+- &ixp4xx_npe_device,
+- &ixp4xx_qmgr_device,
+- &ixp4xx_gpio_device,
+- &ixp4xx_udc_device,
+-};
+-
+-static struct resource ixp46x_i2c_resources[] = {
+- [0] = {
+- .start = 0xc8011000,
+- .end = 0xc801101c,
+- .flags = IORESOURCE_MEM,
+- },
+- [1] = {
+- .start = IRQ_IXP4XX_I2C,
+- .end = IRQ_IXP4XX_I2C,
+- .flags = IORESOURCE_IRQ
+- }
+-};
+-
+-/* A single 32-bit register on IXP46x */
+-#define IXP4XX_HWRANDOM_BASE_PHYS 0x70002100
+-
+-static struct resource ixp46x_hwrandom_resource[] = {
+- {
+- .start = IXP4XX_HWRANDOM_BASE_PHYS,
+- .end = IXP4XX_HWRANDOM_BASE_PHYS + 0x3,
+- .flags = IORESOURCE_MEM,
+- },
+-};
+-
+-static struct platform_device ixp46x_hwrandom_device = {
+- .name = "ixp4xx-hwrandom",
+- .id = -1,
+- .dev = {
+- .coherent_dma_mask = DMA_BIT_MASK(32),
+- },
+- .resource = ixp46x_hwrandom_resource,
+- .num_resources = ARRAY_SIZE(ixp46x_hwrandom_resource),
+-};
+-
+-/*
+- * I2C controller. The IXP46x uses the same block as the IOP3xx, so
+- * we just use the same device name.
+- */
+-static struct platform_device ixp46x_i2c_controller = {
+- .name = "IOP3xx-I2C",
+- .id = 0,
+- .num_resources = 2,
+- .resource = ixp46x_i2c_resources
+-};
+-
+-static struct resource ixp46x_ptp_resources[] = {
+- DEFINE_RES_MEM(IXP4XX_TIMESYNC_BASE_PHYS, SZ_4K),
+- DEFINE_RES_IRQ_NAMED(IRQ_IXP4XX_GPIO8, "master"),
+- DEFINE_RES_IRQ_NAMED(IRQ_IXP4XX_GPIO7, "slave"),
+-};
+-
+-static struct platform_device ixp46x_ptp = {
+- .name = "ptp-ixp46x",
+- .id = -1,
+- .resource = ixp46x_ptp_resources,
+- .num_resources = ARRAY_SIZE(ixp46x_ptp_resources),
+-};
+-
+-static struct platform_device *ixp46x_devices[] __initdata = {
+- &ixp46x_hwrandom_device,
+- &ixp46x_i2c_controller,
+- &ixp46x_ptp,
+-};
+-
+-unsigned long ixp4xx_exp_bus_size;
+-EXPORT_SYMBOL(ixp4xx_exp_bus_size);
+-
+-static struct platform_device_info ixp_dev_info __initdata = {
+- .name = "ixp4xx_crypto",
+- .id = 0,
+- .dma_mask = DMA_BIT_MASK(32),
+-};
+-
+-static int __init ixp_crypto_register(void)
+-{
+- struct platform_device *pdev;
+-
+- if (!(~(*IXP4XX_EXP_CFG2) & (IXP4XX_FEATURE_HASH |
+- IXP4XX_FEATURE_AES | IXP4XX_FEATURE_DES))) {
+- printk(KERN_ERR "ixp_crypto: No HW crypto available\n");
+- return -ENODEV;
+- }
+-
+- pdev = platform_device_register_full(&ixp_dev_info);
+- if (IS_ERR(pdev))
+- return PTR_ERR(pdev);
+-
+- return 0;
+-}
+-
+-void __init ixp4xx_sys_init(void)
+-{
+- ixp4xx_exp_bus_size = SZ_16M;
+-
+- platform_add_devices(ixp4xx_devices, ARRAY_SIZE(ixp4xx_devices));
+-
+- if (IS_ENABLED(CONFIG_CRYPTO_DEV_IXP4XX))
+- ixp_crypto_register();
+-
+- if (cpu_is_ixp46x()) {
+- int region;
+-
+- platform_add_devices(ixp46x_devices,
+- ARRAY_SIZE(ixp46x_devices));
+-
+- for (region = 0; region < 7; region++) {
+- if((*(IXP4XX_EXP_REG(0x4 * region)) & 0x200)) {
+- ixp4xx_exp_bus_size = SZ_32M;
+- break;
+- }
+- }
+- }
+-
+- printk("IXP4xx: Using %luMiB expansion bus window size\n",
+- ixp4xx_exp_bus_size >> 20);
+-}
+-
+-unsigned long ixp4xx_timer_freq = IXP4XX_TIMER_FREQ;
+-EXPORT_SYMBOL(ixp4xx_timer_freq);
+-
+-void ixp4xx_restart(enum reboot_mode mode, const char *cmd)
+-{
+- if (mode == REBOOT_SOFT) {
+- /* Jump into ROM at address 0 */
+- soft_restart(0);
+- } else {
+- /* Use on-chip reset capability */
+-
+- /* set the "key" register to enable access to
+- * "timer" and "enable" registers
+- */
+- *IXP4XX_OSWK = IXP4XX_WDT_KEY;
+-
+- /* write 0 to the timer register for an immediate reset */
+- *IXP4XX_OSWT = 0;
+-
+- *IXP4XX_OSWE = IXP4XX_WDT_RESET_ENABLE | IXP4XX_WDT_COUNT_ENABLE;
+- }
+-}
+diff --git a/arch/arm/mach-ixp4xx/include/mach/hardware.h b/arch/arm/mach-ixp4xx/include/mach/hardware.h
+deleted file mode 100644
+index 41f28fb8e63f..000000000000
+--- a/arch/arm/mach-ixp4xx/include/mach/hardware.h
++++ /dev/null
+@@ -1,26 +0,0 @@
+-/* SPDX-License-Identifier: GPL-2.0-only */
+-/*
+- * arch/arm/mach-ixp4xx/include/mach/hardware.h
+- *
+- * Copyright (C) 2002 Intel Corporation.
+- * Copyright (C) 2003-2004 MontaVista Software, Inc.
+- */
+-
+-/*
+- * Hardware definitions for IXP4xx based systems
+- */
+-
+-#ifndef __ASM_ARCH_HARDWARE_H__
+-#define __ASM_ARCH_HARDWARE_H__
+-
+-/* Register locations and bits */
+-#include "ixp4xx-regs.h"
+-
+-#ifndef __ASSEMBLER__
+-#include <linux/soc/ixp4xx/cpu.h>
+-#endif
+-
+-/* Platform helper functions and definitions */
+-#include "platform.h"
+-
+-#endif /* _ASM_ARCH_HARDWARE_H */
+diff --git a/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h b/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
+deleted file mode 100644
+index 74e63d4531aa..000000000000
+--- a/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
++++ /dev/null
+@@ -1,303 +0,0 @@
+-/* SPDX-License-Identifier: GPL-2.0-only */
+-/*
+- * arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
+- *
+- * Register definitions for IXP4xx chipset. This file contains
+- * register location and bit definitions only. Platform specific
+- * definitions and helper function declarations are in platform.h
+- * and machine-name.h.
+- *
+- * Copyright (C) 2002 Intel Corporation.
+- * Copyright (C) 2003-2004 MontaVista Software, Inc.
+- */
+-
+-#ifndef _ASM_ARM_IXP4XX_H_
+-#define _ASM_ARM_IXP4XX_H_
+-
+-/*
+- * IXP4xx Linux Memory Map:
+- *
+- * Phy Size Virt Description
+- * =========================================================================
+- *
+- * 0x00000000 0x10000000(max) PAGE_OFFSET System RAM
+- *
+- * 0x48000000 0x04000000 ioremap'd PCI Memory Space
+- *
+- * 0x50000000 0x10000000 ioremap'd EXP BUS
+- *
+- * 0xC8000000 0x00013000 0xFEF00000 On-Chip Peripherals
+- *
+- * 0xC0000000 0x00001000 0xFEF13000 PCI CFG
+- *
+- * 0xC4000000 0x00001000 0xFEF14000 EXP CFG
+- *
+- * 0x60000000 0x00004000 0xFEF15000 QMgr
+- */
+-
+-/*
+- * Queue Manager
+- */
+-#define IXP4XX_QMGR_BASE_PHYS 0x60000000
+-
+-/*
+- * Peripheral space, including debug UART. Must be section-aligned so that
+- * it can be used with the low-level debug code.
+- */
+-#define IXP4XX_PERIPHERAL_BASE_PHYS 0xC8000000
+-#define IXP4XX_PERIPHERAL_BASE_VIRT IOMEM(0xFEC00000)
+-#define IXP4XX_PERIPHERAL_REGION_SIZE 0x00013000
+-
+-/*
+- * PCI Config registers
+- */
+-#define IXP4XX_PCI_CFG_BASE_PHYS 0xC0000000
+-#define IXP4XX_PCI_CFG_BASE_VIRT IOMEM(0xFEC13000)
+-#define IXP4XX_PCI_CFG_REGION_SIZE 0x00001000
+-
+-/*
+- * Expansion BUS Configuration registers
+- */
+-#define IXP4XX_EXP_CFG_BASE_PHYS 0xC4000000
+-#define IXP4XX_EXP_CFG_BASE_VIRT 0xFEC14000
+-#define IXP4XX_EXP_CFG_REGION_SIZE 0x00001000
+-
+-#define IXP4XX_EXP_CS0_OFFSET 0x00
+-#define IXP4XX_EXP_CS1_OFFSET 0x04
+-#define IXP4XX_EXP_CS2_OFFSET 0x08
+-#define IXP4XX_EXP_CS3_OFFSET 0x0C
+-#define IXP4XX_EXP_CS4_OFFSET 0x10
+-#define IXP4XX_EXP_CS5_OFFSET 0x14
+-#define IXP4XX_EXP_CS6_OFFSET 0x18
+-#define IXP4XX_EXP_CS7_OFFSET 0x1C
+-#define IXP4XX_EXP_CFG0_OFFSET 0x20
+-#define IXP4XX_EXP_CFG1_OFFSET 0x24
+-#define IXP4XX_EXP_CFG2_OFFSET 0x28
+-#define IXP4XX_EXP_CFG3_OFFSET 0x2C
+-
+-/*
+- * Expansion Bus Controller registers.
+- */
+-#define IXP4XX_EXP_REG(x) ((volatile u32 __iomem *)(IXP4XX_EXP_CFG_BASE_VIRT+(x)))
+-
+-#define IXP4XX_EXP_CS0 IXP4XX_EXP_REG(IXP4XX_EXP_CS0_OFFSET)
+-#define IXP4XX_EXP_CS1 IXP4XX_EXP_REG(IXP4XX_EXP_CS1_OFFSET)
+-#define IXP4XX_EXP_CS2 IXP4XX_EXP_REG(IXP4XX_EXP_CS2_OFFSET)
+-#define IXP4XX_EXP_CS3 IXP4XX_EXP_REG(IXP4XX_EXP_CS3_OFFSET)
+-#define IXP4XX_EXP_CS4 IXP4XX_EXP_REG(IXP4XX_EXP_CS4_OFFSET)
+-#define IXP4XX_EXP_CS5 IXP4XX_EXP_REG(IXP4XX_EXP_CS5_OFFSET)
+-#define IXP4XX_EXP_CS6 IXP4XX_EXP_REG(IXP4XX_EXP_CS6_OFFSET)
+-#define IXP4XX_EXP_CS7 IXP4XX_EXP_REG(IXP4XX_EXP_CS7_OFFSET)
+-
+-#define IXP4XX_EXP_CFG0 IXP4XX_EXP_REG(IXP4XX_EXP_CFG0_OFFSET)
+-#define IXP4XX_EXP_CFG1 IXP4XX_EXP_REG(IXP4XX_EXP_CFG1_OFFSET)
+-#define IXP4XX_EXP_CFG2 IXP4XX_EXP_REG(IXP4XX_EXP_CFG2_OFFSET)
+-#define IXP4XX_EXP_CFG3 IXP4XX_EXP_REG(IXP4XX_EXP_CFG3_OFFSET)
+-
+-
+-/*
+- * Peripheral Space Register Region Base Addresses
+- */
+-#define IXP4XX_UART1_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x0000)
+-#define IXP4XX_UART2_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x1000)
+-#define IXP4XX_PMU_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x2000)
+-#define IXP4XX_INTC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x3000)
+-#define IXP4XX_GPIO_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x4000)
+-#define IXP4XX_TIMER_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x5000)
+-#define IXP4XX_NPEA_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x6000)
+-#define IXP4XX_NPEB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x7000)
+-#define IXP4XX_NPEC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x8000)
+-#define IXP4XX_EthB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x9000)
+-#define IXP4XX_EthC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xA000)
+-#define IXP4XX_USB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xB000)
+-/* ixp46X only */
+-#define IXP4XX_EthA_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xC000)
+-#define IXP4XX_EthB1_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xD000)
+-#define IXP4XX_EthB2_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xE000)
+-#define IXP4XX_EthB3_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xF000)
+-#define IXP4XX_TIMESYNC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x10000)
+-#define IXP4XX_I2C_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x11000)
+-#define IXP4XX_SSP_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x12000)
+-
+-
+-/* The UART is explicitly put in the beginning of fixmap */
+-#define IXP4XX_UART1_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x0000)
+-#define IXP4XX_UART2_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x1000)
+-#define IXP4XX_PMU_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x2000)
+-#define IXP4XX_INTC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x3000)
+-#define IXP4XX_GPIO_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x4000)
+-#define IXP4XX_TIMER_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x5000)
+-#define IXP4XX_EthB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x9000)
+-#define IXP4XX_EthC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xA000)
+-#define IXP4XX_USB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xB000)
+-/* ixp46X only */
+-#define IXP4XX_EthA_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xC000)
+-#define IXP4XX_EthB1_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xD000)
+-#define IXP4XX_EthB2_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xE000)
+-#define IXP4XX_EthB3_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xF000)
+-#define IXP4XX_TIMESYNC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x10000)
+-#define IXP4XX_I2C_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x11000)
+-#define IXP4XX_SSP_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x12000)
+-
+-/*
+- * Constants to make it easy to access Timer Control/Status registers
+- */
+-#define IXP4XX_OSTS_OFFSET 0x00 /* Continious TimeStamp */
+-#define IXP4XX_OST1_OFFSET 0x04 /* Timer 1 Timestamp */
+-#define IXP4XX_OSRT1_OFFSET 0x08 /* Timer 1 Reload */
+-#define IXP4XX_OST2_OFFSET 0x0C /* Timer 2 Timestamp */
+-#define IXP4XX_OSRT2_OFFSET 0x10 /* Timer 2 Reload */
+-#define IXP4XX_OSWT_OFFSET 0x14 /* Watchdog Timer */
+-#define IXP4XX_OSWE_OFFSET 0x18 /* Watchdog Enable */
+-#define IXP4XX_OSWK_OFFSET 0x1C /* Watchdog Key */
+-#define IXP4XX_OSST_OFFSET 0x20 /* Timer Status */
+-
+-/*
+- * Operating System Timer Register Definitions.
+- */
+-
+-#define IXP4XX_TIMER_REG(x) ((volatile u32 *)(IXP4XX_TIMER_BASE_VIRT+(x)))
+-
+-#define IXP4XX_OSTS IXP4XX_TIMER_REG(IXP4XX_OSTS_OFFSET)
+-#define IXP4XX_OST1 IXP4XX_TIMER_REG(IXP4XX_OST1_OFFSET)
+-#define IXP4XX_OSRT1 IXP4XX_TIMER_REG(IXP4XX_OSRT1_OFFSET)
+-#define IXP4XX_OST2 IXP4XX_TIMER_REG(IXP4XX_OST2_OFFSET)
+-#define IXP4XX_OSRT2 IXP4XX_TIMER_REG(IXP4XX_OSRT2_OFFSET)
+-#define IXP4XX_OSWT IXP4XX_TIMER_REG(IXP4XX_OSWT_OFFSET)
+-#define IXP4XX_OSWE IXP4XX_TIMER_REG(IXP4XX_OSWE_OFFSET)
+-#define IXP4XX_OSWK IXP4XX_TIMER_REG(IXP4XX_OSWK_OFFSET)
+-#define IXP4XX_OSST IXP4XX_TIMER_REG(IXP4XX_OSST_OFFSET)
+-
+-/*
+- * Timer register values and bit definitions
+- */
+-#define IXP4XX_OST_ENABLE 0x00000001
+-#define IXP4XX_OST_ONE_SHOT 0x00000002
+-/* Low order bits of reload value ignored */
+-#define IXP4XX_OST_RELOAD_MASK 0x00000003
+-#define IXP4XX_OST_DISABLED 0x00000000
+-#define IXP4XX_OSST_TIMER_1_PEND 0x00000001
+-#define IXP4XX_OSST_TIMER_2_PEND 0x00000002
+-#define IXP4XX_OSST_TIMER_TS_PEND 0x00000004
+-#define IXP4XX_OSST_TIMER_WDOG_PEND 0x00000008
+-#define IXP4XX_OSST_TIMER_WARM_RESET 0x00000010
+-
+-#define IXP4XX_WDT_KEY 0x0000482E
+-
+-#define IXP4XX_WDT_RESET_ENABLE 0x00000001
+-#define IXP4XX_WDT_IRQ_ENABLE 0x00000002
+-#define IXP4XX_WDT_COUNT_ENABLE 0x00000004
+-
+-
+-/*
+- * Constants to make it easy to access PCI Control/Status registers
+- */
+-#define PCI_NP_AD_OFFSET 0x00
+-#define PCI_NP_CBE_OFFSET 0x04
+-#define PCI_NP_WDATA_OFFSET 0x08
+-#define PCI_NP_RDATA_OFFSET 0x0c
+-#define PCI_CRP_AD_CBE_OFFSET 0x10
+-#define PCI_CRP_WDATA_OFFSET 0x14
+-#define PCI_CRP_RDATA_OFFSET 0x18
+-#define PCI_CSR_OFFSET 0x1c
+-#define PCI_ISR_OFFSET 0x20
+-#define PCI_INTEN_OFFSET 0x24
+-#define PCI_DMACTRL_OFFSET 0x28
+-#define PCI_AHBMEMBASE_OFFSET 0x2c
+-#define PCI_AHBIOBASE_OFFSET 0x30
+-#define PCI_PCIMEMBASE_OFFSET 0x34
+-#define PCI_AHBDOORBELL_OFFSET 0x38
+-#define PCI_PCIDOORBELL_OFFSET 0x3C
+-#define PCI_ATPDMA0_AHBADDR_OFFSET 0x40
+-#define PCI_ATPDMA0_PCIADDR_OFFSET 0x44
+-#define PCI_ATPDMA0_LENADDR_OFFSET 0x48
+-#define PCI_ATPDMA1_AHBADDR_OFFSET 0x4C
+-#define PCI_ATPDMA1_PCIADDR_OFFSET 0x50
+-#define PCI_ATPDMA1_LENADDR_OFFSET 0x54
+-
+-/*
+- * PCI Control/Status Registers
+- */
+-#define _IXP4XX_PCI_CSR(x) ((volatile u32 *)(IXP4XX_PCI_CFG_BASE_VIRT+(x)))
+-
+-#define PCI_NP_AD _IXP4XX_PCI_CSR(PCI_NP_AD_OFFSET)
+-#define PCI_NP_CBE _IXP4XX_PCI_CSR(PCI_NP_CBE_OFFSET)
+-#define PCI_NP_WDATA _IXP4XX_PCI_CSR(PCI_NP_WDATA_OFFSET)
+-#define PCI_NP_RDATA _IXP4XX_PCI_CSR(PCI_NP_RDATA_OFFSET)
+-#define PCI_CRP_AD_CBE _IXP4XX_PCI_CSR(PCI_CRP_AD_CBE_OFFSET)
+-#define PCI_CRP_WDATA _IXP4XX_PCI_CSR(PCI_CRP_WDATA_OFFSET)
+-#define PCI_CRP_RDATA _IXP4XX_PCI_CSR(PCI_CRP_RDATA_OFFSET)
+-#define PCI_CSR _IXP4XX_PCI_CSR(PCI_CSR_OFFSET)
+-#define PCI_ISR _IXP4XX_PCI_CSR(PCI_ISR_OFFSET)
+-#define PCI_INTEN _IXP4XX_PCI_CSR(PCI_INTEN_OFFSET)
+-#define PCI_DMACTRL _IXP4XX_PCI_CSR(PCI_DMACTRL_OFFSET)
+-#define PCI_AHBMEMBASE _IXP4XX_PCI_CSR(PCI_AHBMEMBASE_OFFSET)
+-#define PCI_AHBIOBASE _IXP4XX_PCI_CSR(PCI_AHBIOBASE_OFFSET)
+-#define PCI_PCIMEMBASE _IXP4XX_PCI_CSR(PCI_PCIMEMBASE_OFFSET)
+-#define PCI_AHBDOORBELL _IXP4XX_PCI_CSR(PCI_AHBDOORBELL_OFFSET)
+-#define PCI_PCIDOORBELL _IXP4XX_PCI_CSR(PCI_PCIDOORBELL_OFFSET)
+-#define PCI_ATPDMA0_AHBADDR _IXP4XX_PCI_CSR(PCI_ATPDMA0_AHBADDR_OFFSET)
+-#define PCI_ATPDMA0_PCIADDR _IXP4XX_PCI_CSR(PCI_ATPDMA0_PCIADDR_OFFSET)
+-#define PCI_ATPDMA0_LENADDR _IXP4XX_PCI_CSR(PCI_ATPDMA0_LENADDR_OFFSET)
+-#define PCI_ATPDMA1_AHBADDR _IXP4XX_PCI_CSR(PCI_ATPDMA1_AHBADDR_OFFSET)
+-#define PCI_ATPDMA1_PCIADDR _IXP4XX_PCI_CSR(PCI_ATPDMA1_PCIADDR_OFFSET)
+-#define PCI_ATPDMA1_LENADDR _IXP4XX_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET)
+-
+-/*
+- * PCI register values and bit definitions
+- */
+-
+-/* CSR bit definitions */
+-#define PCI_CSR_HOST 0x00000001
+-#define PCI_CSR_ARBEN 0x00000002
+-#define PCI_CSR_ADS 0x00000004
+-#define PCI_CSR_PDS 0x00000008
+-#define PCI_CSR_ABE 0x00000010
+-#define PCI_CSR_DBT 0x00000020
+-#define PCI_CSR_ASE 0x00000100
+-#define PCI_CSR_IC 0x00008000
+-
+-/* ISR (Interrupt status) Register bit definitions */
+-#define PCI_ISR_PSE 0x00000001
+-#define PCI_ISR_PFE 0x00000002
+-#define PCI_ISR_PPE 0x00000004
+-#define PCI_ISR_AHBE 0x00000008
+-#define PCI_ISR_APDC 0x00000010
+-#define PCI_ISR_PADC 0x00000020
+-#define PCI_ISR_ADB 0x00000040
+-#define PCI_ISR_PDB 0x00000080
+-
+-/* INTEN (Interrupt Enable) Register bit definitions */
+-#define PCI_INTEN_PSE 0x00000001
+-#define PCI_INTEN_PFE 0x00000002
+-#define PCI_INTEN_PPE 0x00000004
+-#define PCI_INTEN_AHBE 0x00000008
+-#define PCI_INTEN_APDC 0x00000010
+-#define PCI_INTEN_PADC 0x00000020
+-#define PCI_INTEN_ADB 0x00000040
+-#define PCI_INTEN_PDB 0x00000080
+-
+-/*
+- * Shift value for byte enable on NP cmd/byte enable register
+- */
+-#define IXP4XX_PCI_NP_CBE_BESL 4
+-
+-/*
+- * PCI commands supported by NP access unit
+- */
+-#define NP_CMD_IOREAD 0x2
+-#define NP_CMD_IOWRITE 0x3
+-#define NP_CMD_CONFIGREAD 0xa
+-#define NP_CMD_CONFIGWRITE 0xb
+-#define NP_CMD_MEMREAD 0x6
+-#define NP_CMD_MEMWRITE 0x7
+-
+-/*
+- * Constants for CRP access into local config space
+- */
+-#define CRP_AD_CBE_BESL 20
+-#define CRP_AD_CBE_WRITE 0x00010000
+-
+-#define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
+-
+-#endif
+diff --git a/arch/arm/mach-ixp4xx/include/mach/platform.h b/arch/arm/mach-ixp4xx/include/mach/platform.h
+deleted file mode 100644
+index f9ec07f00be0..000000000000
+--- a/arch/arm/mach-ixp4xx/include/mach/platform.h
++++ /dev/null
+@@ -1,98 +0,0 @@
+-/* SPDX-License-Identifier: GPL-2.0 */
+-/*
+- * arch/arm/mach-ixp4xx/include/mach/platform.h
+- *
+- * Constants and functions that are useful to IXP4xx platform-specific code
+- * and device drivers.
+- *
+- * Copyright (C) 2004 MontaVista Software, Inc.
+- */
+-
+-#ifndef __ASM_ARCH_HARDWARE_H__
+-#error "Do not include this directly, instead #include <mach/hardware.h>"
+-#endif
+-
+-#ifndef __ASSEMBLY__
+-
+-#include <linux/reboot.h>
+-#include <linux/platform_data/eth_ixp4xx.h>
+-
+-#include <asm/types.h>
+-
+-#ifndef __ARMEB__
+-#define REG_OFFSET 0
+-#else
+-#define REG_OFFSET 3
+-#endif
+-
+-/*
+- * Expansion bus memory regions
+- */
+-#define IXP4XX_EXP_BUS_BASE_PHYS (0x50000000)
+-
+-/*
+- * The expansion bus on the IXP4xx can be configured for either 16 or
+- * 32MB windows and the CS offset for each region changes based on the
+- * current configuration. This means that we cannot simply hardcode
+- * each offset. ixp4xx_sys_init() looks at the expansion bus configuration
+- * as setup by the bootloader to determine our window size.
+- */
+-extern unsigned long ixp4xx_exp_bus_size;
+-
+-#define IXP4XX_EXP_BUS_BASE(region)\
+- (IXP4XX_EXP_BUS_BASE_PHYS + ((region) * ixp4xx_exp_bus_size))
+-
+-#define IXP4XX_EXP_BUS_END(region)\
+- (IXP4XX_EXP_BUS_BASE(region) + ixp4xx_exp_bus_size - 1)
+-
+-/* Those macros can be used to adjust timing and configure
+- * other features for each region.
+- */
+-
+-#define IXP4XX_EXP_BUS_RECOVERY_T(x) (((x) & 0x0f) << 16)
+-#define IXP4XX_EXP_BUS_HOLD_T(x) (((x) & 0x03) << 20)
+-#define IXP4XX_EXP_BUS_STROBE_T(x) (((x) & 0x0f) << 22)
+-#define IXP4XX_EXP_BUS_SETUP_T(x) (((x) & 0x03) << 26)
+-#define IXP4XX_EXP_BUS_ADDR_T(x) (((x) & 0x03) << 28)
+-#define IXP4XX_EXP_BUS_SIZE(x) (((x) & 0x0f) << 10)
+-#define IXP4XX_EXP_BUS_CYCLES(x) (((x) & 0x03) << 14)
+-
+-#define IXP4XX_EXP_BUS_CS_EN (1L << 31)
+-#define IXP4XX_EXP_BUS_BYTE_RD16 (1L << 6)
+-#define IXP4XX_EXP_BUS_HRDY_POL (1L << 5)
+-#define IXP4XX_EXP_BUS_MUX_EN (1L << 4)
+-#define IXP4XX_EXP_BUS_SPLT_EN (1L << 3)
+-#define IXP4XX_EXP_BUS_WR_EN (1L << 1)
+-#define IXP4XX_EXP_BUS_BYTE_EN (1L << 0)
+-
+-#define IXP4XX_EXP_BUS_CYCLES_INTEL 0x00
+-#define IXP4XX_EXP_BUS_CYCLES_MOTOROLA 0x01
+-#define IXP4XX_EXP_BUS_CYCLES_HPI 0x02
+-
+-#define IXP4XX_FLASH_WRITABLE (0x2)
+-#define IXP4XX_FLASH_DEFAULT (0xbcd23c40)
+-#define IXP4XX_FLASH_WRITE (0xbcd23c42)
+-
+-/*
+- * Clock Speed Definitions.
+- */
+-#define IXP4XX_PERIPHERAL_BUS_CLOCK (66) /* 66MHzi APB BUS */
+-#define IXP4XX_UART_XTAL 14745600
+-
+-/*
+- * Frequency of clock used for primary clocksource
+- */
+-extern unsigned long ixp4xx_timer_freq;
+-
+-/*
+- * Functions used by platform-level setup code
+- */
+-extern void ixp4xx_map_io(void);
+-extern void ixp4xx_init_early(void);
+-extern void ixp4xx_init_irq(void);
+-extern void ixp4xx_sys_init(void);
+-extern void ixp4xx_timer_init(void);
+-extern void ixp4xx_restart(enum reboot_mode, const char *);
+-
+-#endif // __ASSEMBLY__
+-
+diff --git a/arch/arm/mach-ixp4xx/include/mach/uncompress.h b/arch/arm/mach-ixp4xx/include/mach/uncompress.h
+index 9e08b270cfc7..09e7663e6a55 100644
+--- a/arch/arm/mach-ixp4xx/include/mach/uncompress.h
++++ b/arch/arm/mach-ixp4xx/include/mach/uncompress.h
+@@ -9,10 +9,12 @@
+ #ifndef _ARCH_UNCOMPRESS_H_
+ #define _ARCH_UNCOMPRESS_H_
+
+-#include "ixp4xx-regs.h"
+ #include <asm/mach-types.h>
+ #include <linux/serial_reg.h>
+
++#define IXP4XX_UART1_BASE_PHYS 0xc8000000
++#define IXP4XX_UART2_BASE_PHYS 0xc8001000
++
+ #define TX_DONE (UART_LSR_TEMT|UART_LSR_THRE)
+
+ volatile u32* uart_base;
+diff --git a/arch/arm/mach-ixp4xx/irqs.h b/arch/arm/mach-ixp4xx/irqs.h
+deleted file mode 100644
+index a3e8d6408c56..000000000000
+--- a/arch/arm/mach-ixp4xx/irqs.h
++++ /dev/null
+@@ -1,64 +0,0 @@
+-/* SPDX-License-Identifier: GPL-2.0-only */
+-/*
+- * arch/arm/mach-ixp4xx/include/mach/irqs.h
+- *
+- * IRQ definitions for IXP4XX based systems
+- *
+- * Copyright (C) 2002 Intel Corporation.
+- * Copyright (C) 2003 MontaVista Software, Inc.
+- */
+-
+-#ifndef _ARCH_IXP4XX_IRQS_H_
+-#define _ARCH_IXP4XX_IRQS_H_
+-
+-#define IRQ_IXP4XX_BASE 16
+-
+-#define IRQ_IXP4XX_NPEA (IRQ_IXP4XX_BASE + 0)
+-#define IRQ_IXP4XX_NPEB (IRQ_IXP4XX_BASE + 1)
+-#define IRQ_IXP4XX_NPEC (IRQ_IXP4XX_BASE + 2)
+-#define IRQ_IXP4XX_QM1 (IRQ_IXP4XX_BASE + 3)
+-#define IRQ_IXP4XX_QM2 (IRQ_IXP4XX_BASE + 4)
+-#define IRQ_IXP4XX_TIMER1 (IRQ_IXP4XX_BASE + 5)
+-#define IRQ_IXP4XX_GPIO0 (IRQ_IXP4XX_BASE + 6)
+-#define IRQ_IXP4XX_GPIO1 (IRQ_IXP4XX_BASE + 7)
+-#define IRQ_IXP4XX_PCI_INT (IRQ_IXP4XX_BASE + 8)
+-#define IRQ_IXP4XX_PCI_DMA1 (IRQ_IXP4XX_BASE + 9)
+-#define IRQ_IXP4XX_PCI_DMA2 (IRQ_IXP4XX_BASE + 10)
+-#define IRQ_IXP4XX_TIMER2 (IRQ_IXP4XX_BASE + 11)
+-#define IRQ_IXP4XX_USB (IRQ_IXP4XX_BASE + 12)
+-#define IRQ_IXP4XX_UART2 (IRQ_IXP4XX_BASE + 13)
+-#define IRQ_IXP4XX_TIMESTAMP (IRQ_IXP4XX_BASE + 14)
+-#define IRQ_IXP4XX_UART1 (IRQ_IXP4XX_BASE + 15)
+-#define IRQ_IXP4XX_WDOG (IRQ_IXP4XX_BASE + 16)
+-#define IRQ_IXP4XX_AHB_PMU (IRQ_IXP4XX_BASE + 17)
+-#define IRQ_IXP4XX_XSCALE_PMU (IRQ_IXP4XX_BASE + 18)
+-#define IRQ_IXP4XX_GPIO2 (IRQ_IXP4XX_BASE + 19)
+-#define IRQ_IXP4XX_GPIO3 (IRQ_IXP4XX_BASE + 20)
+-#define IRQ_IXP4XX_GPIO4 (IRQ_IXP4XX_BASE + 21)
+-#define IRQ_IXP4XX_GPIO5 (IRQ_IXP4XX_BASE + 22)
+-#define IRQ_IXP4XX_GPIO6 (IRQ_IXP4XX_BASE + 23)
+-#define IRQ_IXP4XX_GPIO7 (IRQ_IXP4XX_BASE + 24)
+-#define IRQ_IXP4XX_GPIO8 (IRQ_IXP4XX_BASE + 25)
+-#define IRQ_IXP4XX_GPIO9 (IRQ_IXP4XX_BASE + 26)
+-#define IRQ_IXP4XX_GPIO10 (IRQ_IXP4XX_BASE + 27)
+-#define IRQ_IXP4XX_GPIO11 (IRQ_IXP4XX_BASE + 28)
+-#define IRQ_IXP4XX_GPIO12 (IRQ_IXP4XX_BASE + 29)
+-#define IRQ_IXP4XX_SW_INT1 (IRQ_IXP4XX_BASE + 30)
+-#define IRQ_IXP4XX_SW_INT2 (IRQ_IXP4XX_BASE + 31)
+-#define IRQ_IXP4XX_USB_HOST (IRQ_IXP4XX_BASE + 32)
+-#define IRQ_IXP4XX_I2C (IRQ_IXP4XX_BASE + 33)
+-#define IRQ_IXP4XX_SSP (IRQ_IXP4XX_BASE + 34)
+-#define IRQ_IXP4XX_TSYNC (IRQ_IXP4XX_BASE + 35)
+-#define IRQ_IXP4XX_EAU_DONE (IRQ_IXP4XX_BASE + 36)
+-#define IRQ_IXP4XX_SHA_DONE (IRQ_IXP4XX_BASE + 37)
+-#define IRQ_IXP4XX_SWCP_PE (IRQ_IXP4XX_BASE + 58)
+-#define IRQ_IXP4XX_QM_PE (IRQ_IXP4XX_BASE + 60)
+-#define IRQ_IXP4XX_MCU_ECC (IRQ_IXP4XX_BASE + 61)
+-#define IRQ_IXP4XX_EXP_PE (IRQ_IXP4XX_BASE + 62)
+-
+-#define _IXP4XX_GPIO_IRQ(n) (IRQ_IXP4XX_GPIO ## n)
+-#define IXP4XX_GPIO_IRQ(n) _IXP4XX_GPIO_IRQ(n)
+-
+-#define XSCALE_PMU_IRQ (IRQ_IXP4XX_XSCALE_PMU)
+-
+-#endif
+diff --git a/drivers/crypto/ixp4xx_crypto.c b/drivers/crypto/ixp4xx_crypto.c
+index 98730aab287c..d39a386b31ac 100644
+--- a/drivers/crypto/ixp4xx_crypto.c
++++ b/drivers/crypto/ixp4xx_crypto.c
+@@ -33,7 +33,6 @@
+
+ /* Intermittent includes, delete this after v5.14-rc1 */
+ #include <linux/soc/ixp4xx/cpu.h>
+-#include <mach/ixp4xx-regs.h>
+
+ #define MAX_KEYLEN 32
+
+diff --git a/drivers/net/ethernet/xscale/ptp_ixp46x.c b/drivers/net/ethernet/xscale/ptp_ixp46x.c
+index 39234852e01b..1f382777aa5a 100644
+--- a/drivers/net/ethernet/xscale/ptp_ixp46x.c
++++ b/drivers/net/ethernet/xscale/ptp_ixp46x.c
+@@ -16,7 +16,6 @@
+ #include <linux/ptp_clock_kernel.h>
+ #include <linux/platform_device.h>
+ #include <linux/soc/ixp4xx/cpu.h>
+-#include <mach/ixp4xx-regs.h>
+
+ #include "ixp46x_ts.h"
+
+--
+2.20.1
+
--- /dev/null
+From 06954b6a9e6a303b4782d543f5299b3b4020fd1f Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Fri, 11 Feb 2022 23:32:38 +0100
+Subject: [PATCH 14/14] ARM: ixp4xx: Convert to SPARSE_IRQ and P2V
+
+Turn on sparse IRQs and patch-physical-to-virtual for IXP4xx
+as this is required for multiplatform. Drop the PHYS_OFFSET as
+we are now using P2V.
+
+Tested and works like a charm on my systems.
+
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Link: https://lore.kernel.org/r/20220211223238.648934-14-linus.walleij@linaro.org
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ arch/arm/Kconfig | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
+index ec0dbaf73a81..02df28b3ee7e 100644
+--- a/arch/arm/Kconfig
++++ b/arch/arm/Kconfig
+@@ -379,6 +379,7 @@ config ARCH_IXP4XX
+ bool "IXP4xx-based"
+ depends on MMU
+ select ARCH_SUPPORTS_BIG_ENDIAN
++ select ARM_PATCH_PHYS_VIRT
+ select CPU_XSCALE
+ select GENERIC_IRQ_MULTI_HANDLER
+ select GPIO_IXP4XX
+@@ -386,6 +387,7 @@ config ARCH_IXP4XX
+ select HAVE_PCI
+ select IXP4XX_IRQ
+ select IXP4XX_TIMER
++ select SPARSE_IRQ
+ select USB_EHCI_BIG_ENDIAN_DESC
+ select USB_EHCI_BIG_ENDIAN_MMIO
+ help
+--
+2.20.1
+
--- /dev/null
+diff -ruN a/arch/arm/boot/dts/intel-ixp42x-adi-pronghorn-metro.dts b/arch/arm/boot/dts/intel-ixp42x-adi-pronghorn-metro.dts
+--- a/arch/arm/boot/dts/intel-ixp42x-adi-pronghorn-metro.dts 1970-01-01 01:00:00.000000000 +0100
++++ b/arch/arm/boot/dts/intel-ixp42x-adi-pronghorn-metro.dts 2021-05-17 17:33:40.427244073 +0200
+@@ -0,0 +1,175 @@
++// SPDX-License-Identifier: ISC
++/*
++ * Device Tree file for ADI Engineering Pronghorn Metro
++ * Copyright (c) 2021 Zoltan HERPAI <wigyori@uid0.hu>
++ */
++
++/dts-v1/;
++
++#include "intel-ixp42x.dtsi"
++#include <dt-bindings/input/input.h>
++
++/ {
++ model = "ADI Engineering Pronghorn Metro";
++ compatible = "adi,pronghornmetro", "intel,ixp42x";
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ memory@0 {
++ /* 64 MB SDRAM */
++ device_type = "memory";
++ reg = <0x00000000 0x4000000>;
++ };
++
++ chosen {
++ bootargs = "console=ttyS0,115200n8 root=/dev/mtdblock2 rw rootfstype=squashfs,jffs2 rootwait";
++ stdout-path = "uart1:115200n8";
++ };
++
++ aliases {
++ serial0 = &uart1;
++ serial1 = &uart0;
++ };
++
++ leds {
++ compatible = "gpio-leds";
++ led-status {
++ label = "nslu2:red:status";
++ gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
++ default-state = "on";
++ linux,default-trigger = "heartbeat";
++ };
++ led-ready {
++ label = "nslu2:green:ready";
++ gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
++ default-state = "on";
++ };
++ led-disk-1 {
++ label = "nslu2:green:disk-1";
++ gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
++ default-state = "off";
++ };
++ led-disk-2 {
++ label = "nslu2:green:disk-2";
++ gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
++ default-state = "off";
++ };
++ };
++
++ gpio_keys {
++ compatible = "gpio-keys";
++
++ button-power {
++ wakeup-source;
++ linux,code = <KEY_POWER>;
++ label = "power";
++ gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
++ };
++ button-reset {
++ wakeup-source;
++ linux,code = <KEY_ESC>;
++ label = "reset";
++ gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
++ };
++ };
++
++ i2c {
++ compatible = "i2c-gpio";
++ sda-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
++ scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ rtc@6f {
++ compatible = "xicor,x1205";
++ reg = <0x6f>;
++ };
++ };
++
++ gpio-poweroff {
++ compatible = "gpio-poweroff";
++ gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
++ timeout-ms = <5000>;
++ };
++
++ /* The first 16MB region on the expansion bus */
++ flash@50000000 {
++ compatible = "intel,ixp4xx-flash", "cfi-flash";
++ bank-width = <2>;
++ /*
++ * 8 MB of Flash in 0x20000 byte blocks
++ * mapped in at 0x50000000
++ */
++ reg = <0x50000000 0x800000>;
++
++ partitions {
++ compatible = "redboot-fis";
++ /* Eraseblock at 0x7e0000 */
++ fis-index-block = <0x3f>;
++ };
++ };
++
++ soc {
++ pci@c0000000 {
++ status = "ok";
++
++ /*
++ * Taken from NSLU2 PCI boardfile, INT A, B, C swizzled D constant
++ * We have slots (IDSEL) 1, 2 and 3.
++ */
++ interrupt-map =
++ /* IDSEL 1 */
++ <0x0800 0 0 1 &gpio0 11 3>, /* INT A on slot 1 is irq 11 */
++ <0x0800 0 0 2 &gpio0 10 3>, /* INT B on slot 1 is irq 10 */
++ <0x0800 0 0 3 &gpio0 9 3>, /* INT C on slot 1 is irq 9 */
++ <0x0800 0 0 4 &gpio0 8 3>, /* INT D on slot 1 is irq 8 */
++ /* IDSEL 2 */
++ <0x1000 0 0 1 &gpio0 10 3>, /* INT A on slot 2 is irq 10 */
++ <0x1000 0 0 2 &gpio0 9 3>, /* INT B on slot 2 is irq 9 */
++ <0x1000 0 0 3 &gpio0 11 3>, /* INT C on slot 2 is irq 11 */
++ <0x1000 0 0 4 &gpio0 8 3>, /* INT D on slot 2 is irq 8 */
++ /* IDSEL 3 */
++ <0x1800 0 0 1 &gpio0 9 3>, /* INT A on slot 3 is irq 9 */
++ <0x1800 0 0 2 &gpio0 11 3>, /* INT B on slot 3 is irq 11 */
++ <0x1800 0 0 3 &gpio0 10 3>, /* INT C on slot 3 is irq 10 */
++ <0x1800 0 0 4 &gpio0 8 3>; /* INT D on slot 3 is irq 8 */
++ };
++ };
++
++ soc {
++ ethernet@c8009000 {
++ status = "ok";
++ queue-rx = <&qmgr 3>;
++ queue-txready = <&qmgr 20>;
++ phy-mode = "rgmii";
++ phy-handle = <&phy1>;
++
++ mdio {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ phy1: ethernet-phy@1 {
++ reg = <1>;
++ };
++ };
++ };
++
++ ethernet@c800a000 {
++ status = "ok";
++ queue-rx = <&qmgr 4>;
++ queue-txready = <&qmgr 21>;
++ phy-mode = "rgmii";
++ phy-handle = <&phy2>;
++
++ mdio {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ phy2: ethernet-phy@2 {
++ reg = <2>;
++ };
++ };
++ };
++
++ };
++};
+diff -ruN a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
+--- a/arch/arm/boot/dts/Makefile 2021-05-17 17:34:23.627055651 +0200
++++ b/arch/arm/boot/dts/Makefile 2021-05-17 17:33:51.703194925 +0200
+@@ -244,6 +244,7 @@
+ integratorap-im-pd1.dtb \
+ integratorcp.dtb
+ dtb-$(CONFIG_ARCH_IXP4XX) += \
++ intel-ixp42x-adi-pronghorn-metro.dtb \
+ intel-ixp42x-linksys-nslu2.dtb \
+ intel-ixp42x-linksys-wrv54g.dtb \
+ intel-ixp42x-freecom-fsg-3.dtb \
--- /dev/null
+diff -ruN a/arch/arm/boot/dts/intel-ixp42x-titanwireless-tw2662.dts b/arch/arm/boot/dts/intel-ixp42x-titanwireless-tw2662.dts
+--- a/arch/arm/boot/dts/intel-ixp42x-titanwireless-tw2662.dts 1970-01-01 01:00:00.000000000 +0100
++++ b/arch/arm/boot/dts/intel-ixp42x-titanwireless-tw2662.dts 2021-05-20 23:48:13.602479932 +0200
+@@ -0,0 +1,101 @@
++// SPDX-License-Identifier: ISC
++/*
++ * Device Tree file for Titan Wireless TW266-2
++ * Copyright (c) 2021 Zoltan HERPAI <wigyori@uid0.hu>
++ */
++
++/dts-v1/;
++
++#include "intel-ixp42x.dtsi"
++#include <dt-bindings/input/input.h>
++
++/ {
++ model = "Titan Wireless 266-2";
++ compatible = "titanwireless,tw266", "intel,ixp42x";
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ memory@0 {
++ /* 64 MB SDRAM */
++ device_type = "memory";
++ reg = <0x00000000 0x4000000>;
++ };
++
++ chosen {
++ /* mem=64M taken from the tw2662-setup.c boardfile */
++ bootargs = "console=ttyS0,115200n8";
++ stdout-path = "uart0:115200n8";
++ };
++
++/* i2c {
++ compatible = "i2c-gpio";
++ sda-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
++ scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ };
++*/
++ aliases {
++ serial0 = &uart0;
++ };
++
++ soc {
++ bus@50000000 {
++ /* The first 16MB region at CS0 on the expansion bus */
++ flash@0 {
++ compatible = "intel,ixp4xx-flash", "cfi-flash";
++ bank-width = <2>;
++ /*
++ * 16 MB of Flash in 0x20000 byte blocks
++ * mapped in at CS0.
++ */
++ reg = <0x00000000 0x1000000>;
++
++ partitions {
++ compatible = "redboot-fis";
++ /* Eraseblock at 0x7e0000 */
++ fis-index-block = <0x7f>;
++ };
++ };
++ };
++
++ pci@c0000000 {
++ status = "ok";
++
++ interrupt-map =
++ /* IDSEL 1 */
++ <0x0800 0 0 1 &gpio0 11 3>, /* INT A on slot 1 is irq 11 */
++ /* IDSEL 3 */
++ <0x1800 0 0 1 &gpio0 9 3>; /* INT A on slot 3 is irq 9 */
++ };
++
++ ethernet@c8009000 {
++ status = "ok";
++ queue-rx = <&qmgr 3>;
++ queue-txready = <&qmgr 20>;
++ phy-mode = "rgmii";
++ phy-handle = <&phy3>;
++
++ mdio {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ phy1: ethernet-phy@1 {
++ reg = <1>;
++ };
++
++ phy3: ethernet-phy@3 {
++ reg = <3>;
++ };
++ };
++ };
++
++ ethernet@c800a000 {
++ status = "ok";
++ queue-rx = <&qmgr 4>;
++ queue-txready = <&qmgr 21>;
++ phy-mode = "rgmii";
++ phy-handle = <&phy1>;
++ };
++ };
++};
+diff -ruN a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
+--- a/arch/arm/boot/dts/Makefile 2021-05-19 17:41:15.911243339 +0200
++++ b/arch/arm/boot/dts/Makefile 2021-05-20 17:27:15.111961454 +0200
+@@ -247,6 +247,7 @@
+ intel-ixp42x-adi-pronghorn-metro.dtb \
+ intel-ixp42x-gateway-7001.dtb \
+ intel-ixp42x-linksys-nslu2.dtb \
++ intel-ixp42x-titanwireless-tw2662.dtb \
+ intel-ixp42x-linksys-wrv54g.dtb \
+ intel-ixp42x-freecom-fsg-3.dtb \
+ intel-ixp42x-welltech-epbx100.dtb \
--- /dev/null
+--- a/net/core/skbuff.c
++++ b/net/core/skbuff.c
+@@ -215,6 +215,9 @@ struct sk_buff *__alloc_skb(unsigned int
+
+ if (sk_memalloc_socks() && (flags & SKB_ALLOC_RX))
+ gfp_mask |= __GFP_MEMALLOC;
++#ifdef CONFIG_ARCH_IXP4XX
++ gfp_mask |= GFP_DMA;
++#endif
+
+ /* Get the HEAD */
+ skb = kmem_cache_alloc_node(cache, gfp_mask & ~__GFP_DMA, node);
+@@ -1223,6 +1226,10 @@ int pskb_expand_head(struct sk_buff *skb
+ if (skb_shared(skb))
+ BUG();
+
++#ifdef CONFIG_ARCH_IXP4XX
++ gfp_mask |= GFP_DMA;
++#endif
++
+ size = SKB_DATA_ALIGN(size);
+
+ if (skb_pfmemalloc(skb))
--- /dev/null
+diff -ruN a/scripts/Makefile b/scripts/Makefile
+--- a/scripts/Makefile 2021-05-21 17:43:33.989097196 +0200
++++ b/scripts/Makefile 2021-05-21 11:41:14.174017561 +0200
+@@ -20,7 +20,7 @@
+ HOSTCFLAGS_sign-file.o = $(CRYPTO_CFLAGS)
+ HOSTLDLIBS_sign-file = $(CRYPTO_LIBS)
+ HOSTCFLAGS_extract-cert.o = $(CRYPTO_CFLAGS)
+-HOSTLDLIBS_extract-cert = $(CRYPTO_LIBS)
++HOSTLDLIBS_extract-cert = $(CRYPTO_LIBS) -lpthread
+
+ ifdef CONFIG_UNWINDER_ORC
+ ifeq ($(ARCH),x86_64)
projects / openwrt / staging / hauke.git / commitdiff