+From f318a015330a11befd8c69336efc6284e240f535 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Alexis=20Lothor=C3=A9?= <alexis.lothore@bootlin.com>
+Date: Mon, 29 May 2023 10:02:46 +0200
+Subject: [PATCH 898/898] net: dsa: mv88e6xxx: enable support for 88E6361
+ switch
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Marvell 88E6361 is an 8-port switch derived from the
+88E6393X/88E9193X/88E6191X switches family. It can benefit from the
+existing mv88e6xxx driver by simply adding the proper switch description in
+the driver. Main differences with other switches from this
+family are:
+- 8 ports exposed (instead of 11): ports 1, 2 and 8 not available
+- No 5GBase-x nor SFI/USXGMII support
+
+Signed-off-by: Alexis Lothoré <alexis.lothore@bootlin.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Adapt to 5.15 since we dont have phylink_get_caps yet.
+So, update the old mv88e6393x_phylink_validate instead.
+Remove max_sid since 5.15 driver does not support it yet.
+[Robert Marko]
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+---
+ drivers/net/dsa/mv88e6xxx/chip.c | 49 +++++++++++++++++++++++++++++++-
+ drivers/net/dsa/mv88e6xxx/chip.h | 3 +-
+ drivers/net/dsa/mv88e6xxx/port.c | 14 +++++++--
+ drivers/net/dsa/mv88e6xxx/port.h | 1 +
+ 4 files changed, 62 insertions(+), 5 deletions(-)
+
+--- a/drivers/net/dsa/mv88e6xxx/chip.c
++++ b/drivers/net/dsa/mv88e6xxx/chip.c
+@@ -648,6 +648,8 @@ static void mv88e6393x_phylink_validate(
+ {
+ bool is_6191x =
+ chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X;
++ bool is_6361 =
++ chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361;
+
+ if (((port == 0 || port == 9) && !is_6191x) || port == 10) {
+ phylink_set(mask, 10000baseT_Full);
+@@ -662,8 +664,28 @@ static void mv88e6393x_phylink_validate(
+ phylink_set(mask, 2500baseT_Full);
+ }
+
++ if (port == 0 || port == 9 || port == 10) {
++ phylink_set(mask, 1000baseX_Full);
++
++ /* 6191X supports >1G modes only on port 10 */
++ if (!is_6191x || port == 10) {
++ phylink_set(mask, 2500baseX_Full);
++ phylink_set(mask, 2500baseT_Full);
++
++ if (!is_6361) {
++ phylink_set(mask, 10000baseT_Full);
++ phylink_set(mask, 10000baseKR_Full);
++ phylink_set(mask, 10000baseCR_Full);
++ phylink_set(mask, 10000baseSR_Full);
++ phylink_set(mask, 10000baseLR_Full);
++ phylink_set(mask, 10000baseLRM_Full);
++ phylink_set(mask, 10000baseER_Full);
++ phylink_set(mask, 5000baseT_Full);
++ }
++ }
++ }
++
+ phylink_set(mask, 1000baseT_Full);
+- phylink_set(mask, 1000baseX_Full);
+
+ mv88e6065_phylink_validate(chip, port, mask, state);
+ }
+@@ -5649,6 +5671,31 @@ static const struct mv88e6xxx_info mv88e
+ .ptp_support = true,
+ .ops = &mv88e6352_ops,
+ },
++ [MV88E6361] = {
++ .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6361,
++ .family = MV88E6XXX_FAMILY_6393,
++ .name = "Marvell 88E6361",
++ .num_databases = 4096,
++ .num_macs = 16384,
++ .num_ports = 11,
++ /* Ports 1, 2 and 8 are not routed */
++ .invalid_port_mask = BIT(1) | BIT(2) | BIT(8),
++ .num_internal_phys = 5,
++ .internal_phys_offset = 3,
++ .max_vid = 4095,
++ .port_base_addr = 0x0,
++ .phy_base_addr = 0x0,
++ .global1_addr = 0x1b,
++ .global2_addr = 0x1c,
++ .age_time_coeff = 3750,
++ .g1_irqs = 10,
++ .g2_irqs = 14,
++ .atu_move_port_mask = 0x1f,
++ .pvt = true,
++ .multi_chip = true,
++ .ptp_support = true,
++ .ops = &mv88e6393x_ops,
++ },
+ [MV88E6390] = {
+ .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
+ .family = MV88E6XXX_FAMILY_6390,
+--- a/drivers/net/dsa/mv88e6xxx/chip.h
++++ b/drivers/net/dsa/mv88e6xxx/chip.h
+@@ -81,6 +81,7 @@ enum mv88e6xxx_model {
+ MV88E6350,
+ MV88E6351,
+ MV88E6352,
++ MV88E6361,
+ MV88E6390,
+ MV88E6390X,
+ MV88E6393X,
+@@ -99,7 +100,7 @@ enum mv88e6xxx_family {
+ MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */
+ MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */
+ MV88E6XXX_FAMILY_6390, /* 6190 6190X 6191 6290 6390 6390X */
+- MV88E6XXX_FAMILY_6393, /* 6191X 6193X 6393X */
++ MV88E6XXX_FAMILY_6393, /* 6191X 6193X 6361 6393X */
+ };
+
+ /**
+--- a/drivers/net/dsa/mv88e6xxx/port.c
++++ b/drivers/net/dsa/mv88e6xxx/port.c
+@@ -451,6 +451,10 @@ int mv88e6393x_port_set_speed_duplex(str
+ if (speed == SPEED_MAX)
+ speed = (port > 0 && port < 9) ? 1000 : 10000;
+
++ if (chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361 &&
++ speed > 2500)
++ return -EOPNOTSUPP;
++
+ if (speed == 200 && port != 0)
+ return -EOPNOTSUPP;
+
+@@ -533,10 +537,14 @@ int mv88e6393x_port_set_speed_duplex(str
+ phy_interface_t mv88e6393x_port_max_speed_mode(struct mv88e6xxx_chip *chip,
+ int port)
+ {
+- if (port == 0 || port == 9 || port == 10)
+- return PHY_INTERFACE_MODE_10GBASER;
+
+- return PHY_INTERFACE_MODE_NA;
++ if (port != 0 && port != 9 && port != 10)
++ return PHY_INTERFACE_MODE_NA;
++
++ if (chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361)
++ return PHY_INTERFACE_MODE_2500BASEX;
++
++ return PHY_INTERFACE_MODE_10GBASER;
+ }
+
+ static int mv88e6xxx_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
+--- a/drivers/net/dsa/mv88e6xxx/port.h
++++ b/drivers/net/dsa/mv88e6xxx/port.h
+@@ -128,6 +128,7 @@
+ #define MV88E6XXX_PORT_SWITCH_ID_PROD_6220 0x2200
+ #define MV88E6XXX_PORT_SWITCH_ID_PROD_6240 0x2400
+ #define MV88E6XXX_PORT_SWITCH_ID_PROD_6250 0x2500
++#define MV88E6XXX_PORT_SWITCH_ID_PROD_6361 0x2610
+ #define MV88E6XXX_PORT_SWITCH_ID_PROD_6290 0x2900
+ #define MV88E6XXX_PORT_SWITCH_ID_PROD_6321 0x3100
+ #define MV88E6XXX_PORT_SWITCH_ID_PROD_6141 0x3400