X-Git-Url: http://git.openwrt.org/?a=blobdiff_plain;f=target%2Flinux%2Fgeneric%2Ffiles%2Fdrivers%2Fnet%2Fphy%2Far8327.h;h=828dd28f38617a2256948b8b46460ba459199e73;hb=7ccfa826eebfdc514e537ad25f75b76bb2554a60;hp=c606972a04ed724cc41b092ddff9eb483876f015;hpb=cc02d4c72dbe7b4ef143e390776792260503bd53;p=openwrt%2Fopenwrt.git diff --git a/target/linux/generic/files/drivers/net/phy/ar8327.h b/target/linux/generic/files/drivers/net/phy/ar8327.h index c606972a04..828dd28f38 100644 --- a/target/linux/generic/files/drivers/net/phy/ar8327.h +++ b/target/linux/generic/files/drivers/net/phy/ar8327.h @@ -1,7 +1,7 @@ /* * ar8327.h: AR8216 switch driver * - * Copyright (C) 2009 Felix Fietkau + * Copyright (C) 2009 Felix Fietkau * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -84,6 +84,8 @@ #define AR8327_MAX_FRAME_SIZE_MTU BITS(0, 14) #define AR8327_REG_PORT_STATUS(_i) (0x07c + (_i) * 4) +#define AR8327_PORT_STATUS_TXFLOW_AUTO BIT(10) +#define AR8327_PORT_STATUS_RXFLOW_AUTO BIT(11) #define AR8327_REG_HEADER_CTRL 0x098 #define AR8327_REG_PORT_HEADER(_i) (0x09c + (_i) * 4) @@ -96,6 +98,71 @@ #define AR8327_REG_EEE_CTRL 0x100 #define AR8327_EEE_CTRL_DISABLE_PHY(_i) BIT(4 + (_i) * 2) +#define AR8327_REG_FRAME_ACK_CTRL0 0x210 +#define AR8327_FRAME_ACK_CTRL_IGMP_MLD_EN0 BIT(0) +#define AR8327_FRAME_ACK_CTRL_IGMP_JOIN_EN0 BIT(1) +#define AR8327_FRAME_ACK_CTRL_IGMP_LEAVE_EN0 BIT(2) +#define AR8327_FRAME_ACK_CTRL_EAPOL_EN0 BIT(3) +#define AR8327_FRAME_ACK_CTRL_DHCP_EN0 BIT(4) +#define AR8327_FRAME_ACK_CTRL_ARP_ACK_EN0 BIT(5) +#define AR8327_FRAME_ACK_CTRL_ARP_REQ_EN0 BIT(6) +#define AR8327_FRAME_ACK_CTRL_IGMP_MLD_EN1 BIT(8) +#define AR8327_FRAME_ACK_CTRL_IGMP_JOIN_EN1 BIT(9) +#define AR8327_FRAME_ACK_CTRL_IGMP_LEAVE_EN1 BIT(10) +#define AR8327_FRAME_ACK_CTRL_EAPOL_EN1 BIT(11) +#define AR8327_FRAME_ACK_CTRL_DHCP_EN1 BIT(12) +#define AR8327_FRAME_ACK_CTRL_ARP_ACK_EN1 BIT(13) +#define AR8327_FRAME_ACK_CTRL_ARP_REQ_EN1 BIT(14) +#define AR8327_FRAME_ACK_CTRL_IGMP_MLD_EN2 BIT(16) +#define AR8327_FRAME_ACK_CTRL_IGMP_JOIN_EN2 BIT(17) +#define AR8327_FRAME_ACK_CTRL_IGMP_LEAVE_EN2 BIT(18) +#define AR8327_FRAME_ACK_CTRL_EAPOL_EN2 BIT(19) +#define AR8327_FRAME_ACK_CTRL_DHCP_EN2 BIT(20) +#define AR8327_FRAME_ACK_CTRL_ARP_ACK_EN2 BIT(21) +#define AR8327_FRAME_ACK_CTRL_ARP_REQ_EN2 BIT(22) +#define AR8327_FRAME_ACK_CTRL_IGMP_MLD_EN3 BIT(24) +#define AR8327_FRAME_ACK_CTRL_IGMP_JOIN_EN3 BIT(25) +#define AR8327_FRAME_ACK_CTRL_IGMP_LEAVE_EN3 BIT(26) +#define AR8327_FRAME_ACK_CTRL_EAPOL_EN3 BIT(27) +#define AR8327_FRAME_ACK_CTRL_DHCP_EN3 BIT(28) +#define AR8327_FRAME_ACK_CTRL_ARP_ACK_EN3 BIT(29) +#define AR8327_FRAME_ACK_CTRL_ARP_REQ_EN3 BIT(30) + +#define AR8327_REG_FRAME_ACK_CTRL1 0x214 +#define AR8327_FRAME_ACK_CTRL_IGMP_MLD_EN4 BIT(0) +#define AR8327_FRAME_ACK_CTRL_IGMP_JOIN_EN4 BIT(1) +#define AR8327_FRAME_ACK_CTRL_IGMP_LEAVE_EN4 BIT(2) +#define AR8327_FRAME_ACK_CTRL_EAPOL_EN4 BIT(3) +#define AR8327_FRAME_ACK_CTRL_DHCP_EN4 BIT(4) +#define AR8327_FRAME_ACK_CTRL_ARP_ACK_EN4 BIT(5) +#define AR8327_FRAME_ACK_CTRL_ARP_REQ_EN4 BIT(6) +#define AR8327_FRAME_ACK_CTRL_IGMP_MLD_EN5 BIT(8) +#define AR8327_FRAME_ACK_CTRL_IGMP_JOIN_EN5 BIT(9) +#define AR8327_FRAME_ACK_CTRL_IGMP_LEAVE_EN5 BIT(10) +#define AR8327_FRAME_ACK_CTRL_EAPOL_EN5 BIT(11) +#define AR8327_FRAME_ACK_CTRL_DHCP_EN5 BIT(12) +#define AR8327_FRAME_ACK_CTRL_ARP_ACK_EN5 BIT(13) +#define AR8327_FRAME_ACK_CTRL_ARP_REQ_EN5 BIT(14) +#define AR8327_FRAME_ACK_CTRL_IGMP_MLD_EN6 BIT(16) +#define AR8327_FRAME_ACK_CTRL_IGMP_JOIN_EN6 BIT(17) +#define AR8327_FRAME_ACK_CTRL_IGMP_LEAVE_EN6 BIT(18) +#define AR8327_FRAME_ACK_CTRL_EAPOL_EN6 BIT(19) +#define AR8327_FRAME_ACK_CTRL_DHCP_EN6 BIT(20) +#define AR8327_FRAME_ACK_CTRL_ARP_ACK_EN6 BIT(21) +#define AR8327_FRAME_ACK_CTRL_ARP_REQ_EN6 BIT(22) +#define AR8327_FRAME_ACK_CTRL_IGMP_V3_EN BIT(24) +#define AR8327_FRAME_ACK_CTRL_PPPOE_EN BIT(25) + +#define AR8327_REG_FRAME_ACK_CTRL(_i) (0x210 + ((_i) / 4) * 0x4) +#define AR8327_FRAME_ACK_CTRL_IGMP_MLD BIT(0) +#define AR8327_FRAME_ACK_CTRL_IGMP_JOIN BIT(1) +#define AR8327_FRAME_ACK_CTRL_IGMP_LEAVE BIT(2) +#define AR8327_FRAME_ACK_CTRL_EAPOL BIT(3) +#define AR8327_FRAME_ACK_CTRL_DHCP BIT(4) +#define AR8327_FRAME_ACK_CTRL_ARP_ACK BIT(5) +#define AR8327_FRAME_ACK_CTRL_ARP_REQ BIT(6) +#define AR8327_FRAME_ACK_CTRL_S(_i) (((_i) % 4) * 8) + #define AR8327_REG_PORT_VLAN0(_i) (0x420 + (_i) * 0x8) #define AR8327_PORT_VLAN0_DEF_SVID BITS(0, 12) #define AR8327_PORT_VLAN0_DEF_SVID_S 0 @@ -112,8 +179,29 @@ #define AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH 3 #define AR8327_REG_ATU_DATA0 0x600 +#define AR8327_ATU_ADDR0 BITS(0, 8) +#define AR8327_ATU_ADDR0_S 0 +#define AR8327_ATU_ADDR1 BITS(8, 8) +#define AR8327_ATU_ADDR1_S 8 +#define AR8327_ATU_ADDR2 BITS(16, 8) +#define AR8327_ATU_ADDR2_S 16 +#define AR8327_ATU_ADDR3 BITS(24, 8) +#define AR8327_ATU_ADDR3_S 24 #define AR8327_REG_ATU_DATA1 0x604 +#define AR8327_ATU_ADDR4 BITS(0, 8) +#define AR8327_ATU_ADDR4_S 0 +#define AR8327_ATU_ADDR5 BITS(8, 8) +#define AR8327_ATU_ADDR5_S 8 +#define AR8327_ATU_PORTS BITS(16, 7) +#define AR8327_ATU_PORT0 BIT(16) +#define AR8327_ATU_PORT1 BIT(17) +#define AR8327_ATU_PORT2 BIT(18) +#define AR8327_ATU_PORT3 BIT(19) +#define AR8327_ATU_PORT4 BIT(20) +#define AR8327_ATU_PORT5 BIT(21) +#define AR8327_ATU_PORT6 BIT(22) #define AR8327_REG_ATU_DATA2 0x608 +#define AR8327_ATU_STATUS BITS(0, 4) #define AR8327_REG_ATU_FUNC 0x60c #define AR8327_ATU_FUNC_OP BITS(0, 4) @@ -121,11 +209,13 @@ #define AR8327_ATU_FUNC_OP_FLUSH 0x1 #define AR8327_ATU_FUNC_OP_LOAD 0x2 #define AR8327_ATU_FUNC_OP_PURGE 0x3 -#define AR8327_ATU_FUNC_OP_FLUSH_LOCKED 0x4 -#define AR8327_ATU_FUNC_OP_FLUSH_UNICAST 0x5 +#define AR8327_ATU_FUNC_OP_FLUSH_UNLOCKED 0x4 +#define AR8327_ATU_FUNC_OP_FLUSH_PORT 0x5 #define AR8327_ATU_FUNC_OP_GET_NEXT 0x6 #define AR8327_ATU_FUNC_OP_SEARCH_MAC 0x7 #define AR8327_ATU_FUNC_OP_CHANGE_TRUNK 0x8 +#define AR8327_ATU_PORT_NUM BITS(8, 4) +#define AR8327_ATU_PORT_NUM_S 8 #define AR8327_ATU_FUNC_BUSY BIT(31) #define AR8327_REG_VTU_FUNC0 0x0610 @@ -154,6 +244,8 @@ #define AR8327_VTU_FUNC1_VID_S 16 #define AR8327_VTU_FUNC1_BUSY BIT(31) +#define AR8327_REG_ARL_CTRL 0x0618 + #define AR8327_REG_FWD_CTRL0 0x620 #define AR8327_FWD_CTRL0_CPU_PORT_EN BIT(10) #define AR8327_FWD_CTRL0_MIRROR_PORT BITS(4, 4) @@ -180,7 +272,28 @@ #define AR8327_REG_PORT_PRIO(_i) (0x664 + (_i) * 0xc) +#define AR8327_REG_PORT_HOL_CTRL0(_i) (0x970 + (_i) * 0x8) +#define AR8327_PORT_HOL_CTRL0_EG_PRI0_BUF BITS(0, 4) +#define AR8327_PORT_HOL_CTRL0_EG_PRI0_BUF_S 0 +#define AR8327_PORT_HOL_CTRL0_EG_PRI1_BUF BITS(4, 4) +#define AR8327_PORT_HOL_CTRL0_EG_PRI1_BUF_S 4 +#define AR8327_PORT_HOL_CTRL0_EG_PRI2_BUF BITS(8, 4) +#define AR8327_PORT_HOL_CTRL0_EG_PRI2_BUF_S 8 +#define AR8327_PORT_HOL_CTRL0_EG_PRI3_BUF BITS(12, 4) +#define AR8327_PORT_HOL_CTRL0_EG_PRI3_BUF_S 12 +#define AR8327_PORT_HOL_CTRL0_EG_PRI4_BUF BITS(16, 4) +#define AR8327_PORT_HOL_CTRL0_EG_PRI4_BUF_S 16 +#define AR8327_PORT_HOL_CTRL0_EG_PRI5_BUF BITS(20, 4) +#define AR8327_PORT_HOL_CTRL0_EG_PRI5_BUF_S 20 +#define AR8327_PORT_HOL_CTRL0_EG_PORT_BUF BITS(24, 6) +#define AR8327_PORT_HOL_CTRL0_EG_PORT_BUF_S 24 + #define AR8327_REG_PORT_HOL_CTRL1(_i) (0x974 + (_i) * 0x8) +#define AR8327_PORT_HOL_CTRL1_ING_BUF BITS(0, 4) +#define AR8327_PORT_HOL_CTRL1_ING_BUF_S 0 +#define AR8327_PORT_HOL_CTRL1_EG_PRI_BUF_EN BIT(6) +#define AR8327_PORT_HOL_CTRL1_EG_PORT_BUF_EN BIT(7) +#define AR8327_PORT_HOL_CTRL1_WRED_EN BIT(8) #define AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN BIT(16) #define AR8337_PAD_MAC06_EXCHANGE_EN BIT(31) @@ -219,6 +332,9 @@ struct ar8327_data { struct ar8327_led **leds; unsigned int num_leds; + + /* all fields below are cleared on reset */ + bool eee[AR8XXX_NUM_PHYS]; }; #endif