X-Git-Url: http://git.openwrt.org/?a=blobdiff_plain;ds=sidebyside;f=target%2Flinux%2Far71xx%2Fpatches-4.4%2F601-MIPS-ath79-add-more-register-defines.patch;h=03ca106d0d8833cd19e80a4d4adff5be53266605;hb=837285b83221963739cda81911d8004f30f9afb0;hp=0126f6a3b9d83e3366965ae9471943b8ec9a9bc6;hpb=ad0c1d3a310554af94659d82f75ecb5e9013baeb;p=openwrt%2Fstaging%2Fflorian.git

diff --git a/target/linux/ar71xx/patches-4.4/601-MIPS-ath79-add-more-register-defines.patch b/target/linux/ar71xx/patches-4.4/601-MIPS-ath79-add-more-register-defines.patch
index 0126f6a3b9..03ca106d0d 100644
--- a/target/linux/ar71xx/patches-4.4/601-MIPS-ath79-add-more-register-defines.patch
+++ b/target/linux/ar71xx/patches-4.4/601-MIPS-ath79-add-more-register-defines.patch
@@ -58,7 +58,7 @@
  
  #define AR9300_OTP_BASE		0x14000
  #define AR9300_OTP_STATUS	0x15f18
-@@ -174,6 +190,9 @@
+@@ -181,6 +197,9 @@
  #define AR71XX_AHB_DIV_SHIFT		20
  #define AR71XX_AHB_DIV_MASK		0x7
  
@@ -68,7 +68,7 @@
  #define AR724X_PLL_REG_CPU_CONFIG	0x00
  #define AR724X_PLL_REG_PCIE_CONFIG	0x18
  
-@@ -186,6 +205,8 @@
+@@ -193,6 +212,8 @@
  #define AR724X_DDR_DIV_SHIFT		22
  #define AR724X_DDR_DIV_MASK		0x3
  
@@ -77,7 +77,7 @@
  #define AR913X_PLL_REG_CPU_CONFIG	0x00
  #define AR913X_PLL_REG_ETH_CONFIG	0x04
  #define AR913X_PLL_REG_ETH0_INT_CLOCK	0x14
-@@ -198,6 +219,9 @@
+@@ -205,6 +226,9 @@
  #define AR913X_AHB_DIV_SHIFT		19
  #define AR913X_AHB_DIV_MASK		0x1
  
@@ -87,7 +87,7 @@
  #define AR933X_PLL_CPU_CONFIG_REG	0x00
  #define AR933X_PLL_CLOCK_CTRL_REG	0x08
  
-@@ -219,6 +243,8 @@
+@@ -226,6 +250,8 @@
  #define AR934X_PLL_CPU_CONFIG_REG		0x00
  #define AR934X_PLL_DDR_CONFIG_REG		0x04
  #define AR934X_PLL_CPU_DDR_CLK_CTRL_REG		0x08
@@ -96,7 +96,7 @@
  
  #define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT	0
  #define AR934X_PLL_CPU_CONFIG_NFRAC_MASK	0x3f
-@@ -251,9 +277,13 @@
+@@ -258,9 +284,13 @@
  #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL	BIT(21)
  #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL	BIT(24)
  
@@ -110,7 +110,7 @@
  
  #define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT	0
  #define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK	0x3f
-@@ -378,16 +408,83 @@
+@@ -385,16 +415,83 @@
  #define AR913X_RESET_USB_HOST		BIT(5)
  #define AR913X_RESET_USB_PHY		BIT(4)
  
@@ -155,7 +155,7 @@
 +#define AR934X_RESET_LUT		BIT(2)
 +#define AR934X_RESET_MBOX		BIT(1)
 +#define AR934X_RESET_I2S		BIT(0)
-+
+ 
 +#define QCA955X_RESET_HOST		BIT(31)
 +#define QCA955X_RESET_SLIC		BIT(30)
 +#define QCA955X_RESET_HDMA		BIT(29)
@@ -188,13 +188,13 @@
 +#define QCA955X_RESET_LUT		BIT(2)
 +#define QCA955X_RESET_MBOX		BIT(1)
 +#define QCA955X_RESET_I2S		BIT(0)
- 
++
 +#define AR933X_BOOTSTRAP_MDIO_GPIO_EN	BIT(18)
 +#define AR933X_BOOTSTRAP_EEPBUSY	BIT(4)
  #define AR933X_BOOTSTRAP_REF_CLK_40	BIT(0)
  
  #define AR934X_BOOTSTRAP_SW_OPTION8	BIT(23)
-@@ -529,8 +626,22 @@
+@@ -536,8 +633,22 @@
  #define AR71XX_GPIO_REG_INT_ENABLE	0x24
  #define AR71XX_GPIO_REG_FUNC		0x28
  
@@ -217,7 +217,7 @@
  #define AR71XX_GPIO_COUNT		16
  #define AR7240_GPIO_COUNT		18
  #define AR7241_GPIO_COUNT		20
-@@ -560,4 +671,235 @@
+@@ -567,4 +678,235 @@
  #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT	13
  #define AR934X_SRIF_DPLL2_OUTDIV_MASK	0x7