extern struct mutex smi_lock;
-// see_dal_maple_acl_log2PhyTmplteField and src/app/diag_v2/src/diag_acl.c
+/* see_dal_maple_acl_log2PhyTmplteField and src/app/diag_v2/src/diag_acl.c */
/* Definition of the RTL838X-specific template field IDs as used in the PIE */
enum template_field_id {
TEMPLATE_FIELD_SPMMASK = 0,
- TEMPLATE_FIELD_SPM0 = 1, // Source portmask ports 0-15
- TEMPLATE_FIELD_SPM1 = 2, // Source portmask ports 16-28
+ TEMPLATE_FIELD_SPM0 = 1, /* Source portmask ports 0-15 */
+ TEMPLATE_FIELD_SPM1 = 2, /* Source portmask ports 16-28 */
TEMPLATE_FIELD_RANGE_CHK = 3,
- TEMPLATE_FIELD_DMAC0 = 4, // Destination MAC [15:0]
- TEMPLATE_FIELD_DMAC1 = 5, // Destination MAC [31:16]
- TEMPLATE_FIELD_DMAC2 = 6, // Destination MAC [47:32]
- TEMPLATE_FIELD_SMAC0 = 7, // Source MAC [15:0]
- TEMPLATE_FIELD_SMAC1 = 8, // Source MAC [31:16]
- TEMPLATE_FIELD_SMAC2 = 9, // Source MAC [47:32]
- TEMPLATE_FIELD_ETHERTYPE = 10, // Ethernet typ
- TEMPLATE_FIELD_OTAG = 11, // Outer VLAN tag
- TEMPLATE_FIELD_ITAG = 12, // Inner VLAN tag
- TEMPLATE_FIELD_SIP0 = 13, // IPv4 or IPv6 source IP[15:0] or ARP/RARP
- // source protocol address in header
- TEMPLATE_FIELD_SIP1 = 14, // IPv4 or IPv6 source IP[31:16] or ARP/RARP
- TEMPLATE_FIELD_DIP0 = 15, // IPv4 or IPv6 destination IP[15:0]
- TEMPLATE_FIELD_DIP1 = 16, // IPv4 or IPv6 destination IP[31:16]
- TEMPLATE_FIELD_IP_TOS_PROTO = 17, // IPv4 TOS/IPv6 traffic class and
- // IPv4 proto/IPv6 next header fields
- TEMPLATE_FIELD_L34_HEADER = 18, // packet with extra tag and IPv6 with auth, dest,
- // frag, route, hop-by-hop option header,
- // IGMP type, TCP flag
- TEMPLATE_FIELD_L4_SPORT = 19, // TCP/UDP source port
- TEMPLATE_FIELD_L4_DPORT = 20, // TCP/UDP destination port
+ TEMPLATE_FIELD_DMAC0 = 4, /* Destination MAC [15:0] */
+ TEMPLATE_FIELD_DMAC1 = 5, /* Destination MAC [31:16] */
+ TEMPLATE_FIELD_DMAC2 = 6, /* Destination MAC [47:32] */
+ TEMPLATE_FIELD_SMAC0 = 7, /* Source MAC [15:0] */
+ TEMPLATE_FIELD_SMAC1 = 8, /* Source MAC [31:16] */
+ TEMPLATE_FIELD_SMAC2 = 9, /* Source MAC [47:32] */
+ TEMPLATE_FIELD_ETHERTYPE = 10, /* Ethernet typ */
+ TEMPLATE_FIELD_OTAG = 11, /* Outer VLAN tag */
+ TEMPLATE_FIELD_ITAG = 12, /* Inner VLAN tag */
+ TEMPLATE_FIELD_SIP0 = 13, /* IPv4 or IPv6 source IP[15:0] or ARP/RARP */
+ /* source protocol address in header */
+ TEMPLATE_FIELD_SIP1 = 14, /* IPv4 or IPv6 source IP[31:16] or ARP/RARP */
+ TEMPLATE_FIELD_DIP0 = 15, /* IPv4 or IPv6 destination IP[15:0] */
+ TEMPLATE_FIELD_DIP1 = 16, /* IPv4 or IPv6 destination IP[31:16] */
+ TEMPLATE_FIELD_IP_TOS_PROTO = 17, /* IPv4 TOS/IPv6 traffic class and */
+ /* IPv4 proto/IPv6 next header fields */
+ TEMPLATE_FIELD_L34_HEADER = 18, /* packet with extra tag and IPv6 with auth, dest, */
+ /* frag, route, hop-by-hop option header, */
+ /* IGMP type, TCP flag */
+ TEMPLATE_FIELD_L4_SPORT = 19, /* TCP/UDP source port */
+ TEMPLATE_FIELD_L4_DPORT = 20, /* TCP/UDP destination port */
TEMPLATE_FIELD_ICMP_IGMP = 21,
TEMPLATE_FIELD_IP_RANGE = 22,
- TEMPLATE_FIELD_FIELD_SELECTOR_VALID = 23, // Field selector mask
+ TEMPLATE_FIELD_FIELD_SELECTOR_VALID = 23, /* Field selector mask */
TEMPLATE_FIELD_FIELD_SELECTOR_0 = 24,
TEMPLATE_FIELD_FIELD_SELECTOR_1 = 25,
TEMPLATE_FIELD_FIELD_SELECTOR_2 = 26,
TEMPLATE_FIELD_FIELD_SELECTOR_3 = 27,
- TEMPLATE_FIELD_SIP2 = 28, // IPv6 source IP[47:32]
- TEMPLATE_FIELD_SIP3 = 29, // IPv6 source IP[63:48]
- TEMPLATE_FIELD_SIP4 = 30, // IPv6 source IP[79:64]
- TEMPLATE_FIELD_SIP5 = 31, // IPv6 source IP[95:80]
- TEMPLATE_FIELD_SIP6 = 32, // IPv6 source IP[111:96]
- TEMPLATE_FIELD_SIP7 = 33, // IPv6 source IP[127:112]
- TEMPLATE_FIELD_DIP2 = 34, // IPv6 destination IP[47:32]
- TEMPLATE_FIELD_DIP3 = 35, // IPv6 destination IP[63:48]
- TEMPLATE_FIELD_DIP4 = 36, // IPv6 destination IP[79:64]
- TEMPLATE_FIELD_DIP5 = 37, // IPv6 destination IP[95:80]
- TEMPLATE_FIELD_DIP6 = 38, // IPv6 destination IP[111:96]
- TEMPLATE_FIELD_DIP7 = 39, // IPv6 destination IP[127:112]
- TEMPLATE_FIELD_FWD_VID = 40, // Forwarding VLAN-ID
+ TEMPLATE_FIELD_SIP2 = 28, /* IPv6 source IP[47:32] */
+ TEMPLATE_FIELD_SIP3 = 29, /* IPv6 source IP[63:48] */
+ TEMPLATE_FIELD_SIP4 = 30, /* IPv6 source IP[79:64] */
+ TEMPLATE_FIELD_SIP5 = 31, /* IPv6 source IP[95:80] */
+ TEMPLATE_FIELD_SIP6 = 32, /* IPv6 source IP[111:96] */
+ TEMPLATE_FIELD_SIP7 = 33, /* IPv6 source IP[127:112] */
+ TEMPLATE_FIELD_DIP2 = 34, /* IPv6 destination IP[47:32] */
+ TEMPLATE_FIELD_DIP3 = 35, /* IPv6 destination IP[63:48] */
+ TEMPLATE_FIELD_DIP4 = 36, /* IPv6 destination IP[79:64] */
+ TEMPLATE_FIELD_DIP5 = 37, /* IPv6 destination IP[95:80] */
+ TEMPLATE_FIELD_DIP6 = 38, /* IPv6 destination IP[111:96] */
+ TEMPLATE_FIELD_DIP7 = 39, /* IPv6 destination IP[127:112] */
+ TEMPLATE_FIELD_FWD_VID = 40, /* Forwarding VLAN-ID */
TEMPLATE_FIELD_FLOW_LABEL = 41,
};
static void rtl838x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info)
{
u32 v;
- // Read VLAN table (0) via register 0
+ /* Read VLAN table (0) via register 0 */
struct table_reg *r = rtl_table_get(RTL8380_TBL_0, 0);
rtl_table_read(r, vlan);
info->hash_uc_fid = !!(v & 0x10);
info->fid = (v >> 5) & 0x3f;
- // Read UNTAG table (0) via table register 1
+ /* Read UNTAG table (0) via table register 1 */
r = rtl_table_get(RTL8380_TBL_1, 0);
rtl_table_read(r, vlan);
info->untagged_ports = sw_r32(rtl_table_data(r, 0));
static void rtl838x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info)
{
u32 v;
- // Access VLAN table (0) via register 0
+ /* Access VLAN table (0) via register 0 */
struct table_reg *r = rtl_table_get(RTL8380_TBL_0, 0);
sw_w32(info->tagged_ports, rtl_table_data(r, 0));
static void rtl838x_vlan_set_untagged(u32 vlan, u64 portmask)
{
- // Access UNTAG table (0) via register 1
+ /* Access UNTAG table (0) via register 1 */
struct table_reg *r = rtl_table_get(RTL8380_TBL_1, 0);
sw_w32(portmask & 0x1fffffff, rtl_table_data(r, 0));
e->valid = false;
else
e->type = L2_UNICAST;
- } else { // L2 multicast
+ } else { /* L2 multicast */
pr_debug("Got L2 MC entry: %08x %08x %08x\n", r[0], r[1], r[2]);
e->valid = true;
e->type = L2_MULTICAST;
e->mc_portmask_index = (r[0] >> 12) & 0x1ff;
}
- } else { // IPv4 and IPv6 multicast
+ } else { /* IPv4 and IPv6 multicast */
e->valid = true;
e->mc_portmask_index = (r[0] >> 12) & 0x1ff;
e->mc_gip = (r[1] << 20) | (r[2] >> 12);
r[0] |= e->nh_route_id & 0x1ff;
}
r[0] |= (e->age & 0x3) << 17;
- } else { // L2 Multicast
+ } else { /* L2 Multicast */
r[0] |= (e->mc_portmask_index & 0x1ff) << 12;
r[2] |= e->rvid & 0xfff;
r[0] |= e->vid & 0xfff;
pr_debug("FILL MC: %08x %08x %08x\n", r[0], r[1], r[2]);
}
- } else { // IPv4 and IPv6 multicast
+ } else { /* IPv4 and IPv6 multicast */
r[0] |= (e->mc_portmask_index & 0x1ff) << 12;
r[1] = e->mc_gip >> 20;
r[2] = e->mc_gip << 12;
static u64 rtl838x_read_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e)
{
u32 r[3];
- struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 0); // Access L2 Table 0
- u32 idx = (0 << 14) | (hash << 2) | pos; // Search SRAM, with hash and at pos in bucket
+ struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 0); /* Access L2 Table 0 */
+ u32 idx = (0 << 14) | (hash << 2) | pos; /* Search SRAM, with hash and at pos in bucket */
int i;
rtl_table_read(q, idx);
if (!e->valid)
return 0;
- return (((u64) r[1]) << 32) | (r[2]); // mac and vid concatenated as hash seed
+ return (((u64) r[1]) << 32) | (r[2]); /* mac and vid concatenated as hash seed */
}
static void rtl838x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e)
struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 0);
int i;
- u32 idx = (0 << 14) | (hash << 2) | pos; // Access SRAM, with hash and at pos in bucket
+ u32 idx = (0 << 14) | (hash << 2) | pos; /* Access SRAM, with hash and at pos in bucket */
rtl838x_fill_l2_row(r, e);
static u64 rtl838x_read_cam(int idx, struct rtl838x_l2_entry *e)
{
u32 r[3];
- struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 1); // Access L2 Table 1
+ struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 1); /* Access L2 Table 1 */
int i;
rtl_table_read(q, idx);
pr_debug("Found in CAM: R1 %x R2 %x R3 %x\n", r[0], r[1], r[2]);
- // Return MAC with concatenated VID ac concatenated ID
+ /* Return MAC with concatenated VID ac concatenated ID */
return (((u64) r[1]) << 32) | r[2];
}
static void rtl838x_write_cam(int idx, struct rtl838x_l2_entry *e)
{
u32 r[3];
- struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 1); // Access L2 Table 1
+ struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 1); /* Access L2 Table 1 */
int i;
rtl838x_fill_l2_row(r, e);
static u64 rtl838x_read_mcast_pmask(int idx)
{
u32 portmask;
- // Read MC_PMSK (2) via register RTL8380_TBL_L2
+ /* Read MC_PMSK (2) via register RTL8380_TBL_L2 */
struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 2);
rtl_table_read(q, idx);
static void rtl838x_write_mcast_pmask(int idx, u64 portmask)
{
- // Access MC_PMSK (2) via register RTL8380_TBL_L2
+ /* Access MC_PMSK (2) via register RTL8380_TBL_L2 */
struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 2);
sw_w32(((u32)portmask) & 0x1fffffff, rtl_table_data(q, 0));
static void rtl838x_vlan_profile_setup(int profile)
{
u32 pmask_id = UNKNOWN_MC_PMASK;
- // Enable L2 Learning BIT 0, portmask UNKNOWN_MC_PMASK for unknown MC traffic flooding
+ /* Enable L2 Learning BIT 0, portmask UNKNOWN_MC_PMASK for unknown MC traffic flooding */
u32 p = 1 | pmask_id << 1 | pmask_id << 10 | pmask_id << 19;
sw_w32(p, RTL838X_VLAN_PROFILE(profile));
* and per vlan (bit 2) */
sw_w32(0x7, RTL838X_L2_LRN_CONSTRT_EN);
- // Limit learning to maximum: 16k entries, after that just flood (bits 0-1)
+ /* Limit learning to maximum: 16k entries, after that just flood (bits 0-1) */
sw_w32((0x3fff << 2) | 0, RTL838X_L2_LRN_CONSTRT);
- // Do not trap ARP packets to CPU_PORT
+ /* Do not trap ARP packets to CPU_PORT */
sw_w32(0, RTL838X_SPCL_TRAP_ARP_CTRL);
}
static void rtl838x_enable_learning(int port, bool enable)
{
- // Limit learning to maximum: 16k entries
+ /* Limit learning to maximum: 16k entries */
sw_w32_mask(0x3fff << 2, enable ? (0x3fff << 2) : 0,
RTL838X_L2_PORT_LRN_CONSTRT + (port << 2));
{
u32 v;
- // This works only for Ethernet ports, and on the RTL838X, ports from 24 are SFP
+ /* This works only for Ethernet ports, and on the RTL838X, ports from 24 are SFP */
if (port >= 24)
return;
pr_debug("In %s: setting port %d to %d\n", __func__, port, enable);
v = enable ? 0x3 : 0x0;
- // Set EEE state for 100 (bit 9) & 1000MBit (bit 10)
+ /* Set EEE state for 100 (bit 9) & 1000MBit (bit 10) */
sw_w32_mask(0x3 << 9, v << 9, priv->r->mac_force_mode_ctrl(port));
- // Set TX/RX EEE state
+ /* Set TX/RX EEE state */
if (enable) {
sw_w32_mask(0, BIT(port), RTL838X_EEE_PORT_TX_EN);
sw_w32_mask(0, BIT(port), RTL838X_EEE_PORT_RX_EN);
sw_w32(0x5001411, RTL838X_EEE_TX_TIMER_GIGA_CTRL);
sw_w32(0x5001417, RTL838X_EEE_TX_TIMER_GELITE_CTRL);
- // Enable EEE MAC support on ports
+ /* Enable EEE MAC support on ports */
for (i = 0; i < priv->cpu_port; i++) {
if (priv->ports[i].phy)
rtl838x_port_eee_set(priv, i, enable);
int block = index / PIE_BLOCK_SIZE;
u32 block_state = sw_r32(RTL838X_ACL_BLK_LOOKUP_CTRL);
- // Make sure rule-lookup is enabled in the block
+ /* Make sure rule-lookup is enabled in the block */
if (!(block_state & BIT(block)))
sw_w32(block_state | BIT(block), RTL838X_ACL_BLK_LOOKUP_CTRL);
}
pr_debug("%s: from %d to %d\n", __func__, index_from, index_to);
mutex_lock(&priv->reg_mutex);
- // Remember currently active blocks
+ /* Remember currently active blocks */
block_state = sw_r32(RTL838X_ACL_BLK_LOOKUP_CTRL);
- // Make sure rule-lookup is disabled in the relevant blocks
+ /* Make sure rule-lookup is disabled in the relevant blocks */
for (block = block_from; block <= block_to; block++) {
if (block_state & BIT(block))
sw_w32(block_state & (~BIT(block)), RTL838X_ACL_BLK_LOOKUP_CTRL);
}
- // Write from-to and execute bit into control register
+ /* Write from-to and execute bit into control register */
sw_w32(v, RTL838X_ACL_CLR_CTRL);
- // Wait until command has completed
+ /* Wait until command has completed */
do {
} while (sw_r32(RTL838X_ACL_CLR_CTRL) & BIT(0));
- // Re-enable rule lookup
+ /* Re-enable rule lookup */
for (block = block_from; block <= block_to; block++) {
if (!(block_state & BIT(block)))
sw_w32(block_state | BIT(block), RTL838X_ACL_BLK_LOOKUP_CTRL);
break;
case TEMPLATE_FIELD_SIP2:
pr->is_ipv6 = true;
- // Make use of limitiations on the position of the match values
+ /* Make use of limitiations on the position of the match values */
ipv6_addr_set(&pr->sip6, pr->sip, r[5 - i / 2],
r[4 - i / 2], r[3 - i / 2]);
ipv6_addr_set(&pr->sip6_m, pr->sip_m, r[5 - i / 2],
r[14] |= pr->ivalid ? BIT(27) : 0;
if (pr->drop)
- r[17] = 0x1 << 14; // Standard drop action
+ r[17] = 0x1 << 14; /* Standard drop action */
else
r[17] = 0;
r[17] |= pr->fwd_sel ? BIT(13) : 0;
* defines which Action Information Field (0-4) in the IACL table stores
* the additional data of the action (like e.g. the port number a packet is
* forwarded to) */
- // TODO: count bits in selectors to limit to a maximum number of actions
- if (pr->fwd_sel) { // Forwarding action
+ /* TODO: count bits in selectors to limit to a maximum number of actions */
+ if (pr->fwd_sel) { /* Forwarding action */
data = pr->fwd_act << 13;
data |= pr->fwd_data;
data |= pr->bypass_all ? BIT(12) : 0;
fields_used++;
}
- if (pr->ovid_sel) { // Outer VID action
+ if (pr->ovid_sel) { /* Outer VID action */
data = (pr->ovid_act & 0x3) << 12;
data |= pr->ovid_data;
*aif-- = data;
fields_used++;
}
- if (pr->ivid_sel) { // Inner VID action
+ if (pr->ivid_sel) { /* Inner VID action */
data = (pr->ivid_act & 0x3) << 12;
data |= pr->ivid_data;
*aif-- = data;
fields_used++;
}
- if (pr->flt_sel) { // Filter action
+ if (pr->flt_sel) { /* Filter action */
*aif-- = pr->flt_data;
fields_used++;
}
- if (pr->log_sel) { // Log action
+ if (pr->log_sel) { /* Log action */
if (fields_used >= 4)
return -1;
*aif-- = pr->log_data;
fields_used++;
}
- if (pr->rmk_sel) { // Remark action
+ if (pr->rmk_sel) { /* Remark action */
if (fields_used >= 4)
return -1;
*aif-- = pr->rmk_data;
fields_used++;
}
- if (pr->meter_sel) { // Meter action
+ if (pr->meter_sel) { /* Meter action */
if (fields_used >= 4)
return -1;
*aif-- = pr->meter_data;
fields_used++;
}
- if (pr->tagst_sel) { // Egress Tag Status action
+ if (pr->tagst_sel) { /* Egress Tag Status action */
if (fields_used >= 4)
return -1;
*aif-- = pr->tagst_data;
fields_used++;
}
- if (pr->mir_sel) { // Mirror action
+ if (pr->mir_sel) { /* Mirror action */
if (fields_used >= 4)
return -1;
*aif-- = pr->mir_data;
fields_used++;
}
- if (pr->nopri_sel) { // Normal Priority action
+ if (pr->nopri_sel) { /* Normal Priority action */
if (fields_used >= 4)
return -1;
*aif-- = pr->nopri_data;
fields_used++;
}
- if (pr->cpupri_sel) { // CPU Priority action
+ if (pr->cpupri_sel) { /* CPU Priority action */
if (fields_used >= 4)
return -1;
*aif-- = pr->nopri_data;
fields_used++;
}
- if (pr->otpid_sel) { // OTPID action
+ if (pr->otpid_sel) { /* OTPID action */
if (fields_used >= 4)
return -1;
*aif-- = pr->otpid_data;
fields_used++;
}
- if (pr->itpid_sel) { // ITPID action
+ if (pr->itpid_sel) { /* ITPID action */
if (fields_used >= 4)
return -1;
*aif-- = pr->itpid_data;
fields_used++;
}
- if (pr->shaper_sel) { // Traffic shaper action
+ if (pr->shaper_sel) { /* Traffic shaper action */
if (fields_used >= 4)
return -1;
*aif-- = pr->shaper_data;
if (pr->drop)
pr_debug("%s: Action Drop: %d", __func__, pr->drop);
- if (pr->fwd_sel){ // Forwarding action
+ if (pr->fwd_sel){ /* Forwarding action */
pr->fwd_act = *aif >> 13;
pr->fwd_data = *aif--;
pr->bypass_all = pr->fwd_data & BIT(12);
if (pr->bypass_all || pr->bypass_ibc_sc || pr->bypass_igr_stp)
pr->bypass_sel = true;
}
- if (pr->ovid_sel) // Outer VID action
+ if (pr->ovid_sel) /* Outer VID action */
pr->ovid_data = *aif--;
- if (pr->ivid_sel) // Inner VID action
+ if (pr->ivid_sel) /* Inner VID action */
pr->ivid_data = *aif--;
- if (pr->flt_sel) // Filter action
+ if (pr->flt_sel) /* Filter action */
pr->flt_data = *aif--;
- if (pr->log_sel) // Log action
+ if (pr->log_sel) /* Log action */
pr->log_data = *aif--;
- if (pr->rmk_sel) // Remark action
+ if (pr->rmk_sel) /* Remark action */
pr->rmk_data = *aif--;
- if (pr->meter_sel) // Meter action
+ if (pr->meter_sel) /* Meter action */
pr->meter_data = *aif--;
- if (pr->tagst_sel) // Egress Tag Status action
+ if (pr->tagst_sel) /* Egress Tag Status action */
pr->tagst_data = *aif--;
- if (pr->mir_sel) // Mirror action
+ if (pr->mir_sel) /* Mirror action */
pr->mir_data = *aif--;
- if (pr->nopri_sel) // Normal Priority action
+ if (pr->nopri_sel) /* Normal Priority action */
pr->nopri_data = *aif--;
- if (pr->cpupri_sel) // CPU Priority action
+ if (pr->cpupri_sel) /* CPU Priority action */
pr->nopri_data = *aif--;
- if (pr->otpid_sel) // OTPID action
+ if (pr->otpid_sel) /* OTPID action */
pr->otpid_data = *aif--;
- if (pr->itpid_sel) // ITPID action
+ if (pr->itpid_sel) /* ITPID action */
pr->itpid_data = *aif--;
- if (pr->shaper_sel) // Traffic shaper action
+ if (pr->shaper_sel) /* Traffic shaper action */
pr->shaper_data = *aif--;
}
static int rtl838x_pie_rule_read(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr)
{
- // Read IACL table (1) via register 0
+ /* Read IACL table (1) via register 0 */
struct table_reg *q = rtl_table_get(RTL8380_TBL_0, 1);
u32 r[18];
int i;
static int rtl838x_pie_rule_write(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr)
{
- // Access IACL table (1) via register 0
+ /* Access IACL table (1) via register 0 */
struct table_reg *q = rtl_table_get(RTL8380_TBL_0, 1);
u32 r[18];
int i, err = 0;
goto err_out;
}
-// rtl838x_pie_rule_dump_raw(r);
+/* rtl838x_pie_rule_dump_raw(r); */
for (i = 0; i < 18; i++)
sw_w32(r[i], rtl_table_data(q, i));
if (ether_addr_to_u64(pr->dmac) && !rtl838x_pie_templ_has(t, TEMPLATE_FIELD_DMAC0))
return -1;
- // TODO: Check more
+ /* TODO: Check more */
i = find_first_zero_bit(&priv->pie_use_bm[block * 4], PIE_BLOCK_SIZE);
set_bit(idx, priv->pie_use_bm);
pr->valid = true;
- pr->tid = j; // Mapped to template number
+ pr->tid = j; /* Mapped to template number */
pr->tid_m = 0x3;
pr->id = idx;
mutex_init(&priv->pie_mutex);
- // Enable ACL lookup on all ports, including CPU_PORT
+ /* Enable ACL lookup on all ports, including CPU_PORT */
for (i = 0; i <= priv->cpu_port; i++)
sw_w32(1, RTL838X_ACL_PORT_LOOKUP_CTRL(i));
- // Power on all PIE blocks
+ /* Power on all PIE blocks */
for (i = 0; i < priv->n_pie_blocks; i++)
sw_w32_mask(0, BIT(i), RTL838X_ACL_BLK_PWR_CTRL);
- // Include IPG in metering
+ /* Include IPG in metering */
sw_w32(1, RTL838X_METER_GLB_CTRL);
- // Delete all present rules
+ /* Delete all present rules */
rtl838x_pie_rule_del(priv, 0, priv->n_pie_blocks * PIE_BLOCK_SIZE - 1);
- // Routing bypasses source port filter: disable write-protection, first
+ /* Routing bypasses source port filter: disable write-protection, first */
sw_w32_mask(0, 3, RTL838X_INT_RW_CTRL);
sw_w32_mask(0, 1, RTL838X_DMY_REG27);
sw_w32_mask(3, 0, RTL838X_INT_RW_CTRL);
- // Enable predefined templates 0, 1 and 2 for even blocks
+ /* Enable predefined templates 0, 1 and 2 for even blocks */
template_selectors = 0 | (1 << 3) | (2 << 6);
for (i = 0; i < 6; i += 2)
sw_w32(template_selectors, RTL838X_ACL_BLK_TMPLTE_CTRL(i));
- // Enable predefined templates 0, 3 and 4 (IPv6 support) for odd blocks
+ /* Enable predefined templates 0, 3 and 4 (IPv6 support) for odd blocks */
template_selectors = 0 | (3 << 3) | (4 << 6);
for (i = 1; i < priv->n_pie_blocks; i += 2)
sw_w32(template_selectors, RTL838X_ACL_BLK_TMPLTE_CTRL(i));
- // Group each pair of physical blocks together to a logical block
+ /* Group each pair of physical blocks together to a logical block */
sw_w32(0b10101010101, RTL838X_ACL_BLK_GROUP_CTRL);
}
{
u32 v;
- // Read LOG table (3) via register RTL8380_TBL_0
+ /* Read LOG table (3) via register RTL8380_TBL_0 */
struct table_reg *r = rtl_table_get(RTL8380_TBL_0, 3);
pr_debug("In %s, id %d\n", __func__, counter);
pr_debug("Registers: %08x %08x\n",
sw_r32(rtl_table_data(r, 0)), sw_r32(rtl_table_data(r, 1)));
- // The table has a size of 2 registers
+ /* The table has a size of 2 registers */
if (counter % 2)
v = sw_r32(rtl_table_data(r, 0));
else
static void rtl838x_packet_cntr_clear(int counter)
{
- // Access LOG table (3) via register RTL8380_TBL_0
+ /* Access LOG table (3) via register RTL8380_TBL_0 */
struct table_reg *r = rtl_table_get(RTL8380_TBL_0, 3);
pr_debug("In %s, id %d\n", __func__, counter);
- // The table has a size of 2 registers
+ /* The table has a size of 2 registers */
if (counter % 2)
sw_w32(0, rtl_table_data(r, 0));
else
static void rtl838x_route_read(int idx, struct rtl83xx_route *rt)
{
- // Read ROUTING table (2) via register RTL8380_TBL_1
+ /* Read ROUTING table (2) via register RTL8380_TBL_1 */
struct table_reg *r = rtl_table_get(RTL8380_TBL_1, 2);
pr_debug("In %s, id %d\n", __func__, idx);
rtl_table_read(r, idx);
- // The table has a size of 2 registers
+ /* The table has a size of 2 registers */
rt->nh.gw = sw_r32(rtl_table_data(r, 0));
rt->nh.gw <<= 32;
rt->nh.gw |= sw_r32(rtl_table_data(r, 1));
static void rtl838x_route_write(int idx, struct rtl83xx_route *rt)
{
- // Access ROUTING table (2) via register RTL8380_TBL_1
+ /* Access ROUTING table (2) via register RTL8380_TBL_1 */
struct table_reg *r = rtl_table_get(RTL8380_TBL_1, 2);
pr_debug("In %s, id %d, gw: %016llx\n", __func__, idx, rt->nh.gw);
static int rtl838x_l3_setup(struct rtl838x_switch_priv *priv)
{
- // Nothing to be done
+ /* Nothing to be done */
return 0;
}
void rtl838x_set_distribution_algorithm(int group, int algoidx, u32 algomsk)
{
- algoidx &= 1; // RTL838X only supports 2 concurrent algorithms
+ algoidx &= 1; /* RTL838X only supports 2 concurrent algorithms */
sw_w32_mask(1 << (group % 8), algoidx << (group % 8),
RTL838X_TRK_HASH_IDX_CTRL + ((group >> 3) << 2));
sw_w32(algomsk, RTL838X_TRK_HASH_CTRL + (algoidx << 2));
projects / openwrt / staging / pepe2k.git / blobdiff