// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/dts-v1/;
#include "mt7620a.dtsi"
compatible = "gpio-leds";
4g {
- label = "tube-e4g:green:4g";
+ label = "green:4g";
gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
};
lan {
- label = "tube-e4g:blue:lan";
+ label = "blue:lan";
gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
};
power: power {
- label = "tube-e4g:green:power";
+ label = "green:power";
gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
default-state = "keep";
};
sim1 {
- label = "tube-e4g:green:sim1";
+ label = "green:sim1";
gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
default-state = "keep";
};
sim2 {
- label = "tube-e4g:green:sim2";
+ label = "green:sim2";
gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
default-state = "keep";
};
};
ðernet {
- mtd-mac-address = <&factory 0x28>;
-};
-
-&gpio0 {
- status = "okay";
+ nvmem-cells = <&macaddr_factory_28>;
+ nvmem-cell-names = "mac-address";
};
&gpio1 {
status = "okay";
};
-&gsw {
- mediatek,port4 = "ephy";
-};
-
&ohci {
status = "okay";
};
status = "disabled";
};
-&pinctrl {
- state_default: pinctrl0 {
- gpio {
- ralink,group = "ephy", "nd_sd", "pcie", "uartf";
- ralink,function = "gpio";
- };
+&state_default {
+ gpio {
+ groups = "ephy", "nd_sd", "pcie", "uartf";
+ function = "gpio";
};
};
label = "factory";
reg = <0x40000 0x10000>;
read-only;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ macaddr_factory_28: macaddr@28 {
+ reg = <0x28 0x6>;
+ };
+ };
};
partition@50000 {