mvebu: refresh patches for 6.1

[openwrt/staging/jow.git] / target / linux / mvebu / patches-6.1 / 100-aardvark-workaround-PCIe.patch

diff --git a/target/linux/mvebu/patches-6.1/100-aardvark-workaround-PCIe.patch b/target/linux/mvebu/patches-6.1/100-aardvark-workaround-PCIe.patch
index 975eadb80e2746055f93015c1e25ad654b285157..4936f6ad16c0e490e6c7dcec23a8de1b8bb26d13 100644 (file)
--- a/target/linux/mvebu/patches-6.1/100-aardvark-workaround-PCIe.patch
+++ b/target/linux/mvebu/patches-6.1/100-aardvark-workaround-PCIe.patch
@@ -48,7 +48,7 @@ Cc: stable@vger.kernel.org
 
 --- a/drivers/pci/controller/pci-aardvark.c
 +++ b/drivers/pci/controller/pci-aardvark.c
-@@ -210,6 +210,8 @@ enum {
+@@ -212,6 +212,8 @@ enum {
  };
  
  #define VENDOR_ID_REG                         (LMI_BASE_ADDR + 0x44)
@@ -57,7 +57,7 @@ Cc: stable@vger.kernel.org
  
  /* PCIe core controller registers */
  #define CTRL_CORE_BASE_ADDR                   0x18000
-@@ -558,6 +560,11 @@ static void advk_pcie_setup_hw(struct ad
+@@ -560,6 +562,11 @@ static void advk_pcie_setup_hw(struct ad
                PCIE_CORE_CTRL2_TD_ENABLE;
        advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
  
@@ -69,7 +69,7 @@ Cc: stable@vger.kernel.org
        /* Set lane X1 */
        reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
        reg &= ~LANE_CNT_MSK;
-@@ -1580,6 +1587,9 @@ static irqreturn_t advk_pcie_irq_handler
+@@ -1661,6 +1668,9 @@ static irqreturn_t advk_pcie_irq_handler
        struct advk_pcie *pcie = arg;
        u32 status;