kernel: bump 4.14 to 4.14.44
[openwrt/staging/lynxis.git] / target / linux / mediatek / patches-4.14 / 0201-dt-bindings-clock-mediatek-add-missing-required-rese.patch
index 601e5b9855edf64cf156201072bc15905b5784e3..6f22dc24114271931b97027b82563eefe6445795 100644 (file)
@@ -20,8 +20,6 @@ Reviewed-by: Rob Herring <robh@kernel.org>
  Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt | 2 ++
  3 files changed, 5 insertions(+)
 
-diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
-index 7aa3fa167668..52757adf86bb 100644
 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
 @@ -9,6 +9,7 @@ Required Properties:
@@ -32,8 +30,6 @@ index 7aa3fa167668..52757adf86bb 100644
  
  The ethsys controller uses the common clk binding from
  Documentation/devicetree/bindings/clock/clock-bindings.txt
-diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt
-index d5d5f1227665..7fe5dc6097a6 100644
 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt
 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt
 @@ -8,6 +8,7 @@ Required Properties:
@@ -50,8 +46,6 @@ index d5d5f1227665..7fe5dc6097a6 100644
        #clock-cells = <1>;
 +      #reset-cells = <1>;
  };
-diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt
-index 00760019da00..b8184da2508c 100644
 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt
 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt
 @@ -8,6 +8,7 @@ Required Properties:
@@ -68,6 +62,3 @@ index 00760019da00..b8184da2508c 100644
        #clock-cells = <1>;
 +      #reset-cells = <1>;
  };
--- 
-2.11.0
-