#include <dt-bindings/leds/common.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/pinctrl/mt65xx.h>
-#include <dt-bindings/reset/ti-syscon.h>
+#include <dt-bindings/reset/mediatek,mt7988-resets.h>
#include <dt-bindings/thermal/thermal.h>
+/* TOPRGU resets */
+#define MT7988_TOPRGU_SGMII0_GRST 1
+#define MT7988_TOPRGU_SGMII1_GRST 2
+#define MT7988_TOPRGU_XFI0_GRST 12
+#define MT7988_TOPRGU_XFI1_GRST 13
+#define MT7988_TOPRGU_XFI_PEXTP0_GRST 14
+#define MT7988_TOPRGU_XFI_PEXTP1_GRST 15
+#define MT7988_TOPRGU_XFI_PLL_GRST 16
+
/ {
compatible = "mediatek,mt7988";
interrupt-parent = <&gic>;
clock-output-names = "clkxtal";
};
+ fan: pwm-fan {
+ compatible = "pwm-fan";
+ /* cooling level (0, 1, 2) : (0% duty, 50% duty, 100% duty) */
+ cooling-levels = <0 128 255>;
+ #cooling-cells = <2>;
+ #thermal-sensor-cells = <1>;
+ status = "disabled";
+ };
+
pmu {
compatible = "arm,cortex-a73-pmu";
interrupt-parent = <&gic>;
compatible = "mediatek,mt7988-infracfg", "syscon";
reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
topckgen: topckgen@1001b000 {
};
};
+ uart1_0_pins: uart1-0-pins {
+ mux {
+ function = "uart";
+ groups = "uart1_0";
+ };
+ };
+
+ uart1_1_pins: uart1-1-pins {
+ mux {
+ function = "uart";
+ groups = "uart1_1";
+ };
+ };
+
+ uart1_2_pins: uart1-2-pins {
+ mux {
+ function = "uart";
+ groups = "uart1_2";
+ };
+ };
+
+ uart1_2_lite_pins: uart1-2-lite-pins {
+ mux {
+ function = "uart";
+ groups = "uart1_2_lite";
+ };
+ };
+
+ uart2_pins: uart2-pins {
+ mux {
+ function = "uart";
+ groups = "uart2";
+ };
+ };
+
+ uart2_0_pins: uart2-0-pins {
+ mux {
+ function = "uart";
+ groups = "uart2_0";
+ };
+ };
+
+ uart2_1_pins: uart2-1-pins {
+ mux {
+ function = "uart";
+ groups = "uart2_1";
+ };
+ };
+
+ uart2_2_pins: uart2-2-pins {
+ mux {
+ function = "uart";
+ groups = "uart2_2";
+ };
+ };
+
+ uart2_3_pins: uart2-3-pins {
+ mux {
+ function = "uart";
+ groups = "uart2_3";
+ };
+ };
+
snfi_pins: snfi-pins {
mux {
function = "flash";
sgmiisys0: syscon@10060000 {
compatible = "mediatek,mt7988-sgmiisys",
- "mediatek,mt7988-sgmiisys_0",
- "syscon";
+ "mediatek,mt7988-sgmiisys0",
+ "syscon",
+ "simple-mfd";
reg = <0 0x10060000 0 0x1000>;
+ resets = <&watchdog MT7988_TOPRGU_SGMII0_GRST>;
#clock-cells = <1>;
+
+ sgmiipcs0: pcs {
+ compatible = "mediatek,mt7988-sgmii";
+ clocks = <&topckgen CLK_TOP_SGM_0_SEL>,
+ <&sgmiisys0 CLK_SGM0_TX_EN>,
+ <&sgmiisys0 CLK_SGM0_RX_EN>;
+ clock-names = "sgmii_sel", "sgmii_tx", "sgmii_rx";
+ };
};
sgmiisys1: syscon@10070000 {
compatible = "mediatek,mt7988-sgmiisys",
- "mediatek,mt7988-sgmiisys_1",
- "syscon";
+ "mediatek,mt7988-sgmiisys1",
+ "syscon",
+ "simple-mfd";
reg = <0 0x10070000 0 0x1000>;
+ resets = <&watchdog MT7988_TOPRGU_SGMII1_GRST>;
#clock-cells = <1>;
+
+ sgmiipcs1: pcs {
+ compatible = "mediatek,mt7988-sgmii";
+ clocks = <&topckgen CLK_TOP_SGM_1_SEL>,
+ <&sgmiisys1 CLK_SGM1_TX_EN>,
+ <&sgmiisys1 CLK_SGM1_RX_EN>;
+ clock-names = "sgmii_sel", "sgmii_tx", "sgmii_rx";
+ };
};
- usxgmiisys0: usxgmiisys@10080000 {
- compatible = "mediatek,mt7988-usxgmiisys",
- "mediatek,mt7988-usxgmiisys_0",
- "syscon";
+ usxgmiisys0: pcs@10080000 {
+ compatible = "mediatek,mt7988-usxgmiisys";
reg = <0 0x10080000 0 0x1000>;
- #clock-cells = <1>;
+ resets = <&watchdog MT7988_TOPRGU_XFI0_GRST>;
+ clocks = <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>;
};
- usxgmiisys1: usxgmiisys@10081000 {
- compatible = "mediatek,mt7988-usxgmiisys",
- "mediatek,mt7988-usxgmiisys_1",
- "syscon";
+ usxgmiisys1: pcs@10081000 {
+ compatible = "mediatek,mt7988-usxgmiisys";
reg = <0 0x10081000 0 0x1000>;
- #clock-cells = <1>;
+ resets = <&watchdog MT7988_TOPRGU_XFI1_GRST>;
+ clocks = <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>;
};
mcusys: mcusys@100e0000 {
status = "disabled";
};
+ uart1: serial@11000100 {
+ compatible = "mediatek,mt7986-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11000100 0 0x100>;
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+ /*
+ * 8250-mtk driver don't control "baud" clock since commit
+ * e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks
+ * still need to be passed to the driver to prevent probe fail
+ */
+ clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&infracfg CLK_INFRA_52M_UART1_CK>;
+ clock-names = "baud", "bus";
+ assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&infracfg CLK_INFRA_MUX_UART1_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
+ <&topckgen CLK_TOP_UART_SEL>;
+ status = "disabled";
+ };
+
+ uart2: serial@11000200 {
+ compatible = "mediatek,mt7986-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11000200 0 0x100>;
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+ /*
+ * 8250-mtk driver don't control "baud" clock since commit
+ * e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks
+ * still need to be passed to the driver to prevent probe fail
+ */
+ clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&infracfg CLK_INFRA_52M_UART2_CK>;
+ clock-names = "baud", "bus";
+ assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&infracfg CLK_INFRA_MUX_UART2_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
+ <&topckgen CLK_TOP_UART_SEL>;
+ status = "disabled";
+ };
+
snand: spi@11001000 {
compatible = "mediatek,mt7986-snand";
reg = <0 0x11001000 0 0x1000>;
status = "disabled";
};
- fan: pwm-fan {
- compatible = "pwm-fan";
- /* cooling level (0, 1, 2) : (0% duty, 50% duty, 100% duty) */
- cooling-levels = <0 128 255>;
- #cooling-cells = <2>;
- #thermal-sensor-cells = <1>;
- status = "disabled";
- };
-
lvts: lvts@1100a000 {
- compatible = "mediatek,mt7988-lvts";
+ compatible = "mediatek,mt7988-lvts-ap";
reg = <0 0x1100a000 0 0x1000>;
clocks = <&infracfg CLK_INFRA_26M_THERM_SYSTEM>;
clock-names = "lvts_clk";
+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&infracfg MT7988_INFRA_RST1_THERM_CTRL_SWRST>;
nvmem-cells = <&lvts_calibration>;
- nvmem-cell-names = "e_data1";
+ nvmem-cell-names = "lvts-calib-data-1";
#thermal-sensor-cells = <1>;
};
};
};
- xfi_pextp0: xfi-pextp@11f20000 {
- compatible = "mediatek,mt7988-xfi-pextp",
- "mediatek,mt7988-xfi-pextp_0",
- "syscon";
+ xfi_tphy0: phy@11f20000 {
+ compatible = "mediatek,mt7988-xfi-tphy";
reg = <0 0x11f20000 0 0x10000>;
- #clock-cells = <1>;
+ resets = <&watchdog MT7988_TOPRGU_XFI_PEXTP0_GRST>;
+ clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>, <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>;
+ clock-names = "xfipll", "topxtal";
+ mediatek,usxgmii-performance-errata;
+ #phy-cells = <0>;
};
- xfi_pextp1: xfi-pextp@11f30000 {
- compatible = "mediatek,mt7988-xfi-pextp",
- "mediatek,mt7988-xfi-pextp_1",
- "syscon";
+ xfi_tphy1: phy@11f30000 {
+ compatible = "mediatek,mt7988-xfi-tphy";
reg = <0 0x11f30000 0 0x10000>;
- #clock-cells = <1>;
+ resets = <&watchdog MT7988_TOPRGU_XFI_PEXTP1_GRST>;
+ clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>, <&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>;
+ clock-names = "xfipll", "topxtal";
+ #phy-cells = <0>;
};
- xfi_pll: xfi-pll@11f40000 {
- compatible = "mediatek,mt7988-xfi-pll", "syscon";
+ xfi_pll: clock-controller@11f40000 {
+ compatible = "mediatek,mt7988-xfi-pll";
reg = <0 0x11f40000 0 0x1000>;
+ resets = <&watchdog MT7988_TOPRGU_XFI_PLL_GRST>;
#clock-cells = <1>;
};
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
- resets = <ðrst 0>;
+ resets = <ðwarp MT7988_ETHWARP_RST_SWITCH>;
#address-cells = <1>;
#size-cells = <1>;
};
};
- ethwarp: syscon@15031000 {
- compatible = "mediatek,mt7988-ethwarp", "syscon", "simple-mfd";
+ ethwarp: clock-controller@15031000 {
+ compatible = "mediatek,mt7988-ethwarp";
reg = <0 0x15031000 0 0x1000>;
#clock-cells = <1>;
-
- ethrst: reset-controller {
- compatible = "ti,syscon-reset";
- #reset-cells = <1>;
- ti,reset-bits = <
- 0x8 9 0x8 9 0 0 (ASSERT_SET | DEASSERT_CLEAR | STATUS_NONE)
- >;
- };
+ #reset-cells = <1>;
};
eth: ethernet@15100000 {
<ðsys CLK_ETHDMA_GP3_EN>,
<ðsys CLK_ETHDMA_ESW_EN>,
<ðsys CLK_ETHDMA_CRYPT0_EN>,
- <&sgmiisys0 CLK_SGM0_TX_EN>,
- <&sgmiisys0 CLK_SGM0_RX_EN>,
- <&sgmiisys1 CLK_SGM1_TX_EN>,
- <&sgmiisys1 CLK_SGM1_RX_EN>,
<ðwarp CLK_ETHWARP_WOCPU2_EN>,
<ðwarp CLK_ETHWARP_WOCPU1_EN>,
<ðwarp CLK_ETHWARP_WOCPU0_EN>,
- <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
- <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>,
- <&topckgen CLK_TOP_SGM_0_SEL>,
- <&topckgen CLK_TOP_SGM_1_SEL>,
- <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>,
- <&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>,
<&topckgen CLK_TOP_ETH_GMII_SEL>,
<&topckgen CLK_TOP_ETH_REFCK_50M_SEL>,
<&topckgen CLK_TOP_ETH_SYS_200M_SEL>,
<&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>,
<&topckgen CLK_TOP_NETSYS_WARP_SEL>;
clock-names = "xgp1", "xgp2", "xgp3", "fe", "gp2", "gp1",
- "gp3", "esw", "crypto", "sgmii_tx250m",
- "sgmii_rx250m", "sgmii2_tx250m", "sgmii2_rx250m",
+ "gp3", "esw", "crypto",
"ethwarp_wocpu2", "ethwarp_wocpu1",
- "ethwarp_wocpu0", "top_usxgmii0_sel",
- "top_usxgmii1_sel", "top_sgm0_sel",
- "top_sgm1_sel", "top_xfi_phy0_xtal_sel",
- "top_xfi_phy1_xtal_sel", "top_eth_gmii_sel",
+ "ethwarp_wocpu0", "top_eth_gmii_sel",
"top_eth_refck_50m_sel", "top_eth_sys_200m_sel",
"top_eth_sys_sel", "top_eth_xgmii_sel",
"top_eth_mii_sel", "top_netsys_sel",
<&apmixedsys CLK_APMIXED_SGMPLL>,
<&apmixedsys CLK_APMIXED_SGMPLL>;
mediatek,ethsys = <ðsys>;
- mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
- mediatek,usxgmiisys = <&usxgmiisys0>, <&usxgmiisys1>;
- mediatek,xfi-pextp = <&xfi_pextp0>, <&xfi_pextp1>;
- mediatek,xfi-pll = <&xfi_pll>;
mediatek,infracfg = <&topmisc>;
- mediatek,toprgu = <&watchdog>;
- #reset-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "mediatek,eth-mac";
reg = <1>;
status = "disabled";
+ pcs-handle = <&sgmiipcs1>, <&usxgmiisys1>;
+ phys = <&xfi_tphy1>;
};
gmac2: mac@2 {
compatible = "mediatek,eth-mac";
reg = <2>;
status = "disabled";
+ pcs-handle = <&sgmiipcs0>, <&usxgmiisys0>;
+ phys = <&xfi_tphy0>;
};
mdio_bus: mdio-bus {
projects / openwrt / staging / jow.git / blobdiff