+};
--- /dev/null
+++ b/drivers/net/ethernet/lantiq_xrx200.c
-@@ -0,0 +1,1830 @@
+@@ -0,0 +1,1851 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+#define XRX200_DMA_IRQ INT_NUM_IM2_IRL0
+#define XRX200_DMA_RX 0
+#define XRX200_DMA_TX 1
++#define XRX200_DMA_TX_2 3
+#define XRX200_DMA_IS_TX(x) (x%2)
+#define XRX200_DMA_IS_RX(x) (!XRX200_DMA_IS_TX(x))
+
+ struct napi_struct napi;
+ struct ltq_dma_channel dma;
+ struct sk_buff *skb[LTQ_DESC_NUM];
++
++ spinlock_t lock;
+};
+
+struct xrx200_hw {
+ int port_map[XRX200_MAX_PORT];
+ unsigned short wan_map;
+
-+ spinlock_t lock;
-+
+ struct switch_dev swdev;
+};
+
+ for (i = 0; i < XRX200_MAX_DMA; i++) {
+ if (!priv->hw->chan[i].dma.irq)
+ continue;
-+ spin_lock_bh(&priv->hw->lock);
++ spin_lock_bh(&priv->hw->chan[i].lock);
+ if (!priv->hw->chan[i].refcount) {
+ if (XRX200_DMA_IS_RX(i))
+ napi_enable(&priv->hw->chan[i].napi);
+ ltq_dma_open(&priv->hw->chan[i].dma);
+ }
+ priv->hw->chan[i].refcount++;
-+ spin_unlock_bh(&priv->hw->lock);
++ spin_unlock_bh(&priv->hw->chan[i].lock);
+ }
+ for (i = 0; i < priv->num_port; i++)
+ if (priv->port[i].phydev)
+ phy_start(priv->port[i].phydev);
-+ netif_start_queue(dev);
++ netif_wake_queue(dev);
+
+ return 0;
+}
+ for (i = 0; i < XRX200_MAX_DMA; i++) {
+ if (!priv->hw->chan[i].dma.irq)
+ continue;
-+ spin_lock_bh(&priv->hw->lock);
++ spin_lock_bh(&priv->hw->chan[i].lock);
+ priv->hw->chan[i].refcount--;
+ if (!priv->hw->chan[i].refcount) {
+ if (XRX200_DMA_IS_RX(i))
+ napi_disable(&priv->hw->chan[i].napi);
+ ltq_dma_close(&priv->hw->chan[XRX200_DMA_RX].dma);
+ }
-+ spin_unlock_bh(&priv->hw->lock);
++ spin_unlock_bh(&priv->hw->chan[i].lock);
+ }
+
+ return 0;
+ if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
+#ifdef SW_ROUTING
+ struct sk_buff *skb = ch->skb[ch->dma.desc];
-+ u32 *special_tag = (u32*)skb->data;
-+ int port = (special_tag[1] >> SPPID_SHIFT) & SPPID_MASK;
++ u8 *special_tag = (u8*)skb->data;
++ int port = (special_tag[7] >> SPPID_SHIFT) & SPPID_MASK;
+ xrx200_hw_receive(ch, priv->hw->port_map[port]);
+#else
+ xrx200_hw_receive(ch, 0);
+
+static void xrx200_tx_housekeeping(unsigned long ptr)
+{
-+ struct xrx200_hw *hw = (struct xrx200_hw *) ptr;
-+ struct xrx200_chan *ch = &hw->chan[XRX200_DMA_TX];
++ struct xrx200_chan *ch = (struct xrx200_chan *) ptr;
+ int pkts = 0;
+ int i;
+
-+ spin_lock_bh(&hw->lock);
++ spin_lock_bh(&ch->lock);
+ ltq_dma_ack_irq(&ch->dma);
+ while ((ch->dma.desc_base[ch->tx_free].ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
+ struct sk_buff *skb = ch->skb[ch->tx_free];
+ ch->tx_free %= LTQ_DESC_NUM;
+ }
+ ltq_dma_enable_irq(&ch->dma);
-+ spin_unlock_bh(&hw->lock);
++ spin_unlock_bh(&ch->lock);
+
+ if (!pkts)
+ return;
+static int xrx200_start_xmit(struct sk_buff *skb, struct net_device *dev)
+{
+ struct xrx200_priv *priv = netdev_priv(dev);
-+ struct xrx200_chan *ch = &priv->hw->chan[XRX200_DMA_TX];
-+ struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
++ struct xrx200_chan *ch;
++ struct ltq_dma_desc *desc;
+ u32 byte_offset;
++ u16 port_map = 0;
++ int ret = NETDEV_TX_OK;
+ int len;
+#ifdef SW_ROUTING
+ u32 special_tag = (SPID_CPU_PORT << SPID_SHIFT) | DPID_ENABLE;
+#endif
++ if(priv->id)
++ ch = &priv->hw->chan[XRX200_DMA_TX_2];
++ else
++ ch = &priv->hw->chan[XRX200_DMA_TX];
++
++ desc = &ch->dma.desc_base[ch->dma.desc];
+
+ skb->dev = dev;
+ len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
+
-+ if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) {
-+ netdev_err(dev, "tx ring full\n");
-+ netif_stop_queue(dev);
-+ return NETDEV_TX_BUSY;
-+ }
+#ifdef SW_ROUTING
+ if (is_multicast_ether_addr(eth_hdr(skb)->h_dest)) {
-+ u16 port_map = priv->port_map;
-+ special_tag |= PORT_MAP_SEL | PORT_MAP_EN;
+ if (skb->protocol == htons(ETH_P_8021Q)) {
+ u16 vid;
+ int i;
+ }
+ }
+ }
-+ special_tag |= port_map << PORT_MAP_SHIFT;
+ }
-+ special_tag |= priv->port_map << PORT_MAP_SHIFT;
-+ if(priv->id)
++ if (port_map) {
++ special_tag |= (port_map << PORT_MAP_SHIFT) |
++ PORT_MAP_SEL | PORT_MAP_EN;
++ }
++ if(priv->wan)
+ special_tag |= (1 << DPID_SHIFT);
+ if(skb_headroom(skb) < 4) {
+ struct sk_buff *tmp = skb_realloc_headroom(skb, 4);
+
+ /* dma needs to start on a 16 byte aligned address */
+ byte_offset = CPHYSADDR(skb->data) % 16;
++
++ spin_lock_bh(&ch->lock);
++ if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) {
++ netdev_err(dev, "tx ring full\n");
++ netif_stop_queue(dev);
++ ret = NETDEV_TX_BUSY;
++ goto out;
++ }
++
+ ch->skb[ch->dma.desc] = skb;
+
+ dev->trans_start = jiffies;
+
-+ spin_lock_bh(&priv->hw->lock);
+ desc->addr = ((unsigned int) dma_map_single(NULL, skb->data, len,
+ DMA_TO_DEVICE)) - byte_offset;
+ wmb();
+ if (ch->dma.desc == ch->tx_free)
+ netif_stop_queue(dev);
+
-+ spin_unlock_bh(&priv->hw->lock);
+
+ priv->stats.tx_packets++;
+ priv->stats.tx_bytes+=len;
+
-+ return NETDEV_TX_OK;
++out:
++ spin_unlock_bh(&ch->lock);
++
++ return ret;
+}
+
+static irqreturn_t xrx200_dma_irq(int irq, void *priv)
+ int irq = XRX200_DMA_IRQ + i;
+ struct xrx200_chan *ch = &hw->chan[i];
+
++ spin_lock_init(&ch->lock);
++
+ ch->idx = ch->dma.nr = i;
+
+ if (i == XRX200_DMA_TX) {
+ ltq_dma_alloc_tx(&ch->dma);
+ err = request_irq(irq, xrx200_dma_irq, 0, "vrx200_tx", hw);
++ } else if (i == XRX200_DMA_TX_2) {
++ ltq_dma_alloc_tx(&ch->dma);
++ err = request_irq(irq, xrx200_dma_irq, 0, "vrx200_tx_2", hw);
+ } else if (i == XRX200_DMA_RX) {
+ ltq_dma_alloc_rx(&ch->dma);
+ for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM;
+
+ if (!err)
+ ch->dma.irq = irq;
++ else
++ pr_err("net-xrx200: failed to request irq %d\n", irq);
+ }
+
+ return err;
+ }
+
+ /* bring up the dma engine and IP core */
-+ spin_lock_init(&xrx200_hw.lock);
+ xrx200_dma_init(&xrx200_hw);
+ xrx200_hw_init(&xrx200_hw);
-+ tasklet_init(&xrx200_hw.chan[XRX200_DMA_TX].tasklet, xrx200_tx_housekeeping, (u32) &xrx200_hw);
++ tasklet_init(&xrx200_hw.chan[XRX200_DMA_TX].tasklet, xrx200_tx_housekeeping, (u32) &xrx200_hw.chan[XRX200_DMA_TX]);
++ tasklet_init(&xrx200_hw.chan[XRX200_DMA_TX_2].tasklet, xrx200_tx_housekeeping, (u32) &xrx200_hw.chan[XRX200_DMA_TX_2]);
+
+ /* bring up the mdio bus */
+ mdio_np = of_find_compatible_node(pdev->dev.of_node, NULL,
+ for (i = 0; i < xrx200_hw.num_devs; i++) {
+ xrx200_hw.chan[XRX200_DMA_RX].devs[i] = xrx200_hw.devs[i];
+ xrx200_hw.chan[XRX200_DMA_TX].devs[i] = xrx200_hw.devs[i];
++ xrx200_hw.chan[XRX200_DMA_TX_2].devs[i] = xrx200_hw.devs[i];
+ }
+
+ /* setup NAPI */
projects / openwrt / openwrt.git / blobdiff