};
thermal-zones {
- cpu-thermal0 {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
+ tsens_tz_sensor0 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens 0>;
- thermal-sensors = <&gcc 5>;
- coefficients = <1132 0>;
+ trips {
+ cpu-critical-hi {
+ temperature = <125000>;
+ hysteresis = <2000>;
+ type = "critical_high";
+ };
+
+ cpu-config-hi {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "configurable_hi";
+ };
+
+ cpu-config-lo {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "configurable_lo";
+ };
+
+ cpu-critical-low {
+ temperature = <0>;
+ hysteresis = <2000>;
+ type = "critical_low";
+ };
+ };
+ };
+
+ tsens_tz_sensor1 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens 1>;
trips {
- cpu_alert0: trip0 {
- temperature = <75000>;
+ cpu-critical-hi {
+ temperature = <125000>;
hysteresis = <2000>;
- type = "passive";
+ type = "critical_high";
};
- cpu_crit0: trip1 {
- temperature = <110000>;
+
+ cpu-config-hi {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "configurable_hi";
+ };
+
+ cpu-config-lo {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "configurable_lo";
+ };
+
+ cpu-critical-low {
+ temperature = <0>;
hysteresis = <2000>;
- type = "critical";
+ type = "critical_low";
};
};
};
- cpu-thermal1 {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
+ tsens_tz_sensor2 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens 2>;
- thermal-sensors = <&gcc 6>;
- coefficients = <1132 0>;
+ trips {
+ cpu-critical-hi {
+ temperature = <125000>;
+ hysteresis = <2000>;
+ type = "critical_high";
+ };
+
+ cpu-config-hi {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "configurable_hi";
+ };
+
+ cpu-config-lo {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "configurable_lo";
+ };
+
+ cpu-critical-low {
+ temperature = <0>;
+ hysteresis = <2000>;
+ type = "critical_low";
+ };
+ };
+ };
+
+ tsens_tz_sensor3 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens 3>;
trips {
- cpu_alert1: trip0 {
- temperature = <75000>;
+ cpu-critical-hi {
+ temperature = <125000>;
hysteresis = <2000>;
- type = "passive";
+ type = "critical_high";
};
- cpu_crit1: trip1 {
- temperature = <110000>;
+
+ cpu-config-hi {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "configurable_hi";
+ };
+
+ cpu-config-lo {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "configurable_lo";
+ };
+
+ cpu-critical-low {
+ temperature = <0>;
hysteresis = <2000>;
- type = "critical";
+ type = "critical_low";
};
};
};
- cpu-thermal2 {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
+ tsens_tz_sensor4 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens 4>;
- thermal-sensors = <&gcc 7>;
- coefficients = <1199 0>;
+ trips {
+ cpu-critical-hi {
+ temperature = <125000>;
+ hysteresis = <2000>;
+ type = "critical_high";
+ };
+
+ cpu-config-hi {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "configurable_hi";
+ };
+
+ cpu-config-lo {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "configurable_lo";
+ };
+
+ cpu-critical-low {
+ temperature = <0>;
+ hysteresis = <2000>;
+ type = "critical_low";
+ };
+ };
+ };
+
+ tsens_tz_sensor5 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens 5>;
trips {
- cpu_alert2: trip0 {
- temperature = <75000>;
+ cpu-critical-hi {
+ temperature = <125000>;
hysteresis = <2000>;
- type = "passive";
+ type = "critical_high";
};
- cpu_crit2: trip1 {
- temperature = <110000>;
+
+ cpu-config-hi {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "configurable_hi";
+ };
+
+ cpu-config-lo {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "configurable_lo";
+ };
+
+ cpu-critical-low {
+ temperature = <0>;
hysteresis = <2000>;
- type = "critical";
+ type = "critical_low";
};
};
};
- cpu-thermal3 {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
+ tsens_tz_sensor6 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens 6>;
- thermal-sensors = <&gcc 8>;
- coefficients = <1132 0>;
+ trips {
+ cpu-critical-hi {
+ temperature = <125000>;
+ hysteresis = <2000>;
+ type = "critical_high";
+ };
+
+ cpu-config-hi {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "configurable_hi";
+ };
+
+ cpu-config-lo {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "configurable_lo";
+ };
+
+ cpu-critical-low {
+ temperature = <0>;
+ hysteresis = <2000>;
+ type = "critical_low";
+ };
+ };
+ };
+
+ tsens_tz_sensor7 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens 7>;
trips {
- cpu_alert3: trip0 {
- temperature = <75000>;
+ cpu-critical-hi {
+ temperature = <125000>;
hysteresis = <2000>;
- type = "passive";
+ type = "critical_high";
};
- cpu_crit3: trip1 {
- temperature = <110000>;
+
+ cpu-config-hi {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "configurable_hi";
+ };
+
+ cpu-config-lo {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "configurable_lo";
+ };
+
+ cpu-critical-low {
+ temperature = <0>;
hysteresis = <2000>;
- type = "critical";
+ type = "critical_low";
+ };
+ };
+ };
+
+ tsens_tz_sensor8 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens 8>;
+
+ trips {
+ cpu-critical-hi {
+ temperature = <125000>;
+ hysteresis = <2000>;
+ type = "critical_high";
+ };
+
+ cpu-config-hi {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "configurable_hi";
+ };
+
+ cpu-config-lo {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "configurable_lo";
+ };
+
+ cpu-critical-low {
+ temperature = <0>;
+ hysteresis = <2000>;
+ type = "critical_low";
+ };
+ };
+ };
+
+ tsens_tz_sensor9 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens 9>;
+
+ trips {
+ cpu-critical-hi {
+ temperature = <125000>;
+ hysteresis = <2000>;
+ type = "critical_high";
+ };
+
+ cpu-config-hi {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "configurable_hi";
+ };
+
+ cpu-config-lo {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "configurable_lo";
+ };
+
+ cpu-critical-low {
+ temperature = <0>;
+ hysteresis = <2000>;
+ type = "critical_low";
+ };
+ };
+ };
+
+ tsens_tz_sensor10 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens 10>;
+
+ trips {
+ cpu-critical-hi {
+ temperature = <125000>;
+ hysteresis = <2000>;
+ type = "critical_high";
+ };
+
+ cpu-config-hi {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "configurable_hi";
+ };
+
+ cpu-config-lo {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "configurable_lo";
+ };
+
+ cpu-critical-low {
+ temperature = <0>;
+ hysteresis = <2000>;
+ type = "critical_low";
};
};
};
firmware {
scm {
- compatible = "qcom,scm-apq8064";
-
- clocks = <&rpmcc RPM_DAYTONA_FABRIC_CLK>;
- clock-names = "core";
+ compatible = "qcom,scm-ipq806x";
};
};
qfprom: qfprom@700000 {
compatible = "qcom,qfprom", "syscon";
- reg = <0x00700000 0x1000>;
+ reg = <0x700000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
- ranges;
-
- tsens_calib: calib {
+ status = "okay";
+ tsens_calib: calib@400 {
reg = <0x400 0x10>;
};
- tsens_backup: backup_calib {
+ tsens_backup: backup@410 {
reg = <0x410 0x10>;
};
};
gcc: clock-controller@900000 {
compatible = "qcom,gcc-ipq8064";
reg = <0x00900000 0x4000>;
- nvmem-cells = <&tsens_calib>, <&tsens_backup>;
- nvmem-cell-names = "calib", "calib_backup";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
+ };
+
+ tsens: thermal-sensor@900000 {
+ compatible = "qcom,ipq8064-tsens";
+ reg = <0x900000 0x3680>;
+ nvmem-cells = <&tsens_calib>, <&tsens_backup>;
+ nvmem-cell-names = "calib", "calib_backup";
+ interrupts = <0 178 0>;
#thermal-sensor-cells = <1>;
};
clocks = <&gcc USB30_0_MASTER_CLK>;
clock-names = "core";
- syscon-tcsr = <&tcsr 0xb0 1>;
-
ranges;
+ resets = <&gcc USB30_0_MASTER_RESET>;
+ reset-names = "usb30_0_mstr_rst";
+
status = "disabled";
dwc3@11000000 {
clocks = <&gcc USB30_1_MASTER_CLK>;
clock-names = "core";
- syscon-tcsr = <&tcsr 0xb0 0>;
-
ranges;
+ resets = <&gcc USB30_1_MASTER_RESET>;
+ reset-names = "usb30_1_mstr_rst";
+
status = "disabled";
dwc3@10000000 {
perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
+ phy-tx0-term-offset = <7>;
+
status = "disabled";
};
perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
+ phy-tx0-term-offset = <7>;
+
status = "disabled";
};
perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
+ phy-tx0-term-offset = <7>;
+
status = "disabled";
};
reg = <0x1bb00000 0x000001FF>;
};
+ stmmac_axi_setup: stmmac-axi-config {
+ snps,wr_osr_lmt = <7>;
+ snps,rd_osr_lmt = <7>;
+ snps,blen = <16 0 0 0 0 0 0>;
+ };
+
gmac0: ethernet@37000000 {
device_type = "network";
compatible = "qcom,ipq806x-gmac";
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
+ snps,axi-config = <&stmmac_axi_setup>;
+ snps,pbl = <32>;
+ snps,aal = <1>;
+
qcom,nss-common = <&nss_common>;
qcom,qsgmii-csr = <&qsgmii_csr>;
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
+ snps,axi-config = <&stmmac_axi_setup>;
+ snps,pbl = <32>;
+ snps,aal = <1>;
+
qcom,nss-common = <&nss_common>;
qcom,qsgmii-csr = <&qsgmii_csr>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
+ snps,axi-config = <&stmmac_axi_setup>;
+ snps,pbl = <32>;
+ snps,aal = <1>;
+
qcom,nss-common = <&nss_common>;
qcom,qsgmii-csr = <&qsgmii_csr>;
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
+ snps,axi-config = <&stmmac_axi_setup>;
+ snps,pbl = <32>;
+ snps,aal = <1>;
+
qcom,nss-common = <&nss_common>;
qcom,qsgmii-csr = <&qsgmii_csr>;
status = "disabled";
};
+
+ /* Temporary fixed regulator */
+ vsdcc_fixed: vsdcc-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "SDCC Power";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ sdcc1bam:dma@12402000 {
+ compatible = "qcom,bam-v1.3.0";
+ reg = <0x12402000 0x8000>;
+ interrupts = <0 98 0>;
+ clocks = <&gcc SDC1_H_CLK>;
+ clock-names = "bam_clk";
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ };
+
+ sdcc3bam:dma@12182000 {
+ compatible = "qcom,bam-v1.3.0";
+ reg = <0x12182000 0x8000>;
+ interrupts = <0 96 0>;
+ clocks = <&gcc SDC3_H_CLK>;
+ clock-names = "bam_clk";
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ };
+
+ amba {
+ compatible = "arm,amba-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ sdcc1: sdcc@12400000 {
+ status = "disabled";
+ compatible = "arm,pl18x", "arm,primecell";
+ arm,primecell-periphid = <0x00051180>;
+ reg = <0x12400000 0x2000>;
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cmd_irq";
+ clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
+ clock-names = "mclk", "apb_pclk";
+ bus-width = <8>;
+ max-frequency = <96000000>;
+ non-removable;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ vmmc-supply = <&vsdcc_fixed>;
+ dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
+ dma-names = "tx", "rx";
+ };
+
+ sdcc3: sdcc@12180000 {
+ compatible = "arm,pl18x", "arm,primecell";
+ arm,primecell-periphid = <0x00051180>;
+ status = "disabled";
+ reg = <0x12180000 0x2000>;
+ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cmd_irq";
+ clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
+ clock-names = "mclk", "apb_pclk";
+ bus-width = <8>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ max-frequency = <192000000>;
+ #mmc-ddr-1_8v;
+ sd-uhs-sdr104;
+ sd-uhs-ddr50;
+ vqmmc-supply = <&vsdcc_fixed>;
+ dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
+ dma-names = "tx", "rx";
+ };
+ };
};
sfpb_mutex: sfpb-mutex {
projects / openwrt / staging / blogic.git / blobdiff