};
thermal-zones {
- cpu-thermal0 {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
+ tsens_tz_sensor0 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens 0>;
- thermal-sensors = <&gcc 5>;
- coefficients = <1132 0>;
+ trips {
+ cpu-critical-hi {
+ temperature = <125000>;
+ hysteresis = <2000>;
+ type = "critical_high";
+ };
+
+ cpu-config-hi {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "configurable_hi";
+ };
+
+ cpu-config-lo {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "configurable_lo";
+ };
+
+ cpu-critical-low {
+ temperature = <0>;
+ hysteresis = <2000>;
+ type = "critical_low";
+ };
+ };
+ };
+
+ tsens_tz_sensor1 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens 1>;
trips {
- cpu_alert0: trip0 {
- temperature = <75000>;
+ cpu-critical-hi {
+ temperature = <125000>;
hysteresis = <2000>;
- type = "passive";
+ type = "critical_high";
};
- cpu_crit0: trip1 {
- temperature = <110000>;
+
+ cpu-config-hi {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "configurable_hi";
+ };
+
+ cpu-config-lo {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "configurable_lo";
+ };
+
+ cpu-critical-low {
+ temperature = <0>;
hysteresis = <2000>;
- type = "critical";
+ type = "critical_low";
};
};
};
- cpu-thermal1 {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
+ tsens_tz_sensor2 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens 2>;
- thermal-sensors = <&gcc 6>;
- coefficients = <1132 0>;
+ trips {
+ cpu-critical-hi {
+ temperature = <125000>;
+ hysteresis = <2000>;
+ type = "critical_high";
+ };
+
+ cpu-config-hi {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "configurable_hi";
+ };
+
+ cpu-config-lo {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "configurable_lo";
+ };
+
+ cpu-critical-low {
+ temperature = <0>;
+ hysteresis = <2000>;
+ type = "critical_low";
+ };
+ };
+ };
+
+ tsens_tz_sensor3 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens 3>;
trips {
- cpu_alert1: trip0 {
- temperature = <75000>;
+ cpu-critical-hi {
+ temperature = <125000>;
+ hysteresis = <2000>;
+ type = "critical_high";
+ };
+
+ cpu-config-hi {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "configurable_hi";
+ };
+
+ cpu-config-lo {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "configurable_lo";
+ };
+
+ cpu-critical-low {
+ temperature = <0>;
+ hysteresis = <2000>;
+ type = "critical_low";
+ };
+ };
+ };
+
+ tsens_tz_sensor4 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens 4>;
+
+ trips {
+ cpu-critical-hi {
+ temperature = <125000>;
+ hysteresis = <2000>;
+ type = "critical_high";
+ };
+
+ cpu-config-hi {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "configurable_hi";
+ };
+
+ cpu-config-lo {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "configurable_lo";
+ };
+
+ cpu-critical-low {
+ temperature = <0>;
+ hysteresis = <2000>;
+ type = "critical_low";
+ };
+ };
+ };
+
+ tsens_tz_sensor5 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens 5>;
+
+ trips {
+ cpu-critical-hi {
+ temperature = <125000>;
+ hysteresis = <2000>;
+ type = "critical_high";
+ };
+
+ cpu-config-hi {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "configurable_hi";
+ };
+
+ cpu-config-lo {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "configurable_lo";
+ };
+
+ cpu-critical-low {
+ temperature = <0>;
+ hysteresis = <2000>;
+ type = "critical_low";
+ };
+ };
+ };
+
+ tsens_tz_sensor6 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens 6>;
+
+ trips {
+ cpu-critical-hi {
+ temperature = <125000>;
+ hysteresis = <2000>;
+ type = "critical_high";
+ };
+
+ cpu-config-hi {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "configurable_hi";
+ };
+
+ cpu-config-lo {
+ temperature = <95000>;
hysteresis = <2000>;
- type = "passive";
+ type = "configurable_lo";
};
- cpu_crit1: trip1 {
- temperature = <110000>;
+
+ cpu-critical-low {
+ temperature = <0>;
hysteresis = <2000>;
- type = "critical";
+ type = "critical_low";
};
};
};
- cpu-thermal2 {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
+ tsens_tz_sensor7 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens 7>;
+
+ trips {
+ cpu-critical-hi {
+ temperature = <125000>;
+ hysteresis = <2000>;
+ type = "critical_high";
+ };
+
+ cpu-config-hi {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "configurable_hi";
+ };
+
+ cpu-config-lo {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "configurable_lo";
+ };
- thermal-sensors = <&gcc 7>;
- coefficients = <1199 0>;
+ cpu-critical-low {
+ temperature = <0>;
+ hysteresis = <2000>;
+ type = "critical_low";
+ };
+ };
+ };
+
+ tsens_tz_sensor8 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens 8>;
trips {
- cpu_alert2: trip0 {
- temperature = <75000>;
+ cpu-critical-hi {
+ temperature = <125000>;
+ hysteresis = <2000>;
+ type = "critical_high";
+ };
+
+ cpu-config-hi {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "configurable_hi";
+ };
+
+ cpu-config-lo {
+ temperature = <95000>;
hysteresis = <2000>;
- type = "passive";
+ type = "configurable_lo";
};
- cpu_crit2: trip1 {
- temperature = <110000>;
+
+ cpu-critical-low {
+ temperature = <0>;
hysteresis = <2000>;
- type = "critical";
+ type = "critical_low";
};
};
};
- cpu-thermal3 {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
+ tsens_tz_sensor9 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens 9>;
+
+ trips {
+ cpu-critical-hi {
+ temperature = <125000>;
+ hysteresis = <2000>;
+ type = "critical_high";
+ };
+
+ cpu-config-hi {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "configurable_hi";
+ };
+
+ cpu-config-lo {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "configurable_lo";
+ };
- thermal-sensors = <&gcc 8>;
- coefficients = <1132 0>;
+ cpu-critical-low {
+ temperature = <0>;
+ hysteresis = <2000>;
+ type = "critical_low";
+ };
+ };
+ };
+
+ tsens_tz_sensor10 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens 10>;
trips {
- cpu_alert3: trip0 {
- temperature = <75000>;
+ cpu-critical-hi {
+ temperature = <125000>;
hysteresis = <2000>;
- type = "passive";
+ type = "critical_high";
};
- cpu_crit3: trip1 {
- temperature = <110000>;
+
+ cpu-config-hi {
+ temperature = <105000>;
hysteresis = <2000>;
- type = "critical";
+ type = "configurable_hi";
+ };
+
+ cpu-config-lo {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "configurable_lo";
+ };
+
+ cpu-critical-low {
+ temperature = <0>;
+ hysteresis = <2000>;
+ type = "critical_low";
};
};
};
firmware {
scm {
- compatible = "qcom,scm-apq8064";
-
- clocks = <&rpmcc RPM_DAYTONA_FABRIC_CLK>;
- clock-names = "core";
+ compatible = "qcom,scm-ipq806x";
};
};
qfprom: qfprom@700000 {
compatible = "qcom,qfprom", "syscon";
- reg = <0x00700000 0x1000>;
+ reg = <0x700000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
- ranges;
-
- tsens_calib: calib {
+ status = "okay";
+ tsens_calib: calib@400 {
reg = <0x400 0x10>;
};
- tsens_backup: backup_calib {
+ tsens_backup: backup@410 {
reg = <0x410 0x10>;
};
};
gcc: clock-controller@900000 {
compatible = "qcom,gcc-ipq8064";
reg = <0x00900000 0x4000>;
- nvmem-cells = <&tsens_calib>, <&tsens_backup>;
- nvmem-cell-names = "calib", "calib_backup";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
+ };
+
+ tsens: thermal-sensor@900000 {
+ compatible = "qcom,ipq8064-tsens";
+ reg = <0x900000 0x3680>;
+ nvmem-cells = <&tsens_calib>, <&tsens_backup>;
+ nvmem-cell-names = "calib", "calib_backup";
+ interrupts = <0 178 0>;
#thermal-sensor-cells = <1>;
};
reg = <0x01200600 0x100>;
};
- hs_phy_1: phy@100f8800 {
+ hs_phy_1: phy@110f8800 {
compatible = "qcom,dwc3-hs-usb-phy";
- reg = <0x100f8800 0x30>;
+ reg = <0x110f8800 0x30>;
clocks = <&gcc USB30_1_UTMI_CLK>;
clock-names = "ref";
#phy-cells = <0>;
status = "disabled";
};
- ss_phy_1: phy@100f8830 {
+ ss_phy_1: phy@110f8830 {
compatible = "qcom,dwc3-ss-usb-phy";
- reg = <0x100f8830 0x30>;
+ reg = <0x110f8830 0x30>;
clocks = <&gcc USB30_1_MASTER_CLK>;
clock-names = "ref";
#phy-cells = <0>;
status = "disabled";
};
- hs_phy_0: phy@110f8800 {
+ hs_phy_0: phy@100f8800 {
compatible = "qcom,dwc3-hs-usb-phy";
- reg = <0x110f8800 0x30>;
+ reg = <0x100f8800 0x30>;
clocks = <&gcc USB30_0_UTMI_CLK>;
clock-names = "ref";
#phy-cells = <0>;
status = "disabled";
};
- ss_phy_0: phy@110f8830 {
+ ss_phy_0: phy@100f8830 {
compatible = "qcom,dwc3-ss-usb-phy";
- reg = <0x110f8830 0x30>;
+ reg = <0x100f8830 0x30>;
clocks = <&gcc USB30_0_MASTER_CLK>;
clock-names = "ref";
#phy-cells = <0>;
clocks = <&gcc USB30_0_MASTER_CLK>;
clock-names = "core";
- syscon-tcsr = <&tcsr 0xb0 1>;
-
ranges;
status = "disabled";
- dwc3@11000000 {
+ dwc3@10000000 {
compatible = "snps,dwc3";
- reg = <0x11000000 0xcd00>;
- interrupts = <0 110 0x4>;
+ reg = <0x10000000 0xcd00>;
+ interrupts = <0 205 0x4>;
phys = <&hs_phy_0>, <&ss_phy_0>;
phy-names = "usb2-phy", "usb3-phy";
dr_mode = "host";
clocks = <&gcc USB30_1_MASTER_CLK>;
clock-names = "core";
- syscon-tcsr = <&tcsr 0xb0 0>;
-
ranges;
status = "disabled";
- dwc3@10000000 {
+ dwc3@11000000 {
compatible = "snps,dwc3";
- reg = <0x10000000 0xcd00>;
- interrupts = <0 205 0x4>;
+ reg = <0x11000000 0xcd00>;
+ interrupts = <0 110 0x4>;
phys = <&hs_phy_1>, <&ss_phy_1>;
phy-names = "usb2-phy", "usb3-phy";
dr_mode = "host";
reg = <0x1bb00000 0x000001FF>;
};
+ stmmac_axi_setup: stmmac-axi-config {
+ snps,wr_osr_lmt = <7>;
+ snps,rd_osr_lmt = <7>;
+ snps,blen = <16 0 0 0 0 0 0>;
+ };
+
gmac0: ethernet@37000000 {
device_type = "network";
compatible = "qcom,ipq806x-gmac";
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
+ snps,axi-config = <&stmmac_axi_setup>;
+ snps,pbl = <32>;
+ snps,aal = <1>;
+
qcom,nss-common = <&nss_common>;
qcom,qsgmii-csr = <&qsgmii_csr>;
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
+ snps,axi-config = <&stmmac_axi_setup>;
+ snps,pbl = <32>;
+ snps,aal = <1>;
+
qcom,nss-common = <&nss_common>;
qcom,qsgmii-csr = <&qsgmii_csr>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
+ snps,axi-config = <&stmmac_axi_setup>;
+ snps,pbl = <32>;
+ snps,aal = <1>;
+
qcom,nss-common = <&nss_common>;
qcom,qsgmii-csr = <&qsgmii_csr>;
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
+ snps,axi-config = <&stmmac_axi_setup>;
+ snps,pbl = <32>;
+ snps,aal = <1>;
+
qcom,nss-common = <&nss_common>;
qcom,qsgmii-csr = <&qsgmii_csr>;