#size-cells = <1>;
compatible = "brcm,bcm63268";
+ aliases {
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ spi0 = &lsspi;
+ spi1 = &hsspi;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
};
};
+ cpu_intc: interrupt-controller {
+ #address-cells = <0>;
+ compatible = "mti,cpu-interrupt-controller";
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
memory { device_type = "memory"; reg = <0 0>; };
ubus@10000000 {
#size-cells = <1>;
ranges;
compatible = "simple-bus";
+ interrupt-parent = <&periph_intc>;
+
+ ext_intc: interrupt-controller@10000018 {
+ compatible = "brcm,bcm6345-ext-intc";
+ reg = <0x10000018 0x4>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupts = <44>, <45>, <46>, <47>;
+ };
+
+ periph_intc: interrupt-controller@10000020 {
+ compatible = "brcm,bcm6345-l1-intc";
+ reg = <0x10000020 0x20>,
+ <0x10000040 0x20>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <&cpu_intc>;
+ interrupts = <2>, <3>;
+ };
+
+ gpio1: gpio-controller@100000c0 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x100000c0 4>, <0x100000c8 4>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ ngpios = <20>;
+
+ interrupt-parent = <&periph_intc>;
+ interrupts = <0 0>, <1 0>, <2 0>, <3 0>;
+ interrupt-names = "gpio0", "gpio1", "gpio2", "gpio3";
+ };
+
+ gpio0: gpio-controller@100000c4 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x100000c4 4>, <0x100000cc 4>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ lsspi: spi@10000800 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,bcm6358-spi";
+ reg = <0x10000800 0x70c>;
+ interrupts = <80>;
+ /* clocks = <&clkctl 15>; */
+ };
+
+ hsspi: spi@10001000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,bcm6328-hsspi";
+ reg = <0x10001000 0x600>;
+ interrupts = <6>;
+ /* clocks = <&clkctl 16>; */
+ };
};
};