ar71xx: use ath79_setup_qca955x_eth_cfg helper for QCA955x based boards

[openwrt/openwrt.git] / target / linux / ar71xx / files / arch / mips / ath79 / mach-archer-c7.c

diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-archer-c7.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-archer-c7.c
index dc5034114fc0b30b539099eae66c018760088d8e..01719eb5b5a47e89cae8837ecc9b6f0f978800bd 100644 (file)
--- a/target/linux/ar71xx/files/arch/mips/ath79/mach-archer-c7.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-archer-c7.c
@@ -182,23 +182,6 @@ static struct mdio_board_info archer_c7_mdio0_info[] = {
        },
 };
 
-static void __init archer_c7_gmac_setup(void)
-{
-       void __iomem *base;
-       u32 t;
-
-       base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
-
-       t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
-
-       t &= ~(QCA955X_ETH_CFG_RGMII_EN | QCA955X_ETH_CFG_GE0_SGMII);
-       t |= QCA955X_ETH_CFG_RGMII_EN;
-
-       __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
-
-       iounmap(base);
-}
-
 static void __init common_setup(bool pcie_slot)
 {
        u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
@@ -227,7 +210,7 @@ static void __init common_setup(bool pcie_slot)
                                    ARRAY_SIZE(archer_c7_mdio0_info));
        ath79_register_mdio(0, 0x0);
 
-       archer_c7_gmac_setup();
+       ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
 
        /* GMAC0 is connected to the RMGII interface */
        ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;