toolchain/musl/patches/100-ppc64-check-for-AltiVec-in-setjmp-longjmp.patch

   1 From 0b6f90a930fcda6df287065d39e6b865428e3c69 Mon Sep 17 00:00:00 2001
   2 From: Stijn Tintel <stijn@linux-ipv6.be>
   3 Date: Sat, 27 Nov 2021 04:58:50 +0200
   4 Subject: [PATCH] ppc64: check for AltiVec in setjmp/longjmp
   5
   6 On machines without AltiVec, the lvx and stvx instructions are not
   7 supported. Use __hwcap to test if AltiVec is supported.
   8
   9 Fixes SIGILL on PowerPC 64 processors without AltiVec support.
  10 Runtime-tested on e5500 and e6500.
  11
  12 Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
  13 ---
  14  src/setjmp/powerpc64/longjmp.s | 13 ++++++++++++-
  15  src/setjmp/powerpc64/setjmp.s  | 13 ++++++++++++-
  16  2 files changed, 24 insertions(+), 2 deletions(-)
  17
  18 diff --git a/src/setjmp/powerpc64/longjmp.s b/src/setjmp/powerpc64/longjmp.s
  19 index 81d45ff6..da7172af 100644
  20 --- a/src/setjmp/powerpc64/longjmp.s
  21 +++ b/src/setjmp/powerpc64/longjmp.s
  22 @@ -56,7 +56,17 @@ longjmp:
  23         lfd 30, 38*8(3)
  24         lfd 31, 39*8(3)
  25
  26 -       # 6) restore vector registers v20-v31
  27 +       # 6) restore vector registers v20-v31 if hardware supports AltiVec
  28 +       mflr 0
  29 +       bl 1f
  30 +       .hidden __hwcap
  31 +       .long __hwcap-.
  32 +1:      mflr 4
  33 +       lwz 5, 0(4)
  34 +       add 4, 4, 5
  35 +       ld 4, 0(4)
  36 +       andis. 4, 4, 0x1000
  37 +       beq 1f
  38         addi 3, 3, 40*8
  39         lvx 20, 0, 3 ; addi 3, 3, 16
  40         lvx 21, 0, 3 ; addi 3, 3, 16
  41 @@ -70,6 +80,7 @@ longjmp:
  42         lvx 29, 0, 3 ; addi 3, 3, 16
  43         lvx 30, 0, 3 ; addi 3, 3, 16
  44         lvx 31, 0, 3
  45 +1:     mtlr 0
  46
  47         # 7) return r4 ? r4 : 1
  48         mr    3,   4
  49 diff --git a/src/setjmp/powerpc64/setjmp.s b/src/setjmp/powerpc64/setjmp.s
  50 index 37683fda..32853693 100644
  51 --- a/src/setjmp/powerpc64/setjmp.s
  52 +++ b/src/setjmp/powerpc64/setjmp.s
  53 @@ -69,7 +69,17 @@ __setjmp_toc:
  54         stfd 30, 38*8(3)
  55         stfd 31, 39*8(3)
  56
  57 -       # 5) store vector registers v20-v31
  58 +       # 5) store vector registers v20-v31 if hardware supports AltiVec
  59 +       mflr 0
  60 +       bl 1f
  61 +       .hidden __hwcap
  62 +       .long __hwcap-.
  63 +1:     mflr 4
  64 +       lwz 5, 0(4)
  65 +       add 4, 4, 5
  66 +       ld 4, 0(4)
  67 +       andis. 4, 4, 0x1000
  68 +       beq 1f
  69         addi  3, 3, 40*8
  70         stvx 20, 0, 3 ; addi 3, 3, 16
  71         stvx 21, 0, 3 ; addi 3, 3, 16
  72 @@ -83,6 +93,7 @@ __setjmp_toc:
  73         stvx 29, 0, 3 ; addi 3, 3, 16
  74         stvx 30, 0, 3 ; addi 3, 3, 16
  75         stvx 31, 0, 3
  76 +1:     mtlr 0
  77
  78         # 6) return 0
  79         li 3, 0
  80 --
  81 2.32.0
  82