target/linux/ubicom32/files/arch/ubicom32/include/asm/plio.h

   1 /*
   2  * plio.h
   3  *      PLIO defines.
   4  *
   5  * Copyright © 2009 Ubicom Inc. <www.ubicom.com>.  All Rights Reserved.
   6  *
   7  * This file is part of the Ubicom32 Linux Kernel Port.
   8  *
   9  * The Ubicom32 Linux Kernel Port is free software: you can
  10  * redistribute it and/or modify it under the terms of the GNU General
  11  * Public License as published by the Free Software Foundation, either
  12  * version 2 of the License, or (at your option) any later version.
  13  *
  14  * The Ubicom32 Linux Kernel Port is distributed in the hope that it
  15  * will be useful, but WITHOUT ANY WARRANTY; without even the implied
  16  * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  17  * See the GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with the Ubicom32 Linux Kernel Port.  If not,
  21  * see <http://www.gnu.org/licenses/>.
  22  * This file contains confidential information of Ubicom, Inc. and your use of
  23  * this file is subject to the Ubicom Software License Agreement distributed with
  24  * this file. If you are uncertain whether you are an authorized user or to report
  25  * any unauthorized use, please contact Ubicom, Inc. at +1-408-789-2200.
  26  * Unauthorized reproduction or distribution of this file is subject to civil and
  27  * criminal penalties.
  28  */
  29
  30 #ifndef __PLIO__H__
  31 #define __PLIO__H__
  32
  33 #include <asm/ip5000.h>
  34 #include <asm/thread.h>
  35
  36 #define PLIO_PORT               RD
  37 #define PLIO_EXT_PORT           RI
  38
  39 #define TRANSMIT_FIFO_WATERMARK 8
  40
  41 /*
  42  * PLIO non-blocking register definitions
  43  */
  44 #define PLIO_FN         2
  45
  46 typedef struct {
  47         unsigned        : 10;
  48         unsigned        rxfifo_thread_enable: 1;   /* allowed rxfifo thread enable */
  49         unsigned        : 1;
  50         unsigned        rxfifo_thread: 4;          /* allowed rxfifo thread access */
  51         unsigned        : 4;
  52         unsigned        br_thread: 4;              /* allowed blocking region thread access */
  53         unsigned        fn_reset: 4;               /* function reset bit vector */
  54         unsigned        rxfifo_sel: 1;             /* select between RXFIFO 0 and 1 */
  55         unsigned        fn_sel: 3;                 /* select port function */
  56 } plio_io_function_t;
  57
  58 typedef struct {
  59         unsigned        : 24;
  60         unsigned        pin:8;
  61 } plio_gpio_t;
  62
  63 typedef struct {
  64         unsigned        : 16;
  65         unsigned        txfifo_uf: 1;              /* TXFIFO underflow */
  66         unsigned        txfifo_wm: 1;              /* TXFIFO watermark */
  67         unsigned        rxfifo_of: 1;              /* RXFIFO overflow */
  68         unsigned        rxfifo_wm: 1;              /* RXFIFO watermark */
  69         unsigned        : 5;
  70         unsigned        lreg_int_addr_rd: 1;       /* read from specified LREG address */
  71         unsigned        lreg_int_addr_wr: 1;       /* write to specified LREG address */
  72         unsigned        extctl_int: 4;             /* synchronized external interrupts */
  73         unsigned        pfsm_int: 1;               /* state machine */
  74 } plio_intstat_t;
  75
  76 typedef struct {
  77         unsigned        txfifo_reset: 1;           /* TXFIFO reset for int_set only */
  78         unsigned        rxfifo_reset: 1;           /* RXFIFO reset for int_set only */
  79         unsigned        : 11;
  80         unsigned        idif_txfifo_flush: 1;      /* flush TXFIFO and idif_txfifo */
  81         unsigned        idif_rxfifo_flush: 1;      /* flush RXFIFO and idif_rxfifo */
  82         unsigned        pfsm_start: 1;             /* input to fsm */
  83         unsigned        txfifo_uf: 1;              /* TXFIFO underflow */
  84         unsigned        txfifo_wm: 1;              /* TXFIFO watermark */
  85         unsigned        rxfifo_of: 1;              /* RXFIFO overflow */
  86         unsigned        rxfifo_wm: 1;              /* RXFIFO watermark */
  87         unsigned        : 5;
  88         unsigned        lreg_int_addr_rd: 1;       /* read from specified LREG address */
  89         unsigned        lreg_int_addr_wr: 1;       /* write to specified LREG address */
  90         unsigned        extctl_int: 4;             /* synchronized external interrupts */
  91         unsigned        pfsm_int: 1;               /* state machine */
  92 } plio_intset_t;
  93
  94 typedef enum {
  95         PLIO_PORT_MODE_D,
  96         PLIO_PORT_MODE_DE,
  97         PLIO_PORT_MODE_DI,
  98         PLIO_PORT_MODE_DEI,
  99         PLIO_PORT_MODE_DC,
 100 } plio_port_mode_t;
 101
 102 typedef enum {
 103         PLIO_CLK_CORE,  /* CORE CLK */
 104         PLIO_CLK_IO,    /* IO CLK */
 105         PLIO_CLK_EXT,   /* EXT CLK */
 106 } plio_clk_src_t;
 107 typedef struct {
 108         unsigned                : 4;
 109         unsigned                edif_iaena_sel: 1;         /* Input Address Enable Select */
 110         unsigned                edif_iaclk_sel: 1;         /* Input Address Clock Select */
 111         unsigned                edif_iald_inv: 1;          /* Input Address Strobe Invert */
 112         unsigned                edif_idclk_sel: 1;         /* Input Data Clock Select */
 113         unsigned                edif_idld_inv: 1;          /* Input Data Strobe Invert */
 114         unsigned                edif_ds: 3;                /* specify IDR and ODR data shift */
 115         unsigned                edif_cmp_mode: 1;          /* configure IDR comparator output */
 116         unsigned                edif_idena_sel: 1;         /* Input Data Enable Select */
 117         unsigned                ecif_extclk_ena: 1;        /* plio_extctl output select */
 118         unsigned                idif_tx_fifo_cmd_sel: 1;   /* select pfsm_cmd data word position */
 119         unsigned                ptif_porti_cfg: 2;         /* select port I pin configuration */
 120         unsigned                ptif_portd_cfg: 3;         /* select port D pin configuration */
 121         plio_port_mode_t        ptif_port_mode: 3;      /* select other plio ports  */
 122         unsigned                icif_clk_plio_ext_inv: 1;  /* invert external plio clock when set */
 123         unsigned                icif_rst_plio: 1;          /* reset plio function and io fifos */
 124         plio_clk_src_t          icif_clk_src_sel: 2;      /* select plio clock source */
 125         unsigned                pfsm_prog: 1;              /* enable pfsm programming */
 126         unsigned                pfsm_cmd: 3;               /* software input to pfsm */
 127 } plio_fctl0_t;
 128
 129 typedef struct {
 130         unsigned        : 2;
 131         unsigned        idif_byteswap_tx: 3;       /* swap TXFIFO byte order */
 132         unsigned        idif_byteswap_rx: 3;       /* swap RXFIFO byte order */
 133         unsigned        : 1;
 134         unsigned        lreg_ena: 1;               /* enable local register map */
 135         unsigned        lreg_addr_fifo_cmp_ena: 1; /* enable a specific LREG address from/to TX/RX fifos */
 136         unsigned        lreg_addr_fifo_cmp: 5;     /* LREG address routed from/to TX/RX fifos */
 137         unsigned        : 1;
 138         unsigned        dcod_iald_idld_sel: 2;     /* select address/data strobes */
 139         unsigned        dcod_rw_src_sel: 1;        /* select LREG strobe source */
 140         unsigned        dcod_rd_sel: 5;            /* select read strobe source */
 141         unsigned        dcod_wr_sel: 5;            /* select write strobe source */
 142         unsigned        dcod_rd_lvl: 1;            /* select active level of read strobe */
 143         unsigned        dcod_wr_lvl: 1;            /* select active level of read strobe */
 144 } plio_fctl1_t;
 145
 146 typedef struct {
 147         unsigned        icif_eclk_div: 16;         /* external plio clock divider */
 148         unsigned        icif_iclk_div: 16;         /* internal plio clock divider */
 149 } plio_fctl2_t;
 150
 151 typedef struct {
 152         unsigned        : 27;
 153         unsigned        pfsm_state: 5;             /* current pfsm state */
 154 } plio_stat_0_t;
 155
 156 typedef struct {
 157         unsigned        : 3;
 158         unsigned        lreg_r_int_addr: 5;
 159         unsigned        : 11;
 160         unsigned        lreg_w_int_addr: 5;
 161         unsigned        lreg_w_int_data: 8;
 162 } plio_stat_1_t;
 163
 164 typedef struct {
 165         unsigned        : 32;
 166 } plio_stat_2_t;
 167
 168 typedef struct {
 169         unsigned        tx: 16;
 170         unsigned        rx: 16;
 171 } plio_io_fifo_wm_t, plio_io_fifo_lvl_t;
 172
 173
 174 /* plio blocking region register definitions
 175  */
 176 typedef struct {
 177         unsigned         ns1: 5;
 178         unsigned         ic1: 7;
 179         unsigned         ec1: 4;
 180         unsigned         ns0: 5;
 181         unsigned         ic0: 7;
 182         unsigned         ec0: 4;
 183 } plio_sram_t;
 184
 185 typedef struct {
 186         unsigned         : 2;
 187         unsigned         s9: 3;
 188         unsigned         s8: 3;
 189         unsigned         s7: 3;
 190         unsigned         s6: 3;
 191         unsigned         s5: 3;
 192         unsigned         s4: 3;
 193         unsigned         s3: 3;
 194         unsigned         s2: 3;
 195         unsigned         s1: 3;
 196         unsigned         s0: 3;
 197 } plio_grpsel_t;
 198
 199 typedef struct {
 200         unsigned        s7: 4;
 201         unsigned        s6: 4;
 202         unsigned        s5: 4;
 203         unsigned        s4: 4;
 204         unsigned        s3: 4;
 205         unsigned        s2: 4;
 206         unsigned        s1: 4;
 207         unsigned        s0: 4;
 208 } plio_cs_lut_t;
 209
 210 typedef struct {
 211         unsigned        lut3: 8;
 212         unsigned        lut2: 8;
 213         unsigned        lut1: 8;
 214         unsigned        lut0: 8;
 215 } plio_extctl_t;
 216
 217 typedef struct {
 218         plio_grpsel_t   grpsel[4];
 219         u16_t           cv[16];
 220         plio_cs_lut_t   cs_lut[4];
 221         plio_extctl_t   extctl_o_lut[8];
 222 } plio_pfsm_t;
 223
 224 typedef struct {
 225         u32_t           odr_oe_sel;
 226         u32_t           odr_oe;
 227         u32_t           cmp;
 228         u32_t           ncmp;
 229         u32_t           cmp_mask;
 230 } plio_edif_t;
 231
 232 typedef enum {
 233         PLIO_ECIF_CLK_OUT       = 9,
 234         PLIO_ECIF_IALD          = 9,
 235         PLIO_ECIF_CLK_IN        = 8,
 236         PLIO_ECIF_IDLD          = 8,
 237         PLIO_ECIF_INT           = 2,
 238 } plio_ecif_output_t;
 239
 240 typedef struct {
 241         u32_t           bypass_sync;
 242         u32_t           ift;
 243         u32_t           output_type;
 244         u32_t           output_ena;
 245         u32_t           output_lvl;
 246 } plio_ecif_t;
 247
 248 typedef struct {
 249         u32_t           idr_addr_pos_mask;
 250         u32_t           reserved;
 251         u32_t           lreg_bar;
 252 } plio_dcod_t;
 253
 254 typedef struct {
 255         u32_t           addr_rd_ena;
 256         u32_t           addr_wr_ena;
 257         u32_t           addr_rd_int_ena;
 258         u32_t           addr_wr_int_ena;
 259 } plio_lcfg_t;
 260
 261
 262 /*
 263  * PLIO configuration
 264  */
 265 typedef struct {
 266         plio_fctl0_t    fctl0;
 267         plio_fctl1_t    fctl1;
 268         plio_fctl2_t    fctl2;
 269 } plio_fctl_t;
 270
 271 typedef struct {
 272         plio_pfsm_t     pfsm;
 273         plio_edif_t     edif;
 274         plio_ecif_t     ecif;
 275         plio_dcod_t     dcod;
 276         plio_lcfg_t     lcfg;
 277 } plio_config_t;
 278
 279 typedef struct {
 280         plio_io_function_t      function;
 281         plio_gpio_t             gpio_ctl;
 282         plio_gpio_t             gpio_out;
 283         plio_gpio_t             gpio_in;
 284         plio_intstat_t          intstat;
 285         plio_intstat_t          intmask;
 286         plio_intset_t           intset;
 287         plio_intstat_t          intclr;
 288         unsigned                tx_lo;
 289         unsigned                tx_hi;
 290         unsigned                rx_lo;
 291         unsigned                rx_hi;
 292         plio_fctl0_t            fctl0;
 293         plio_fctl1_t            fctl1;
 294         plio_fctl2_t            fctl2;
 295         plio_stat_0_t           stat0;
 296         plio_stat_1_t           stat1;
 297         plio_stat_2_t           stat2;
 298         plio_io_fifo_wm_t       fifo_wm;
 299         plio_io_fifo_lvl_t      fifo_lvl;
 300 } plio_nbr_t;
 301
 302 typedef struct {
 303         u32_t                   pfsm_sram[256];
 304         plio_config_t           config;
 305 } plio_br_t;
 306
 307 #define PLIO_NBR        ((plio_nbr_t *)(PLIO_PORT))
 308 #define PLIO_BR         ((plio_br_t *)((PLIO_PORT + IO_PORT_BR_OFFSET)))
 309 #define PEXT_NBR        ((plio_nbr_t *)(PLIO_EXT_PORT))
 310
 311 extern void plio_init(const plio_fctl_t *plio_fctl, const plio_config_t *plio_config, const plio_sram_t plio_sram_cfg[], int sram_cfg_size);
 312
 313 #endif // __PLIO__H__