target/linux/sunxi/patches-4.14/080-arm64-allwinner-a64-add-SPI-nodes.patch

   1 From b518bb159032aac33503fd4cf98706dc84cc1266 Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Stefan=20Br=C3=BCns?= <stefan.bruens@rwth-aachen.de>
   3 Date: Thu, 31 Aug 2017 01:06:37 +0200
   4 Subject: [PATCH] arm64: allwinner: a64: add SPI nodes
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 The A64 SPI controllers are register compatible to the h3/h5 SPI
  10 controllers.
  11
  12 The A64 has two SPI controllers, each with a single chip select.
  13 The handles for the DMA channels (23/24 for SPI0/SPI1) are omitted,
  14 as the A64 DMA support is currently missing.
  15
  16 Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
  17 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  18 ---
  19  arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 41 +++++++++++++++++++
  20  1 file changed, 41 insertions(+)
  21
  22 diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
  23 index 8c8db1b057df..20aba7b186aa 100644
  24 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
  25 +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
  26 @@ -325,6 +325,16 @@
  27                                 drive-strength = <40>;
  28                         };
  29
  30 +                       spi0_pins: spi0 {
  31 +                               pins = "PC0", "PC1", "PC2", "PC3";
  32 +                               function = "spi0";
  33 +                       };
  34 +
  35 +                       spi1_pins: spi1 {
  36 +                               pins = "PD0", "PD1", "PD2", "PD3";
  37 +                               function = "spi1";
  38 +                       };
  39 +
  40                         uart0_pins_a: uart0@0 {
  41                                 pins = "PB8", "PB9";
  42                                 function = "uart0";
  43 @@ -449,6 +459,37 @@
  44                         #size-cells = <0>;
  45                 };
  46
  47 +
  48 +               spi0: spi@01c68000 {
  49 +                       compatible = "allwinner,sun8i-h3-spi";
  50 +                       reg = <0x01c68000 0x1000>;
  51 +                       interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
  52 +                       clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
  53 +                       clock-names = "ahb", "mod";
  54 +                       pinctrl-names = "default";
  55 +                       pinctrl-0 = <&spi0_pins>;
  56 +                       resets = <&ccu RST_BUS_SPI0>;
  57 +                       status = "disabled";
  58 +                       num-cs = <1>;
  59 +                       #address-cells = <1>;
  60 +                       #size-cells = <0>;
  61 +               };
  62 +
  63 +               spi1: spi@01c69000 {
  64 +                       compatible = "allwinner,sun8i-h3-spi";
  65 +                       reg = <0x01c69000 0x1000>;
  66 +                       interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
  67 +                       clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
  68 +                       clock-names = "ahb", "mod";
  69 +                       pinctrl-names = "default";
  70 +                       pinctrl-0 = <&spi1_pins>;
  71 +                       resets = <&ccu RST_BUS_SPI1>;
  72 +                       status = "disabled";
  73 +                       num-cs = <1>;
  74 +                       #address-cells = <1>;
  75 +                       #size-cells = <0>;
  76 +               };
  77 +
  78                 gic: interrupt-controller@1c81000 {
  79                         compatible = "arm,gic-400";
  80                         reg = <0x01c81000 0x1000>,
  81 --
  82 2.17.1
  83