target/linux/sunxi/patches-3.13/116-clk-sunxi-add-pll4.patch

   1 From ff0b5fdb65bc7f10af7e83bb0919cb6bec2dc624 Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
   3 Date: Mon, 23 Dec 2013 00:32:35 -0300
   4 Subject: [PATCH] ARM: sunxi: add PLL4 support
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 This commit adds the PLL4 definition to the sun4i, sun5i and sun7i
  10 device trees. PLL4 is compatible with PLL1.
  11
  12 Signed-off-by: Emilio López <emilio@elopez.com.ar>
  13 Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  14 ---
  15  arch/arm/boot/dts/sun4i-a10.dtsi  | 7 +++++++
  16  arch/arm/boot/dts/sun5i-a10s.dtsi | 7 +++++++
  17  arch/arm/boot/dts/sun5i-a13.dtsi  | 7 +++++++
  18  arch/arm/boot/dts/sun7i-a20.dtsi  | 7 +++++++
  19  4 files changed, 28 insertions(+)
  20
  21 --- a/arch/arm/boot/dts/sun4i-a10.dtsi
  22 +++ b/arch/arm/boot/dts/sun4i-a10.dtsi
  23 @@ -66,6 +66,13 @@
  24                         clocks = <&osc24M>;
  25                 };
  26
  27 +               pll4: pll4@01c20018 {
  28 +                       #clock-cells = <0>;
  29 +                       compatible = "allwinner,sun4i-pll1-clk";
  30 +                       reg = <0x01c20018 0x4>;
  31 +                       clocks = <&osc24M>;
  32 +               };
  33 +
  34                 /* dummy is 200M */
  35                 cpu: cpu@01c20054 {
  36                         #clock-cells = <0>;
  37 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi
  38 +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
  39 @@ -63,6 +63,13 @@
  40                         clocks = <&osc24M>;
  41                 };
  42
  43 +               pll4: pll4@01c20018 {
  44 +                       #clock-cells = <0>;
  45 +                       compatible = "allwinner,sun4i-pll1-clk";
  46 +                       reg = <0x01c20018 0x4>;
  47 +                       clocks = <&osc24M>;
  48 +               };
  49 +
  50                 /* dummy is 200M */
  51                 cpu: cpu@01c20054 {
  52                         #clock-cells = <0>;
  53 --- a/arch/arm/boot/dts/sun5i-a13.dtsi
  54 +++ b/arch/arm/boot/dts/sun5i-a13.dtsi
  55 @@ -67,6 +67,13 @@
  56                         clocks = <&osc24M>;
  57                 };
  58
  59 +               pll4: pll4@01c20018 {
  60 +                       #clock-cells = <0>;
  61 +                       compatible = "allwinner,sun4i-pll1-clk";
  62 +                       reg = <0x01c20018 0x4>;
  63 +                       clocks = <&osc24M>;
  64 +               };
  65 +
  66                 /* dummy is 200M */
  67                 cpu: cpu@01c20054 {
  68                         #clock-cells = <0>;
  69 --- a/arch/arm/boot/dts/sun7i-a20.dtsi
  70 +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
  71 @@ -62,6 +62,13 @@
  72                         clocks = <&osc24M>;
  73                 };
  74
  75 +               pll4: pll4@01c20018 {
  76 +                       #clock-cells = <0>;
  77 +                       compatible = "allwinner,sun4i-pll1-clk";
  78 +                       reg = <0x01c20018 0x4>;
  79 +                       clocks = <&osc24M>;
  80 +               };
  81 +
  82                 /*
  83                  * This is a dummy clock, to be used as placeholder on
  84                  * other mux clocks when a specific parent clock is not