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[openwrt/staging/mkresin.git] / target / linux / rtl838x / files-5.4 / drivers / net / ethernet / rtl838x_eth.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * linux/drivers/net/ethernet/rtl838x_eth.c
4 * Copyright (C) 2020 B. Koblitz
5 */
6
7 #include <linux/dma-mapping.h>
8 #include <linux/etherdevice.h>
9 #include <linux/interrupt.h>
10 #include <linux/io.h>
11 #include <linux/platform_device.h>
12 #include <linux/sched.h>
13 #include <linux/slab.h>
14 #include <linux/of.h>
15 #include <linux/of_net.h>
16 #include <linux/of_mdio.h>
17 #include <linux/module.h>
18 #include <linux/phylink.h>
19 #include <net/dsa.h>
20
21 #include <asm/mach-rtl838x/mach-rtl838x.h>
22 #include "rtl838x_eth.h"
23
24 extern struct rtl838x_soc_info soc_info;
25
26 /*
27 * Maximum number of RX rings is 8, assigned by switch based on
28 * packet/port priortity (not implemented)
29 * Maximum number of TX rings is 2 (only ring 0 used)
30 * RX ringlength needs to be at least 200, otherwise CPU and Switch
31 * may gridlock.
32 */
33 #define RXRINGS 2
34 #define RXRINGLEN 300
35 #define TXRINGS 2
36 #define TXRINGLEN 160
37 #define TX_EN 0x8
38 #define RX_EN 0x4
39 #define TX_DO 0x2
40 #define WRAP 0x2
41
42 #define RING_BUFFER 1600
43
44 struct p_hdr {
45 uint8_t *buf;
46 uint16_t reserved;
47 uint16_t size; /* buffer size */
48 uint16_t offset;
49 uint16_t len; /* pkt len */
50 uint16_t reserved2;
51 uint16_t cpu_tag[5];
52 } __packed __aligned(1);
53
54 struct ring_b {
55 uint32_t rx_r[RXRINGS][RXRINGLEN];
56 uint32_t tx_r[TXRINGS][TXRINGLEN];
57 struct p_hdr rx_header[RXRINGS][RXRINGLEN];
58 struct p_hdr tx_header[TXRINGS][TXRINGLEN];
59 uint32_t c_rx[RXRINGS];
60 uint32_t c_tx[TXRINGS];
61 uint8_t rx_space[RXRINGS*RXRINGLEN*RING_BUFFER];
62 uint8_t tx_space[TXRINGLEN*RING_BUFFER];
63 };
64
65 struct rtl838x_eth_priv {
66 struct net_device *netdev;
67 struct platform_device *pdev;
68 void *membase;
69 spinlock_t lock;
70 struct mii_bus *mii_bus;
71 struct napi_struct napi;
72 struct phylink *phylink;
73 struct phylink_config phylink_config;
74 u16 id;
75 u16 family_id;
76 const struct rtl838x_reg *r;
77 u8 cpu_port;
78 };
79
80 static const struct rtl838x_reg rtl838x_reg = {
81 .mac_port_ctrl = rtl838x_mac_port_ctrl,
82 .dma_if_intr_sts = RTL838X_DMA_IF_INTR_STS,
83 .dma_if_intr_msk = RTL838X_DMA_IF_INTR_MSK,
84 .dma_if_ctrl = RTL838X_DMA_IF_CTRL,
85 .mac_force_mode_ctrl = rtl838x_mac_force_mode_ctrl,
86 .dma_rx_base = rtl838x_dma_rx_base,
87 .dma_tx_base = rtl838x_dma_tx_base,
88 .dma_if_rx_ring_size = rtl838x_dma_if_rx_ring_size,
89 .dma_if_rx_ring_cntr = rtl838x_dma_if_rx_ring_cntr,
90 .dma_if_rx_cur = rtl838x_dma_if_rx_cur,
91 .rst_glb_ctrl = RTL838X_RST_GLB_CTRL_0,
92 .get_mac_link_sts = rtl838x_get_mac_link_sts,
93 .get_mac_link_dup_sts = rtl838x_get_mac_link_dup_sts,
94 .get_mac_link_spd_sts = rtl838x_get_mac_link_spd_sts,
95 .get_mac_rx_pause_sts = rtl838x_get_mac_rx_pause_sts,
96 .get_mac_tx_pause_sts = rtl838x_get_mac_tx_pause_sts,
97 .mac = RTL838X_MAC,
98 .l2_tbl_flush_ctrl = RTL838X_L2_TBL_FLUSH_CTRL,
99 };
100
101 static const struct rtl838x_reg rtl839x_reg = {
102 .mac_port_ctrl = rtl839x_mac_port_ctrl,
103 .dma_if_intr_sts = RTL839X_DMA_IF_INTR_STS,
104 .dma_if_intr_msk = RTL839X_DMA_IF_INTR_MSK,
105 .dma_if_ctrl = RTL839X_DMA_IF_CTRL,
106 .mac_force_mode_ctrl = rtl839x_mac_force_mode_ctrl,
107 .dma_rx_base = rtl839x_dma_rx_base,
108 .dma_tx_base = rtl839x_dma_tx_base,
109 .dma_if_rx_ring_size = rtl839x_dma_if_rx_ring_size,
110 .dma_if_rx_ring_cntr = rtl839x_dma_if_rx_ring_cntr,
111 .dma_if_rx_cur = rtl839x_dma_if_rx_cur,
112 .rst_glb_ctrl = RTL839X_RST_GLB_CTRL,
113 .get_mac_link_sts = rtl839x_get_mac_link_sts,
114 .get_mac_link_dup_sts = rtl839x_get_mac_link_dup_sts,
115 .get_mac_link_spd_sts = rtl839x_get_mac_link_spd_sts,
116 .get_mac_rx_pause_sts = rtl839x_get_mac_rx_pause_sts,
117 .get_mac_tx_pause_sts = rtl839x_get_mac_tx_pause_sts,
118 .mac = RTL839X_MAC,
119 .l2_tbl_flush_ctrl = RTL839X_L2_TBL_FLUSH_CTRL,
120 };
121
122 /*
123 * Discard the RX ring-buffers, called as part of the net-ISR
124 * when the buffer runs over
125 * Caller needs to hold priv->lock
126 */
127 static void rtl838x_rb_cleanup(struct rtl838x_eth_priv *priv)
128 {
129 int r;
130 u32 *last;
131 struct p_hdr *h;
132 struct ring_b *ring = priv->membase;
133
134 for (r = 0; r < RXRINGS; r++) {
135 last = (u32 *)KSEG1ADDR(sw_r32(priv->r->dma_if_rx_cur(r)));
136 do {
137 if ((ring->rx_r[r][ring->c_rx[r]] & 0x1))
138 break;
139 h = &ring->rx_header[r][ring->c_rx[r]];
140 h->buf = (u8 *)CPHYSADDR(ring->rx_space
141 + r * ring->c_rx[r] * RING_BUFFER);
142 h->size = RING_BUFFER;
143 h->len = 0;
144 /* make sure the header is visible to the ASIC */
145 mb();
146
147 ring->rx_r[r][ring->c_rx[r]] = CPHYSADDR(h) | 0x1
148 | (ring->c_rx[r] == (RXRINGLEN-1) ? WRAP : 0x1);
149 ring->c_rx[r] = (ring->c_rx[r] + 1) % RXRINGLEN;
150 } while (&ring->rx_r[r][ring->c_rx[r]] != last);
151 }
152 }
153
154 static irqreturn_t rtl838x_net_irq(int irq, void *dev_id)
155 {
156 struct net_device *dev = dev_id;
157 struct rtl838x_eth_priv *priv = netdev_priv(dev);
158 u32 status = sw_r32(priv->r->dma_if_intr_sts);
159
160 spin_lock(&priv->lock);
161 /* Ignore TX interrupt */
162 if ((status & 0xf0000)) {
163 /* Clear ISR */
164 sw_w32(0x000f0000, priv->r->dma_if_intr_sts);
165 }
166
167 /* RX interrupt */
168 if (status & 0x0ff00) {
169 /* Disable RX interrupt */
170 sw_w32_mask(0xff00, 0, priv->r->dma_if_intr_msk);
171 sw_w32(0x0000ff00, priv->r->dma_if_intr_sts);
172 napi_schedule(&priv->napi);
173 }
174
175 /* RX buffer overrun */
176 if (status & 0x000ff) {
177 sw_w32(0x000000ff, priv->r->dma_if_intr_sts);
178 rtl838x_rb_cleanup(priv);
179 }
180
181 spin_unlock(&priv->lock);
182 return IRQ_HANDLED;
183 }
184
185 static void rtl838x_hw_reset(struct rtl838x_eth_priv *priv)
186 {
187 u32 int_saved;
188
189 pr_info("RESETTING %x, CPU_PORT %d\n", priv->family_id, priv->cpu_port);
190 /* Stop TX/RX */
191 sw_w32(0x0, priv->r->mac_port_ctrl(priv->cpu_port));
192 mdelay(500);
193
194 int_saved = sw_r32(priv->r->dma_if_intr_msk);
195 /* Reset NIC */
196 sw_w32(0x08, priv->r->rst_glb_ctrl);
197 do {
198 udelay(20);
199 } while (sw_r32(priv->r->rst_glb_ctrl) & 0x08);
200 mdelay(100);
201
202 /* Restore notification settings: on RTL838x these bits are null */
203 sw_w32_mask(7 << 20, int_saved & (7 << 20), priv->r->dma_if_intr_msk);
204
205 /* Restart TX/RX to CPU port */
206 sw_w32(0x03, priv->r->mac_port_ctrl(priv->cpu_port));
207
208 if (priv->family_id == RTL8380_FAMILY_ID) {
209 /* Set Speed, duplex, flow control
210 * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
211 * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
212 * | MEDIA_SEL
213 */
214 sw_w32(0x6192F, priv->r->mac_force_mode_ctrl(priv->cpu_port));
215 /* allow CRC errors on CPU-port */
216 sw_w32_mask(0, 0x8, priv->r->mac_port_ctrl(priv->cpu_port));
217 } else {
218 /* Force CPU port link up */
219 sw_w32_mask(0, 3, priv->r->mac_force_mode_ctrl(priv->cpu_port));
220 }
221
222 /* Disable and clear interrupts */
223 sw_w32(0x00000000, priv->r->dma_if_intr_msk);
224 sw_w32(0xffffffff, priv->r->dma_if_intr_sts);
225 }
226
227 static void rtl838x_hw_ring_setup(struct rtl838x_eth_priv *priv)
228 {
229 int i;
230 struct ring_b *ring = priv->membase;
231
232 for (i = 0; i < RXRINGS; i++)
233 sw_w32(CPHYSADDR(&ring->rx_r[i]), priv->r->dma_rx_base(i));
234
235 for (i = 0; i < TXRINGS; i++)
236 sw_w32(CPHYSADDR(&ring->tx_r[i]), priv->r->dma_tx_base(i));
237 }
238
239 static void rtl838x_hw_en_rxtx(struct rtl838x_eth_priv *priv)
240 {
241 u32 v;
242
243 pr_info("%s\n", __func__);
244 /* Disable Head of Line features for all RX rings */
245 sw_w32(0xffffffff, priv->r->dma_if_rx_ring_size(0));
246
247 /* Truncate RX buffer to 0x640 (1600) bytes, pad TX */
248 sw_w32(0x06400020, priv->r->dma_if_ctrl);
249
250 /* Enable RX done, RX overflow and TX done interrupts */
251 sw_w32(0xfffff, priv->r->dma_if_intr_msk);
252
253 /* Enable traffic, engine expects empty FCS field */
254 sw_w32_mask(0, RX_EN | TX_EN, priv->r->dma_if_ctrl);
255
256 /* Make sure to flood all traffic to CPU_PORT */
257 if (priv->family_id == RTL8390_FAMILY_ID) {
258 /* CPU port joins Lookup Miss Flooding Portmask */
259 /* Table access: CMD: read, table = 2 */
260 /* Sets MC_PMSK table port bit for port 52 to 1 */
261 sw_w32(0x28000, RTL839X_TBL_ACCESS_L2_CTRL);
262 do { } while (sw_r32(RTL839X_TBL_ACCESS_L2_CTRL) & (1 << 17));
263 v = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(0));
264 sw_w32(v | 0x80000000, RTL839X_TBL_ACCESS_L2_DATA(0));
265 sw_w32(0x38000, RTL839X_TBL_ACCESS_L2_CTRL);
266 do { } while (sw_r32(RTL839X_TBL_ACCESS_L2_CTRL) & (1 << 17));
267 }
268 }
269
270 static void rtl838x_setup_ring_buffer(struct ring_b *ring)
271 {
272 int i, j;
273
274 struct p_hdr *h;
275
276 for (i = 0; i < RXRINGS; i++) {
277 for (j = 0; j < RXRINGLEN; j++) {
278 h = &ring->rx_header[i][j];
279 h->buf = (u8 *)CPHYSADDR(ring->rx_space + i * j * RING_BUFFER);
280 h->reserved = 0;
281 h->size = RING_BUFFER;
282 h->offset = 0;
283 h->len = 0;
284 /* All rings owned by switch, last one wraps */
285 ring->rx_r[i][j] = CPHYSADDR(h) | 1 | (j == (RXRINGLEN - 1) ? WRAP : 0);
286 }
287 ring->c_rx[i] = 0;
288 }
289
290 for (i = 0; i < TXRINGS; i++) {
291 for (j = 0; j < TXRINGLEN; j++) {
292 h = &ring->tx_header[i][j];
293 h->buf = (u8 *)CPHYSADDR(ring->tx_space + i * j * RING_BUFFER);
294 h->reserved = 0;
295 h->size = RING_BUFFER;
296 h->offset = 0;
297 h->len = 0;
298 ring->tx_r[i][j] = CPHYSADDR(&ring->tx_header[i][j]);
299 }
300 /* Last header is wrapping around */
301 ring->tx_r[i][j-1] |= 2;
302 ring->c_tx[i] = 0;
303 }
304 }
305
306 static int rtl838x_eth_open(struct net_device *ndev)
307 {
308 unsigned long flags;
309 struct rtl838x_eth_priv *priv = netdev_priv(ndev);
310 struct ring_b *ring = priv->membase;
311 int err;
312
313 pr_info("%s called %x, ring %x\n", __func__, (uint32_t)priv, (uint32_t)ring);
314 spin_lock_irqsave(&priv->lock, flags);
315 rtl838x_hw_reset(priv);
316 rtl838x_setup_ring_buffer(ring);
317 rtl838x_hw_ring_setup(priv);
318 err = request_irq(ndev->irq, rtl838x_net_irq, IRQF_SHARED,
319 ndev->name, ndev);
320 if (err) {
321 netdev_err(ndev, "%s: could not acquire interrupt: %d\n",
322 __func__, err);
323 return err;
324 }
325 phylink_start(priv->phylink);
326
327 napi_enable(&priv->napi);
328 netif_start_queue(ndev);
329
330 rtl838x_hw_en_rxtx(priv);
331
332 spin_unlock_irqrestore(&priv->lock, flags);
333
334 return 0;
335 }
336
337 static void rtl838x_hw_stop(struct rtl838x_eth_priv *priv)
338 {
339 int i;
340
341 /* Block all ports */
342 if (priv->family_id == RTL8380_FAMILY_ID) {
343 sw_w32(0x03000000, RTL838X_TBL_ACCESS_DATA_0(0));
344 sw_w32(0x00000000, RTL838X_TBL_ACCESS_DATA_0(1));
345 sw_w32(1 << 15 | 2 << 12, RTL838X_TBL_ACCESS_CTRL_0);
346 }
347
348 /* Flush L2 address cache */
349 if (priv->family_id == RTL8380_FAMILY_ID) {
350 for (i = 0; i <= priv->cpu_port; i++) {
351 sw_w32(1 << 26 | 1 << 23 | i << 5, priv->r->l2_tbl_flush_ctrl);
352 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & (1 << 26));
353 }
354 } else {
355 for (i = 0; i <= priv->cpu_port; i++) {
356 sw_w32(1 << 28 | 1 << 25 | i << 5, priv->r->l2_tbl_flush_ctrl);
357 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & (1 << 28));
358 }
359 }
360
361 /* CPU-Port: Link down BUG: Works only for RTL838x */
362 sw_w32(0x6192D, priv->r->mac_force_mode_ctrl(priv->cpu_port));
363 mdelay(100);
364
365 /* Disable traffic */
366 sw_w32_mask(RX_EN | TX_EN, 0, priv->r->dma_if_ctrl);
367 mdelay(200);
368
369 /* Disable all TX/RX interrupts */
370 sw_w32(0x00000000, priv->r->dma_if_intr_msk);
371 sw_w32(0x000fffff, priv->r->dma_if_intr_sts);
372 sw_w32(0x00000000, priv->r->dma_if_ctrl);
373 mdelay(200);
374 }
375
376 static int rtl838x_eth_stop(struct net_device *ndev)
377 {
378 unsigned long flags;
379 struct rtl838x_eth_priv *priv = netdev_priv(ndev);
380
381 pr_info("in %s\n", __func__);
382
383 spin_lock_irqsave(&priv->lock, flags);
384 phylink_stop(priv->phylink);
385 rtl838x_hw_stop(priv);
386 free_irq(ndev->irq, ndev);
387 napi_disable(&priv->napi);
388 netif_stop_queue(ndev);
389 spin_unlock_irqrestore(&priv->lock, flags);
390 return 0;
391 }
392
393 static void rtl838x_eth_set_multicast_list(struct net_device *dev)
394 {
395
396 }
397
398 static void rtl838x_eth_tx_timeout(struct net_device *ndev)
399 {
400 unsigned long flags;
401 struct rtl838x_eth_priv *priv = netdev_priv(ndev);
402
403 pr_info("in %s\n", __func__);
404 spin_lock_irqsave(&priv->lock, flags);
405 rtl838x_hw_stop(priv);
406 rtl838x_hw_ring_setup(priv);
407 rtl838x_hw_en_rxtx(priv);
408 netif_trans_update(ndev);
409 netif_start_queue(ndev);
410 spin_unlock_irqrestore(&priv->lock, flags);
411 }
412
413 static int rtl838x_eth_tx(struct sk_buff *skb, struct net_device *dev)
414 {
415 int len, i;
416 struct rtl838x_eth_priv *priv = netdev_priv(dev);
417 struct ring_b *ring = priv->membase;
418 uint32_t val;
419 int ret;
420 unsigned long flags;
421 struct p_hdr *h;
422 int dest_port = -1;
423
424 spin_lock_irqsave(&priv->lock, flags);
425 len = skb->len;
426
427 /* Check for DSA tagging at the end of the buffer */
428 if (netdev_uses_dsa(dev) && skb->data[len-4] == 0x80 && skb->data[len-3] > 0
429 && skb->data[len-3] < 28 && skb->data[len-2] == 0x10
430 && skb->data[len-1] == 0x00) {
431 /* Reuse tag space for CRC */
432 dest_port = skb->data[len-3];
433 len -= 4;
434 }
435 if (len < ETH_ZLEN)
436 len = ETH_ZLEN;
437
438 /* ASIC expects that packet includes CRC, so we extend by 4 bytes */
439 len += 4;
440
441 if (skb_padto(skb, len)) {
442 ret = NETDEV_TX_OK;
443 goto txdone;
444 }
445
446 /* We can send this packet if CPU owns the descriptor */
447 if (!(ring->tx_r[0][ring->c_tx[0]] & 0x1)) {
448 /* Set descriptor for tx */
449 h = &ring->tx_header[0][ring->c_tx[0]];
450
451 h->buf = (u8 *)CPHYSADDR(ring->tx_space);
452 h->size = len;
453 h->len = len;
454
455 /* Create cpu_tag */
456 if (dest_port > 0) {
457 h->cpu_tag[0] = 0x0400;
458 h->cpu_tag[1] = 0x0200;
459 h->cpu_tag[2] = 0x0000;
460 h->cpu_tag[3] = (1 << dest_port) >> 16;
461 h->cpu_tag[4] = (1 << dest_port) & 0xffff;
462 } else {
463 h->cpu_tag[0] = 0;
464 h->cpu_tag[1] = 0;
465 h->cpu_tag[2] = 0;
466 h->cpu_tag[3] = 0;
467 h->cpu_tag[4] = 0;
468 }
469
470 /* Copy packet data to tx buffer */
471 memcpy((void *)KSEG1ADDR(h->buf), skb->data, len);
472 /* Make sure packet data is visible to ASIC */
473 mb();
474
475 /* Hand over to switch */
476 ring->tx_r[0][ring->c_tx[0]] = ring->tx_r[0][ring->c_tx[0]] | 0x1;
477
478 /* BUG: before tx fetch, need to make sure right data is accessed */
479 for (i = 0; i < 10; i++) {
480 val = sw_r32(priv->r->dma_if_ctrl);
481 if ((val & 0xc) == 0xc)
482 break;
483 }
484
485 /* Tell switch to send data */
486 sw_w32_mask(0, TX_DO, priv->r->dma_if_ctrl);
487
488 dev->stats.tx_packets++;
489 dev->stats.tx_bytes += len;
490 dev_kfree_skb(skb);
491 ring->c_tx[0] = (ring->c_tx[0] + 1) % TXRINGLEN;
492 ret = NETDEV_TX_OK;
493 } else {
494 dev_warn(&priv->pdev->dev, "Data is owned by switch\n");
495 ret = NETDEV_TX_BUSY;
496 }
497 txdone:
498 spin_unlock_irqrestore(&priv->lock, flags);
499 return ret;
500 }
501
502 static int rtl838x_hw_receive(struct net_device *dev, int r, int budget)
503 {
504 struct rtl838x_eth_priv *priv = netdev_priv(dev);
505 struct ring_b *ring = priv->membase;
506 struct sk_buff *skb;
507 unsigned long flags;
508 int i, len, work_done = 0;
509 u8 *data, *skb_data;
510 unsigned int val;
511 u32 *last;
512 struct p_hdr *h;
513 bool dsa = netdev_uses_dsa(dev);
514
515 spin_lock_irqsave(&priv->lock, flags);
516 last = (u32 *)KSEG1ADDR(sw_r32(priv->r->dma_if_rx_cur(r)));
517
518 if (&ring->rx_r[r][ring->c_rx[r]] == last) {
519 spin_unlock_irqrestore(&priv->lock, flags);
520 return 0;
521 }
522 do {
523 if ((ring->rx_r[r][ring->c_rx[r]] & 0x1)) {
524 netdev_warn(dev, "WARNING Ring contention: ring %x, last %x, current %x, cPTR %x, ISR %x\n", r, (uint32_t)last,
525 (u32) &ring->rx_r[r][ring->c_rx[r]],
526 ring->rx_r[r][ring->c_rx[r]],
527 sw_r32(priv->r->dma_if_intr_sts));
528 break;
529 }
530
531 h = &ring->rx_header[r][ring->c_rx[r]];
532 data = (u8 *)KSEG1ADDR(h->buf);
533 len = h->len;
534
535 if (!len)
536 break;
537 h->buf = (u8 *)CPHYSADDR(ring->rx_space
538 + r * ring->c_rx[r] * RING_BUFFER);
539 h->size = RING_BUFFER;
540 h->len = 0;
541 work_done++;
542
543 len -= 4; /* strip the CRC */
544 /* Add 4 bytes for cpu_tag */
545 if (dsa)
546 len += 4;
547
548 skb = alloc_skb(len + 4, GFP_KERNEL);
549 skb_reserve(skb, NET_IP_ALIGN);
550
551 if (likely(skb)) {
552 /* BUG: Prevent ASIC bug */
553 sw_w32(0xffffffff, priv->r->dma_if_rx_ring_size(0));
554 for (i = 0; i < RXRINGS; i++) {
555 /* Update each ring cnt */
556 val = sw_r32(priv->r->dma_if_rx_ring_cntr(i));
557 sw_w32(val, priv->r->dma_if_rx_ring_cntr(i));
558 }
559
560 skb_data = skb_put(skb, len);
561 /* Make sure data is visible */
562 mb();
563 memcpy(skb->data, (u8 *)KSEG1ADDR(data), len);
564 /* Overwrite CRC with cpu_tag */
565 if (dsa) {
566 skb->data[len-4] = 0x80;
567 skb->data[len-3] = h->cpu_tag[0] & 0x1f;
568 skb->data[len-2] = 0x10;
569 skb->data[len-1] = 0x00;
570 }
571
572 skb->protocol = eth_type_trans(skb, dev);
573 dev->stats.rx_packets++;
574 dev->stats.rx_bytes += len;
575
576 netif_receive_skb(skb);
577 } else {
578 if (net_ratelimit())
579 dev_warn(&dev->dev, "low on memory - packet dropped\n");
580 dev->stats.rx_dropped++;
581 }
582 ring->rx_r[r][ring->c_rx[r]]
583 = CPHYSADDR(h) | 0x1 | (ring->c_rx[r] == (RXRINGLEN-1) ? WRAP : 0x1);
584 ring->c_rx[r] = (ring->c_rx[r] + 1) % RXRINGLEN;
585 } while (&ring->rx_r[r][ring->c_rx[r]] != last && work_done < budget);
586
587 spin_unlock_irqrestore(&priv->lock, flags);
588 return work_done;
589 }
590
591 static int rtl838x_poll_rx(struct napi_struct *napi, int budget)
592 {
593 struct rtl838x_eth_priv *priv = container_of(napi, struct rtl838x_eth_priv, napi);
594 int work_done = 0, r = 0;
595
596 while (work_done < budget && r < RXRINGS) {
597 work_done += rtl838x_hw_receive(priv->netdev, r, budget - work_done);
598 r++;
599 }
600
601 if (work_done < budget) {
602 napi_complete_done(napi, work_done);
603 /* Enable RX interrupt */
604 sw_w32(0xfffff, priv->r->dma_if_intr_msk);
605 }
606 return work_done;
607 }
608
609
610 static void rtl838x_validate(struct phylink_config *config,
611 unsigned long *supported,
612 struct phylink_link_state *state)
613 {
614 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
615
616 pr_info("In %s\n", __func__);
617
618 if (!phy_interface_mode_is_rgmii(state->interface) &&
619 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
620 state->interface != PHY_INTERFACE_MODE_MII &&
621 state->interface != PHY_INTERFACE_MODE_REVMII &&
622 state->interface != PHY_INTERFACE_MODE_GMII &&
623 state->interface != PHY_INTERFACE_MODE_QSGMII &&
624 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
625 state->interface != PHY_INTERFACE_MODE_SGMII) {
626 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
627 pr_err("Unsupported interface: %d\n", state->interface);
628 return;
629 }
630
631 /* Allow all the expected bits */
632 phylink_set(mask, Autoneg);
633 phylink_set_port_modes(mask);
634 phylink_set(mask, Pause);
635 phylink_set(mask, Asym_Pause);
636
637 /* With the exclusion of MII and Reverse MII, we support Gigabit,
638 * including Half duplex
639 */
640 if (state->interface != PHY_INTERFACE_MODE_MII &&
641 state->interface != PHY_INTERFACE_MODE_REVMII) {
642 phylink_set(mask, 1000baseT_Full);
643 phylink_set(mask, 1000baseT_Half);
644 }
645
646 phylink_set(mask, 10baseT_Half);
647 phylink_set(mask, 10baseT_Full);
648 phylink_set(mask, 100baseT_Half);
649 phylink_set(mask, 100baseT_Full);
650
651 bitmap_and(supported, supported, mask,
652 __ETHTOOL_LINK_MODE_MASK_NBITS);
653 bitmap_and(state->advertising, state->advertising, mask,
654 __ETHTOOL_LINK_MODE_MASK_NBITS);
655 }
656
657
658 static void rtl838x_mac_config(struct phylink_config *config,
659 unsigned int mode,
660 const struct phylink_link_state *state)
661 {
662 /* This is only being called for the master device,
663 * i.e. the CPU-Port
664 */
665
666 pr_info("In %s, mode %x\n", __func__, mode);
667 }
668
669 static void rtl838x_mac_an_restart(struct phylink_config *config)
670 {
671 struct net_device *dev = container_of(config->dev, struct net_device, dev);
672 struct rtl838x_eth_priv *priv = netdev_priv(dev);
673
674 pr_info("In %s\n", __func__);
675 /* Restart by disabling and re-enabling link */
676 sw_w32(0x6192D, priv->r->mac_force_mode_ctrl(priv->cpu_port));
677 mdelay(20);
678 sw_w32(0x6192F, priv->r->mac_force_mode_ctrl(priv->cpu_port));
679 }
680
681 static int rtl838x_mac_pcs_get_state(struct phylink_config *config,
682 struct phylink_link_state *state)
683 {
684 u32 speed;
685 struct net_device *dev = container_of(config->dev, struct net_device, dev);
686 struct rtl838x_eth_priv *priv = netdev_priv(dev);
687 int port = priv->cpu_port;
688
689 pr_info("In %s\n", __func__);
690
691 state->link = priv->r->get_mac_link_sts(port) ? 1 : 0;
692 state->duplex = priv->r->get_mac_link_dup_sts(port) ? 1 : 0;
693
694 speed = priv->r->get_mac_link_spd_sts(port);
695 switch (speed) {
696 case 0:
697 state->speed = SPEED_10;
698 break;
699 case 1:
700 state->speed = SPEED_100;
701 break;
702 state->speed = SPEED_1000;
703 break;
704 default:
705 state->speed = SPEED_UNKNOWN;
706 break;
707 }
708
709 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
710 if (priv->r->get_mac_rx_pause_sts(port))
711 state->pause |= MLO_PAUSE_RX;
712 if (priv->r->get_mac_tx_pause_sts(port))
713 state->pause |= MLO_PAUSE_TX;
714
715 return 1;
716 }
717
718 static void dump_mac_conf(struct rtl838x_eth_priv *priv)
719 {
720 int p;
721
722 for (p = 8; p < 16; p++) {
723 pr_debug("%d: %x, force %x\n", p, sw_r32(priv->r->mac_port_ctrl(p)),
724 sw_r32(priv->r->mac_force_mode_ctrl(p))
725 );
726 }
727 pr_debug("CPU: %x, force %x\n", sw_r32(priv->r->mac_port_ctrl(priv->cpu_port)),
728 sw_r32(priv->r->mac_force_mode_ctrl(priv->cpu_port))
729 );
730 }
731
732 static void rtl838x_mac_link_down(struct phylink_config *config,
733 unsigned int mode,
734 phy_interface_t interface)
735 {
736 struct net_device *dev = container_of(config->dev, struct net_device, dev);
737 struct rtl838x_eth_priv *priv = netdev_priv(dev);
738
739 pr_info("In %s\n", __func__);
740 /* Stop TX/RX to port */
741 sw_w32_mask(0x03, 0, priv->r->mac_port_ctrl(priv->cpu_port));
742 }
743
744 static void rtl838x_mac_link_up(struct phylink_config *config, unsigned int mode,
745 phy_interface_t interface,
746 struct phy_device *phy)
747 {
748 struct net_device *dev = container_of(config->dev, struct net_device, dev);
749 struct rtl838x_eth_priv *priv = netdev_priv(dev);
750
751 pr_info("In %s\n", __func__);
752 /* Restart TX/RX to port */
753 sw_w32_mask(0, 0x03, priv->r->mac_port_ctrl(priv->cpu_port));
754 }
755
756 static void rtl838x_set_mac_hw(struct net_device *dev, u8 *mac)
757 {
758 struct rtl838x_eth_priv *priv = netdev_priv(dev);
759 unsigned long flags;
760
761 spin_lock_irqsave(&priv->lock, flags);
762 pr_info("In %s\n", __func__);
763 sw_w32((mac[0] << 8) | mac[1], priv->r->mac);
764 sw_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5], priv->r->mac + 4);
765
766 if (priv->family_id == RTL8380_FAMILY_ID) {
767 /* 2 more registers, ALE/MAC block */
768 sw_w32((mac[0] << 8) | mac[1], RTL838X_MAC_ALE);
769 sw_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
770 (RTL838X_MAC_ALE + 4));
771
772 sw_w32((mac[0] << 8) | mac[1], RTL838X_MAC2);
773 sw_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
774 RTL838X_MAC2 + 4);
775 }
776 spin_unlock_irqrestore(&priv->lock, flags);
777 }
778
779 static int rtl838x_set_mac_address(struct net_device *dev, void *p)
780 {
781 struct rtl838x_eth_priv *priv = netdev_priv(dev);
782 const struct sockaddr *addr = p;
783 u8 *mac = (u8 *) (addr->sa_data);
784
785 if (!is_valid_ether_addr(addr->sa_data))
786 return -EADDRNOTAVAIL;
787
788 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
789 rtl838x_set_mac_hw(dev, mac);
790
791 pr_info("Using MAC %08x%08x\n", sw_r32(priv->r->mac), sw_r32(priv->r->mac + 4));
792 return 0;
793 }
794
795 static int rtl8390_init_mac(struct rtl838x_eth_priv *priv)
796 {
797 pr_info("Configuring RTL8390 MAC\n");
798 // from mac_config_init
799 sw_w32(0x80, RTL839X_MAC_EFUSE_CTRL);
800 sw_w32(0x4, RTL839X_RST_GLB_CTRL);
801 sw_w32(0x3c324f40, RTL839X_MAC_GLB_CTRL);
802 /* Unlimited egress rate */
803 sw_w32(0x1297b961, RTL839X_SCHED_LB_TICK_TKN_CTRL);
804
805 return 0;
806 }
807
808 static int rtl8380_init_mac(struct rtl838x_eth_priv *priv)
809 {
810 int i;
811
812 if (priv->family_id == 0x8390)
813 return rtl8390_init_mac(priv);
814
815 if (priv->family_id != 0x8380)
816 return 0;
817
818 pr_info("%s\n", __func__);
819 /* fix timer for EEE */
820 sw_w32(0x5001411, RTL838X_EEE_TX_TIMER_GIGA_CTRL);
821 sw_w32(0x5001417, RTL838X_EEE_TX_TIMER_GELITE_CTRL);
822
823 /* Init VLAN */
824 if (priv->id == 0x8382) {
825 for (i = 0; i <= 28; i++)
826 sw_w32(0, 0xd57c + i * 0x80);
827 }
828 if (priv->id == 0x8380) {
829 for (i = 8; i <= 28; i++)
830 sw_w32(0, 0xd57c + i * 0x80);
831 }
832 return 0;
833 }
834
835 static int rtl838x_get_link_ksettings(struct net_device *ndev,
836 struct ethtool_link_ksettings *cmd)
837 {
838 struct rtl838x_eth_priv *priv = netdev_priv(ndev);
839
840 pr_info("%s called\n", __func__);
841 return phylink_ethtool_ksettings_get(priv->phylink, cmd);
842 }
843
844 static int rtl838x_set_link_ksettings(struct net_device *ndev,
845 const struct ethtool_link_ksettings *cmd)
846 {
847 struct rtl838x_eth_priv *priv = netdev_priv(ndev);
848
849 pr_info("%s called\n", __func__);
850 return phylink_ethtool_ksettings_set(priv->phylink, cmd);
851 }
852
853
854 static int rtl838x_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
855 {
856 u32 val;
857 u32 offset = 0;
858 int err;
859 struct rtl838x_eth_priv *priv = bus->priv;
860
861 if (mii_id >= 24 && mii_id <= 27 && priv->id == 0x8380) {
862 if (mii_id == 26)
863 offset = 0x100;
864 val = sw_r32(MAPLE_SDS4_FIB_REG0r + offset + (regnum << 2)) & 0xffff;
865 return val;
866 }
867 err = rtl838x_read_phy(mii_id, 0, regnum, &val);
868 if (err)
869 return err;
870 return val;
871 }
872
873 static int rtl839x_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
874 {
875 u32 val;
876 int err;
877
878 err = rtl839x_read_phy(mii_id, 0, regnum, &val);
879 if (err)
880 return err;
881 return val;
882 }
883
884 static int rtl838x_mdio_write(struct mii_bus *bus, int mii_id,
885 int regnum, u16 value)
886 {
887 u32 offset = 0;
888 struct rtl838x_eth_priv *priv = bus->priv;
889
890 if (mii_id >= 24 && mii_id <= 27 && priv->id == 0x8380) {
891 if (mii_id == 26)
892 offset = 0x100;
893 sw_w32(value, MAPLE_SDS4_FIB_REG0r + offset + (regnum << 2));
894 return 0;
895 }
896 return rtl838x_write_phy(mii_id, 0, regnum, value);
897 }
898
899 static int rtl839x_mdio_write(struct mii_bus *bus, int mii_id,
900 int regnum, u16 value)
901 {
902 return rtl839x_write_phy(mii_id, 0, regnum, value);
903 }
904
905 static int rtl838x_mdio_reset(struct mii_bus *bus)
906 {
907 pr_info("%s called\n", __func__);
908 /* Disable MAC polling the PHY so that we can start configuration */
909 sw_w32(0x00000000, RTL838X_SMI_POLL_CTRL);
910
911 /* Enable PHY control via SoC */
912 sw_w32_mask(0, 1 << 15, RTL838X_SMI_GLB_CTRL);
913
914 return 0;
915 }
916
917 static int rtl839x_mdio_reset(struct mii_bus *bus)
918 {
919 pr_info("%s called\n", __func__);
920 /* Disable MAC polling the PHY so that we can start configuration */
921 sw_w32(0x00000000, RTL839X_SMI_PORT_POLLING_CTRL);
922 sw_w32(0x00000000, RTL839X_SMI_PORT_POLLING_CTRL + 4);
923 /* Disable PHY polling via SoC */
924 sw_w32_mask(1 << 7, 0, RTL839X_SMI_GLB_CTRL);
925
926 return 0;
927 }
928
929
930 static int rtl838x_mdio_init(struct rtl838x_eth_priv *priv)
931 {
932 struct device_node *mii_np;
933 int ret;
934
935 pr_info("%s called\n", __func__);
936 mii_np = of_get_child_by_name(priv->pdev->dev.of_node, "mdio-bus");
937
938 if (!mii_np) {
939 dev_err(&priv->pdev->dev, "no %s child node found", "mdio-bus");
940 return -ENODEV;
941 }
942
943 if (!of_device_is_available(mii_np)) {
944 ret = -ENODEV;
945 goto err_put_node;
946 }
947
948 priv->mii_bus = devm_mdiobus_alloc(&priv->pdev->dev);
949 if (!priv->mii_bus) {
950 ret = -ENOMEM;
951 goto err_put_node;
952 }
953
954 if (priv->family_id == RTL8380_FAMILY_ID) {
955 priv->mii_bus->name = "rtl838x-eth-mdio";
956 priv->mii_bus->read = rtl838x_mdio_read;
957 priv->mii_bus->write = rtl838x_mdio_write;
958 priv->mii_bus->reset = rtl838x_mdio_reset;
959 } else {
960 priv->mii_bus->name = "rtl839x-eth-mdio";
961 priv->mii_bus->read = rtl839x_mdio_read;
962 priv->mii_bus->write = rtl839x_mdio_write;
963 priv->mii_bus->reset = rtl839x_mdio_reset;
964 }
965 priv->mii_bus->priv = priv;
966 priv->mii_bus->parent = &priv->pdev->dev;
967
968 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np);
969 ret = of_mdiobus_register(priv->mii_bus, mii_np);
970
971 err_put_node:
972 of_node_put(mii_np);
973 return ret;
974 }
975
976 static int rtl838x_mdio_remove(struct rtl838x_eth_priv *priv)
977 {
978 pr_info("%s called\n", __func__);
979 if (!priv->mii_bus)
980 return 0;
981
982 mdiobus_unregister(priv->mii_bus);
983 mdiobus_free(priv->mii_bus);
984
985 return 0;
986 }
987
988 static const struct net_device_ops rtl838x_eth_netdev_ops = {
989 .ndo_open = rtl838x_eth_open,
990 .ndo_stop = rtl838x_eth_stop,
991 .ndo_start_xmit = rtl838x_eth_tx,
992 .ndo_set_mac_address = rtl838x_set_mac_address,
993 .ndo_validate_addr = eth_validate_addr,
994 .ndo_set_rx_mode = rtl838x_eth_set_multicast_list,
995 .ndo_tx_timeout = rtl838x_eth_tx_timeout,
996 };
997
998 static const struct phylink_mac_ops rtl838x_phylink_ops = {
999 .validate = rtl838x_validate,
1000 .mac_link_state = rtl838x_mac_pcs_get_state,
1001 .mac_an_restart = rtl838x_mac_an_restart,
1002 .mac_config = rtl838x_mac_config,
1003 .mac_link_down = rtl838x_mac_link_down,
1004 .mac_link_up = rtl838x_mac_link_up,
1005 };
1006
1007 static const struct ethtool_ops rtl838x_ethtool_ops = {
1008 .get_link_ksettings = rtl838x_get_link_ksettings,
1009 .set_link_ksettings = rtl838x_set_link_ksettings,
1010 };
1011
1012 static int __init rtl838x_eth_probe(struct platform_device *pdev)
1013 {
1014 struct net_device *dev;
1015 struct device_node *dn = pdev->dev.of_node;
1016 struct rtl838x_eth_priv *priv;
1017 struct resource *res, *mem;
1018 const void *mac;
1019 phy_interface_t phy_mode;
1020 struct phylink *phylink;
1021 int err = 0;
1022
1023 pr_info("Probing RTL838X eth device pdev: %x, dev: %x\n",
1024 (u32)pdev, (u32)(&(pdev->dev)));
1025
1026 if (!dn) {
1027 dev_err(&pdev->dev, "No DT found\n");
1028 return -EINVAL;
1029 }
1030
1031 dev = alloc_etherdev(sizeof(struct rtl838x_eth_priv));
1032 if (!dev) {
1033 err = -ENOMEM;
1034 goto err_free;
1035 }
1036 SET_NETDEV_DEV(dev, &pdev->dev);
1037 priv = netdev_priv(dev);
1038
1039 /* obtain buffer memory space */
1040 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1041 if (res) {
1042 mem = devm_request_mem_region(&pdev->dev, res->start,
1043 resource_size(res), res->name);
1044 if (!mem) {
1045 dev_err(&pdev->dev, "cannot request memory space\n");
1046 err = -ENXIO;
1047 goto err_free;
1048 }
1049
1050 dev->mem_start = mem->start;
1051 dev->mem_end = mem->end;
1052 } else {
1053 dev_err(&pdev->dev, "cannot request IO resource\n");
1054 err = -ENXIO;
1055 goto err_free;
1056 }
1057
1058 /* Allocate buffer memory */
1059 priv->membase = dmam_alloc_coherent(&pdev->dev,
1060 sizeof(struct ring_b), (void *)&dev->mem_start,
1061 GFP_KERNEL);
1062 if (!priv->membase) {
1063 dev_err(&pdev->dev, "cannot allocate DMA buffer\n");
1064 err = -ENOMEM;
1065 goto err_free;
1066 }
1067
1068 spin_lock_init(&priv->lock);
1069
1070 /* obtain device IRQ number */
1071 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1072 if (!res) {
1073 dev_err(&pdev->dev, "cannot obtain IRQ, using default 24\n");
1074 dev->irq = 24;
1075 } else {
1076 dev->irq = res->start;
1077 }
1078 dev->ethtool_ops = &rtl838x_ethtool_ops;
1079
1080 priv->id = soc_info.id;
1081 priv->family_id = soc_info.family;
1082 if (priv->id) {
1083 pr_info("Found SoC ID: %4x: %s, family %x\n",
1084 priv->id, soc_info.name, priv->family_id);
1085 } else {
1086 pr_err("Unknown chip id (%04x)\n", priv->id);
1087 return -ENODEV;
1088 }
1089
1090 if (priv->family_id == 0x8390) {
1091 priv->cpu_port = RTL839X_CPU_PORT;
1092 priv->r = &rtl839x_reg;
1093 } else {
1094 priv->cpu_port = RTL838X_CPU_PORT;
1095 priv->r = &rtl838x_reg;
1096 }
1097
1098 rtl8380_init_mac(priv);
1099
1100 /* try to get mac address in the following order:
1101 * 1) from device tree data
1102 * 2) from internal registers set by bootloader
1103 */
1104 mac = of_get_mac_address(pdev->dev.of_node);
1105 if (!IS_ERR(mac)) {
1106 memcpy(dev->dev_addr, mac, ETH_ALEN);
1107 rtl838x_set_mac_hw(dev, (u8 *)mac);
1108 } else {
1109 dev->dev_addr[0] = (sw_r32(priv->r->mac) >> 8) & 0xff;
1110 dev->dev_addr[1] = sw_r32(priv->r->mac) & 0xff;
1111 dev->dev_addr[2] = (sw_r32(priv->r->mac + 4) >> 24) & 0xff;
1112 dev->dev_addr[3] = (sw_r32(priv->r->mac + 4) >> 16) & 0xff;
1113 dev->dev_addr[4] = (sw_r32(priv->r->mac + 4) >> 8) & 0xff;
1114 dev->dev_addr[5] = sw_r32(priv->r->mac + 4) & 0xff;
1115 }
1116 /* if the address is invalid, use a random value */
1117 if (!is_valid_ether_addr(dev->dev_addr)) {
1118 struct sockaddr sa = { AF_UNSPEC };
1119
1120 netdev_warn(dev, "Invalid MAC address, using random\n");
1121 eth_hw_addr_random(dev);
1122 memcpy(sa.sa_data, dev->dev_addr, ETH_ALEN);
1123 if (rtl838x_set_mac_address(dev, &sa))
1124 netdev_warn(dev, "Failed to set MAC address.\n");
1125 }
1126 pr_info("Using MAC %08x%08x\n", sw_r32(priv->r->mac),
1127 sw_r32(priv->r->mac + 4));
1128 strcpy(dev->name, "eth%d");
1129 dev->netdev_ops = &rtl838x_eth_netdev_ops;
1130 priv->pdev = pdev;
1131 priv->netdev = dev;
1132
1133 err = rtl838x_mdio_init(priv);
1134 if (err)
1135 goto err_free;
1136
1137 err = register_netdev(dev);
1138 if (err)
1139 goto err_free;
1140
1141 netif_napi_add(dev, &priv->napi, rtl838x_poll_rx, 64);
1142 platform_set_drvdata(pdev, dev);
1143
1144 phy_mode = of_get_phy_mode(dn);
1145 if (phy_mode < 0) {
1146 dev_err(&pdev->dev, "incorrect phy-mode\n");
1147 err = -EINVAL;
1148 goto err_free;
1149 }
1150 priv->phylink_config.dev = &dev->dev;
1151 priv->phylink_config.type = PHYLINK_NETDEV;
1152
1153 phylink = phylink_create(&priv->phylink_config, pdev->dev.fwnode,
1154 phy_mode, &rtl838x_phylink_ops);
1155 if (IS_ERR(phylink)) {
1156 err = PTR_ERR(phylink);
1157 goto err_free;
1158 }
1159 priv->phylink = phylink;
1160 return 0;
1161
1162 err_free:
1163 pr_err("Error setting up netdev, freeing it again.\n");
1164 free_netdev(dev);
1165 return err;
1166 }
1167
1168 static int rtl838x_eth_remove(struct platform_device *pdev)
1169 {
1170 struct net_device *dev = platform_get_drvdata(pdev);
1171 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1172
1173 if (dev) {
1174 pr_info("Removing platform driver for rtl838x-eth\n");
1175 rtl838x_mdio_remove(priv);
1176 rtl838x_hw_stop(priv);
1177 netif_stop_queue(dev);
1178 netif_napi_del(&priv->napi);
1179 unregister_netdev(dev);
1180 free_netdev(dev);
1181 }
1182 return 0;
1183 }
1184
1185 static const struct of_device_id rtl838x_eth_of_ids[] = {
1186 { .compatible = "realtek,rtl838x-eth"},
1187 { /* sentinel */ }
1188 };
1189 MODULE_DEVICE_TABLE(of, rtl838x_eth_of_ids);
1190
1191 static struct platform_driver rtl838x_eth_driver = {
1192 .probe = rtl838x_eth_probe,
1193 .remove = rtl838x_eth_remove,
1194 .driver = {
1195 .name = "rtl838x-eth",
1196 .pm = NULL,
1197 .of_match_table = rtl838x_eth_of_ids,
1198 },
1199 };
1200
1201 module_platform_driver(rtl838x_eth_driver);
1202
1203 MODULE_AUTHOR("B. Koblitz");
1204 MODULE_DESCRIPTION("RTL838X SoC Ethernet Driver");
1205 MODULE_LICENSE("GPL");
Staging tree of Mathias Kresin