target/linux/rtl838x/files-5.4/arch/mips/rtl838x/irq.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Realtek RTL838X architecture specific IRQ handling
   4  *
   5  * Copyright  (C) 2020 B. Koblitz
   6  * based on the original BSP
   7  * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com)
   8  *
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/irqchip.h>
  15 #include <linux/of_irq.h>
  16 #include <linux/of_address.h>
  17 #include <linux/spinlock.h>
  18
  19 #include <asm/irq_cpu.h>
  20 #include <asm/mipsregs.h>
  21 #include <mach-rtl838x.h>
  22
  23 extern struct rtl838x_soc_info soc_info;
  24
  25 #define icu_r32(reg)                    rtl838x_r32(soc_info.icu_base + reg)
  26 #define icu_w32(val, reg)               rtl838x_w32(val, soc_info.icu_base + reg)
  27 #define icu_w32_mask(clear, set, reg)   rtl838x_w32_mask(clear, set, soc_info.icu_base + reg)
  28
  29 static DEFINE_RAW_SPINLOCK(irq_lock);
  30
  31 extern irqreturn_t c0_compare_interrupt(int irq, void *dev_id);
  32
  33
  34 static void rtl838x_ictl_enable_irq(struct irq_data *i)
  35 {
  36         unsigned long flags;
  37
  38         raw_spin_lock_irqsave(&irq_lock, flags);
  39         icu_w32_mask(0, 1 << i->irq, GIMR);
  40         raw_spin_unlock_irqrestore(&irq_lock, flags);
  41 }
  42
  43 static void rtl838x_ictl_disable_irq(struct irq_data *i)
  44 {
  45         unsigned long flags;
  46
  47         raw_spin_lock_irqsave(&irq_lock, flags);
  48         icu_w32_mask(1 << i->irq, 0, GIMR);
  49         raw_spin_unlock_irqrestore(&irq_lock, flags);
  50 }
  51
  52 static void rtl838x_ictl_eoi_irq(struct irq_data *i)
  53 {
  54         unsigned long flags;
  55
  56         raw_spin_lock_irqsave(&irq_lock, flags);
  57         icu_w32_mask(0, 1 << i->irq, GIMR);
  58         raw_spin_unlock_irqrestore(&irq_lock, flags);
  59 }
  60
  61 static struct irq_chip rtl838x_ictl_irq = {
  62         .name = "RTL83xx",
  63         .irq_enable = rtl838x_ictl_enable_irq,
  64         .irq_disable = rtl838x_ictl_disable_irq,
  65         .irq_ack = rtl838x_ictl_disable_irq,
  66         .irq_mask = rtl838x_ictl_disable_irq,
  67         .irq_unmask = rtl838x_ictl_enable_irq,
  68         .irq_eoi = rtl838x_ictl_eoi_irq,
  69 };
  70
  71 /*
  72  *  RTL8390/80/28 Interrupt Scheme
  73  *
  74  *  Source       IRQ      CPU INT
  75  *  --------   -------    -------
  76  *  UART0          31        IP3
  77  *  UART1          30        IP2
  78  *  TIMER0         29        IP6
  79  *  TIMER1         28        IP2
  80  *  OCPTO          27        IP2
  81  *  HLXTO          26        IP2
  82  *  SLXTO          25        IP2
  83  *  NIC            24        IP5
  84  *  GPIO_ABCD      23        IP5
  85  *  SWCORE         20        IP4
  86  */
  87
  88 asmlinkage void plat_irq_dispatch(void)
  89 {
  90         unsigned int pending, ext_int;
  91
  92         pending =  read_c0_cause();
  93
  94         if (pending & CAUSEF_IP7) {
  95                 c0_compare_interrupt(7, NULL);
  96         } else if (pending & CAUSEF_IP6) {
  97                 do_IRQ(TC0_IRQ);
  98         } else if (pending & CAUSEF_IP5) {
  99                 ext_int = icu_r32(GIMR) & icu_r32(GISR);
 100                 if (ext_int & NIC_IP)
 101                         do_IRQ(NIC_IRQ);
 102                 else if (ext_int & GPIO_ABCD_IP)
 103                         do_IRQ(GPIO_ABCD_IRQ);
 104                 else if ((ext_int & GPIO_EFGH_IP) && (soc_info.family == RTL8328_FAMILY_ID))
 105                         do_IRQ(GPIO_EFGH_IRQ);
 106                 else
 107                         spurious_interrupt();
 108         } else if (pending & CAUSEF_IP4) {
 109                 do_IRQ(SWCORE_IRQ);
 110         } else if (pending & CAUSEF_IP3) {
 111                 do_IRQ(UART0_IRQ);
 112         } else if (pending & CAUSEF_IP2) {
 113                 ext_int = icu_r32(GIMR) & icu_r32(GISR);
 114                 if (ext_int & TC1_IP)
 115                         do_IRQ(TC1_IRQ);
 116                 else if (ext_int & UART1_IP)
 117                         do_IRQ(UART1_IRQ);
 118                 else
 119                         spurious_interrupt();
 120         } else {
 121                 spurious_interrupt();
 122         }
 123 }
 124
 125 static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
 126 {
 127         irq_set_chip_and_handler(hw, &rtl838x_ictl_irq, handle_level_irq);
 128
 129         return 0;
 130 }
 131
 132 static const struct irq_domain_ops irq_domain_ops = {
 133         .xlate = irq_domain_xlate_onecell,
 134         .map = intc_map,
 135 };
 136
 137 int __init icu_of_init(struct device_node *node, struct device_node *parent)
 138 {
 139         int i;
 140         struct irq_domain *domain;
 141         struct resource res;
 142
 143         pr_info("Found Interrupt controller: %s (%s)\n", node->name, node->full_name);
 144         if (of_address_to_resource(node, 0, &res))
 145                 panic("Failed to get icu memory range");
 146
 147         if (!request_mem_region(res.start, resource_size(&res), res.name))
 148                 pr_err("Failed to request icu memory\n");
 149
 150         soc_info.icu_base = ioremap(res.start, resource_size(&res));
 151         pr_info("ICU Memory: %08x\n", (u32)soc_info.icu_base);
 152
 153         mips_cpu_irq_init();
 154
 155         domain = irq_domain_add_simple(node, 32, 0, &irq_domain_ops, NULL);
 156
 157         /* Setup all external HW irqs */
 158         for (i = 8; i < RTL838X_IRQ_ICTL_NUM; i++) {
 159                 irq_domain_associate(domain, i, i);
 160                 irq_set_chip_and_handler(RTL838X_IRQ_ICTL_BASE + i,
 161                                          &rtl838x_ictl_irq, handle_level_irq);
 162         }
 163
 164         if (request_irq(RTL838X_ICTL1_IRQ, no_action, IRQF_NO_THREAD,
 165                         "IRQ cascade 1", NULL)) {
 166                 pr_err("request_irq() cascade 1 for irq %d failed\n", RTL838X_ICTL1_IRQ);
 167         }
 168         if (request_irq(RTL838X_ICTL2_IRQ, no_action, IRQF_NO_THREAD,
 169                         "IRQ cascade 2", NULL)) {
 170                 pr_err("request_irq() cascade 2 for irq %d failed\n", RTL838X_ICTL2_IRQ);
 171         }
 172         if (request_irq(RTL838X_ICTL3_IRQ, no_action, IRQF_NO_THREAD,
 173                         "IRQ cascade 3", NULL)) {
 174                 pr_err("request_irq() cascade 3 for irq %d failed\n", RTL838X_ICTL3_IRQ);
 175         }
 176         if (request_irq(RTL838X_ICTL4_IRQ, no_action, IRQF_NO_THREAD,
 177                         "IRQ cascade 4", NULL)) {
 178                 pr_err("request_irq() cascade 4 for irq %d failed\n", RTL838X_ICTL4_IRQ);
 179         }
 180         if (request_irq(RTL838X_ICTL5_IRQ, no_action, IRQF_NO_THREAD,
 181                         "IRQ cascade 5", NULL)) {
 182                 pr_err("request_irq() cascade 5 for irq %d failed\n", RTL838X_ICTL5_IRQ);
 183         }
 184
 185         /* Set up interrupt routing scheme */
 186         icu_w32(IRR0_SETTING, IRR0);
 187         if (soc_info.family == RTL8380_FAMILY_ID)
 188                 icu_w32(IRR1_SETTING_RTL838X, IRR1);
 189         else
 190                 icu_w32(IRR1_SETTING_RTL839X, IRR1);
 191         icu_w32(IRR2_SETTING, IRR2);
 192         icu_w32(IRR3_SETTING, IRR3);
 193
 194         /* Enable timer0 and uart0 interrupts */
 195         icu_w32(TC0_IE | UART0_IE, GIMR);
 196         return 0;
 197 }
 198
 199 void __init arch_init_irq(void)
 200 {
 201         /* do board-specific irq initialization */
 202         irqchip_init();
 203 }
 204
 205 IRQCHIP_DECLARE(mips_cpu_intc, "rtl838x,icu", icu_of_init);