target/linux/realtek/patches-5.10/100-watchdog-add-realtek-otto-watchdog-timer.patch

   1 From 2dbf0c6e0eebf523008c15794434d2d1a9b1260e Mon Sep 17 00:00:00 2001
   2 Message-Id: <2dbf0c6e0eebf523008c15794434d2d1a9b1260e.1636018117.git.sander@svanheule.net>
   3 In-Reply-To: <cover.1636018117.git.sander@svanheule.net>
   4 References: <cover.1636018117.git.sander@svanheule.net>
   5 From: Sander Vanheule <sander@svanheule.net>
   6 Date: Sun, 3 Oct 2021 09:25:27 +0200
   7 Subject: [PATCH v3 2/2] watchdog: Add Realtek Otto watchdog timer
   8
   9 Realtek MIPS SoCs (platform name Otto) have a watchdog timer with
  10 pretimeout notifitication support. The WDT can (partially) hard reset,
  11 or soft reset the SoC.
  12
  13 This driver implements all features as described in the devicetree
  14 binding, except the phase2 interrupt, and also functions as a restart
  15 handler. The cpu reset mode is considered to be a "warm" restart, since
  16 this mode does not reset all peripherals. Being an embedded system
  17 though, the "cpu" and "software" modes will still cause the bootloader
  18 to run on restart.
  19
  20 It is not known how a forced system reset can be disabled on the
  21 supported platforms. This means that the phase2 interrupt will only fire
  22 at the same time as reset, so implementing phase2 is of little use.
  23
  24 Signed-off-by: Sander Vanheule <sander@svanheule.net>
  25 ---
  26  MAINTAINERS                         |   7 +
  27  drivers/watchdog/Kconfig            |  13 +
  28  drivers/watchdog/Makefile           |   1 +
  29  drivers/watchdog/realtek_otto_wdt.c | 361 ++++++++++++++++++++++++++++
  30  4 files changed, 382 insertions(+)
  31  create mode 100644 drivers/watchdog/realtek_otto_wdt.c
  32
  33 diff --git a/MAINTAINERS b/MAINTAINERS
  34 index 2c9070aeba2a..54c8f788d3e5 100644
  35 --- a/MAINTAINERS
  36 +++ b/MAINTAINERS
  37 @@ -15991,6 +15991,13 @@ S:     Maintained
  38  F:     include/sound/rt*.h
  39  F:     sound/soc/codecs/rt*
  40
  41 +REALTEK OTTO WATCHDOG
  42 +M:     Sander Vanheule <sander@svanheule.net>
  43 +L:     linux-watchdog@vger.kernel.org
  44 +S:     Maintained
  45 +F:     Documentation/devicetree/bindings/watchdog/realtek,otto-wdt.yaml
  46 +F:     driver/watchdog/realtek_otto_wdt.c
  47 +
  48  REALTEK RTL83xx SMI DSA ROUTER CHIPS
  49  M:     Linus Walleij <linus.walleij@linaro.org>
  50  S:     Maintained
  51 diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
  52 index bf59faeb3de1..d308e13a9aa1 100644
  53 --- a/drivers/watchdog/Kconfig
  54 +++ b/drivers/watchdog/Kconfig
  55 @@ -954,6 +954,19 @@ config RTD119X_WATCHDOG
  56           Say Y here to include support for the watchdog timer in
  57           Realtek RTD1295 SoCs.
  58
  59 +config REALTEK_OTTO_WDT
  60 +       tristate "Realtek Otto MIPS watchdog support"
  61 +       depends on MACH_REALTEK_RTL || COMPILE_TEST
  62 +       depends on COMMON_CLK
  63 +       select WATCHDOG_CORE
  64 +       default MACH_REALTEK_RTL
  65 +       help
  66 +         Say Y here to include support for the watchdog timer on Realtek
  67 +         RTL838x, RTL839x, RTL930x SoCs. This watchdog has pretimeout
  68 +         notifications and system reset on timeout.
  69 +
  70 +         When built as a module this will be called realtek_otto_wdt.
  71 +
  72  config SPRD_WATCHDOG
  73         tristate "Spreadtrum watchdog support"
  74         depends on ARCH_SPRD || COMPILE_TEST
  75 diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
  76 index 1bd2d6f37c53..a8dccf819163 100644
  77 --- a/drivers/watchdog/Makefile
  78 +++ b/drivers/watchdog/Makefile
  79 @@ -171,6 +171,7 @@ obj-$(CONFIG_IMGPDC_WDT) += imgpdc_wdt.o
  80  obj-$(CONFIG_MT7621_WDT) += mt7621_wdt.o
  81  obj-$(CONFIG_PIC32_WDT) += pic32-wdt.o
  82  obj-$(CONFIG_PIC32_DMT) += pic32-dmt.o
  83 +obj-$(CONFIG_REALTEK_OTTO_WDT) += realtek_otto_wdt.o
  84
  85  # PARISC Architecture
  86
  87 diff --git a/drivers/watchdog/realtek_otto_wdt.c b/drivers/watchdog/realtek_otto_wdt.c
  88 new file mode 100644
  89 index 000000000000..48bc8dfefc25
  90 --- /dev/null
  91 +++ b/drivers/watchdog/realtek_otto_wdt.c
  92 @@ -0,0 +1,361 @@
  93 +// SPDX-License-Identifier: GPL-2.0-only
  94 +
  95 +/*
  96 + * Realtek Otto MIPS platform watchdog
  97 + *
  98 + * Watchdog timer that will reset the system after timeout, using the selected
  99 + * reset mode.
 100 + *
 101 + * Counter scaling and timeouts:
 102 + * - Base prescale of (2 << 25), providing tick duration T_0: 168ms @ 200MHz
 103 + * - PRESCALE: logarithmic prescaler adding a factor of {1, 2, 4, 8}
 104 + * - Phase 1: Times out after (PHASE1 + 1) × PRESCALE × T_0
 105 + *   Generates an interrupt, WDT cannot be stopped after phase 1
 106 + * - Phase 2: starts after phase 1, times out after (PHASE2 + 1) × PRESCALE × T_0
 107 + *   Resets the system according to RST_MODE
 108 + */
 109 +
 110 +#include <linux/bits.h>
 111 +#include <linux/bitfield.h>
 112 +#include <linux/clk.h>
 113 +#include <linux/delay.h>
 114 +#include <linux/interrupt.h>
 115 +#include <linux/io.h>
 116 +#include <linux/math.h>
 117 +#include <linux/minmax.h>
 118 +#include <linux/module.h>
 119 +#include <linux/mod_devicetable.h>
 120 +#include <linux/platform_device.h>
 121 +#include <linux/property.h>
 122 +#include <linux/reboot.h>
 123 +#include <linux/watchdog.h>
 124 +
 125 +#define OTTO_WDT_REG_CNTR              0x0
 126 +#define OTTO_WDT_CNTR_PING             BIT(31)
 127 +
 128 +#define OTTO_WDT_REG_INTR              0x4
 129 +#define OTTO_WDT_INTR_PHASE_1          BIT(31)
 130 +#define OTTO_WDT_INTR_PHASE_2          BIT(30)
 131 +
 132 +#define OTTO_WDT_REG_CTRL              0x8
 133 +#define OTTO_WDT_CTRL_ENABLE           BIT(31)
 134 +#define OTTO_WDT_CTRL_PRESCALE         GENMASK(30, 29)
 135 +#define OTTO_WDT_CTRL_PHASE1           GENMASK(26, 22)
 136 +#define OTTO_WDT_CTRL_PHASE2           GENMASK(19, 15)
 137 +#define OTTO_WDT_CTRL_RST_MODE         GENMASK(1, 0)
 138 +#define OTTO_WDT_MODE_SOC              0
 139 +#define OTTO_WDT_MODE_CPU              1
 140 +#define OTTO_WDT_MODE_SOFTWARE         2
 141 +#define OTTO_WDT_CTRL_DEFAULT          OTTO_WDT_MODE_CPU
 142 +
 143 +#define OTTO_WDT_PRESCALE_MAX          3
 144 +
 145 +/*
 146 + * One higher than the max values contained in PHASE{1,2}, since a value of 0
 147 + * corresponds to one tick.
 148 + */
 149 +#define OTTO_WDT_PHASE_TICKS_MAX       32
 150 +
 151 +/*
 152 + * The maximum reset delay is actually 2×32 ticks, but that would require large
 153 + * pretimeout values for timeouts longer than 32 ticks. Limit the maximum timeout
 154 + * to 32 + 1 to ensure small pretimeout values can be configured as expected.
 155 + */
 156 +#define OTTO_WDT_TIMEOUT_TICKS_MAX     (OTTO_WDT_PHASE_TICKS_MAX + 1)
 157 +
 158 +struct otto_wdt_ctrl {
 159 +       struct watchdog_device wdev;
 160 +       struct device *dev;
 161 +       void __iomem *base;
 162 +       struct clk *clk;
 163 +       int irq_phase1;
 164 +};
 165 +
 166 +static int otto_wdt_start(struct watchdog_device *wdev)
 167 +{
 168 +       struct otto_wdt_ctrl *ctrl = watchdog_get_drvdata(wdev);
 169 +       u32 v;
 170 +
 171 +       v = ioread32(ctrl->base + OTTO_WDT_REG_CTRL);
 172 +       v |= OTTO_WDT_CTRL_ENABLE;
 173 +       iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL);
 174 +
 175 +       return 0;
 176 +}
 177 +
 178 +static int otto_wdt_stop(struct watchdog_device *wdev)
 179 +{
 180 +       struct otto_wdt_ctrl *ctrl = watchdog_get_drvdata(wdev);
 181 +       u32 v;
 182 +
 183 +       v = ioread32(ctrl->base + OTTO_WDT_REG_CTRL);
 184 +       v &= ~OTTO_WDT_CTRL_ENABLE;
 185 +       iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL);
 186 +
 187 +       return 0;
 188 +}
 189 +
 190 +static int otto_wdt_ping(struct watchdog_device *wdev)
 191 +{
 192 +       struct otto_wdt_ctrl *ctrl = watchdog_get_drvdata(wdev);
 193 +
 194 +       iowrite32(OTTO_WDT_CNTR_PING, ctrl->base + OTTO_WDT_REG_CNTR);
 195 +
 196 +       return 0;
 197 +}
 198 +
 199 +static int otto_wdt_tick_ms(struct otto_wdt_ctrl *ctrl, int prescale)
 200 +{
 201 +       unsigned int rate_khz = clk_get_rate(ctrl->clk) / 1000;
 202 +
 203 +       if (!rate_khz)
 204 +               return 0;
 205 +
 206 +       return DIV_ROUND_CLOSEST(1 << (25 + prescale), rate_khz);
 207 +}
 208 +
 209 +/*
 210 + * The timer asserts the PHASE1/PHASE2 IRQs when the number of ticks exceeds
 211 + * the value stored in those fields. This means each phase will run for at least
 212 + * one tick, so small values need to be clamped to correctly reflect the timeout.
 213 + */
 214 +static inline unsigned int div_round_ticks(unsigned int val, unsigned int tick_duration,
 215 +               unsigned int min_ticks)
 216 +{
 217 +       return max(min_ticks, DIV_ROUND_UP(val, tick_duration));
 218 +}
 219 +
 220 +static int otto_wdt_determine_timeouts(struct watchdog_device *wdev, unsigned int timeout,
 221 +               unsigned int pretimeout)
 222 +{
 223 +       struct otto_wdt_ctrl *ctrl = watchdog_get_drvdata(wdev);
 224 +       unsigned int pretimeout_ms = pretimeout * 1000;
 225 +       unsigned int timeout_ms = timeout * 1000;
 226 +       unsigned int prescale_next = 0;
 227 +       unsigned int phase1_ticks;
 228 +       unsigned int phase2_ticks;
 229 +       unsigned int total_ticks;
 230 +       unsigned int prescale;
 231 +       unsigned int tick_ms;
 232 +       u32 v;
 233 +
 234 +       do {
 235 +               prescale = prescale_next;
 236 +               if (prescale > OTTO_WDT_PRESCALE_MAX)
 237 +                       return -EINVAL;
 238 +
 239 +               tick_ms = otto_wdt_tick_ms(ctrl, prescale);
 240 +               total_ticks = div_round_ticks(timeout_ms, tick_ms, 2);
 241 +               phase1_ticks = div_round_ticks(timeout_ms - pretimeout_ms, tick_ms, 1);
 242 +               phase2_ticks = total_ticks - phase1_ticks;
 243 +
 244 +               prescale_next++;
 245 +       } while (phase1_ticks > OTTO_WDT_PHASE_TICKS_MAX
 246 +               || phase2_ticks > OTTO_WDT_PHASE_TICKS_MAX);
 247 +
 248 +       v = ioread32(ctrl->base + OTTO_WDT_REG_CTRL);
 249 +
 250 +       v &= ~(OTTO_WDT_CTRL_PRESCALE | OTTO_WDT_CTRL_PHASE1 | OTTO_WDT_CTRL_PHASE2);
 251 +       v |= FIELD_PREP(OTTO_WDT_CTRL_PHASE1, phase1_ticks - 1);
 252 +       v |= FIELD_PREP(OTTO_WDT_CTRL_PHASE2, phase2_ticks - 1);
 253 +       v |= FIELD_PREP(OTTO_WDT_CTRL_PRESCALE, prescale);
 254 +
 255 +       iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL);
 256 +
 257 +       timeout_ms = total_ticks * tick_ms;
 258 +       ctrl->wdev.timeout = timeout_ms / 1000;
 259 +
 260 +       pretimeout_ms = phase2_ticks * tick_ms;
 261 +       ctrl->wdev.pretimeout = pretimeout_ms / 1000;
 262 +
 263 +       return 0;
 264 +}
 265 +
 266 +static int otto_wdt_set_timeout(struct watchdog_device *wdev, unsigned int val)
 267 +{
 268 +       return otto_wdt_determine_timeouts(wdev, val, min(wdev->pretimeout, val - 1));
 269 +}
 270 +
 271 +static int otto_wdt_set_pretimeout(struct watchdog_device *wdev, unsigned int val)
 272 +{
 273 +       return otto_wdt_determine_timeouts(wdev, wdev->timeout, val);
 274 +}
 275 +
 276 +static int otto_wdt_restart(struct watchdog_device *wdev, unsigned long reboot_mode,
 277 +               void *data)
 278 +{
 279 +       struct otto_wdt_ctrl *ctrl = watchdog_get_drvdata(wdev);
 280 +       u32 reset_mode;
 281 +       u32 v;
 282 +
 283 +       disable_irq(ctrl->irq_phase1);
 284 +
 285 +       switch (reboot_mode) {
 286 +       case REBOOT_SOFT:
 287 +               reset_mode = OTTO_WDT_MODE_SOFTWARE;
 288 +               break;
 289 +       case REBOOT_WARM:
 290 +               reset_mode = OTTO_WDT_MODE_CPU;
 291 +               break;
 292 +       default:
 293 +               reset_mode = OTTO_WDT_MODE_SOC;
 294 +               break;
 295 +       }
 296 +
 297 +       /* Configure for shortest timeout and wait for reset to occur */
 298 +       v = FIELD_PREP(OTTO_WDT_CTRL_RST_MODE, reset_mode) | OTTO_WDT_CTRL_ENABLE;
 299 +       iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL);
 300 +
 301 +       mdelay(3 * otto_wdt_tick_ms(ctrl, 0));
 302 +
 303 +       return 0;
 304 +}
 305 +
 306 +static irqreturn_t otto_wdt_phase1_isr(int irq, void *dev_id)
 307 +{
 308 +       struct otto_wdt_ctrl *ctrl = dev_id;
 309 +
 310 +       iowrite32(OTTO_WDT_INTR_PHASE_1, ctrl->base + OTTO_WDT_REG_INTR);
 311 +       dev_crit(ctrl->dev, "phase 1 timeout\n");
 312 +       watchdog_notify_pretimeout(&ctrl->wdev);
 313 +
 314 +       return IRQ_HANDLED;
 315 +}
 316 +
 317 +static const struct watchdog_ops otto_wdt_ops = {
 318 +       .owner = THIS_MODULE,
 319 +       .start = otto_wdt_start,
 320 +       .stop = otto_wdt_stop,
 321 +       .ping = otto_wdt_ping,
 322 +       .set_timeout = otto_wdt_set_timeout,
 323 +       .set_pretimeout = otto_wdt_set_pretimeout,
 324 +       .restart = otto_wdt_restart,
 325 +};
 326 +
 327 +static const struct watchdog_info otto_wdt_info = {
 328 +       .identity = "Realtek Otto watchdog timer",
 329 +       .options = WDIOF_KEEPALIVEPING |
 330 +               WDIOF_MAGICCLOSE |
 331 +               WDIOF_SETTIMEOUT |
 332 +               WDIOF_PRETIMEOUT,
 333 +};
 334 +
 335 +static int otto_wdt_probe_reset_mode(struct otto_wdt_ctrl *ctrl)
 336 +{
 337 +       static const char *mode_property = "realtek,reset-mode";
 338 +       const struct fwnode_handle *node = ctrl->dev->fwnode;
 339 +       int mode_count;
 340 +       u32 mode;
 341 +       u32 v;
 342 +
 343 +       if (!node)
 344 +               return -ENXIO;
 345 +
 346 +       mode_count = fwnode_property_string_array_count(node, mode_property);
 347 +       if (mode_count < 0)
 348 +               return mode_count;
 349 +       else if (mode_count == 0)
 350 +               return 0;
 351 +       else if (mode_count != 1)
 352 +               return -EINVAL;
 353 +
 354 +       if (fwnode_property_match_string(node, mode_property, "soc") == 0)
 355 +               mode = OTTO_WDT_MODE_SOC;
 356 +       else if (fwnode_property_match_string(node, mode_property, "cpu") == 0)
 357 +               mode = OTTO_WDT_MODE_CPU;
 358 +       else if (fwnode_property_match_string(node, mode_property, "software") == 0)
 359 +               mode = OTTO_WDT_MODE_SOFTWARE;
 360 +       else
 361 +               return -EINVAL;
 362 +
 363 +       v = ioread32(ctrl->base + OTTO_WDT_REG_CTRL);
 364 +       v &= ~OTTO_WDT_CTRL_RST_MODE;
 365 +       v |= FIELD_PREP(OTTO_WDT_CTRL_RST_MODE, mode);
 366 +       iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL);
 367 +
 368 +       return 0;
 369 +}
 370 +
 371 +static int otto_wdt_probe(struct platform_device *pdev)
 372 +{
 373 +       struct device *dev = &pdev->dev;
 374 +       struct otto_wdt_ctrl *ctrl;
 375 +       unsigned int max_tick_ms;
 376 +       int ret;
 377 +
 378 +       ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
 379 +       if (!ctrl)
 380 +               return -ENOMEM;
 381 +
 382 +       ctrl->dev = dev;
 383 +       ctrl->base = devm_platform_ioremap_resource(pdev, 0);
 384 +       if (IS_ERR(ctrl->base))
 385 +               return PTR_ERR(ctrl->base);
 386 +
 387 +       /* Clear any old interrupts and reset initial state */
 388 +       iowrite32(OTTO_WDT_INTR_PHASE_1 | OTTO_WDT_INTR_PHASE_2,
 389 +                       ctrl->base + OTTO_WDT_REG_INTR);
 390 +       iowrite32(OTTO_WDT_CTRL_DEFAULT, ctrl->base + OTTO_WDT_REG_CTRL);
 391 +
 392 +       ctrl->clk = devm_clk_get(dev, NULL);
 393 +       if (IS_ERR(ctrl->clk))
 394 +               return dev_err_probe(dev, PTR_ERR(ctrl->clk), "Failed to get clock\n");
 395 +
 396 +       ctrl->irq_phase1 = platform_get_irq_byname(pdev, "phase1");
 397 +       if (ctrl->irq_phase1 < 0)
 398 +               return dev_err_probe(dev, ctrl->irq_phase1, "phase1 IRQ not found\n");
 399 +
 400 +       ret = devm_request_irq(dev, ctrl->irq_phase1, otto_wdt_phase1_isr, 0,
 401 +                       "realtek-otto-wdt", ctrl);
 402 +       if (ret)
 403 +               return dev_err_probe(dev, ret, "Failed to get IRQ for phase1\n");
 404 +
 405 +       ret = otto_wdt_probe_reset_mode(ctrl);
 406 +       if (ret)
 407 +               return dev_err_probe(dev, ret, "Invalid reset mode specified\n");
 408 +
 409 +       ctrl->wdev.parent = dev;
 410 +       ctrl->wdev.info = &otto_wdt_info;
 411 +       ctrl->wdev.ops = &otto_wdt_ops;
 412 +
 413 +       /*
 414 +        * Since pretimeout cannot be disabled, min. timeout is twice the
 415 +        * subsystem resolution. max. timeout is ca. 43s at a bus clock of 200MHz.
 416 +        */
 417 +       ctrl->wdev.min_timeout = 2;
 418 +       max_tick_ms = otto_wdt_tick_ms(ctrl, OTTO_WDT_PRESCALE_MAX);
 419 +       ctrl->wdev.max_hw_heartbeat_ms = max_tick_ms * OTTO_WDT_TIMEOUT_TICKS_MAX;
 420 +       ctrl->wdev.timeout = min(30U, ctrl->wdev.max_hw_heartbeat_ms / 1000);
 421 +
 422 +       watchdog_set_drvdata(&ctrl->wdev, ctrl);
 423 +       watchdog_init_timeout(&ctrl->wdev, 0, dev);
 424 +       watchdog_stop_on_reboot(&ctrl->wdev);
 425 +       watchdog_set_restart_priority(&ctrl->wdev, 128);
 426 +
 427 +       ret = otto_wdt_determine_timeouts(&ctrl->wdev, ctrl->wdev.timeout, 1);
 428 +       if (ret)
 429 +               return dev_err_probe(dev, ret, "Failed to set timeout\n");
 430 +
 431 +       return devm_watchdog_register_device(dev, &ctrl->wdev);
 432 +}
 433 +
 434 +static const struct of_device_id otto_wdt_ids[] = {
 435 +       { .compatible = "realtek,rtl8380-wdt" },
 436 +       { .compatible = "realtek,rtl8390-wdt" },
 437 +       { .compatible = "realtek,rtl9300-wdt" },
 438 +       { }
 439 +};
 440 +MODULE_DEVICE_TABLE(of, otto_wdt_ids);
 441 +
 442 +static struct platform_driver otto_wdt_driver = {
 443 +       .probe = otto_wdt_probe,
 444 +       .driver = {
 445 +               .name = "realtek-otto-watchdog",
 446 +               .of_match_table = otto_wdt_ids,
 447 +       },
 448 +};
 449 +module_platform_driver(otto_wdt_driver);
 450 +
 451 +MODULE_LICENSE("GPL v2");
 452 +MODULE_AUTHOR("Sander Vanheule <sander@svanheule.net>");
 453 +MODULE_DESCRIPTION("Realtek Otto watchdog timer driver");
 454 --
 455 2.31.1
 456