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realtek: need to handle PHY_INTERFACE_MODE_NA for sfps
[openwrt/staging/jow.git] / target / linux / realtek / files-5.4 / drivers / net / dsa / rtl83xx / dsa.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <net/dsa.h>
4 #include <linux/if_bridge.h>
5
6 #include <asm/mach-rtl838x/mach-rtl83xx.h>
7 #include "rtl83xx.h"
8
9
10 extern struct rtl83xx_soc_info soc_info;
11
12
13 static void rtl83xx_init_stats(struct rtl838x_switch_priv *priv)
14 {
15 mutex_lock(&priv->reg_mutex);
16
17 /* Enable statistics module: all counters plus debug.
18 * On RTL839x all counters are enabled by default
19 */
20 if (priv->family_id == RTL8380_FAMILY_ID)
21 sw_w32_mask(0, 3, RTL838X_STAT_CTRL);
22
23 /* Reset statistics counters */
24 sw_w32_mask(0, 1, priv->r->stat_rst);
25
26 mutex_unlock(&priv->reg_mutex);
27 }
28
29 static void rtl83xx_write_cam(int idx, u32 *r)
30 {
31 u32 cmd = BIT(16) /* Execute cmd */
32 | BIT(15) /* Read */
33 | BIT(13) /* Table type 0b01 */
34 | (idx & 0x3f);
35
36 sw_w32(r[0], RTL838X_TBL_ACCESS_L2_DATA(0));
37 sw_w32(r[1], RTL838X_TBL_ACCESS_L2_DATA(1));
38 sw_w32(r[2], RTL838X_TBL_ACCESS_L2_DATA(2));
39
40 sw_w32(cmd, RTL838X_TBL_ACCESS_L2_CTRL);
41 do { } while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL) & BIT(16));
42 }
43
44 static u64 rtl83xx_hash_key(struct rtl838x_switch_priv *priv, u64 mac, u32 vid)
45 {
46 switch (priv->family_id) {
47 case RTL8380_FAMILY_ID:
48 return rtl838x_hash(priv, mac << 12 | vid);
49 case RTL8390_FAMILY_ID:
50 return rtl839x_hash(priv, mac << 12 | vid);
51 case RTL9300_FAMILY_ID:
52 return rtl930x_hash(priv, ((u64)vid) << 48 | mac);
53 default:
54 pr_err("Hash not implemented\n");
55 }
56 return 0;
57 }
58
59 static void rtl83xx_write_hash(int idx, u32 *r)
60 {
61 u32 cmd = BIT(16) /* Execute cmd */
62 | 0 << 15 /* Write */
63 | 0 << 13 /* Table type 0b00 */
64 | (idx & 0x1fff);
65
66 sw_w32(0, RTL838X_TBL_ACCESS_L2_DATA(0));
67 sw_w32(0, RTL838X_TBL_ACCESS_L2_DATA(1));
68 sw_w32(0, RTL838X_TBL_ACCESS_L2_DATA(2));
69 sw_w32(cmd, RTL838X_TBL_ACCESS_L2_CTRL);
70 do { } while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL) & BIT(16));
71 }
72
73 static void rtl83xx_enable_phy_polling(struct rtl838x_switch_priv *priv)
74 {
75 int i;
76 u64 v = 0;
77
78 msleep(1000);
79 /* Enable all ports with a PHY, including the SFP-ports */
80 for (i = 0; i < priv->cpu_port; i++) {
81 if (priv->ports[i].phy)
82 v |= BIT(i);
83 }
84
85 pr_debug("%s: %16llx\n", __func__, v);
86 priv->r->set_port_reg_le(v, priv->r->smi_poll_ctrl);
87
88 /* PHY update complete, there is no global PHY polling enable bit on the 9300 */
89 if (priv->family_id == RTL8390_FAMILY_ID)
90 sw_w32_mask(0, BIT(7), RTL839X_SMI_GLB_CTRL);
91 else if(priv->family_id == RTL9300_FAMILY_ID)
92 sw_w32_mask(0, 0x8000, RTL838X_SMI_GLB_CTRL);
93 }
94
95 const struct rtl83xx_mib_desc rtl83xx_mib[] = {
96 MIB_DESC(2, 0xf8, "ifInOctets"),
97 MIB_DESC(2, 0xf0, "ifOutOctets"),
98 MIB_DESC(1, 0xec, "dot1dTpPortInDiscards"),
99 MIB_DESC(1, 0xe8, "ifInUcastPkts"),
100 MIB_DESC(1, 0xe4, "ifInMulticastPkts"),
101 MIB_DESC(1, 0xe0, "ifInBroadcastPkts"),
102 MIB_DESC(1, 0xdc, "ifOutUcastPkts"),
103 MIB_DESC(1, 0xd8, "ifOutMulticastPkts"),
104 MIB_DESC(1, 0xd4, "ifOutBroadcastPkts"),
105 MIB_DESC(1, 0xd0, "ifOutDiscards"),
106 MIB_DESC(1, 0xcc, ".3SingleCollisionFrames"),
107 MIB_DESC(1, 0xc8, ".3MultipleCollisionFrames"),
108 MIB_DESC(1, 0xc4, ".3DeferredTransmissions"),
109 MIB_DESC(1, 0xc0, ".3LateCollisions"),
110 MIB_DESC(1, 0xbc, ".3ExcessiveCollisions"),
111 MIB_DESC(1, 0xb8, ".3SymbolErrors"),
112 MIB_DESC(1, 0xb4, ".3ControlInUnknownOpcodes"),
113 MIB_DESC(1, 0xb0, ".3InPauseFrames"),
114 MIB_DESC(1, 0xac, ".3OutPauseFrames"),
115 MIB_DESC(1, 0xa8, "DropEvents"),
116 MIB_DESC(1, 0xa4, "tx_BroadcastPkts"),
117 MIB_DESC(1, 0xa0, "tx_MulticastPkts"),
118 MIB_DESC(1, 0x9c, "CRCAlignErrors"),
119 MIB_DESC(1, 0x98, "tx_UndersizePkts"),
120 MIB_DESC(1, 0x94, "rx_UndersizePkts"),
121 MIB_DESC(1, 0x90, "rx_UndersizedropPkts"),
122 MIB_DESC(1, 0x8c, "tx_OversizePkts"),
123 MIB_DESC(1, 0x88, "rx_OversizePkts"),
124 MIB_DESC(1, 0x84, "Fragments"),
125 MIB_DESC(1, 0x80, "Jabbers"),
126 MIB_DESC(1, 0x7c, "Collisions"),
127 MIB_DESC(1, 0x78, "tx_Pkts64Octets"),
128 MIB_DESC(1, 0x74, "rx_Pkts64Octets"),
129 MIB_DESC(1, 0x70, "tx_Pkts65to127Octets"),
130 MIB_DESC(1, 0x6c, "rx_Pkts65to127Octets"),
131 MIB_DESC(1, 0x68, "tx_Pkts128to255Octets"),
132 MIB_DESC(1, 0x64, "rx_Pkts128to255Octets"),
133 MIB_DESC(1, 0x60, "tx_Pkts256to511Octets"),
134 MIB_DESC(1, 0x5c, "rx_Pkts256to511Octets"),
135 MIB_DESC(1, 0x58, "tx_Pkts512to1023Octets"),
136 MIB_DESC(1, 0x54, "rx_Pkts512to1023Octets"),
137 MIB_DESC(1, 0x50, "tx_Pkts1024to1518Octets"),
138 MIB_DESC(1, 0x4c, "rx_StatsPkts1024to1518Octets"),
139 MIB_DESC(1, 0x48, "tx_Pkts1519toMaxOctets"),
140 MIB_DESC(1, 0x44, "rx_Pkts1519toMaxOctets"),
141 MIB_DESC(1, 0x40, "rxMacDiscards")
142 };
143
144
145 /* DSA callbacks */
146
147
148 static enum dsa_tag_protocol rtl83xx_get_tag_protocol(struct dsa_switch *ds, int port)
149 {
150 /* The switch does not tag the frames, instead internally the header
151 * structure for each packet is tagged accordingly.
152 */
153 return DSA_TAG_PROTO_TRAILER;
154 }
155
156 static int rtl83xx_setup(struct dsa_switch *ds)
157 {
158 int i;
159 struct rtl838x_switch_priv *priv = ds->priv;
160 u64 port_bitmap = BIT_ULL(priv->cpu_port);
161
162 pr_debug("%s called\n", __func__);
163
164 /* Disable MAC polling the PHY so that we can start configuration */
165 priv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl);
166
167 for (i = 0; i < ds->num_ports; i++)
168 priv->ports[i].enable = false;
169 priv->ports[priv->cpu_port].enable = true;
170
171 /* Isolate ports from each other: traffic only CPU <-> port */
172 /* Setting bit j in register RTL838X_PORT_ISO_CTRL(i) allows
173 * traffic from source port i to destination port j
174 */
175 for (i = 0; i < priv->cpu_port; i++) {
176 if (priv->ports[i].phy) {
177 priv->r->set_port_reg_be(BIT_ULL(priv->cpu_port) | BIT(i),
178 priv->r->port_iso_ctrl(i));
179 port_bitmap |= BIT_ULL(i);
180 }
181 }
182 priv->r->set_port_reg_be(port_bitmap, priv->r->port_iso_ctrl(priv->cpu_port));
183
184 if (priv->family_id == RTL8380_FAMILY_ID)
185 rtl838x_print_matrix();
186 else
187 rtl839x_print_matrix();
188
189 rtl83xx_init_stats(priv);
190
191 ds->configure_vlan_while_not_filtering = true;
192
193 /* Enable MAC Polling PHY again */
194 rtl83xx_enable_phy_polling(priv);
195 pr_debug("Please wait until PHY is settled\n");
196 msleep(1000);
197 return 0;
198 }
199
200 static int rtl930x_setup(struct dsa_switch *ds)
201 {
202 int i;
203 struct rtl838x_switch_priv *priv = ds->priv;
204 u32 port_bitmap = BIT(priv->cpu_port);
205
206 pr_info("%s called\n", __func__);
207
208 // Enable CSTI STP mode
209 // sw_w32(1, RTL930X_ST_CTRL);
210
211 /* Disable MAC polling the PHY so that we can start configuration */
212 sw_w32(0, RTL930X_SMI_POLL_CTRL);
213
214 // Disable all ports except CPU port
215 for (i = 0; i < ds->num_ports; i++)
216 priv->ports[i].enable = false;
217 priv->ports[priv->cpu_port].enable = true;
218
219 for (i = 0; i < priv->cpu_port; i++) {
220 if (priv->ports[i].phy) {
221 priv->r->traffic_set(i, BIT(priv->cpu_port) | BIT(i));
222 port_bitmap |= 1ULL << i;
223 }
224 }
225 priv->r->traffic_set(priv->cpu_port, port_bitmap);
226
227 rtl930x_print_matrix();
228
229 // TODO: Initialize statistics
230
231 ds->configure_vlan_while_not_filtering = true;
232
233 rtl83xx_enable_phy_polling(priv);
234
235 return 0;
236 }
237
238 static void rtl83xx_phylink_validate(struct dsa_switch *ds, int port,
239 unsigned long *supported,
240 struct phylink_link_state *state)
241 {
242 struct rtl838x_switch_priv *priv = ds->priv;
243 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
244
245 pr_debug("In %s port %d", __func__, port);
246
247 if (!phy_interface_mode_is_rgmii(state->interface) &&
248 state->interface != PHY_INTERFACE_MODE_NA &&
249 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
250 state->interface != PHY_INTERFACE_MODE_MII &&
251 state->interface != PHY_INTERFACE_MODE_REVMII &&
252 state->interface != PHY_INTERFACE_MODE_GMII &&
253 state->interface != PHY_INTERFACE_MODE_QSGMII &&
254 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
255 state->interface != PHY_INTERFACE_MODE_SGMII) {
256 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
257 dev_err(ds->dev,
258 "Unsupported interface: %d for port %d\n",
259 state->interface, port);
260 return;
261 }
262
263 /* Allow all the expected bits */
264 phylink_set(mask, Autoneg);
265 phylink_set_port_modes(mask);
266 phylink_set(mask, Pause);
267 phylink_set(mask, Asym_Pause);
268
269 /* With the exclusion of MII and Reverse MII, we support Gigabit,
270 * including Half duplex
271 */
272 if (state->interface != PHY_INTERFACE_MODE_MII &&
273 state->interface != PHY_INTERFACE_MODE_REVMII) {
274 phylink_set(mask, 1000baseT_Full);
275 phylink_set(mask, 1000baseT_Half);
276 }
277
278 /* On both the 8380 and 8382, ports 24-27 are SFP ports */
279 if (port >= 24 && port <= 27 && priv->family_id == RTL8380_FAMILY_ID)
280 phylink_set(mask, 1000baseX_Full);
281
282 phylink_set(mask, 10baseT_Half);
283 phylink_set(mask, 10baseT_Full);
284 phylink_set(mask, 100baseT_Half);
285 phylink_set(mask, 100baseT_Full);
286
287 bitmap_and(supported, supported, mask,
288 __ETHTOOL_LINK_MODE_MASK_NBITS);
289 bitmap_and(state->advertising, state->advertising, mask,
290 __ETHTOOL_LINK_MODE_MASK_NBITS);
291 }
292
293 static int rtl83xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
294 struct phylink_link_state *state)
295 {
296 struct rtl838x_switch_priv *priv = ds->priv;
297 u64 speed;
298 u64 link;
299
300 if (port < 0 || port > priv->cpu_port)
301 return -EINVAL;
302
303 /*
304 * On the RTL9300 for at least the RTL8226B PHY, the MAC-side link
305 * state needs to be read twice in order to read a correct result.
306 * This would not be necessary for ports connected e.g. to RTL8218D
307 * PHYs.
308 */
309 state->link = 0;
310 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
311 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
312 if (link & BIT_ULL(port))
313 state->link = 1;
314 pr_debug("%s: link state: %llx\n", __func__, link & BIT_ULL(port));
315
316 state->duplex = 0;
317 if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
318 state->duplex = 1;
319
320 speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
321 speed >>= (port % 16) << 1;
322 switch (speed & 0x3) {
323 case 0:
324 state->speed = SPEED_10;
325 break;
326 case 1:
327 state->speed = SPEED_100;
328 break;
329 case 2:
330 state->speed = SPEED_1000;
331 break;
332 case 3:
333 if (port == 24 || port == 26) /* Internal serdes */
334 state->speed = SPEED_2500;
335 else
336 state->speed = SPEED_100; /* Is in fact 500Mbit */
337 }
338
339 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
340 if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
341 state->pause |= MLO_PAUSE_RX;
342 if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
343 state->pause |= MLO_PAUSE_TX;
344 return 1;
345 }
346
347 static void rtl83xx_phylink_mac_config(struct dsa_switch *ds, int port,
348 unsigned int mode,
349 const struct phylink_link_state *state)
350 {
351 struct rtl838x_switch_priv *priv = ds->priv;
352 u32 reg;
353 int speed_bit = priv->family_id == RTL8380_FAMILY_ID ? 4 : 3;
354
355 pr_debug("%s port %d, mode %x\n", __func__, port, mode);
356
357 // BUG: Make this work on RTL93XX
358 if (priv->family_id >= RTL9300_FAMILY_ID)
359 return;
360
361 if (port == priv->cpu_port) {
362 /* Set Speed, duplex, flow control
363 * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
364 * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
365 * | MEDIA_SEL
366 */
367 if (priv->family_id == RTL8380_FAMILY_ID) {
368 sw_w32(0x6192F, priv->r->mac_force_mode_ctrl(priv->cpu_port));
369 /* allow CRC errors on CPU-port */
370 sw_w32_mask(0, 0x8, RTL838X_MAC_PORT_CTRL(priv->cpu_port));
371 } else {
372 sw_w32_mask(0, 3, priv->r->mac_force_mode_ctrl(priv->cpu_port));
373 }
374 return;
375 }
376
377 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
378 /* Auto-Negotiation does not work for MAC in RTL8390 */
379 if (priv->family_id == RTL8380_FAMILY_ID) {
380 if (mode == MLO_AN_PHY) {
381 pr_debug("PHY autonegotiates\n");
382 reg |= BIT(2);
383 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
384 return;
385 }
386 }
387
388 if (mode != MLO_AN_FIXED)
389 pr_debug("Fixed state.\n");
390
391 if (priv->family_id == RTL8380_FAMILY_ID) {
392 /* Clear id_mode_dis bit, and the existing port mode, let
393 * RGMII_MODE_EN bet set by mac_link_{up,down}
394 */
395 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
396
397 if (state->pause & MLO_PAUSE_TXRX_MASK) {
398 if (state->pause & MLO_PAUSE_TX)
399 reg |= TX_PAUSE_EN;
400 reg |= RX_PAUSE_EN;
401 }
402 }
403
404 reg &= ~(3 << speed_bit);
405 switch (state->speed) {
406 case SPEED_1000:
407 reg |= 2 << speed_bit;
408 break;
409 case SPEED_100:
410 reg |= 1 << speed_bit;
411 break;
412 }
413
414 if (priv->family_id == RTL8380_FAMILY_ID) {
415 reg &= ~(DUPLEX_FULL | FORCE_LINK_EN);
416 if (state->link)
417 reg |= FORCE_LINK_EN;
418 if (state->duplex == DUPLEX_FULL)
419 reg |= DUPLX_MODE;
420 }
421
422 // Disable AN
423 if (priv->family_id == RTL8380_FAMILY_ID)
424 reg &= ~BIT(2);
425 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
426 }
427
428 static void rtl83xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
429 unsigned int mode,
430 phy_interface_t interface)
431 {
432 struct rtl838x_switch_priv *priv = ds->priv;
433 /* Stop TX/RX to port */
434 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
435 }
436
437 static void rtl83xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
438 unsigned int mode,
439 phy_interface_t interface,
440 struct phy_device *phydev)
441 {
442 struct rtl838x_switch_priv *priv = ds->priv;
443 /* Restart TX/RX to port */
444 sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
445 }
446
447 static void rtl83xx_get_strings(struct dsa_switch *ds,
448 int port, u32 stringset, u8 *data)
449 {
450 int i;
451
452 if (stringset != ETH_SS_STATS)
453 return;
454
455 for (i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++)
456 strncpy(data + i * ETH_GSTRING_LEN, rtl83xx_mib[i].name,
457 ETH_GSTRING_LEN);
458 }
459
460 static void rtl83xx_get_ethtool_stats(struct dsa_switch *ds, int port,
461 uint64_t *data)
462 {
463 struct rtl838x_switch_priv *priv = ds->priv;
464 const struct rtl83xx_mib_desc *mib;
465 int i;
466 u64 h;
467
468 for (i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++) {
469 mib = &rtl83xx_mib[i];
470
471 data[i] = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 252 - mib->offset);
472 if (mib->size == 2) {
473 h = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 248 - mib->offset);
474 data[i] |= h << 32;
475 }
476 }
477 }
478
479 static int rtl83xx_get_sset_count(struct dsa_switch *ds, int port, int sset)
480 {
481 if (sset != ETH_SS_STATS)
482 return 0;
483
484 return ARRAY_SIZE(rtl83xx_mib);
485 }
486
487 static int rtl83xx_port_enable(struct dsa_switch *ds, int port,
488 struct phy_device *phydev)
489 {
490 struct rtl838x_switch_priv *priv = ds->priv;
491 u64 v;
492
493 pr_debug("%s: %x %d", __func__, (u32) priv, port);
494 priv->ports[port].enable = true;
495
496 /* enable inner tagging on egress, do not keep any tags */
497 if (priv->family_id == RTL9310_FAMILY_ID)
498 sw_w32(BIT(4), priv->r->vlan_port_tag_sts_ctrl + (port << 2));
499 else
500 sw_w32(1, priv->r->vlan_port_tag_sts_ctrl + (port << 2));
501
502 if (dsa_is_cpu_port(ds, port))
503 return 0;
504
505 /* add port to switch mask of CPU_PORT */
506 priv->r->traffic_enable(priv->cpu_port, port);
507
508 /* add all other ports in the same bridge to switch mask of port */
509 v = priv->r->traffic_get(port);
510 v |= priv->ports[port].pm;
511 priv->r->traffic_set(port, v);
512
513 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_SABLK_CTRL);
514 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_DABLK_CTRL);
515
516 return 0;
517 }
518
519 static void rtl83xx_port_disable(struct dsa_switch *ds, int port)
520 {
521 struct rtl838x_switch_priv *priv = ds->priv;
522 u64 v;
523
524 pr_debug("%s %x: %d", __func__, (u32)priv, port);
525 /* you can only disable user ports */
526 if (!dsa_is_user_port(ds, port))
527 return;
528
529 // BUG: This does not work on RTL931X
530 /* remove port from switch mask of CPU_PORT */
531 priv->r->traffic_disable(priv->cpu_port, port);
532
533 /* remove all other ports in the same bridge from switch mask of port */
534 v = priv->r->traffic_get(port);
535 v &= ~priv->ports[port].pm;
536 priv->r->traffic_set(port, v);
537
538 priv->ports[port].enable = false;
539 }
540
541 static int rtl83xx_get_mac_eee(struct dsa_switch *ds, int port,
542 struct ethtool_eee *e)
543 {
544 struct rtl838x_switch_priv *priv = ds->priv;
545
546 pr_debug("%s: port %d", __func__, port);
547 e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full;
548 if (sw_r32(priv->r->mac_force_mode_ctrl(port)) & BIT(9))
549 e->advertised |= ADVERTISED_100baseT_Full;
550
551 if (sw_r32(priv->r->mac_force_mode_ctrl(port)) & BIT(10))
552 e->advertised |= ADVERTISED_1000baseT_Full;
553
554 e->eee_enabled = priv->ports[port].eee_enabled;
555 pr_debug("enabled: %d, active %x\n", e->eee_enabled, e->advertised);
556
557 if (sw_r32(RTL838X_MAC_EEE_ABLTY) & BIT(port)) {
558 e->lp_advertised = ADVERTISED_100baseT_Full;
559 e->lp_advertised |= ADVERTISED_1000baseT_Full;
560 }
561
562 e->eee_active = !!(e->advertised & e->lp_advertised);
563 pr_debug("active: %d, lp %x\n", e->eee_active, e->lp_advertised);
564
565 return 0;
566 }
567
568 static int rtl83xx_set_mac_eee(struct dsa_switch *ds, int port,
569 struct ethtool_eee *e)
570 {
571 struct rtl838x_switch_priv *priv = ds->priv;
572
573 pr_debug("%s: port %d", __func__, port);
574 if (e->eee_enabled) {
575 pr_debug("Globally enabling EEE\n");
576 sw_w32_mask(0x4, 0, RTL838X_SMI_GLB_CTRL);
577 }
578 if (e->eee_enabled) {
579 pr_debug("Enabling EEE for MAC %d\n", port);
580 sw_w32_mask(0, 3 << 9, priv->r->mac_force_mode_ctrl(port));
581 sw_w32_mask(0, BIT(port), RTL838X_EEE_PORT_TX_EN);
582 sw_w32_mask(0, BIT(port), RTL838X_EEE_PORT_RX_EN);
583 priv->ports[port].eee_enabled = true;
584 e->eee_enabled = true;
585 } else {
586 pr_debug("Disabling EEE for MAC %d\n", port);
587 sw_w32_mask(3 << 9, 0, priv->r->mac_force_mode_ctrl(port));
588 sw_w32_mask(BIT(port), 0, RTL838X_EEE_PORT_TX_EN);
589 sw_w32_mask(BIT(port), 0, RTL838X_EEE_PORT_RX_EN);
590 priv->ports[port].eee_enabled = false;
591 e->eee_enabled = false;
592 }
593 return 0;
594 }
595
596 /*
597 * Set Switch L2 Aging time, t is time in milliseconds
598 * t = 0: aging is disabled
599 */
600 static int rtl83xx_set_l2aging(struct dsa_switch *ds, u32 t)
601 {
602 struct rtl838x_switch_priv *priv = ds->priv;
603 int t_max = priv->family_id == RTL8380_FAMILY_ID ? 0x7fffff : 0x1FFFFF;
604
605 /* Convert time in mseconds to internal value */
606 if (t > 0x10000000) { /* Set to maximum */
607 t = t_max;
608 } else {
609 if (priv->family_id == RTL8380_FAMILY_ID)
610 t = ((t * 625) / 1000 + 127) / 128;
611 else
612 t = (t * 5 + 2) / 3;
613 }
614 sw_w32(t, priv->r->l2_ctrl_1);
615 return 0;
616 }
617
618 static int rtl83xx_port_bridge_join(struct dsa_switch *ds, int port,
619 struct net_device *bridge)
620 {
621 struct rtl838x_switch_priv *priv = ds->priv;
622 u64 port_bitmap = 1ULL << priv->cpu_port, v;
623 int i;
624
625 pr_debug("%s %x: %d %llx", __func__, (u32)priv, port, port_bitmap);
626 mutex_lock(&priv->reg_mutex);
627 for (i = 0; i < ds->num_ports; i++) {
628 /* Add this port to the port matrix of the other ports in the
629 * same bridge. If the port is disabled, port matrix is kept
630 * and not being setup until the port becomes enabled.
631 */
632 if (dsa_is_user_port(ds, i) && i != port) {
633 if (dsa_to_port(ds, i)->bridge_dev != bridge)
634 continue;
635 if (priv->ports[i].enable)
636 priv->r->traffic_enable(i, port);
637
638 priv->ports[i].pm |= 1ULL << port;
639 port_bitmap |= 1ULL << i;
640 }
641 }
642
643 /* Add all other ports to this port matrix. */
644 if (priv->ports[port].enable) {
645 priv->r->traffic_enable(priv->cpu_port, port);
646 v = priv->r->traffic_get(port);
647 v |= port_bitmap;
648 priv->r->traffic_set(port, v);
649 }
650 priv->ports[port].pm |= port_bitmap;
651 mutex_unlock(&priv->reg_mutex);
652
653 return 0;
654 }
655
656 static void rtl83xx_port_bridge_leave(struct dsa_switch *ds, int port,
657 struct net_device *bridge)
658 {
659 struct rtl838x_switch_priv *priv = ds->priv;
660 u64 port_bitmap = 1ULL << priv->cpu_port, v;
661 int i;
662
663 pr_debug("%s %x: %d", __func__, (u32)priv, port);
664 mutex_lock(&priv->reg_mutex);
665 for (i = 0; i < ds->num_ports; i++) {
666 /* Remove this port from the port matrix of the other ports
667 * in the same bridge. If the port is disabled, port matrix
668 * is kept and not being setup until the port becomes enabled.
669 * And the other port's port matrix cannot be broken when the
670 * other port is still a VLAN-aware port.
671 */
672 if (dsa_is_user_port(ds, i) && i != port) {
673 if (dsa_to_port(ds, i)->bridge_dev != bridge)
674 continue;
675 if (priv->ports[i].enable)
676 priv->r->traffic_disable(i, port);
677
678 priv->ports[i].pm |= 1ULL << port;
679 port_bitmap &= ~BIT_ULL(i);
680 }
681 }
682
683 /* Add all other ports to this port matrix. */
684 if (priv->ports[port].enable) {
685 v = priv->r->traffic_get(port);
686 v |= port_bitmap;
687 priv->r->traffic_set(port, v);
688 }
689 priv->ports[port].pm &= ~port_bitmap;
690
691 mutex_unlock(&priv->reg_mutex);
692 }
693
694 void rtl83xx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
695 {
696 u32 msti = 0;
697 u32 port_state[4];
698 int index, bit;
699 int pos = port;
700 struct rtl838x_switch_priv *priv = ds->priv;
701 int n = priv->port_width << 1;
702
703 /* Ports above or equal CPU port can never be configured */
704 if (port >= priv->cpu_port)
705 return;
706
707 mutex_lock(&priv->reg_mutex);
708
709 /* For the RTL839x and following, the bits are left-aligned, 838x and 930x
710 * have 64 bit fields, 839x and 931x have 128 bit fields
711 */
712 if (priv->family_id == RTL8390_FAMILY_ID)
713 pos += 12;
714 if (priv->family_id == RTL9300_FAMILY_ID)
715 pos += 3;
716 if (priv->family_id == RTL9310_FAMILY_ID)
717 pos += 8;
718
719 index = n - (pos >> 4) - 1;
720 bit = (pos << 1) % 32;
721
722 priv->r->stp_get(priv, msti, port_state);
723
724 pr_debug("Current state, port %d: %d\n", port, (port_state[index] >> bit) & 3);
725 port_state[index] &= ~(3 << bit);
726
727 switch (state) {
728 case BR_STATE_DISABLED: /* 0 */
729 port_state[index] |= (0 << bit);
730 break;
731 case BR_STATE_BLOCKING: /* 4 */
732 case BR_STATE_LISTENING: /* 1 */
733 port_state[index] |= (1 << bit);
734 break;
735 case BR_STATE_LEARNING: /* 2 */
736 port_state[index] |= (2 << bit);
737 break;
738 case BR_STATE_FORWARDING: /* 3*/
739 port_state[index] |= (3 << bit);
740 default:
741 break;
742 }
743
744 priv->r->stp_set(priv, msti, port_state);
745
746 mutex_unlock(&priv->reg_mutex);
747 }
748
749 void rtl83xx_fast_age(struct dsa_switch *ds, int port)
750 {
751 struct rtl838x_switch_priv *priv = ds->priv;
752 int s = priv->family_id == RTL8390_FAMILY_ID ? 2 : 0;
753
754 pr_debug("FAST AGE port %d\n", port);
755 mutex_lock(&priv->reg_mutex);
756 /* RTL838X_L2_TBL_FLUSH_CTRL register bits, 839x has 1 bit larger
757 * port fields:
758 * 0-4: Replacing port
759 * 5-9: Flushed/replaced port
760 * 10-21: FVID
761 * 22: Entry types: 1: dynamic, 0: also static
762 * 23: Match flush port
763 * 24: Match FVID
764 * 25: Flush (0) or replace (1) L2 entries
765 * 26: Status of action (1: Start, 0: Done)
766 */
767 sw_w32(1 << (26 + s) | 1 << (23 + s) | port << (5 + (s / 2)), priv->r->l2_tbl_flush_ctrl);
768
769 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(26 + s));
770
771 mutex_unlock(&priv->reg_mutex);
772 }
773
774 void rtl930x_fast_age(struct dsa_switch *ds, int port)
775 {
776 struct rtl838x_switch_priv *priv = ds->priv;
777
778 pr_debug("FAST AGE port %d\n", port);
779 mutex_lock(&priv->reg_mutex);
780 sw_w32(port << 11, RTL930X_L2_TBL_FLUSH_CTRL + 4);
781
782 sw_w32(BIT(26) | BIT(30), RTL930X_L2_TBL_FLUSH_CTRL);
783
784 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(30));
785
786 mutex_unlock(&priv->reg_mutex);
787 }
788
789 static int rtl83xx_vlan_filtering(struct dsa_switch *ds, int port,
790 bool vlan_filtering)
791 {
792 struct rtl838x_switch_priv *priv = ds->priv;
793
794 pr_debug("%s: port %d\n", __func__, port);
795 mutex_lock(&priv->reg_mutex);
796
797 if (vlan_filtering) {
798 /* Enable ingress and egress filtering
799 * The VLAN_PORT_IGR_FILTER register uses 2 bits for each port to define
800 * the filter action:
801 * 0: Always Forward
802 * 1: Drop packet
803 * 2: Trap packet to CPU port
804 * The Egress filter used 1 bit per state (0: DISABLED, 1: ENABLED)
805 */
806 if (port != priv->cpu_port)
807 sw_w32_mask(0b10 << ((port % 16) << 1), 0b01 << ((port % 16) << 1),
808 priv->r->vlan_port_igr_filter + ((port >> 5) << 2));
809 sw_w32_mask(0, BIT(port % 32), priv->r->vlan_port_egr_filter + ((port >> 4) << 2));
810 } else {
811 /* Disable ingress and egress filtering */
812 if (port != priv->cpu_port)
813 sw_w32_mask(0b11 << ((port % 16) << 1), 0,
814 priv->r->vlan_port_igr_filter + ((port >> 5) << 2));
815 sw_w32_mask(BIT(port % 32), 0, priv->r->vlan_port_egr_filter + ((port >> 4) << 2));
816 }
817
818 /* Do we need to do something to the CPU-Port, too? */
819 mutex_unlock(&priv->reg_mutex);
820
821 return 0;
822 }
823
824 static int rtl83xx_vlan_prepare(struct dsa_switch *ds, int port,
825 const struct switchdev_obj_port_vlan *vlan)
826 {
827 struct rtl838x_vlan_info info;
828 struct rtl838x_switch_priv *priv = ds->priv;
829
830 pr_info("%s: port %d\n", __func__, port);
831
832 mutex_lock(&priv->reg_mutex);
833
834 priv->r->vlan_profile_dump(1);
835 priv->r->vlan_tables_read(1, &info);
836
837 pr_info("Tagged ports %llx, untag %llx, prof %x, MC# %d, UC# %d, FID %x\n",
838 info.tagged_ports, info.untagged_ports, info.profile_id,
839 info.hash_mc_fid, info.hash_uc_fid, info.fid);
840
841 priv->r->vlan_set_untagged(1, info.untagged_ports);
842 pr_debug("SET: Untagged ports, VLAN %d: %llx\n", 1, info.untagged_ports);
843
844 priv->r->vlan_set_tagged(1, &info);
845 pr_debug("SET: Tagged ports, VLAN %d: %llx\n", 1, info.tagged_ports);
846
847 mutex_unlock(&priv->reg_mutex);
848 return 0;
849 }
850
851 static void rtl83xx_vlan_add(struct dsa_switch *ds, int port,
852 const struct switchdev_obj_port_vlan *vlan)
853 {
854 struct rtl838x_vlan_info info;
855 struct rtl838x_switch_priv *priv = ds->priv;
856 int v;
857
858 pr_info("%s port %d, vid_end %d, vid_end %d, flags %x\n", __func__,
859 port, vlan->vid_begin, vlan->vid_end, vlan->flags);
860
861 if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) {
862 dev_err(priv->dev, "VLAN out of range: %d - %d",
863 vlan->vid_begin, vlan->vid_end);
864 return;
865 }
866
867 mutex_lock(&priv->reg_mutex);
868
869 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) {
870 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
871 if (!v)
872 continue;
873 /* Set both inner and outer PVID of the port */
874 sw_w32((v << 16) | v << 2, priv->r->vlan_port_pb + (port << 2));
875 priv->ports[port].pvid = vlan->vid_end;
876 }
877 }
878
879 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
880 if (!v)
881 continue;
882
883 /* Get port memberships of this vlan */
884 priv->r->vlan_tables_read(v, &info);
885
886 /* new VLAN? */
887 if (!info.tagged_ports) {
888 info.fid = 0;
889 info.hash_mc_fid = false;
890 info.hash_uc_fid = false;
891 info.profile_id = 0;
892 }
893
894 /* sanitize untagged_ports - must be a subset */
895 if (info.untagged_ports & ~info.tagged_ports)
896 info.untagged_ports = 0;
897
898 info.tagged_ports |= BIT_ULL(port);
899 if (vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED)
900 info.untagged_ports |= BIT_ULL(port);
901
902 priv->r->vlan_set_untagged(v, info.untagged_ports);
903 pr_info("Untagged ports, VLAN %d: %llx\n", v, info.untagged_ports);
904
905 priv->r->vlan_set_tagged(v, &info);
906 pr_info("Tagged ports, VLAN %d: %llx\n", v, info.tagged_ports);
907 }
908
909 mutex_unlock(&priv->reg_mutex);
910 }
911
912 static int rtl83xx_vlan_del(struct dsa_switch *ds, int port,
913 const struct switchdev_obj_port_vlan *vlan)
914 {
915 struct rtl838x_vlan_info info;
916 struct rtl838x_switch_priv *priv = ds->priv;
917 int v;
918 u16 pvid;
919
920 pr_debug("%s: port %d, vid_end %d, vid_end %d, flags %x\n", __func__,
921 port, vlan->vid_begin, vlan->vid_end, vlan->flags);
922
923 if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) {
924 dev_err(priv->dev, "VLAN out of range: %d - %d",
925 vlan->vid_begin, vlan->vid_end);
926 return -ENOTSUPP;
927 }
928
929 mutex_lock(&priv->reg_mutex);
930 pvid = priv->ports[port].pvid;
931
932 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
933 /* Reset to default if removing the current PVID */
934 if (v == pvid)
935 sw_w32(0, priv->r->vlan_port_pb + (port << 2));
936
937 /* Get port memberships of this vlan */
938 priv->r->vlan_tables_read(v, &info);
939
940 /* remove port from both tables */
941 info.untagged_ports &= (~BIT_ULL(port));
942 /* always leave vid 1 */
943 if (v != 1)
944 info.tagged_ports &= (~BIT_ULL(port));
945
946 priv->r->vlan_set_untagged(v, info.untagged_ports);
947 pr_debug("Untagged ports, VLAN %d: %llx\n", v, info.untagged_ports);
948
949 priv->r->vlan_set_tagged(v, &info);
950 pr_debug("Tagged ports, VLAN %d: %llx\n", v, info.tagged_ports);
951 }
952 mutex_unlock(&priv->reg_mutex);
953
954 return 0;
955 }
956
957 static int rtl83xx_port_fdb_add(struct dsa_switch *ds, int port,
958 const unsigned char *addr, u16 vid)
959 {
960 struct rtl838x_switch_priv *priv = ds->priv;
961 u64 mac = ether_addr_to_u64(addr);
962 u32 key = rtl83xx_hash_key(priv, mac, vid);
963 struct rtl838x_l2_entry e;
964 u32 r[3];
965 u64 entry;
966 int idx = -1, err = 0, i;
967
968 mutex_lock(&priv->reg_mutex);
969 for (i = 0; i < 4; i++) {
970 entry = priv->r->read_l2_entry_using_hash(key, i, &e);
971 if (!e.valid) {
972 idx = (key << 2) | i;
973 break;
974 }
975 if ((entry & 0x0fffffffffffffffULL) == ((mac << 12) | vid)) {
976 idx = (key << 2) | i;
977 break;
978 }
979 }
980 if (idx >= 0) {
981 r[0] = 3 << 17 | port << 12; // Aging and port
982 r[0] |= vid;
983 r[1] = mac >> 16;
984 r[2] = (mac & 0xffff) << 12; /* rvid = 0 */
985 rtl83xx_write_hash(idx, r);
986 goto out;
987 }
988
989 /* Hash buckets full, try CAM */
990 for (i = 0; i < 64; i++) {
991 entry = priv->r->read_cam(i, &e);
992 if (!e.valid) {
993 if (idx < 0) /* First empty entry? */
994 idx = i;
995 break;
996 } else if ((entry & 0x0fffffffffffffffULL) == ((mac << 12) | vid)) {
997 pr_debug("Found entry in CAM\n");
998 idx = i;
999 break;
1000 }
1001 }
1002 if (idx >= 0) {
1003 r[0] = 3 << 17 | port << 12; // Aging
1004 r[0] |= vid;
1005 r[1] = mac >> 16;
1006 r[2] = (mac & 0xffff) << 12; /* rvid = 0 */
1007 rtl83xx_write_cam(idx, r);
1008 goto out;
1009 }
1010 err = -ENOTSUPP;
1011 out:
1012 mutex_unlock(&priv->reg_mutex);
1013 return err;
1014 }
1015
1016 static int rtl83xx_port_fdb_del(struct dsa_switch *ds, int port,
1017 const unsigned char *addr, u16 vid)
1018 {
1019 struct rtl838x_switch_priv *priv = ds->priv;
1020 u64 mac = ether_addr_to_u64(addr);
1021 u32 key = rtl83xx_hash_key(priv, mac, vid);
1022 struct rtl838x_l2_entry e;
1023 u32 r[3];
1024 u64 entry;
1025 int idx = -1, err = 0, i;
1026
1027 pr_debug("In %s, mac %llx, vid: %d, key: %x08x\n", __func__, mac, vid, key);
1028 mutex_lock(&priv->reg_mutex);
1029 for (i = 0; i < 4; i++) {
1030 entry = priv->r->read_l2_entry_using_hash(key, i, &e);
1031 if (!e.valid)
1032 continue;
1033 if ((entry & 0x0fffffffffffffffULL) == ((mac << 12) | vid)) {
1034 idx = (key << 2) | i;
1035 break;
1036 }
1037 }
1038
1039 if (idx >= 0) {
1040 r[0] = r[1] = r[2] = 0;
1041 rtl83xx_write_hash(idx, r);
1042 goto out;
1043 }
1044
1045 /* Check CAM for spillover from hash buckets */
1046 for (i = 0; i < 64; i++) {
1047 entry = priv->r->read_cam(i, &e);
1048 if ((entry & 0x0fffffffffffffffULL) == ((mac << 12) | vid)) {
1049 idx = i;
1050 break;
1051 }
1052 }
1053 if (idx >= 0) {
1054 r[0] = r[1] = r[2] = 0;
1055 rtl83xx_write_cam(idx, r);
1056 goto out;
1057 }
1058 err = -ENOENT;
1059 out:
1060 mutex_unlock(&priv->reg_mutex);
1061 return err;
1062 }
1063
1064 static int rtl83xx_port_fdb_dump(struct dsa_switch *ds, int port,
1065 dsa_fdb_dump_cb_t *cb, void *data)
1066 {
1067 struct rtl838x_l2_entry e;
1068 struct rtl838x_switch_priv *priv = ds->priv;
1069 int i;
1070 u32 fid;
1071 u32 pkey;
1072 u64 mac;
1073
1074 mutex_lock(&priv->reg_mutex);
1075
1076 for (i = 0; i < priv->fib_entries; i++) {
1077 priv->r->read_l2_entry_using_hash(i >> 2, i & 0x3, &e);
1078
1079 if (!e.valid)
1080 continue;
1081
1082 if (e.port == port) {
1083 fid = (i & 0x3ff) | (e.rvid & ~0x3ff);
1084 mac = ether_addr_to_u64(&e.mac[0]);
1085 pkey = rtl838x_hash(priv, mac << 12 | fid);
1086 fid = (pkey & 0x3ff) | (fid & ~0x3ff);
1087 pr_debug("-> mac %016llx, fid: %d\n", mac, fid);
1088 cb(e.mac, e.vid, e.is_static, data);
1089 }
1090 }
1091
1092 for (i = 0; i < 64; i++) {
1093 priv->r->read_cam(i, &e);
1094
1095 if (!e.valid)
1096 continue;
1097
1098 if (e.port == port)
1099 cb(e.mac, e.vid, e.is_static, data);
1100 }
1101
1102 mutex_unlock(&priv->reg_mutex);
1103 return 0;
1104 }
1105
1106 static int rtl83xx_port_mirror_add(struct dsa_switch *ds, int port,
1107 struct dsa_mall_mirror_tc_entry *mirror,
1108 bool ingress)
1109 {
1110 /* We support 4 mirror groups, one destination port per group */
1111 int group;
1112 struct rtl838x_switch_priv *priv = ds->priv;
1113 int ctrl_reg, dpm_reg, spm_reg;
1114
1115 pr_debug("In %s\n", __func__);
1116
1117 for (group = 0; group < 4; group++) {
1118 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1119 break;
1120 }
1121 if (group >= 4) {
1122 for (group = 0; group < 4; group++) {
1123 if (priv->mirror_group_ports[group] < 0)
1124 break;
1125 }
1126 }
1127
1128 if (group >= 4)
1129 return -ENOSPC;
1130
1131 ctrl_reg = priv->r->mir_ctrl + group * 4;
1132 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1133 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1134
1135 pr_debug("Using group %d\n", group);
1136 mutex_lock(&priv->reg_mutex);
1137
1138 if (priv->family_id == RTL8380_FAMILY_ID) {
1139 /* Enable mirroring to port across VLANs (bit 11) */
1140 sw_w32(1 << 11 | (mirror->to_local_port << 4) | 1, ctrl_reg);
1141 } else {
1142 /* Enable mirroring to destination port */
1143 sw_w32((mirror->to_local_port << 4) | 1, ctrl_reg);
1144 }
1145
1146 if (ingress && (priv->r->get_port_reg_be(spm_reg) & (1ULL << port))) {
1147 mutex_unlock(&priv->reg_mutex);
1148 return -EEXIST;
1149 }
1150 if ((!ingress) && (priv->r->get_port_reg_be(dpm_reg) & (1ULL << port))) {
1151 mutex_unlock(&priv->reg_mutex);
1152 return -EEXIST;
1153 }
1154
1155 if (ingress)
1156 priv->r->mask_port_reg_be(0, 1ULL << port, spm_reg);
1157 else
1158 priv->r->mask_port_reg_be(0, 1ULL << port, dpm_reg);
1159
1160 priv->mirror_group_ports[group] = mirror->to_local_port;
1161 mutex_unlock(&priv->reg_mutex);
1162 return 0;
1163 }
1164
1165 static void rtl83xx_port_mirror_del(struct dsa_switch *ds, int port,
1166 struct dsa_mall_mirror_tc_entry *mirror)
1167 {
1168 int group = 0;
1169 struct rtl838x_switch_priv *priv = ds->priv;
1170 int ctrl_reg, dpm_reg, spm_reg;
1171
1172 pr_debug("In %s\n", __func__);
1173 for (group = 0; group < 4; group++) {
1174 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1175 break;
1176 }
1177 if (group >= 4)
1178 return;
1179
1180 ctrl_reg = priv->r->mir_ctrl + group * 4;
1181 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1182 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1183
1184 mutex_lock(&priv->reg_mutex);
1185 if (mirror->ingress) {
1186 /* Ingress, clear source port matrix */
1187 priv->r->mask_port_reg_be(1ULL << port, 0, spm_reg);
1188 } else {
1189 /* Egress, clear destination port matrix */
1190 priv->r->mask_port_reg_be(1ULL << port, 0, dpm_reg);
1191 }
1192
1193 if (!(sw_r32(spm_reg) || sw_r32(dpm_reg))) {
1194 priv->mirror_group_ports[group] = -1;
1195 sw_w32(0, ctrl_reg);
1196 }
1197
1198 mutex_unlock(&priv->reg_mutex);
1199 }
1200
1201 int dsa_phy_read(struct dsa_switch *ds, int phy_addr, int phy_reg)
1202 {
1203 u32 val;
1204 u32 offset = 0;
1205 struct rtl838x_switch_priv *priv = ds->priv;
1206
1207 if (phy_addr >= 24 && phy_addr <= 27
1208 && priv->ports[24].phy == PHY_RTL838X_SDS) {
1209 if (phy_addr == 26)
1210 offset = 0x100;
1211 val = sw_r32(RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2)) & 0xffff;
1212 return val;
1213 }
1214
1215 read_phy(phy_addr, 0, phy_reg, &val);
1216 return val;
1217 }
1218
1219 int dsa_phy_write(struct dsa_switch *ds, int phy_addr, int phy_reg, u16 val)
1220 {
1221 u32 offset = 0;
1222 struct rtl838x_switch_priv *priv = ds->priv;
1223
1224 if (phy_addr >= 24 && phy_addr <= 27
1225 && priv->ports[24].phy == PHY_RTL838X_SDS) {
1226 if (phy_addr == 26)
1227 offset = 0x100;
1228 sw_w32(val, RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2));
1229 return 0;
1230 }
1231 return write_phy(phy_addr, 0, phy_reg, val);
1232 }
1233
1234 const struct dsa_switch_ops rtl83xx_switch_ops = {
1235 .get_tag_protocol = rtl83xx_get_tag_protocol,
1236 .setup = rtl83xx_setup,
1237
1238 .phy_read = dsa_phy_read,
1239 .phy_write = dsa_phy_write,
1240
1241 .phylink_validate = rtl83xx_phylink_validate,
1242 .phylink_mac_link_state = rtl83xx_phylink_mac_link_state,
1243 .phylink_mac_config = rtl83xx_phylink_mac_config,
1244 .phylink_mac_link_down = rtl83xx_phylink_mac_link_down,
1245 .phylink_mac_link_up = rtl83xx_phylink_mac_link_up,
1246
1247 .get_strings = rtl83xx_get_strings,
1248 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
1249 .get_sset_count = rtl83xx_get_sset_count,
1250
1251 .port_enable = rtl83xx_port_enable,
1252 .port_disable = rtl83xx_port_disable,
1253
1254 .get_mac_eee = rtl83xx_get_mac_eee,
1255 .set_mac_eee = rtl83xx_set_mac_eee,
1256
1257 .set_ageing_time = rtl83xx_set_l2aging,
1258 .port_bridge_join = rtl83xx_port_bridge_join,
1259 .port_bridge_leave = rtl83xx_port_bridge_leave,
1260 .port_stp_state_set = rtl83xx_port_stp_state_set,
1261 .port_fast_age = rtl83xx_fast_age,
1262
1263 .port_vlan_filtering = rtl83xx_vlan_filtering,
1264 .port_vlan_prepare = rtl83xx_vlan_prepare,
1265 .port_vlan_add = rtl83xx_vlan_add,
1266 .port_vlan_del = rtl83xx_vlan_del,
1267
1268 .port_fdb_add = rtl83xx_port_fdb_add,
1269 .port_fdb_del = rtl83xx_port_fdb_del,
1270 .port_fdb_dump = rtl83xx_port_fdb_dump,
1271
1272 .port_mirror_add = rtl83xx_port_mirror_add,
1273 .port_mirror_del = rtl83xx_port_mirror_del,
1274 };
1275
1276 const struct dsa_switch_ops rtl930x_switch_ops = {
1277 .get_tag_protocol = rtl83xx_get_tag_protocol,
1278 .setup = rtl930x_setup,
1279
1280 .phy_read = dsa_phy_read,
1281 .phy_write = dsa_phy_write,
1282
1283 .phylink_validate = rtl83xx_phylink_validate,
1284 .phylink_mac_link_state = rtl83xx_phylink_mac_link_state,
1285 .phylink_mac_config = rtl83xx_phylink_mac_config,
1286 .phylink_mac_link_down = rtl83xx_phylink_mac_link_down,
1287 .phylink_mac_link_up = rtl83xx_phylink_mac_link_up,
1288
1289 .get_strings = rtl83xx_get_strings,
1290 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
1291 .get_sset_count = rtl83xx_get_sset_count,
1292
1293 .port_enable = rtl83xx_port_enable,
1294 .port_disable = rtl83xx_port_disable,
1295
1296 .set_ageing_time = rtl83xx_set_l2aging,
1297 .port_bridge_join = rtl83xx_port_bridge_join,
1298 .port_bridge_leave = rtl83xx_port_bridge_leave,
1299 .port_stp_state_set = rtl83xx_port_stp_state_set,
1300 .port_fast_age = rtl930x_fast_age,
1301
1302 .port_vlan_filtering = rtl83xx_vlan_filtering,
1303 .port_vlan_prepare = rtl83xx_vlan_prepare,
1304 .port_vlan_add = rtl83xx_vlan_add,
1305 .port_vlan_del = rtl83xx_vlan_del,
1306
1307 .port_fdb_add = rtl83xx_port_fdb_add,
1308 .port_fdb_del = rtl83xx_port_fdb_del,
1309 .port_fdb_dump = rtl83xx_port_fdb_dump,
1310 };
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