target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/debugfs.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2
   3 #include <linux/debugfs.h>
   4 #include <linux/kernel.h>
   5
   6 #include <asm/mach-rtl838x/mach-rtl83xx.h>
   7 #include "rtl83xx.h"
   8
   9 #define RTL838X_DRIVER_NAME "rtl838x"
  10
  11 #define RTL8380_LED_GLB_CTRL                    (0xA000)
  12 #define RTL8380_LED_MODE_SEL                    (0x1004)
  13 #define RTL8380_LED_MODE_CTRL                   (0xA004)
  14 #define RTL8380_LED_P_EN_CTRL                   (0xA008)
  15 #define RTL8380_LED_SW_CTRL                     (0xA00C)
  16 #define RTL8380_LED0_SW_P_EN_CTRL               (0xA010)
  17 #define RTL8380_LED1_SW_P_EN_CTRL               (0xA014)
  18 #define RTL8380_LED2_SW_P_EN_CTRL               (0xA018)
  19 #define RTL8380_LED_SW_P_CTRL(p)                (0xA01C + (((p) << 2)))
  20
  21 #define RTL8390_LED_GLB_CTRL                    (0x00E4)
  22 #define RTL8390_LED_SET_2_3_CTRL                (0x00E8)
  23 #define RTL8390_LED_SET_0_1_CTRL                (0x00EC)
  24 #define RTL8390_LED_COPR_SET_SEL_CTRL(p)        (0x00F0 + (((p >> 4) << 2)))
  25 #define RTL8390_LED_FIB_SET_SEL_CTRL(p)         (0x0100 + (((p >> 4) << 2)))
  26 #define RTL8390_LED_COPR_PMASK_CTRL(p)          (0x0110 + (((p >> 5) << 2)))
  27 #define RTL8390_LED_FIB_PMASK_CTRL(p)           (0x00118 + (((p >> 5) << 2)))
  28 #define RTL8390_LED_COMBO_CTRL(p)               (0x0120 + (((p >> 5) << 2)))
  29 #define RTL8390_LED_SW_CTRL                     (0x0128)
  30 #define RTL8390_LED_SW_P_EN_CTRL(p)             (0x012C + (((p / 10) << 2)))
  31 #define RTL8390_LED_SW_P_CTRL(p)                (0x0144 + (((p) << 2)))
  32
  33 #define RTL838X_MIR_QID_CTRL(grp)               (0xAD44 + (((grp) << 2)))
  34 #define RTL838X_MIR_RSPAN_VLAN_CTRL(grp)        (0xA340 + (((grp) << 2)))
  35 #define RTL838X_MIR_RSPAN_VLAN_CTRL_MAC(grp)    (0xAA70 + (((grp) << 2)))
  36 #define RTL838X_MIR_RSPAN_TX_CTRL               (0xA350)
  37 #define RTL838X_MIR_RSPAN_TX_TAG_RM_CTRL        (0xAA80)
  38 #define RTL838X_MIR_RSPAN_TX_TAG_EN_CTRL        (0xAA84)
  39 #define RTL839X_MIR_RSPAN_VLAN_CTRL(grp)        (0xA340 + (((grp) << 2)))
  40 #define RTL839X_MIR_RSPAN_TX_CTRL               (0x69b0)
  41 #define RTL839X_MIR_RSPAN_TX_TAG_RM_CTRL        (0x2550)
  42 #define RTL839X_MIR_RSPAN_TX_TAG_EN_CTRL        (0x2554)
  43 #define RTL839X_MIR_SAMPLE_RATE_CTRL                (0x2558)
  44
  45 int rtl83xx_port_get_stp_state(struct rtl838x_switch_priv *priv, int port);
  46 void rtl83xx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state);
  47 void rtl83xx_fast_age(struct dsa_switch *ds, int port);
  48 u32 rtl838x_get_egress_rate(struct rtl838x_switch_priv *priv, int port);
  49 u32 rtl839x_get_egress_rate(struct rtl838x_switch_priv *priv, int port);
  50 int rtl838x_set_egress_rate(struct rtl838x_switch_priv *priv, int port, u32 rate);
  51 int rtl839x_set_egress_rate(struct rtl838x_switch_priv *priv, int port, u32 rate);
  52
  53 static ssize_t rtl838x_common_read(char __user *buffer, size_t count,
  54                                         loff_t *ppos, unsigned int value)
  55 {
  56         char *buf;
  57         ssize_t len;
  58
  59         if (*ppos != 0)
  60                 return 0;
  61
  62         buf = kasprintf(GFP_KERNEL, "0x%08x\n", value);
  63         if (!buf)
  64                 return -ENOMEM;
  65
  66         if (count < strlen(buf)) {
  67                 kfree(buf);
  68                 return -ENOSPC;
  69         }
  70
  71         len = simple_read_from_buffer(buffer, count, ppos, buf, strlen(buf));
  72         kfree(buf);
  73
  74         return len;
  75 }
  76
  77 static ssize_t rtl838x_common_write(const char __user *buffer, size_t count,
  78                                  loff_t *ppos, unsigned int *value)
  79 {
  80         char b[32];
  81         ssize_t len;
  82         int ret;
  83
  84         if (*ppos != 0)
  85                 return -EINVAL;
  86
  87         if (count >= sizeof(b))
  88                 return -ENOSPC;
  89
  90         len = simple_write_to_buffer(b, sizeof(b) - 1, ppos,
  91                                      buffer, count);
  92         if (len < 0)
  93                 return len;
  94
  95         b[len] = '\0';
  96         ret = kstrtouint(b, 16, value);
  97         if (ret)
  98                 return -EIO;
  99
 100         return len;
 101 }
 102
 103 static ssize_t stp_state_read(struct file *filp, char __user *buffer, size_t count,
 104                              loff_t *ppos)
 105 {
 106         struct rtl838x_port *p = filp->private_data;
 107         struct dsa_switch *ds = p->dp->ds;
 108         int value = rtl83xx_port_get_stp_state(ds->priv, p->dp->index);
 109
 110         if (value < 0)
 111                 return -EINVAL;
 112
 113         return rtl838x_common_read(buffer, count, ppos, (u32)value);
 114 }
 115
 116 static ssize_t stp_state_write(struct file *filp, const char __user *buffer,
 117                                 size_t count, loff_t *ppos)
 118 {
 119         struct rtl838x_port *p = filp->private_data;
 120         u32 value;
 121         size_t res = rtl838x_common_write(buffer, count, ppos, &value);
 122         if (res < 0)
 123                 return res;
 124
 125         rtl83xx_port_stp_state_set(p->dp->ds, p->dp->index, (u8)value);
 126
 127         return res;
 128 }
 129
 130 static const struct file_operations stp_state_fops = {
 131         .owner = THIS_MODULE,
 132         .open = simple_open,
 133         .read = stp_state_read,
 134         .write = stp_state_write,
 135 };
 136
 137 static ssize_t age_out_read(struct file *filp, char __user *buffer, size_t count,
 138                              loff_t *ppos)
 139 {
 140         struct rtl838x_port *p = filp->private_data;
 141         struct dsa_switch *ds = p->dp->ds;
 142         struct rtl838x_switch_priv *priv = ds->priv;
 143         int value = sw_r32(priv->r->l2_port_aging_out);
 144
 145         if (value < 0)
 146                 return -EINVAL;
 147
 148         return rtl838x_common_read(buffer, count, ppos, (u32)value);
 149 }
 150
 151 static ssize_t age_out_write(struct file *filp, const char __user *buffer,
 152                                 size_t count, loff_t *ppos)
 153 {
 154         struct rtl838x_port *p = filp->private_data;
 155         u32 value;
 156         size_t res = rtl838x_common_write(buffer, count, ppos, &value);
 157         if (res < 0)
 158                 return res;
 159
 160         rtl83xx_fast_age(p->dp->ds, p->dp->index);
 161
 162         return res;
 163 }
 164
 165 static const struct file_operations age_out_fops = {
 166         .owner = THIS_MODULE,
 167         .open = simple_open,
 168         .read = age_out_read,
 169         .write = age_out_write,
 170 };
 171
 172 static ssize_t port_egress_rate_read(struct file *filp, char __user *buffer, size_t count,
 173                                 loff_t *ppos)
 174 {
 175         struct rtl838x_port *p = filp->private_data;
 176         struct dsa_switch *ds = p->dp->ds;
 177         struct rtl838x_switch_priv *priv = ds->priv;
 178         int value;
 179         if (priv->family_id == RTL8380_FAMILY_ID)
 180                 value = rtl838x_get_egress_rate(priv, p->dp->index);
 181         else
 182                 value = rtl839x_get_egress_rate(priv, p->dp->index);
 183
 184         if (value < 0)
 185                 return -EINVAL;
 186
 187         return rtl838x_common_read(buffer, count, ppos, (u32)value);
 188 }
 189
 190 static ssize_t port_egress_rate_write(struct file *filp, const char __user *buffer,
 191                                 size_t count, loff_t *ppos)
 192 {
 193         struct rtl838x_port *p = filp->private_data;
 194         struct dsa_switch *ds = p->dp->ds;
 195         struct rtl838x_switch_priv *priv = ds->priv;
 196         u32 value;
 197         size_t res = rtl838x_common_write(buffer, count, ppos, &value);
 198         if (res < 0)
 199                 return res;
 200
 201         if (priv->family_id == RTL8380_FAMILY_ID)
 202                 rtl838x_set_egress_rate(priv, p->dp->index, value);
 203         else
 204                 rtl839x_set_egress_rate(priv, p->dp->index, value);
 205
 206         return res;
 207 }
 208
 209 static const struct file_operations port_egress_fops = {
 210         .owner = THIS_MODULE,
 211         .open = simple_open,
 212         .read = port_egress_rate_read,
 213         .write = port_egress_rate_write,
 214 };
 215
 216
 217 static const struct debugfs_reg32 port_ctrl_regs[] = {
 218         { .name = "port_isolation", .offset = RTL838X_PORT_ISO_CTRL(0), },
 219         { .name = "mac_force_mode", .offset = RTL838X_MAC_FORCE_MODE_CTRL, },
 220 };
 221
 222 void rtl838x_dbgfs_cleanup(struct rtl838x_switch_priv *priv)
 223 {
 224         debugfs_remove_recursive(priv->dbgfs_dir);
 225
 226 //      kfree(priv->dbgfs_entries);
 227 }
 228
 229 static int rtl838x_dbgfs_port_init(struct dentry *parent, struct rtl838x_switch_priv *priv,
 230                                    int port)
 231 {
 232         struct dentry *port_dir;
 233         struct debugfs_regset32 *port_ctrl_regset;
 234
 235         port_dir = debugfs_create_dir(priv->ports[port].dp->name, parent);
 236
 237         if (priv->family_id == RTL8380_FAMILY_ID) {
 238                 debugfs_create_x32("storm_rate_uc", 0644, port_dir,
 239                                 (u32 *)(RTL838X_SW_BASE + RTL838X_STORM_CTRL_PORT_UC(port)));
 240
 241                 debugfs_create_x32("storm_rate_mc", 0644, port_dir,
 242                                 (u32 *)(RTL838X_SW_BASE + RTL838X_STORM_CTRL_PORT_MC(port)));
 243
 244                 debugfs_create_x32("storm_rate_bc", 0644, port_dir,
 245                                 (u32 *)(RTL838X_SW_BASE + RTL838X_STORM_CTRL_PORT_BC(port)));
 246
 247                 debugfs_create_x32("vlan_port_tag_sts_ctrl", 0644, port_dir,
 248                                 (u32 *)(RTL838X_SW_BASE + RTL838X_VLAN_PORT_TAG_STS_CTRL
 249                                 + (port << 2)));
 250         } else {
 251                 debugfs_create_x32("storm_rate_uc", 0644, port_dir,
 252                                 (u32 *)(RTL838X_SW_BASE + RTL839X_STORM_CTRL_PORT_UC_0(port)));
 253
 254                 debugfs_create_x32("storm_rate_mc", 0644, port_dir,
 255                                 (u32 *)(RTL838X_SW_BASE + RTL839X_STORM_CTRL_PORT_MC_0(port)));
 256
 257                 debugfs_create_x32("storm_rate_bc", 0644, port_dir,
 258                                 (u32 *)(RTL838X_SW_BASE + RTL839X_STORM_CTRL_PORT_BC_0(port)));
 259
 260                 debugfs_create_x32("vlan_port_tag_sts_ctrl", 0644, port_dir,
 261                                 (u32 *)(RTL838X_SW_BASE + RTL839X_VLAN_PORT_TAG_STS_CTRL
 262                                 + (port << 2)));
 263         }
 264
 265         debugfs_create_u32("id", 0444, port_dir, (u32 *)&priv->ports[port].dp->index);
 266
 267         port_ctrl_regset = devm_kzalloc(priv->dev, sizeof(*port_ctrl_regset), GFP_KERNEL);
 268         if (!port_ctrl_regset)
 269                 return -ENOMEM;
 270
 271         port_ctrl_regset->regs = port_ctrl_regs;
 272         port_ctrl_regset->nregs = ARRAY_SIZE(port_ctrl_regs);
 273         port_ctrl_regset->base = (void *)(RTL838X_SW_BASE + (port << 2));
 274         debugfs_create_regset32("port_ctrl", 0400, port_dir, port_ctrl_regset);
 275
 276         debugfs_create_file("stp_state", 0600, port_dir, &priv->ports[port], &stp_state_fops);
 277         debugfs_create_file("age_out", 0600, port_dir, &priv->ports[port], &age_out_fops);
 278         debugfs_create_file("port_egress_rate", 0600, port_dir, &priv->ports[port],
 279                             &port_egress_fops);
 280         return 0;
 281 }
 282
 283 static int rtl838x_dbgfs_leds(struct dentry *parent, struct rtl838x_switch_priv *priv)
 284 {
 285         struct dentry *led_dir;
 286         int p;
 287         char led_sw_p_ctrl_name[20];
 288         char port_led_name[20];
 289
 290         led_dir = debugfs_create_dir("led", parent);
 291
 292         if (priv->family_id == RTL8380_FAMILY_ID) {
 293                 debugfs_create_x32("led_glb_ctrl", 0644, led_dir,
 294                                 (u32 *)(RTL838X_SW_BASE + RTL8380_LED_GLB_CTRL));
 295                 debugfs_create_x32("led_mode_sel", 0644, led_dir,
 296                                 (u32 *)(RTL838X_SW_BASE + RTL8380_LED_MODE_SEL));
 297                 debugfs_create_x32("led_mode_ctrl", 0644, led_dir,
 298                                 (u32 *)(RTL838X_SW_BASE + RTL8380_LED_MODE_CTRL));
 299                 debugfs_create_x32("led_p_en_ctrl", 0644, led_dir,
 300                                 (u32 *)(RTL838X_SW_BASE + RTL8380_LED_P_EN_CTRL));
 301                 debugfs_create_x32("led_sw_ctrl", 0644, led_dir,
 302                                 (u32 *)(RTL838X_SW_BASE + RTL8380_LED_SW_CTRL));
 303                 debugfs_create_x32("led0_sw_p_en_ctrl", 0644, led_dir,
 304                                 (u32 *)(RTL838X_SW_BASE + RTL8380_LED0_SW_P_EN_CTRL));
 305                 debugfs_create_x32("led1_sw_p_en_ctrl", 0644, led_dir,
 306                                 (u32 *)(RTL838X_SW_BASE + RTL8380_LED1_SW_P_EN_CTRL));
 307                 debugfs_create_x32("led2_sw_p_en_ctrl", 0644, led_dir,
 308                                 (u32 *)(RTL838X_SW_BASE + RTL8380_LED2_SW_P_EN_CTRL));
 309                 for (p = 0; p < 28; p++) {
 310                         snprintf(led_sw_p_ctrl_name, sizeof(led_sw_p_ctrl_name),
 311                                  "led_sw_p_ctrl.%02d", p);
 312                         debugfs_create_x32(led_sw_p_ctrl_name, 0644, led_dir,
 313                                 (u32 *)(RTL838X_SW_BASE + RTL8380_LED_SW_P_CTRL(p)));
 314                 }
 315         } else if (priv->family_id == RTL8390_FAMILY_ID) {
 316                 debugfs_create_x32("led_glb_ctrl", 0644, led_dir,
 317                                 (u32 *)(RTL838X_SW_BASE + RTL8390_LED_GLB_CTRL));
 318                 debugfs_create_x32("led_set_2_3", 0644, led_dir,
 319                                 (u32 *)(RTL838X_SW_BASE + RTL8390_LED_SET_2_3_CTRL));
 320                 debugfs_create_x32("led_set_0_1", 0644, led_dir,
 321                                 (u32 *)(RTL838X_SW_BASE + RTL8390_LED_SET_0_1_CTRL));
 322                 for (p = 0; p < 4; p++) {
 323                         snprintf(port_led_name, sizeof(port_led_name), "led_copr_set_sel.%1d", p);
 324                         debugfs_create_x32(port_led_name, 0644, led_dir,
 325                                 (u32 *)(RTL838X_SW_BASE + RTL8390_LED_COPR_SET_SEL_CTRL(p << 4)));
 326                         snprintf(port_led_name, sizeof(port_led_name), "led_fib_set_sel.%1d", p);
 327                         debugfs_create_x32(port_led_name, 0644, led_dir,
 328                                 (u32 *)(RTL838X_SW_BASE + RTL8390_LED_FIB_SET_SEL_CTRL(p << 4)));
 329                 }
 330                 debugfs_create_x32("led_copr_pmask_ctrl_0", 0644, led_dir,
 331                                 (u32 *)(RTL838X_SW_BASE + RTL8390_LED_COPR_PMASK_CTRL(0)));
 332                 debugfs_create_x32("led_copr_pmask_ctrl_1", 0644, led_dir,
 333                                 (u32 *)(RTL838X_SW_BASE + RTL8390_LED_COPR_PMASK_CTRL(32)));
 334                 debugfs_create_x32("led_fib_pmask_ctrl_0", 0644, led_dir,
 335                                 (u32 *)(RTL838X_SW_BASE + RTL8390_LED_FIB_PMASK_CTRL(0)));
 336                 debugfs_create_x32("led_fib_pmask_ctrl_1", 0644, led_dir,
 337                                 (u32 *)(RTL838X_SW_BASE + RTL8390_LED_FIB_PMASK_CTRL(32)));
 338                 debugfs_create_x32("led_combo_ctrl_0", 0644, led_dir,
 339                                 (u32 *)(RTL838X_SW_BASE + RTL8390_LED_COMBO_CTRL(0)));
 340                 debugfs_create_x32("led_combo_ctrl_1", 0644, led_dir,
 341                                 (u32 *)(RTL838X_SW_BASE + RTL8390_LED_COMBO_CTRL(32)));
 342                 debugfs_create_x32("led_sw_ctrl", 0644, led_dir,
 343                                 (u32 *)(RTL838X_SW_BASE + RTL8390_LED_SW_CTRL));
 344                 for (p = 0; p < 5; p++) {
 345                         snprintf(port_led_name, sizeof(port_led_name), "led_sw_p_en_ctrl.%1d", p);
 346                         debugfs_create_x32(port_led_name, 0644, led_dir,
 347                                 (u32 *)(RTL838X_SW_BASE + RTL8390_LED_SW_P_EN_CTRL(p * 10)));
 348                 }
 349                 for (p = 0; p < 28; p++) {
 350                         snprintf(port_led_name, sizeof(port_led_name), "led_sw_p_ctrl.%02d", p);
 351                         debugfs_create_x32(port_led_name, 0644, led_dir,
 352                                 (u32 *)(RTL838X_SW_BASE + RTL8390_LED_SW_P_CTRL(p)));
 353                 }
 354         }
 355         return 0;
 356 }
 357
 358 void rtl838x_dbgfs_init(struct rtl838x_switch_priv *priv)
 359 {
 360         struct dentry *rtl838x_dir;
 361         struct dentry *port_dir;
 362         struct dentry *mirror_dir;
 363         struct debugfs_regset32 *port_ctrl_regset;
 364         int ret, i;
 365         char lag_name[10];
 366         char mirror_name[10];
 367
 368         pr_info("%s called\n", __func__);
 369         rtl838x_dir = debugfs_lookup(RTL838X_DRIVER_NAME, NULL);
 370         if (!rtl838x_dir)
 371                 rtl838x_dir = debugfs_create_dir(RTL838X_DRIVER_NAME, NULL);
 372
 373         priv->dbgfs_dir = rtl838x_dir;
 374
 375         debugfs_create_u32("soc", 0444, rtl838x_dir,
 376                            (u32 *)(RTL838X_SW_BASE + RTL838X_MODEL_NAME_INFO));
 377
 378         /* Create one directory per port */
 379         for (i = 0; i < priv->cpu_port; i++) {
 380                 if (priv->ports[i].phy) {
 381                         ret = rtl838x_dbgfs_port_init(rtl838x_dir, priv, i);
 382                         if (ret)
 383                                 goto err;
 384                 }
 385         }
 386
 387         /* Create directory for CPU-port */
 388         port_dir = debugfs_create_dir("cpu_port", rtl838x_dir);
 389         port_ctrl_regset = devm_kzalloc(priv->dev, sizeof(*port_ctrl_regset), GFP_KERNEL);
 390         if (!port_ctrl_regset) {
 391                 ret = -ENOMEM;
 392                 goto err;
 393         }
 394
 395         port_ctrl_regset->regs = port_ctrl_regs;
 396         port_ctrl_regset->nregs = ARRAY_SIZE(port_ctrl_regs);
 397         port_ctrl_regset->base = (void *)(RTL838X_SW_BASE + (priv->cpu_port << 2));
 398         debugfs_create_regset32("port_ctrl", 0400, port_dir, port_ctrl_regset);
 399         debugfs_create_u8("id", 0444, port_dir, &priv->cpu_port);
 400
 401         /* Create entries for LAGs */
 402         for (i = 0; i < priv->n_lags; i++) {
 403                 snprintf(lag_name, sizeof(lag_name), "lag.%02d", i);
 404                 if (priv->family_id == RTL8380_FAMILY_ID)
 405                         debugfs_create_x32(lag_name, 0644, rtl838x_dir,
 406                                 (u32 *)(RTL838X_SW_BASE + priv->r->trk_mbr_ctr(i)));
 407                 else
 408                         debugfs_create_x64(lag_name, 0644, rtl838x_dir,
 409                                 (u64 *)(RTL838X_SW_BASE + priv->r->trk_mbr_ctr(i)));
 410         }
 411
 412         /* Create directories for mirror groups */
 413         for (i = 0; i < 4; i++) {
 414                 snprintf(mirror_name, sizeof(mirror_name), "mirror.%1d", i);
 415                 mirror_dir = debugfs_create_dir(mirror_name, rtl838x_dir);
 416                 if (priv->family_id == RTL8380_FAMILY_ID) {
 417                         debugfs_create_x32("ctrl", 0644, mirror_dir,
 418                                 (u32 *)(RTL838X_SW_BASE + RTL838X_MIR_CTRL + i * 4));
 419                         debugfs_create_x32("ingress_pm", 0644, mirror_dir,
 420                                 (u32 *)(RTL838X_SW_BASE + priv->r->mir_spm + i * 4));
 421                         debugfs_create_x32("egress_pm", 0644, mirror_dir,
 422                                 (u32 *)(RTL838X_SW_BASE + priv->r->mir_dpm + i * 4));
 423                         debugfs_create_x32("qid", 0644, mirror_dir,
 424                                 (u32 *)(RTL838X_SW_BASE + RTL838X_MIR_QID_CTRL(i)));
 425                         debugfs_create_x32("rspan_vlan", 0644, mirror_dir,
 426                                 (u32 *)(RTL838X_SW_BASE + RTL838X_MIR_RSPAN_VLAN_CTRL(i)));
 427                         debugfs_create_x32("rspan_vlan_mac", 0644, mirror_dir,
 428                                 (u32 *)(RTL838X_SW_BASE + RTL838X_MIR_RSPAN_VLAN_CTRL_MAC(i)));
 429                         debugfs_create_x32("rspan_tx", 0644, mirror_dir,
 430                                 (u32 *)(RTL838X_SW_BASE + RTL838X_MIR_RSPAN_TX_CTRL));
 431                         debugfs_create_x32("rspan_tx_tag_rm", 0644, mirror_dir,
 432                                 (u32 *)(RTL838X_SW_BASE + RTL838X_MIR_RSPAN_TX_TAG_RM_CTRL));
 433                         debugfs_create_x32("rspan_tx_tag_en", 0644, mirror_dir,
 434                                 (u32 *)(RTL838X_SW_BASE + RTL838X_MIR_RSPAN_TX_TAG_EN_CTRL));
 435                 } else {
 436                         debugfs_create_x32("ctrl", 0644, mirror_dir,
 437                                 (u32 *)(RTL838X_SW_BASE + RTL839X_MIR_CTRL + i * 4));
 438                         debugfs_create_x64("ingress_pm", 0644, mirror_dir,
 439                                 (u64 *)(RTL838X_SW_BASE + priv->r->mir_spm + i * 8));
 440                         debugfs_create_x64("egress_pm", 0644, mirror_dir,
 441                                 (u64 *)(RTL838X_SW_BASE + priv->r->mir_dpm + i * 8));
 442                         debugfs_create_x32("rspan_vlan", 0644, mirror_dir,
 443                                 (u32 *)(RTL838X_SW_BASE + RTL839X_MIR_RSPAN_VLAN_CTRL(i)));
 444                         debugfs_create_x32("rspan_tx", 0644, mirror_dir,
 445                                 (u32 *)(RTL838X_SW_BASE + RTL839X_MIR_RSPAN_TX_CTRL));
 446                         debugfs_create_x32("rspan_tx_tag_rm", 0644, mirror_dir,
 447                                 (u32 *)(RTL838X_SW_BASE + RTL839X_MIR_RSPAN_TX_TAG_RM_CTRL));
 448                         debugfs_create_x32("rspan_tx_tag_en", 0644, mirror_dir,
 449                                 (u32 *)(RTL838X_SW_BASE + RTL839X_MIR_RSPAN_TX_TAG_EN_CTRL));
 450                         debugfs_create_x64("sample_rate", 0644, mirror_dir,
 451                                 (u64 *)(RTL838X_SW_BASE + RTL839X_MIR_SAMPLE_RATE_CTRL));
 452                 }
 453         }
 454
 455         if (priv->family_id == RTL8380_FAMILY_ID)
 456                 debugfs_create_x32("bpdu_flood_mask", 0644, rtl838x_dir,
 457                                 (u32 *)(RTL838X_SW_BASE + priv->r->rma_bpdu_fld_pmask));
 458         else
 459                 debugfs_create_x64("bpdu_flood_mask", 0644, rtl838x_dir,
 460                                 (u64 *)(RTL838X_SW_BASE + priv->r->rma_bpdu_fld_pmask));
 461
 462         if (priv->family_id == RTL8380_FAMILY_ID)
 463                 debugfs_create_x32("vlan_ctrl", 0644, rtl838x_dir,
 464                                 (u32 *)(RTL838X_SW_BASE + RTL838X_VLAN_CTRL));
 465         else
 466                 debugfs_create_x32("vlan_ctrl", 0644, rtl838x_dir,
 467                                 (u32 *)(RTL838X_SW_BASE + RTL839X_VLAN_CTRL));
 468
 469         ret = rtl838x_dbgfs_leds(rtl838x_dir, priv);
 470         if (ret)
 471                 goto err;
 472
 473         return;
 474 err:
 475         rtl838x_dbgfs_cleanup(priv);
 476 }