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realtek: fix link-state interrupt
[openwrt/staging/jow.git] / target / linux / realtek / files-5.4 / drivers / net / dsa / rtl83xx / common.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <linux/of_mdio.h>
4 #include <linux/of_platform.h>
5
6 #include <asm/mach-rtl838x/mach-rtl83xx.h>
7 #include "rtl83xx.h"
8
9 extern struct rtl83xx_soc_info soc_info;
10
11 extern const struct rtl838x_reg rtl838x_reg;
12 extern const struct rtl838x_reg rtl839x_reg;
13 extern const struct rtl838x_reg rtl930x_reg;
14 extern const struct rtl838x_reg rtl931x_reg;
15
16 extern const struct dsa_switch_ops rtl83xx_switch_ops;
17 extern const struct dsa_switch_ops rtl930x_switch_ops;
18
19 DEFINE_MUTEX(smi_lock);
20
21 // TODO: unused
22 static void dump_fdb(struct rtl838x_switch_priv *priv)
23 {
24 struct rtl838x_l2_entry e;
25 int i;
26
27 mutex_lock(&priv->reg_mutex);
28
29 for (i = 0; i < priv->fib_entries; i++) {
30 priv->r->read_l2_entry_using_hash(i >> 2, i & 0x3, &e);
31
32 if (!e.valid) /* Check for invalid entry */
33 continue;
34
35 pr_debug("-> port %02d: mac %pM, vid: %d, rvid: %d, MC: %d, %d\n",
36 e.port, &e.mac[0], e.vid, e.rvid, e.is_ip_mc, e.is_ipv6_mc);
37 }
38
39 mutex_unlock(&priv->reg_mutex);
40 }
41
42 int rtl83xx_port_get_stp_state(struct rtl838x_switch_priv *priv, int port)
43 {
44 u32 msti = 0;
45 u32 port_state[4];
46 int index, bit;
47 int pos = port;
48 int n = priv->port_width << 1;
49
50 /* Ports above or equal CPU port can never be configured */
51 if (port >= priv->cpu_port)
52 return -1;
53
54 mutex_lock(&priv->reg_mutex);
55
56 /* For the RTL839x and following, the bits are left-aligned in the 64/128 bit field */
57 if (priv->family_id == RTL8390_FAMILY_ID)
58 pos += 12;
59 if (priv->family_id == RTL9300_FAMILY_ID)
60 pos += 3;
61 if (priv->family_id == RTL9310_FAMILY_ID)
62 pos += 8;
63
64 index = n - (pos >> 4) - 1;
65 bit = (pos << 1) % 32;
66
67 priv->r->stp_get(priv, msti, port_state);
68
69 mutex_unlock(&priv->reg_mutex);
70
71 return (port_state[index] >> bit) & 3;
72 }
73
74 static struct table_reg rtl838x_tbl_regs[] = {
75 TBL_DESC(0x6900, 0x6908, 3, 15, 13, 1), // RTL8380_TBL_L2
76 TBL_DESC(0x6914, 0x6918, 18, 14, 12, 1), // RTL8380_TBL_0
77 TBL_DESC(0xA4C8, 0xA4CC, 6, 14, 12, 1), // RTL8380_TBL_1
78
79 TBL_DESC(0x1180, 0x1184, 3, 16, 14, 0), // RTL8390_TBL_L2
80 TBL_DESC(0x1190, 0x1194, 17, 15, 12, 0), // RTL8390_TBL_0
81 TBL_DESC(0x6B80, 0x6B84, 4, 14, 12, 0), // RTL8390_TBL_1
82 TBL_DESC(0x611C, 0x6120, 9, 8, 6, 0), // RTL8390_TBL_2
83
84 TBL_DESC(0xB320, 0xB334, 3, 18, 16, 0), // RTL9300_TBL_L2
85 TBL_DESC(0xB340, 0xB344, 19, 16, 12, 0), // RTL9300_TBL_0
86 TBL_DESC(0xB3A0, 0xB3A4, 20, 16, 13, 0), // RTL9300_TBL_1
87 TBL_DESC(0xCE04, 0xCE08, 6, 14, 12, 0), // RTL9300_TBL_2
88 TBL_DESC(0xD600, 0xD604, 30, 7, 6, 0), // RTL9300_TBL_HSB
89 TBL_DESC(0x7880, 0x7884, 22, 9, 8, 0), // RTL9300_TBL_HSA
90
91 TBL_DESC(0x8500, 0x8508, 8, 19, 15, 0), // RTL9310_TBL_0
92 TBL_DESC(0x40C0, 0x40C4, 22, 16, 14, 0), // RTL9310_TBL_1
93 TBL_DESC(0x8528, 0x852C, 6, 18, 14, 0), // RTL9310_TBL_2
94 TBL_DESC(0x0200, 0x0204, 9, 15, 12, 0), // RTL9310_TBL_3
95 TBL_DESC(0x20dc, 0x20e0, 29, 7, 6, 0), // RTL9310_TBL_4
96 TBL_DESC(0x7e1c, 0x7e20, 53, 8, 6, 0), // RTL9310_TBL_5
97 };
98
99 void rtl_table_init(void)
100 {
101 int i;
102
103 for (i = 0; i < RTL_TBL_END; i++)
104 mutex_init(&rtl838x_tbl_regs[i].lock);
105 }
106
107 /*
108 * Request access to table t in table access register r
109 * Returns a handle to a lock for that table
110 */
111 struct table_reg *rtl_table_get(rtl838x_tbl_reg_t r, int t)
112 {
113 if (r >= RTL_TBL_END)
114 return NULL;
115
116 if (t >= BIT(rtl838x_tbl_regs[r].c_bit-rtl838x_tbl_regs[r].t_bit))
117 return NULL;
118
119 mutex_lock(&rtl838x_tbl_regs[r].lock);
120 rtl838x_tbl_regs[r].tbl = t;
121
122 return &rtl838x_tbl_regs[r];
123 }
124
125 /*
126 * Release a table r, unlock the corresponding lock
127 */
128 void rtl_table_release(struct table_reg *r)
129 {
130 if (!r)
131 return;
132
133 // pr_info("Unlocking %08x\n", (u32)r);
134 mutex_unlock(&r->lock);
135 // pr_info("Unlock done\n");
136 }
137
138 /*
139 * Reads table index idx into the data registers of the table
140 */
141 void rtl_table_read(struct table_reg *r, int idx)
142 {
143 u32 cmd = r->rmode ? BIT(r->c_bit) : 0;
144
145 cmd |= BIT(r->c_bit + 1) | (r->tbl << r->t_bit) | (idx & (BIT(r->t_bit) - 1));
146 sw_w32(cmd, r->addr);
147 pr_debug("Writing %08x to %x for read\n", cmd, r->addr);
148 do { } while (sw_r32(r->addr) & BIT(r->c_bit + 1));
149 }
150
151 /*
152 * Writes the content of the table data registers into the table at index idx
153 */
154 void rtl_table_write(struct table_reg *r, int idx)
155 {
156 u32 cmd = r->rmode ? 0 : BIT(r->c_bit);
157
158 cmd |= BIT(r->c_bit + 1) | (r->tbl << r->t_bit) | (idx & (BIT(r->t_bit) - 1));
159 pr_debug("Writing %08x to %x for write, value %08x\n",
160 cmd, r->addr, sw_r32(0xb344));
161 sw_w32(cmd, r->addr);
162 do { } while (sw_r32(r->addr) & BIT(r->c_bit + 1));
163 }
164
165 /*
166 * Returns the address of the ith data register of table register r
167 * the address is relative to the beginning of the Switch-IO block at 0xbb000000
168 */
169 inline u16 rtl_table_data(struct table_reg *r, int i)
170 {
171 if (i >= r->max_data)
172 i = r->max_data - 1;
173 return r->data + i * 4;
174 }
175
176 inline u32 rtl_table_data_r(struct table_reg *r, int i)
177 {
178 return sw_r32(rtl_table_data(r, i));
179 }
180
181 inline void rtl_table_data_w(struct table_reg *r, u32 v, int i)
182 {
183 sw_w32(v, rtl_table_data(r, i));
184 }
185
186 /* Port register accessor functions for the RTL838x and RTL930X SoCs */
187 void rtl838x_mask_port_reg(u64 clear, u64 set, int reg)
188 {
189 sw_w32_mask((u32)clear, (u32)set, reg);
190 }
191
192 void rtl838x_set_port_reg(u64 set, int reg)
193 {
194 sw_w32((u32)set, reg);
195 }
196
197 u64 rtl838x_get_port_reg(int reg)
198 {
199 return ((u64) sw_r32(reg));
200 }
201
202 /* Port register accessor functions for the RTL839x and RTL931X SoCs */
203 void rtl839x_mask_port_reg_be(u64 clear, u64 set, int reg)
204 {
205 sw_w32_mask((u32)(clear >> 32), (u32)(set >> 32), reg);
206 sw_w32_mask((u32)(clear & 0xffffffff), (u32)(set & 0xffffffff), reg + 4);
207 }
208
209 u64 rtl839x_get_port_reg_be(int reg)
210 {
211 u64 v = sw_r32(reg);
212
213 v <<= 32;
214 v |= sw_r32(reg + 4);
215 return v;
216 }
217
218 void rtl839x_set_port_reg_be(u64 set, int reg)
219 {
220 sw_w32(set >> 32, reg);
221 sw_w32(set & 0xffffffff, reg + 4);
222 }
223
224 void rtl839x_mask_port_reg_le(u64 clear, u64 set, int reg)
225 {
226 sw_w32_mask((u32)clear, (u32)set, reg);
227 sw_w32_mask((u32)(clear >> 32), (u32)(set >> 32), reg + 4);
228 }
229
230 void rtl839x_set_port_reg_le(u64 set, int reg)
231 {
232 sw_w32(set, reg);
233 sw_w32(set >> 32, reg + 4);
234 }
235
236 u64 rtl839x_get_port_reg_le(int reg)
237 {
238 u64 v = sw_r32(reg + 4);
239
240 v <<= 32;
241 v |= sw_r32(reg);
242 return v;
243 }
244
245 int read_phy(u32 port, u32 page, u32 reg, u32 *val)
246 {
247 switch (soc_info.family) {
248 case RTL8380_FAMILY_ID:
249 return rtl838x_read_phy(port, page, reg, val);
250 case RTL8390_FAMILY_ID:
251 return rtl839x_read_phy(port, page, reg, val);
252 case RTL9300_FAMILY_ID:
253 return rtl930x_read_phy(port, page, reg, val);
254 case RTL9310_FAMILY_ID:
255 return rtl931x_read_phy(port, page, reg, val);
256 }
257 return -1;
258 }
259
260 int write_phy(u32 port, u32 page, u32 reg, u32 val)
261 {
262 switch (soc_info.family) {
263 case RTL8380_FAMILY_ID:
264 return rtl838x_write_phy(port, page, reg, val);
265 case RTL8390_FAMILY_ID:
266 return rtl839x_write_phy(port, page, reg, val);
267 case RTL9300_FAMILY_ID:
268 return rtl930x_write_phy(port, page, reg, val);
269 case RTL9310_FAMILY_ID:
270 return rtl931x_write_phy(port, page, reg, val);
271 }
272 return -1;
273 }
274
275 static int __init rtl83xx_mdio_probe(struct rtl838x_switch_priv *priv)
276 {
277 struct device *dev = priv->dev;
278 struct device_node *dn, *mii_np = dev->of_node;
279 struct mii_bus *bus;
280 int ret;
281 u32 pn;
282
283 pr_debug("In %s\n", __func__);
284 mii_np = of_find_compatible_node(NULL, NULL, "realtek,rtl838x-mdio");
285 if (mii_np) {
286 pr_debug("Found compatible MDIO node!\n");
287 } else {
288 dev_err(priv->dev, "no %s child node found", "mdio-bus");
289 return -ENODEV;
290 }
291
292 priv->mii_bus = of_mdio_find_bus(mii_np);
293 if (!priv->mii_bus) {
294 pr_debug("Deferring probe of mdio bus\n");
295 return -EPROBE_DEFER;
296 }
297 if (!of_device_is_available(mii_np))
298 ret = -ENODEV;
299
300 bus = devm_mdiobus_alloc(priv->ds->dev);
301 if (!bus)
302 return -ENOMEM;
303
304 bus->name = "rtl838x slave mii";
305
306 /*
307 * Since the NIC driver is loaded first, we can use the mdio rw functions
308 * assigned there.
309 */
310 bus->read = priv->mii_bus->read;
311 bus->write = priv->mii_bus->write;
312 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d", bus->name, dev->id);
313
314 bus->parent = dev;
315 priv->ds->slave_mii_bus = bus;
316 priv->ds->slave_mii_bus->priv = priv;
317
318 ret = mdiobus_register(priv->ds->slave_mii_bus);
319 if (ret && mii_np) {
320 of_node_put(dn);
321 return ret;
322 }
323
324 dn = mii_np;
325 for_each_node_by_name(dn, "ethernet-phy") {
326 if (of_property_read_u32(dn, "reg", &pn))
327 continue;
328
329 priv->ports[pn].dp = dsa_to_port(priv->ds, pn);
330
331 // Check for the integrated SerDes of the RTL8380M first
332 if (of_property_read_bool(dn, "phy-is-integrated")
333 && priv->id == 0x8380 && pn >= 24) {
334 pr_debug("----> FÓUND A SERDES\n");
335 priv->ports[pn].phy = PHY_RTL838X_SDS;
336 continue;
337 }
338
339 if (of_property_read_bool(dn, "phy-is-integrated")
340 && !of_property_read_bool(dn, "sfp")) {
341 priv->ports[pn].phy = PHY_RTL8218B_INT;
342 continue;
343 }
344
345 if (!of_property_read_bool(dn, "phy-is-integrated")
346 && of_property_read_bool(dn, "sfp")) {
347 priv->ports[pn].phy = PHY_RTL8214FC;
348 continue;
349 }
350
351 if (!of_property_read_bool(dn, "phy-is-integrated")
352 && !of_property_read_bool(dn, "sfp")) {
353 priv->ports[pn].phy = PHY_RTL8218B_EXT;
354 continue;
355 }
356 }
357
358 // TODO: Do this needs to come from the .dts, at least the SerDes number
359 if (priv->family_id == RTL9300_FAMILY_ID) {
360 priv->ports[24].is2G5 = true;
361 priv->ports[25].is2G5 = true;
362 priv->ports[24].sds_num = 1;
363 priv->ports[24].sds_num = 2;
364 }
365
366 /* Disable MAC polling the PHY so that we can start configuration */
367 priv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl);
368
369 /* Enable PHY control via SoC */
370 if (priv->family_id == RTL8380_FAMILY_ID) {
371 /* Enable PHY control via SoC */
372 sw_w32_mask(0, BIT(15), RTL838X_SMI_GLB_CTRL);
373 } else {
374 /* Disable PHY polling via SoC */
375 sw_w32_mask(BIT(7), 0, RTL839X_SMI_GLB_CTRL);
376 }
377
378 /* Power on fibre ports and reset them if necessary */
379 if (priv->ports[24].phy == PHY_RTL838X_SDS) {
380 pr_debug("Powering on fibre ports & reset\n");
381 rtl8380_sds_power(24, 1);
382 rtl8380_sds_power(26, 1);
383 }
384
385 // TODO: Only power on SerDes with external PHYs connected
386 if (priv->family_id == RTL9300_FAMILY_ID) {
387 pr_info("RTL9300 Powering on SerDes ports\n");
388 rtl9300_sds_power(24, 1);
389 rtl9300_sds_power(25, 1);
390 rtl9300_sds_power(26, 1);
391 rtl9300_sds_power(27, 1);
392 }
393
394 pr_debug("%s done\n", __func__);
395 return 0;
396 }
397
398 static int __init rtl83xx_get_l2aging(struct rtl838x_switch_priv *priv)
399 {
400 int t = sw_r32(priv->r->l2_ctrl_1);
401
402 t &= priv->family_id == RTL8380_FAMILY_ID ? 0x7fffff : 0x1FFFFF;
403
404 if (priv->family_id == RTL8380_FAMILY_ID)
405 t = t * 128 / 625; /* Aging time in seconds. 0: L2 aging disabled */
406 else
407 t = (t * 3) / 5;
408
409 pr_debug("L2 AGING time: %d sec\n", t);
410 pr_debug("Dynamic aging for ports: %x\n", sw_r32(priv->r->l2_port_aging_out));
411 return t;
412 }
413
414 /* Caller must hold priv->reg_mutex */
415 int rtl83xx_lag_add(struct dsa_switch *ds, int group, int port)
416 {
417 struct rtl838x_switch_priv *priv = ds->priv;
418 int i;
419
420 pr_info("%s: Adding port %d to LA-group %d\n", __func__, port, group);
421 if (group >= priv->n_lags) {
422 pr_err("Link Agrregation group too large.\n");
423 return -EINVAL;
424 }
425
426 if (port >= priv->cpu_port) {
427 pr_err("Invalid port number.\n");
428 return -EINVAL;
429 }
430
431 for (i = 0; i < priv->n_lags; i++) {
432 if (priv->lags_port_members[i] & BIT_ULL(i))
433 break;
434 }
435 if (i != priv->n_lags) {
436 pr_err("%s: Port already member of LAG: %d\n", __func__, i);
437 return -ENOSPC;
438 }
439
440 priv->r->mask_port_reg_be(0, BIT_ULL(port), priv->r->trk_mbr_ctr(group));
441 priv->lags_port_members[group] |= BIT_ULL(port);
442
443 pr_info("lags_port_members %d now %016llx\n", group, priv->lags_port_members[group]);
444 return 0;
445 }
446
447 /* Caller must hold priv->reg_mutex */
448 int rtl83xx_lag_del(struct dsa_switch *ds, int group, int port)
449 {
450 struct rtl838x_switch_priv *priv = ds->priv;
451
452 pr_info("%s: Removing port %d from LA-group %d\n", __func__, port, group);
453
454 if (group >= priv->n_lags) {
455 pr_err("Link Agrregation group too large.\n");
456 return -EINVAL;
457 }
458
459 if (port >= priv->cpu_port) {
460 pr_err("Invalid port number.\n");
461 return -EINVAL;
462 }
463
464
465 if (!(priv->lags_port_members[group] & BIT_ULL(port))) {
466 pr_err("%s: Port not member of LAG: %d\n", __func__, group
467 );
468 return -ENOSPC;
469 }
470
471 priv->r->mask_port_reg_be(BIT_ULL(port), 0, priv->r->trk_mbr_ctr(group));
472 priv->lags_port_members[group] &= ~BIT_ULL(port);
473
474 pr_info("lags_port_members %d now %016llx\n", group, priv->lags_port_members[group]);
475 return 0;
476 }
477
478 static int rtl83xx_handle_changeupper(struct rtl838x_switch_priv *priv,
479 struct net_device *ndev,
480 struct netdev_notifier_changeupper_info *info)
481 {
482 struct net_device *upper = info->upper_dev;
483 int i, j, err;
484
485 if (!netif_is_lag_master(upper))
486 return 0;
487
488 mutex_lock(&priv->reg_mutex);
489
490 for (i = 0; i < priv->n_lags; i++) {
491 if ((!priv->lag_devs[i]) || (priv->lag_devs[i] == upper))
492 break;
493 }
494 for (j = 0; j < priv->cpu_port; j++) {
495 if (priv->ports[j].dp->slave == ndev)
496 break;
497 }
498 if (j >= priv->cpu_port) {
499 err = -EINVAL;
500 goto out;
501 }
502
503 if (info->linking) {
504 if (!priv->lag_devs[i])
505 priv->lag_devs[i] = upper;
506 err = rtl83xx_lag_add(priv->ds, i, priv->ports[j].dp->index);
507 if (err) {
508 err = -EINVAL;
509 goto out;
510 }
511 } else {
512 if (!priv->lag_devs[i])
513 err = -EINVAL;
514 err = rtl83xx_lag_del(priv->ds, i, priv->ports[j].dp->index);
515 if (err) {
516 err = -EINVAL;
517 goto out;
518 }
519 if (!priv->lags_port_members[i])
520 priv->lag_devs[i] = NULL;
521 }
522
523 out:
524 mutex_unlock(&priv->reg_mutex);
525 return 0;
526 }
527
528 static int rtl83xx_netdevice_event(struct notifier_block *this,
529 unsigned long event, void *ptr)
530 {
531 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
532 struct rtl838x_switch_priv *priv;
533 int err;
534
535 pr_debug("In: %s, event: %lu\n", __func__, event);
536
537 if ((event != NETDEV_CHANGEUPPER) && (event != NETDEV_CHANGELOWERSTATE))
538 return NOTIFY_DONE;
539
540 priv = container_of(this, struct rtl838x_switch_priv, nb);
541 switch (event) {
542 case NETDEV_CHANGEUPPER:
543 err = rtl83xx_handle_changeupper(priv, ndev, ptr);
544 break;
545 }
546
547 if (err)
548 return err;
549
550 return NOTIFY_DONE;
551 }
552
553 static int __init rtl83xx_sw_probe(struct platform_device *pdev)
554 {
555 int err = 0, i;
556 struct rtl838x_switch_priv *priv;
557 struct device *dev = &pdev->dev;
558 u64 bpdu_mask;
559
560 pr_debug("Probing RTL838X switch device\n");
561 if (!pdev->dev.of_node) {
562 dev_err(dev, "No DT found\n");
563 return -EINVAL;
564 }
565
566 // Initialize access to RTL switch tables
567 rtl_table_init();
568
569 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
570 if (!priv)
571 return -ENOMEM;
572
573 priv->ds = dsa_switch_alloc(dev, DSA_MAX_PORTS);
574
575 if (!priv->ds)
576 return -ENOMEM;
577 priv->ds->dev = dev;
578 priv->ds->priv = priv;
579 priv->ds->ops = &rtl83xx_switch_ops;
580 priv->dev = dev;
581
582 priv->family_id = soc_info.family;
583 priv->id = soc_info.id;
584 switch(soc_info.family) {
585 case RTL8380_FAMILY_ID:
586 priv->ds->ops = &rtl83xx_switch_ops;
587 priv->cpu_port = RTL838X_CPU_PORT;
588 priv->port_mask = 0x1f;
589 priv->port_width = 1;
590 priv->irq_mask = 0x0FFFFFFF;
591 priv->r = &rtl838x_reg;
592 priv->ds->num_ports = 29;
593 priv->fib_entries = 8192;
594 rtl8380_get_version(priv);
595 priv->n_lags = 8;
596 break;
597 case RTL8390_FAMILY_ID:
598 priv->ds->ops = &rtl83xx_switch_ops;
599 priv->cpu_port = RTL839X_CPU_PORT;
600 priv->port_mask = 0x3f;
601 priv->port_width = 2;
602 priv->irq_mask = 0xFFFFFFFFFFFFFULL;
603 priv->r = &rtl839x_reg;
604 priv->ds->num_ports = 53;
605 priv->fib_entries = 16384;
606 rtl8390_get_version(priv);
607 priv->n_lags = 16;
608 break;
609 case RTL9300_FAMILY_ID:
610 priv->ds->ops = &rtl930x_switch_ops;
611 priv->cpu_port = RTL930X_CPU_PORT;
612 priv->port_mask = 0x1f;
613 priv->port_width = 1;
614 priv->irq_mask = 0x0FFFFFFF;
615 priv->r = &rtl930x_reg;
616 priv->ds->num_ports = 29;
617 priv->fib_entries = 16384;
618 priv->version = RTL8390_VERSION_A;
619 priv->n_lags = 16;
620 sw_w32(1, RTL930X_ST_CTRL);
621 break;
622 case RTL9310_FAMILY_ID:
623 priv->ds->ops = &rtl930x_switch_ops;
624 priv->cpu_port = RTL931X_CPU_PORT;
625 priv->port_mask = 0x3f;
626 priv->port_width = 2;
627 priv->irq_mask = 0xFFFFFFFFFFFFFULL;
628 priv->r = &rtl931x_reg;
629 priv->ds->num_ports = 57;
630 priv->fib_entries = 16384;
631 priv->version = RTL8390_VERSION_A;
632 priv->n_lags = 16;
633 break;
634 }
635 pr_debug("Chip version %c\n", priv->version);
636
637 err = rtl83xx_mdio_probe(priv);
638 if (err) {
639 /* Probing fails the 1st time because of missing ethernet driver
640 * initialization. Use this to disable traffic in case the bootloader left if on
641 */
642 return err;
643 }
644 err = dsa_register_switch(priv->ds);
645 if (err) {
646 dev_err(dev, "Error registering switch: %d\n", err);
647 return err;
648 }
649
650 /* Enable link and media change interrupts. Are the SERDES masks needed? */
651 sw_w32_mask(0, 3, priv->r->isr_glb_src);
652
653 priv->r->set_port_reg_le(priv->irq_mask, priv->r->isr_port_link_sts_chg);
654 priv->r->set_port_reg_le(priv->irq_mask, priv->r->imr_port_link_sts_chg);
655
656 priv->link_state_irq = platform_get_irq(pdev, 0);
657 pr_info("LINK state irq: %d\n", priv->link_state_irq);
658 switch (priv->family_id) {
659 case RTL8380_FAMILY_ID:
660 err = request_irq(priv->link_state_irq, rtl838x_switch_irq,
661 IRQF_SHARED, "rtl838x-link-state", priv->ds);
662 break;
663 case RTL8390_FAMILY_ID:
664 err = request_irq(priv->link_state_irq, rtl839x_switch_irq,
665 IRQF_SHARED, "rtl839x-link-state", priv->ds);
666 break;
667 case RTL9300_FAMILY_ID:
668 err = request_irq(priv->link_state_irq, rtl930x_switch_irq,
669 IRQF_SHARED, "rtl930x-link-state", priv->ds);
670 break;
671 case RTL9310_FAMILY_ID:
672 err = request_irq(priv->link_state_irq, rtl931x_switch_irq,
673 IRQF_SHARED, "rtl931x-link-state", priv->ds);
674 break;
675 }
676 if (err) {
677 dev_err(dev, "Error setting up switch interrupt.\n");
678 /* Need to free allocated switch here */
679 }
680
681 /* Enable interrupts for switch, on RTL931x, the IRQ is always on globally */
682 if (soc_info.family != RTL9310_FAMILY_ID)
683 sw_w32(0x1, priv->r->imr_glb);
684
685 rtl83xx_get_l2aging(priv);
686
687 rtl83xx_setup_qos(priv);
688
689 /* Clear all destination ports for mirror groups */
690 for (i = 0; i < 4; i++)
691 priv->mirror_group_ports[i] = -1;
692
693 priv->nb.notifier_call = rtl83xx_netdevice_event;
694 if (register_netdevice_notifier(&priv->nb)) {
695 priv->nb.notifier_call = NULL;
696 dev_err(dev, "Failed to register LAG netdev notifier\n");
697 }
698
699 // Flood BPDUs to all ports including cpu-port
700 if (soc_info.family != RTL9300_FAMILY_ID) { // TODO: Port this functionality
701 bpdu_mask = soc_info.family == RTL8380_FAMILY_ID ? 0x1FFFFFFF : 0x1FFFFFFFFFFFFF;
702 priv->r->set_port_reg_be(bpdu_mask, priv->r->rma_bpdu_fld_pmask);
703
704 // TRAP 802.1X frames (EAPOL) to the CPU-Port, bypass STP and VLANs
705 sw_w32(7, priv->r->spcl_trap_eapol_ctrl);
706
707 rtl838x_dbgfs_init(priv);
708 }
709
710 return err;
711 }
712
713 static int rtl83xx_sw_remove(struct platform_device *pdev)
714 {
715 // TODO:
716 pr_debug("Removing platform driver for rtl83xx-sw\n");
717 return 0;
718 }
719
720 static const struct of_device_id rtl83xx_switch_of_ids[] = {
721 { .compatible = "realtek,rtl83xx-switch"},
722 { /* sentinel */ }
723 };
724
725
726 MODULE_DEVICE_TABLE(of, rtl83xx_switch_of_ids);
727
728 static struct platform_driver rtl83xx_switch_driver = {
729 .probe = rtl83xx_sw_probe,
730 .remove = rtl83xx_sw_remove,
731 .driver = {
732 .name = "rtl83xx-switch",
733 .pm = NULL,
734 .of_match_table = rtl83xx_switch_of_ids,
735 },
736 };
737
738 module_platform_driver(rtl83xx_switch_driver);
739
740 MODULE_AUTHOR("B. Koblitz");
741 MODULE_DESCRIPTION("RTL83XX SoC Switch Driver");
742 MODULE_LICENSE("GPL");
Staging tree of Jo-Philipp Wich