target/linux/realtek/files-5.15/drivers/net/phy/rtl83xx-phy.h

   1 // SPDX-License-Identifier: GPL-2.0-only
   2
   3 struct rtl83xx_shared_private {
   4         char *name;
   5 };
   6
   7 struct __attribute__ ((__packed__)) part {
   8         uint16_t start;
   9         uint8_t wordsize;
  10         uint8_t words;
  11 };
  12
  13 struct __attribute__ ((__packed__)) fw_header {
  14         uint32_t magic;
  15         uint32_t phy;
  16         uint32_t checksum;
  17         uint32_t version;
  18         struct part parts[10];
  19 };
  20
  21 // TODO: fixed path?
  22 #define FIRMWARE_838X_8380_1    "rtl838x_phy/rtl838x_8380.fw"
  23 #define FIRMWARE_838X_8214FC_1  "rtl838x_phy/rtl838x_8214fc.fw"
  24 #define FIRMWARE_838X_8218b_1   "rtl838x_phy/rtl838x_8218b.fw"
  25
  26 /* External RTL8218B and RTL8214FC IDs are identical */
  27 #define PHY_ID_RTL8214C         0x001cc942
  28 #define PHY_ID_RTL8214FC        0x001cc981
  29 #define PHY_ID_RTL8218B_E       0x001cc981
  30 #define PHY_ID_RTL8218D         0x001cc983
  31 #define PHY_ID_RTL8218B_I       0x001cca40
  32 #define PHY_ID_RTL8221B         0x001cc849
  33 #define PHY_ID_RTL8226          0x001cc838
  34 #define PHY_ID_RTL8390_GENERIC  0x001ccab0
  35 #define PHY_ID_RTL8393_I        0x001c8393
  36 #define PHY_ID_RTL9300_I        0x70d03106
  37
  38 // PHY MMD devices
  39 #define MMD_AN          7
  40 #define MMD_VEND2       31
  41
  42 /* Registers of the internal Serdes of the 8380 */
  43 #define RTL838X_SDS_MODE_SEL                    (0x0028)
  44 #define RTL838X_SDS_CFG_REG                     (0x0034)
  45 #define RTL838X_INT_MODE_CTRL                   (0x005c)
  46 #define RTL838X_DMY_REG31                       (0x3b28)
  47
  48 #define RTL8380_SDS4_FIB_REG0                   (0xF800)
  49 #define RTL838X_SDS4_REG28                      (0xef80)
  50 #define RTL838X_SDS4_DUMMY0                     (0xef8c)
  51 #define RTL838X_SDS5_EXT_REG6                   (0xf18c)
  52 #define RTL838X_SDS4_FIB_REG0                   (RTL838X_SDS4_REG28 + 0x880)
  53 #define RTL838X_SDS5_FIB_REG0                   (RTL838X_SDS4_REG28 + 0x980)
  54
  55 /* Registers of the internal SerDes of the RTL8390 */
  56 #define RTL839X_SDS12_13_XSG0                   (0xB800)
  57
  58 /* Registers of the internal Serdes of the 9300 */
  59 #define RTL930X_SDS_INDACS_CMD                  (0x03B0)
  60 #define RTL930X_SDS_INDACS_DATA                 (0x03B4)
  61 #define RTL930X_MAC_FORCE_MODE_CTRL             (0xCA1C)
  62
  63 /*Registers of the internal SerDes of the 9310 */
  64 #define RTL931X_SERDES_INDRT_ACCESS_CTRL        (0x5638)
  65 #define RTL931X_SERDES_INDRT_DATA_CTRL          (0x563C)
  66 #define RTL931X_SERDES_MODE_CTRL                (0x13cc)
  67 #define RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR    (0x13F4)
  68 #define RTL931X_MAC_SERDES_MODE_CTRL(sds)       (0x136C + (((sds) << 2)))