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realtek: add RTL821X_CHIP_ID
[openwrt/staging/stintel.git] / target / linux / realtek / files-5.15 / drivers / net / phy / rtl83xx-phy.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Realtek RTL838X Ethernet MDIO interface driver
3 *
4 * Copyright (C) 2020 B. Koblitz
5 */
6
7 #include <linux/module.h>
8 #include <linux/delay.h>
9 #include <linux/of.h>
10 #include <linux/phy.h>
11 #include <linux/netdevice.h>
12 #include <linux/firmware.h>
13 #include <linux/crc32.h>
14 #include <linux/sfp.h>
15 #include <linux/mii.h>
16 #include <linux/mdio.h>
17
18 #include <asm/mach-rtl838x/mach-rtl83xx.h>
19 #include "rtl83xx-phy.h"
20
21 extern struct rtl83xx_soc_info soc_info;
22 extern struct mutex smi_lock;
23
24 #define PHY_PAGE_2 2
25 #define PHY_PAGE_4 4
26
27 /* all Clause-22 RealTek MDIO PHYs use register 0x1f for page select */
28 #define RTL8XXX_PAGE_SELECT 0x1f
29
30 #define RTL8XXX_PAGE_MAIN 0x0000
31 #define RTL821X_PAGE_PORT 0x0266
32 #define RTL821X_PAGE_POWER 0x0a40
33 #define RTL821X_PAGE_GPHY 0x0a42
34 #define RTL821X_PAGE_MAC 0x0a43
35 #define RTL821X_PAGE_STATE 0x0b80
36 #define RTL821X_PAGE_PATCH 0x0b82
37
38 /* Using the special page 0xfff with the MDIO controller found in
39 * RealTek SoCs allows to access the PHY in RAW mode, ie. bypassing
40 * the cache and paging engine of the MDIO controller.
41 */
42 #define RTL83XX_PAGE_RAW 0x0fff
43
44 /* internal RTL821X PHY uses register 0x1d to select media page */
45 #define RTL821XINT_MEDIA_PAGE_SELECT 0x1d
46 /* external RTL821X PHY uses register 0x1e to select media page */
47 #define RTL821XEXT_MEDIA_PAGE_SELECT 0x1e
48
49 #define RTL821X_CHIP_ID 0x6276
50
51 #define RTL821X_MEDIA_PAGE_AUTO 0
52 #define RTL821X_MEDIA_PAGE_COPPER 1
53 #define RTL821X_MEDIA_PAGE_FIBRE 3
54 #define RTL821X_MEDIA_PAGE_INTERNAL 8
55
56 #define RTL9300_PHY_ID_MASK 0xf0ffffff
57
58 /* RTL930X SerDes supports the following modes:
59 * 0x02: SGMII 0x04: 1000BX_FIBER 0x05: FIBER100
60 * 0x06: QSGMII 0x09: RSGMII 0x0d: USXGMII
61 * 0x10: XSGMII 0x12: HISGMII 0x16: 2500Base_X
62 * 0x17: RXAUI_LITE 0x19: RXAUI_PLUS 0x1a: 10G Base-R
63 * 0x1b: 10GR1000BX_AUTO 0x1f: OFF
64 */
65 #define RTL930X_SDS_MODE_SGMII 0x02
66 #define RTL930X_SDS_MODE_1000BASEX 0x04
67 #define RTL930X_SDS_MODE_USXGMII 0x0d
68 #define RTL930X_SDS_MODE_XGMII 0x10
69 #define RTL930X_SDS_MODE_HSGMII 0x12
70 #define RTL930X_SDS_MODE_2500BASEX 0x16
71 #define RTL930X_SDS_MODE_10GBASER 0x1a
72 #define RTL930X_SDS_OFF 0x1f
73 #define RTL930X_SDS_MASK 0x1f
74
75 /* This lock protects the state of the SoC automatically polling the PHYs over the SMI
76 * bus to detect e.g. link and media changes. For operations on the PHYs such as
77 * patching or other configuration changes such as EEE, polling needs to be disabled
78 * since otherwise these operations may fails or lead to unpredictable results.
79 */
80 DEFINE_MUTEX(poll_lock);
81
82 static const struct firmware rtl838x_8380_fw;
83 static const struct firmware rtl838x_8214fc_fw;
84 static const struct firmware rtl838x_8218b_fw;
85
86 static u64 disable_polling(int port)
87 {
88 u64 saved_state;
89
90 mutex_lock(&poll_lock);
91
92 switch (soc_info.family) {
93 case RTL8380_FAMILY_ID:
94 saved_state = sw_r32(RTL838X_SMI_POLL_CTRL);
95 sw_w32_mask(BIT(port), 0, RTL838X_SMI_POLL_CTRL);
96 break;
97 case RTL8390_FAMILY_ID:
98 saved_state = sw_r32(RTL839X_SMI_PORT_POLLING_CTRL + 4);
99 saved_state <<= 32;
100 saved_state |= sw_r32(RTL839X_SMI_PORT_POLLING_CTRL);
101 sw_w32_mask(BIT(port % 32), 0,
102 RTL839X_SMI_PORT_POLLING_CTRL + ((port >> 5) << 2));
103 break;
104 case RTL9300_FAMILY_ID:
105 saved_state = sw_r32(RTL930X_SMI_POLL_CTRL);
106 sw_w32_mask(BIT(port), 0, RTL930X_SMI_POLL_CTRL);
107 break;
108 case RTL9310_FAMILY_ID:
109 pr_warn("%s not implemented for RTL931X\n", __func__);
110 break;
111 }
112
113 mutex_unlock(&poll_lock);
114
115 return saved_state;
116 }
117
118 static int resume_polling(u64 saved_state)
119 {
120 mutex_lock(&poll_lock);
121
122 switch (soc_info.family) {
123 case RTL8380_FAMILY_ID:
124 sw_w32(saved_state, RTL838X_SMI_POLL_CTRL);
125 break;
126 case RTL8390_FAMILY_ID:
127 sw_w32(saved_state >> 32, RTL839X_SMI_PORT_POLLING_CTRL + 4);
128 sw_w32(saved_state, RTL839X_SMI_PORT_POLLING_CTRL);
129 break;
130 case RTL9300_FAMILY_ID:
131 sw_w32(saved_state, RTL930X_SMI_POLL_CTRL);
132 break;
133 case RTL9310_FAMILY_ID:
134 pr_warn("%s not implemented for RTL931X\n", __func__);
135 break;
136 }
137
138 mutex_unlock(&poll_lock);
139
140 return 0;
141 }
142
143 static void rtl8380_int_phy_on_off(struct phy_device *phydev, bool on)
144 {
145 phy_modify(phydev, 0, BMCR_PDOWN, on ? 0 : BMCR_PDOWN);
146 }
147
148 static void rtl8380_rtl8214fc_on_off(struct phy_device *phydev, bool on)
149 {
150 /* fiber ports */
151 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_FIBRE);
152 phy_modify(phydev, 0x10, BMCR_PDOWN, on ? 0 : BMCR_PDOWN);
153
154 /* copper ports */
155 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
156 phy_modify_paged(phydev, RTL821X_PAGE_POWER, 0x10, BMCR_PDOWN, on ? 0 : BMCR_PDOWN);
157 }
158
159 static void rtl8380_phy_reset(struct phy_device *phydev)
160 {
161 phy_modify(phydev, 0, BMCR_RESET, BMCR_RESET);
162 }
163
164 /* The access registers for SDS_MODE_SEL and the LSB for each SDS within */
165 u16 rtl9300_sds_regs[] = { 0x0194, 0x0194, 0x0194, 0x0194, 0x02a0, 0x02a0, 0x02a0, 0x02a0,
166 0x02A4, 0x02A4, 0x0198, 0x0198 };
167 u8 rtl9300_sds_lsb[] = { 0, 6, 12, 18, 0, 6, 12, 18, 0, 6, 0, 6};
168
169 /* Reset the SerDes by powering it off and set a new operation mode
170 * of the SerDes.
171 */
172 void rtl9300_sds_rst(int sds_num, u32 mode)
173 {
174 pr_info("%s %d\n", __func__, mode);
175 if (sds_num < 0 || sds_num > 11) {
176 pr_err("Wrong SerDes number: %d\n", sds_num);
177 return;
178 }
179
180 sw_w32_mask(RTL930X_SDS_MASK << rtl9300_sds_lsb[sds_num],
181 RTL930X_SDS_OFF << rtl9300_sds_lsb[sds_num],
182 rtl9300_sds_regs[sds_num]);
183 mdelay(10);
184
185 sw_w32_mask(RTL930X_SDS_MASK << rtl9300_sds_lsb[sds_num], mode << rtl9300_sds_lsb[sds_num],
186 rtl9300_sds_regs[sds_num]);
187 mdelay(10);
188
189 pr_debug("%s: 194:%08x 198:%08x 2a0:%08x 2a4:%08x\n", __func__,
190 sw_r32(0x194), sw_r32(0x198), sw_r32(0x2a0), sw_r32(0x2a4));
191 }
192
193 void rtl9300_sds_set(int sds_num, u32 mode)
194 {
195 pr_info("%s %d\n", __func__, mode);
196 if (sds_num < 0 || sds_num > 11) {
197 pr_err("Wrong SerDes number: %d\n", sds_num);
198 return;
199 }
200
201 sw_w32_mask(RTL930X_SDS_MASK << rtl9300_sds_lsb[sds_num], mode << rtl9300_sds_lsb[sds_num],
202 rtl9300_sds_regs[sds_num]);
203 mdelay(10);
204
205 pr_debug("%s: 194:%08x 198:%08x 2a0:%08x 2a4:%08x\n", __func__,
206 sw_r32(0x194), sw_r32(0x198), sw_r32(0x2a0), sw_r32(0x2a4));
207 }
208
209 u32 rtl9300_sds_mode_get(int sds_num)
210 {
211 u32 v;
212
213 if (sds_num < 0 || sds_num > 11) {
214 pr_err("Wrong SerDes number: %d\n", sds_num);
215 return 0;
216 }
217
218 v = sw_r32(rtl9300_sds_regs[sds_num]);
219 v >>= rtl9300_sds_lsb[sds_num];
220
221 return v & RTL930X_SDS_MASK;
222 }
223
224 /* On the RTL839x family of SoCs with inbuilt SerDes, these SerDes are accessed through
225 * a 2048 bit register that holds the contents of the PHY being simulated by the SoC.
226 */
227 int rtl839x_read_sds_phy(int phy_addr, int phy_reg)
228 {
229 int offset = 0;
230 int reg;
231 u32 val;
232
233 if (phy_addr == 49)
234 offset = 0x100;
235
236 /* For the RTL8393 internal SerDes, we simulate a PHY ID in registers 2/3
237 * which would otherwise read as 0.
238 */
239 if (soc_info.id == 0x8393) {
240 if (phy_reg == MII_PHYSID1)
241 return 0x1c;
242 if (phy_reg == MII_PHYSID2)
243 return 0x8393;
244 }
245
246 /* Register RTL839X_SDS12_13_XSG0 is 2048 bit broad, the MSB (bit 15) of the
247 * 0th PHY register is bit 1023 (in byte 0x80). Because PHY-registers are 16
248 * bit broad, we offset by reg << 1. In the SoC 2 registers are stored in
249 * one 32 bit register.
250 */
251 reg = (phy_reg << 1) & 0xfc;
252 val = sw_r32(RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);
253
254 if (phy_reg & 1)
255 val = (val >> 16) & 0xffff;
256 else
257 val &= 0xffff;
258
259 return val;
260 }
261
262 /* On the RTL930x family of SoCs, the internal SerDes are accessed through an IO
263 * register which simulates commands to an internal MDIO bus.
264 */
265 int rtl930x_read_sds_phy(int phy_addr, int page, int phy_reg)
266 {
267 int i;
268 u32 cmd = phy_addr << 2 | page << 7 | phy_reg << 13 | 1;
269
270 sw_w32(cmd, RTL930X_SDS_INDACS_CMD);
271
272 for (i = 0; i < 100; i++) {
273 if (!(sw_r32(RTL930X_SDS_INDACS_CMD) & 0x1))
274 break;
275 mdelay(1);
276 }
277
278 if (i >= 100)
279 return -EIO;
280
281 return sw_r32(RTL930X_SDS_INDACS_DATA) & 0xffff;
282 }
283
284 int rtl930x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v)
285 {
286 int i;
287 u32 cmd;
288
289 sw_w32(v, RTL930X_SDS_INDACS_DATA);
290 cmd = phy_addr << 2 | page << 7 | phy_reg << 13 | 0x3;
291
292 sw_w32(cmd, RTL930X_SDS_INDACS_CMD);
293
294 for (i = 0; i < 100; i++) {
295 if (!(sw_r32(RTL930X_SDS_INDACS_CMD) & 0x1))
296 break;
297 mdelay(1);
298 }
299
300
301 if (i >= 100) {
302 pr_info("%s ERROR !!!!!!!!!!!!!!!!!!!!\n", __func__);
303 return -EIO;
304 }
305
306 return 0;
307 }
308
309 int rtl931x_read_sds_phy(int phy_addr, int page, int phy_reg)
310 {
311 int i;
312 u32 cmd = phy_addr << 2 | page << 7 | phy_reg << 13 | 1;
313
314 pr_debug("%s: phy_addr(SDS-ID) %d, phy_reg: %d\n", __func__, phy_addr, phy_reg);
315 sw_w32(cmd, RTL931X_SERDES_INDRT_ACCESS_CTRL);
316
317 for (i = 0; i < 100; i++) {
318 if (!(sw_r32(RTL931X_SERDES_INDRT_ACCESS_CTRL) & 0x1))
319 break;
320 mdelay(1);
321 }
322
323 if (i >= 100)
324 return -EIO;
325
326 pr_debug("%s: returning %04x\n", __func__, sw_r32(RTL931X_SERDES_INDRT_DATA_CTRL) & 0xffff);
327
328 return sw_r32(RTL931X_SERDES_INDRT_DATA_CTRL) & 0xffff;
329 }
330
331 int rtl931x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v)
332 {
333 int i;
334 u32 cmd;
335
336 cmd = phy_addr << 2 | page << 7 | phy_reg << 13;
337 sw_w32(cmd, RTL931X_SERDES_INDRT_ACCESS_CTRL);
338
339 sw_w32(v, RTL931X_SERDES_INDRT_DATA_CTRL);
340
341 cmd = sw_r32(RTL931X_SERDES_INDRT_ACCESS_CTRL) | 0x3;
342 sw_w32(cmd, RTL931X_SERDES_INDRT_ACCESS_CTRL);
343
344 for (i = 0; i < 100; i++) {
345 if (!(sw_r32(RTL931X_SERDES_INDRT_ACCESS_CTRL) & 0x1))
346 break;
347 mdelay(1);
348 }
349
350 if (i >= 100)
351 return -EIO;
352
353 return 0;
354 }
355
356 /* On the RTL838x SoCs, the internal SerDes is accessed through direct access to
357 * standard PHY registers, where a 32 bit register holds a 16 bit word as found
358 * in a standard page 0 of a PHY
359 */
360 int rtl838x_read_sds_phy(int phy_addr, int phy_reg)
361 {
362 int offset = 0;
363 u32 val;
364
365 if (phy_addr == 26)
366 offset = 0x100;
367 val = sw_r32(RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2)) & 0xffff;
368
369 return val;
370 }
371
372 int rtl839x_write_sds_phy(int phy_addr, int phy_reg, u16 v)
373 {
374 int offset = 0;
375 int reg;
376 u32 val;
377
378 if (phy_addr == 49)
379 offset = 0x100;
380
381 reg = (phy_reg << 1) & 0xfc;
382 val = v;
383 if (phy_reg & 1) {
384 val = val << 16;
385 sw_w32_mask(0xffff0000, val,
386 RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);
387 } else {
388 sw_w32_mask(0xffff, val,
389 RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);
390 }
391
392 return 0;
393 }
394
395 /* Read the link and speed status of the 2 internal SGMII/1000Base-X
396 * ports of the RTL838x SoCs
397 */
398 static int rtl8380_read_status(struct phy_device *phydev)
399 {
400 int err;
401
402 err = genphy_read_status(phydev);
403
404 if (phydev->link) {
405 phydev->speed = SPEED_1000;
406 phydev->duplex = DUPLEX_FULL;
407 }
408
409 return err;
410 }
411
412 /* Read the link and speed status of the 2 internal SGMII/1000Base-X
413 * ports of the RTL8393 SoC
414 */
415 static int rtl8393_read_status(struct phy_device *phydev)
416 {
417 int offset = 0;
418 int err;
419 int phy_addr = phydev->mdio.addr;
420 u32 v;
421
422 err = genphy_read_status(phydev);
423 if (phy_addr == 49)
424 offset = 0x100;
425
426 if (phydev->link) {
427 phydev->speed = SPEED_100;
428 /* Read SPD_RD_00 (bit 13) and SPD_RD_01 (bit 6) out of the internal
429 * PHY registers
430 */
431 v = sw_r32(RTL839X_SDS12_13_XSG0 + offset + 0x80);
432 if (!(v & (1 << 13)) && (v & (1 << 6)))
433 phydev->speed = SPEED_1000;
434 phydev->duplex = DUPLEX_FULL;
435 }
436
437 return err;
438 }
439
440 static int rtl8226_read_page(struct phy_device *phydev)
441 {
442 return __phy_read(phydev, RTL8XXX_PAGE_SELECT);
443 }
444
445 static int rtl8226_write_page(struct phy_device *phydev, int page)
446 {
447 return __phy_write(phydev, RTL8XXX_PAGE_SELECT, page);
448 }
449
450 static int rtl8226_read_status(struct phy_device *phydev)
451 {
452 int ret = 0;
453 u32 val;
454
455 /* TODO: ret = genphy_read_status(phydev);
456 * if (ret < 0) {
457 * pr_info("%s: genphy_read_status failed\n", __func__);
458 * return ret;
459 * }
460 */
461
462 /* Link status must be read twice */
463 for (int i = 0; i < 2; i++)
464 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xA402);
465
466 phydev->link = val & BIT(2) ? 1 : 0;
467 if (!phydev->link)
468 goto out;
469
470 /* Read duplex status */
471 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xA434);
472 if (val < 0)
473 goto out;
474 phydev->duplex = !!(val & BIT(3));
475
476 /* Read speed */
477 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xA434);
478 switch (val & 0x0630) {
479 case 0x0000:
480 phydev->speed = SPEED_10;
481 break;
482 case 0x0010:
483 phydev->speed = SPEED_100;
484 break;
485 case 0x0020:
486 phydev->speed = SPEED_1000;
487 break;
488 case 0x0200:
489 phydev->speed = SPEED_10000;
490 break;
491 case 0x0210:
492 phydev->speed = SPEED_2500;
493 break;
494 case 0x0220:
495 phydev->speed = SPEED_5000;
496 break;
497 default:
498 break;
499 }
500
501 out:
502 return ret;
503 }
504
505 static int rtl8226_advertise_aneg(struct phy_device *phydev)
506 {
507 int ret = 0;
508 u32 v;
509
510 pr_info("In %s\n", __func__);
511
512 v = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
513 if (v < 0)
514 goto out;
515
516 v |= ADVERTISE_10HALF;
517 v |= ADVERTISE_10FULL;
518 v |= ADVERTISE_100HALF;
519 v |= ADVERTISE_100FULL;
520
521 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE, v);
522
523 /* Allow 1GBit */
524 v = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xA412);
525 if (v < 0)
526 goto out;
527 v |= ADVERTISE_1000FULL;
528
529 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 0xA412, v);
530 if (ret < 0)
531 goto out;
532
533 /* Allow 2.5G */
534 v = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL);
535 if (v < 0)
536 goto out;
537
538 v |= MDIO_AN_10GBT_CTRL_ADV2_5G;
539 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, v);
540
541 out:
542 return ret;
543 }
544
545 static int rtl8226_config_aneg(struct phy_device *phydev)
546 {
547 int ret = 0;
548 u32 v;
549
550 pr_debug("In %s\n", __func__);
551 if (phydev->autoneg == AUTONEG_ENABLE) {
552 ret = rtl8226_advertise_aneg(phydev);
553 if (ret)
554 goto out;
555 /* AutoNegotiationEnable */
556 v = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
557 if (v < 0)
558 goto out;
559
560 v |= MDIO_AN_CTRL1_ENABLE; /* Enable AN */
561 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1, v);
562 if (ret < 0)
563 goto out;
564
565 /* RestartAutoNegotiation */
566 v = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xA400);
567 if (v < 0)
568 goto out;
569 v |= MDIO_AN_CTRL1_RESTART;
570
571 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 0xA400, v);
572 }
573
574 /* TODO: ret = __genphy_config_aneg(phydev, ret); */
575
576 out:
577 return ret;
578 }
579
580 static int rtl8226_get_eee(struct phy_device *phydev,
581 struct ethtool_eee *e)
582 {
583 u32 val;
584 int addr = phydev->mdio.addr;
585
586 pr_debug("In %s, port %d, was enabled: %d\n", __func__, addr, e->eee_enabled);
587
588 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
589 if (e->eee_enabled) {
590 e->eee_enabled = !!(val & MDIO_EEE_100TX);
591 if (!e->eee_enabled) {
592 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV2);
593 e->eee_enabled = !!(val & MDIO_EEE_2_5GT);
594 }
595 }
596 pr_debug("%s: enabled: %d\n", __func__, e->eee_enabled);
597
598 return 0;
599 }
600
601 static int rtl8226_set_eee(struct phy_device *phydev, struct ethtool_eee *e)
602 {
603 int port = phydev->mdio.addr;
604 u64 poll_state;
605 bool an_enabled;
606 u32 val;
607
608 pr_info("In %s, port %d, enabled %d\n", __func__, port, e->eee_enabled);
609
610 poll_state = disable_polling(port);
611
612 /* Remember aneg state */
613 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
614 an_enabled = !!(val & MDIO_AN_CTRL1_ENABLE);
615
616 /* Setup 100/1000MBit */
617 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
618 if (e->eee_enabled)
619 val |= (MDIO_EEE_100TX | MDIO_EEE_1000T);
620 else
621 val &= (MDIO_EEE_100TX | MDIO_EEE_1000T);
622 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
623
624 /* Setup 2.5GBit */
625 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV2);
626 if (e->eee_enabled)
627 val |= MDIO_EEE_2_5GT;
628 else
629 val &= MDIO_EEE_2_5GT;
630 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV2, val);
631
632 /* RestartAutoNegotiation */
633 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xA400);
634 val |= MDIO_AN_CTRL1_RESTART;
635 phy_write_mmd(phydev, MDIO_MMD_VEND2, 0xA400, val);
636
637 resume_polling(poll_state);
638
639 return 0;
640 }
641
642 static struct fw_header *rtl838x_request_fw(struct phy_device *phydev,
643 const struct firmware *fw,
644 const char *name)
645 {
646 struct device *dev = &phydev->mdio.dev;
647 int err;
648 struct fw_header *h;
649 uint32_t checksum, my_checksum;
650
651 err = request_firmware(&fw, name, dev);
652 if (err < 0)
653 goto out;
654
655 if (fw->size < sizeof(struct fw_header)) {
656 pr_err("Firmware size too small.\n");
657 err = -EINVAL;
658 goto out;
659 }
660
661 h = (struct fw_header *) fw->data;
662 pr_info("Firmware loaded. Size %d, magic: %08x\n", fw->size, h->magic);
663
664 if (h->magic != 0x83808380) {
665 pr_err("Wrong firmware file: MAGIC mismatch.\n");
666 goto out;
667 }
668
669 checksum = h->checksum;
670 h->checksum = 0;
671 my_checksum = ~crc32(0xFFFFFFFFU, fw->data, fw->size);
672 if (checksum != my_checksum) {
673 pr_err("Firmware checksum mismatch.\n");
674 err = -EINVAL;
675 goto out;
676 }
677 h->checksum = checksum;
678
679 return h;
680 out:
681 dev_err(dev, "Unable to load firmware %s (%d)\n", name, err);
682 return NULL;
683 }
684
685 static void rtl821x_phy_setup_package_broadcast(struct phy_device *phydev, bool enable)
686 {
687 int mac = phydev->mdio.addr;
688
689 /* select main page 0 */
690 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
691 /* write to 0x8 to register 0x1d on main page 0 */
692 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL);
693 /* select page 0x266 */
694 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL821X_PAGE_PORT);
695 /* set phy id and target broadcast bitmap in register 0x16 on page 0x266 */
696 phy_write_paged(phydev, RTL83XX_PAGE_RAW, 0x16, (enable?0xff00:0x00) | mac);
697 /* return to main page 0 */
698 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
699 /* write to 0x0 to register 0x1d on main page 0 */
700 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
701 mdelay(1);
702 }
703
704 static int rtl8390_configure_generic(struct phy_device *phydev)
705 {
706 int mac = phydev->mdio.addr;
707 u32 val, phy_id;
708
709 val = phy_read(phydev, 2);
710 phy_id = val << 16;
711 val = phy_read(phydev, 3);
712 phy_id |= val;
713 pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
714
715 /* Read internal PHY ID */
716 phy_write_paged(phydev, 31, 27, 0x0002);
717 val = phy_read_paged(phydev, 31, 28);
718
719 /* Internal RTL8218B, version 2 */
720 phydev_info(phydev, "Detected unknown %x\n", val);
721
722 return 0;
723 }
724
725 static int rtl8380_configure_int_rtl8218b(struct phy_device *phydev)
726 {
727 u32 val, phy_id;
728 int mac = phydev->mdio.addr;
729 struct fw_header *h;
730 u32 *rtl838x_6275B_intPhy_perport;
731 u32 *rtl8218b_6276B_hwEsd_perport;
732
733 val = phy_read(phydev, 2);
734 phy_id = val << 16;
735 val = phy_read(phydev, 3);
736 phy_id |= val;
737 pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
738
739 /* Read internal PHY ID */
740 phy_write_paged(phydev, 31, 27, 0x0002);
741 val = phy_read_paged(phydev, 31, 28);
742 if (val != 0x6275) {
743 phydev_err(phydev, "Expected internal RTL8218B, found PHY-ID %x\n", val);
744 return -1;
745 }
746
747 /* Internal RTL8218B, version 2 */
748 phydev_info(phydev, "Detected internal RTL8218B\n");
749
750 h = rtl838x_request_fw(phydev, &rtl838x_8380_fw, FIRMWARE_838X_8380_1);
751 if (!h)
752 return -1;
753
754 if (h->phy != 0x83800000) {
755 phydev_err(phydev, "Wrong firmware file: PHY mismatch.\n");
756 return -1;
757 }
758
759 rtl838x_6275B_intPhy_perport = (void *)h + sizeof(struct fw_header) + h->parts[8].start;
760 rtl8218b_6276B_hwEsd_perport = (void *)h + sizeof(struct fw_header) + h->parts[9].start;
761
762 // Currently not used
763 // if (sw_r32(RTL838X_DMY_REG31) == 0x1) {
764 // int ipd_flag = 1;
765 // }
766
767 val = phy_read(phydev, MII_BMCR);
768 if (val & BMCR_PDOWN)
769 rtl8380_int_phy_on_off(phydev, true);
770 else
771 rtl8380_phy_reset(phydev);
772 msleep(100);
773
774 /* Ready PHY for patch */
775 for (int p = 0; p < 8; p++) {
776 phy_package_port_write_paged(phydev, p, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL821X_PAGE_PATCH);
777 phy_package_port_write_paged(phydev, p, RTL83XX_PAGE_RAW, 0x10, 0x0010);
778 }
779 msleep(500);
780 for (int p = 0; p < 8; p++) {
781 int i;
782
783 for (i = 0; i < 100 ; i++) {
784 val = phy_package_port_read_paged(phydev, p, RTL821X_PAGE_STATE, 0x10);
785 if (val & 0x40)
786 break;
787 }
788 if (i >= 100) {
789 phydev_err(phydev,
790 "ERROR: Port %d not ready for patch.\n",
791 mac + p);
792 return -1;
793 }
794 }
795 for (int p = 0; p < 8; p++) {
796 int i;
797
798 i = 0;
799 while (rtl838x_6275B_intPhy_perport[i * 2]) {
800 phy_package_port_write_paged(phydev, p, RTL83XX_PAGE_RAW,
801 rtl838x_6275B_intPhy_perport[i * 2],
802 rtl838x_6275B_intPhy_perport[i * 2 + 1]);
803 i++;
804 }
805 i = 0;
806 while (rtl8218b_6276B_hwEsd_perport[i * 2]) {
807 phy_package_port_write_paged(phydev, p, RTL83XX_PAGE_RAW,
808 rtl8218b_6276B_hwEsd_perport[i * 2],
809 rtl8218b_6276B_hwEsd_perport[i * 2 + 1]);
810 i++;
811 }
812 }
813
814 return 0;
815 }
816
817 static int rtl8380_configure_ext_rtl8218b(struct phy_device *phydev)
818 {
819 u32 val, ipd, phy_id;
820 int mac = phydev->mdio.addr;
821 struct fw_header *h;
822 u32 *rtl8380_rtl8218b_perchip;
823 u32 *rtl8218B_6276B_rtl8380_perport;
824 u32 *rtl8380_rtl8218b_perport;
825
826 if (soc_info.family == RTL8380_FAMILY_ID && mac != 0 && mac != 16) {
827 phydev_err(phydev, "External RTL8218B must have PHY-IDs 0 or 16!\n");
828 return -1;
829 }
830 val = phy_read(phydev, 2);
831 phy_id = val << 16;
832 val = phy_read(phydev, 3);
833 phy_id |= val;
834 pr_info("Phy on MAC %d: %x\n", mac, phy_id);
835
836 /* Read internal PHY ID */
837 phy_write_paged(phydev, 31, 27, 0x0002);
838 val = phy_read_paged(phydev, 31, 28);
839 if (val != RTL821X_CHIP_ID) {
840 phydev_err(phydev, "Expected external RTL8218B, found PHY-ID %x\n", val);
841 return -1;
842 }
843 phydev_info(phydev, "Detected external RTL8218B\n");
844
845 h = rtl838x_request_fw(phydev, &rtl838x_8218b_fw, FIRMWARE_838X_8218b_1);
846 if (!h)
847 return -1;
848
849 if (h->phy != 0x8218b000) {
850 phydev_err(phydev, "Wrong firmware file: PHY mismatch.\n");
851 return -1;
852 }
853
854 rtl8380_rtl8218b_perchip = (void *)h + sizeof(struct fw_header) + h->parts[0].start;
855 rtl8218B_6276B_rtl8380_perport = (void *)h + sizeof(struct fw_header) + h->parts[1].start;
856 rtl8380_rtl8218b_perport = (void *)h + sizeof(struct fw_header) + h->parts[2].start;
857
858 val = phy_read(phydev, MII_BMCR);
859 if (val & BMCR_PDOWN)
860 rtl8380_int_phy_on_off(phydev, true);
861 else
862 rtl8380_phy_reset(phydev);
863
864 msleep(100);
865
866 /* Get Chip revision */
867 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
868 phy_write_paged(phydev, RTL83XX_PAGE_RAW, 0x1b, 0x4);
869 val = phy_read_paged(phydev, RTL83XX_PAGE_RAW, 0x1c);
870
871 phydev_info(phydev, "Detected chip revision %04x\n", val);
872
873 for (int i = 0; rtl8380_rtl8218b_perchip[i * 3] &&
874 rtl8380_rtl8218b_perchip[i * 3 + 1]; i++) {
875 phy_package_port_write_paged(phydev, rtl8380_rtl8218b_perchip[i * 3],
876 RTL83XX_PAGE_RAW, rtl8380_rtl8218b_perchip[i * 3 + 1],
877 rtl8380_rtl8218b_perchip[i * 3 + 2]);
878 }
879
880 /* Enable PHY */
881 for (int i = 0; i < 8; i++) {
882 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
883 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, 0x00, 0x1140);
884 }
885 mdelay(100);
886
887 /* Request patch */
888 for (int i = 0; i < 8; i++) {
889 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL821X_PAGE_PATCH);
890 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, 0x10, 0x0010);
891 }
892
893 mdelay(300);
894
895 /* Verify patch readiness */
896 for (int i = 0; i < 8; i++) {
897 int l;
898
899 for (l = 0; l < 100; l++) {
900 val = phy_package_port_read_paged(phydev, i, RTL821X_PAGE_STATE, 0x10);
901 if (val & 0x40)
902 break;
903 }
904 if (l >= 100) {
905 phydev_err(phydev, "Could not patch PHY\n");
906 return -1;
907 }
908 }
909
910 /* Use Broadcast ID method for patching */
911 rtl821x_phy_setup_package_broadcast(phydev, true);
912
913 phy_write_paged(phydev, RTL83XX_PAGE_RAW, 30, 8);
914 phy_write_paged(phydev, 0x26e, 17, 0xb);
915 phy_write_paged(phydev, 0x26e, 16, 0x2);
916 mdelay(1);
917 ipd = phy_read_paged(phydev, 0x26e, 19);
918 phy_write_paged(phydev, 0, 30, 0);
919 ipd = (ipd >> 4) & 0xf; /* unused ? */
920
921 for (int i = 0; rtl8218B_6276B_rtl8380_perport[i * 2]; i++) {
922 phy_write_paged(phydev, RTL83XX_PAGE_RAW, rtl8218B_6276B_rtl8380_perport[i * 2],
923 rtl8218B_6276B_rtl8380_perport[i * 2 + 1]);
924 }
925
926 /* Disable broadcast ID */
927 rtl821x_phy_setup_package_broadcast(phydev, false);
928
929 return 0;
930 }
931
932 static int rtl8218b_ext_match_phy_device(struct phy_device *phydev)
933 {
934 int addr = phydev->mdio.addr;
935
936 /* Both the RTL8214FC and the external RTL8218B have the same
937 * PHY ID. On the RTL838x, the RTL8218B can only be attached_dev
938 * at PHY IDs 0-7, while the RTL8214FC must be attached via
939 * the pair of SGMII/1000Base-X with higher PHY-IDs
940 */
941 if (soc_info.family == RTL8380_FAMILY_ID)
942 return phydev->phy_id == PHY_ID_RTL8218B_E && addr < 8;
943 else
944 return phydev->phy_id == PHY_ID_RTL8218B_E;
945 }
946
947 static bool rtl8214fc_media_is_fibre(struct phy_device *phydev)
948 {
949 int mac = phydev->mdio.addr;
950
951 static int reg[] = {16, 19, 20, 21};
952 u32 val;
953
954 phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL);
955 val = phy_package_read_paged(phydev, RTL821X_PAGE_PORT, reg[mac % 4]);
956 phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
957
958 if (val & BMCR_PDOWN)
959 return false;
960
961 return true;
962 }
963
964 static void rtl8214fc_power_set(struct phy_device *phydev, int port, bool on)
965 {
966 char *state = on ? "on" : "off";
967
968 if (port == PORT_FIBRE) {
969 pr_info("%s: Powering %s FIBRE (port %d)\n", __func__, state, phydev->mdio.addr);
970 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_FIBRE);
971 } else {
972 pr_info("%s: Powering %s COPPER (port %d)\n", __func__, state, phydev->mdio.addr);
973 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
974 }
975
976 if (on) {
977 phy_modify_paged(phydev, RTL821X_PAGE_POWER, 0x10, BMCR_PDOWN, 0);
978 } else {
979 phy_modify_paged(phydev, RTL821X_PAGE_POWER, 0x10, 0, BMCR_PDOWN);
980 }
981
982 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
983 }
984
985 static int rtl8214fc_suspend(struct phy_device *phydev)
986 {
987 rtl8214fc_power_set(phydev, PORT_MII, false);
988 rtl8214fc_power_set(phydev, PORT_FIBRE, false);
989
990 return 0;
991 }
992
993 static int rtl8214fc_resume(struct phy_device *phydev)
994 {
995 if (rtl8214fc_media_is_fibre(phydev)) {
996 rtl8214fc_power_set(phydev, PORT_MII, false);
997 rtl8214fc_power_set(phydev, PORT_FIBRE, true);
998 } else {
999 rtl8214fc_power_set(phydev, PORT_FIBRE, false);
1000 rtl8214fc_power_set(phydev, PORT_MII, true);
1001 }
1002
1003 return 0;
1004 }
1005
1006 static void rtl8214fc_media_set(struct phy_device *phydev, bool set_fibre)
1007 {
1008 int mac = phydev->mdio.addr;
1009
1010 static int reg[] = {16, 19, 20, 21};
1011 int val;
1012
1013 pr_info("%s: port %d, set_fibre: %d\n", __func__, mac, set_fibre);
1014 phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL);
1015 val = phy_package_read_paged(phydev, RTL821X_PAGE_PORT, reg[mac % 4]);
1016
1017 val |= BIT(10);
1018 if (set_fibre) {
1019 val &= ~BMCR_PDOWN;
1020 } else {
1021 val |= BMCR_PDOWN;
1022 }
1023
1024 phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL);
1025 phy_package_write_paged(phydev, RTL821X_PAGE_PORT, reg[mac % 4], val);
1026 phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1027
1028 if (!phydev->suspended) {
1029 if (set_fibre) {
1030 rtl8214fc_power_set(phydev, PORT_MII, false);
1031 rtl8214fc_power_set(phydev, PORT_FIBRE, true);
1032 } else {
1033 rtl8214fc_power_set(phydev, PORT_FIBRE, false);
1034 rtl8214fc_power_set(phydev, PORT_MII, true);
1035 }
1036 }
1037 }
1038
1039 static int rtl8214fc_set_port(struct phy_device *phydev, int port)
1040 {
1041 bool is_fibre = (port == PORT_FIBRE ? true : false);
1042 int addr = phydev->mdio.addr;
1043
1044 pr_debug("%s port %d to %d\n", __func__, addr, port);
1045
1046 rtl8214fc_media_set(phydev, is_fibre);
1047
1048 return 0;
1049 }
1050
1051 static int rtl8214fc_get_port(struct phy_device *phydev)
1052 {
1053 int addr = phydev->mdio.addr;
1054
1055 pr_debug("%s: port %d\n", __func__, addr);
1056 if (rtl8214fc_media_is_fibre(phydev))
1057 return PORT_FIBRE;
1058
1059 return PORT_MII;
1060 }
1061
1062 /* Enable EEE on the RTL8218B PHYs
1063 * The method used is not the preferred way (which would be based on the MAC-EEE state,
1064 * but the only way that works since the kernel first enables EEE in the MAC
1065 * and then sets up the PHY. The MAC-based approach would require the oppsite.
1066 */
1067 void rtl8218d_eee_set(struct phy_device *phydev, bool enable)
1068 {
1069 u32 val;
1070 bool an_enabled;
1071
1072 pr_debug("In %s %d, enable %d\n", __func__, phydev->mdio.addr, enable);
1073 /* Set GPHY page to copper */
1074 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1075
1076 val = phy_read(phydev, MII_BMCR);
1077 an_enabled = val & BMCR_ANENABLE;
1078
1079 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
1080 val |= MDIO_EEE_1000T | MDIO_EEE_100TX;
1081 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, enable ? (MDIO_EEE_100TX | MDIO_EEE_1000T) : 0);
1082
1083 /* 500M EEE ability */
1084 val = phy_read_paged(phydev, RTL821X_PAGE_GPHY, 20);
1085 if (enable)
1086 val |= BIT(7);
1087 else
1088 val &= ~BIT(7);
1089 phy_write_paged(phydev, RTL821X_PAGE_GPHY, 20, val);
1090
1091 /* Restart AN if enabled */
1092 if (an_enabled) {
1093 val = phy_read(phydev, MII_BMCR);
1094 val |= BMCR_ANRESTART;
1095 phy_write(phydev, MII_BMCR, val);
1096 }
1097
1098 /* GPHY page back to auto */
1099 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1100 }
1101
1102 static int rtl8218b_get_eee(struct phy_device *phydev,
1103 struct ethtool_eee *e)
1104 {
1105 u32 val;
1106 int addr = phydev->mdio.addr;
1107
1108 pr_debug("In %s, port %d, was enabled: %d\n", __func__, addr, e->eee_enabled);
1109
1110 /* Set GPHY page to copper */
1111 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1112
1113 val = phy_read_paged(phydev, 7, MDIO_AN_EEE_ADV);
1114 if (e->eee_enabled) {
1115 /* Verify vs MAC-based EEE */
1116 e->eee_enabled = !!(val & BIT(7));
1117 if (!e->eee_enabled) {
1118 val = phy_read_paged(phydev, RTL821X_PAGE_MAC, 25);
1119 e->eee_enabled = !!(val & BIT(4));
1120 }
1121 }
1122 pr_debug("%s: enabled: %d\n", __func__, e->eee_enabled);
1123
1124 /* GPHY page to auto */
1125 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1126
1127 return 0;
1128 }
1129
1130 static int rtl8218d_get_eee(struct phy_device *phydev,
1131 struct ethtool_eee *e)
1132 {
1133 u32 val;
1134 int addr = phydev->mdio.addr;
1135
1136 pr_debug("In %s, port %d, was enabled: %d\n", __func__, addr, e->eee_enabled);
1137
1138 /* Set GPHY page to copper */
1139 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1140
1141 val = phy_read_paged(phydev, 7, MDIO_AN_EEE_ADV);
1142 if (e->eee_enabled)
1143 e->eee_enabled = !!(val & BIT(7));
1144 pr_debug("%s: enabled: %d\n", __func__, e->eee_enabled);
1145
1146 /* GPHY page to auto */
1147 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1148
1149 return 0;
1150 }
1151
1152 static int rtl8214fc_set_eee(struct phy_device *phydev,
1153 struct ethtool_eee *e)
1154 {
1155 u32 poll_state;
1156 int port = phydev->mdio.addr;
1157 bool an_enabled;
1158 u32 val;
1159
1160 pr_debug("In %s port %d, enabled %d\n", __func__, port, e->eee_enabled);
1161
1162 if (rtl8214fc_media_is_fibre(phydev)) {
1163 netdev_err(phydev->attached_dev, "Port %d configured for FIBRE", port);
1164 return -ENOTSUPP;
1165 }
1166
1167 poll_state = disable_polling(port);
1168
1169 /* Set GPHY page to copper */
1170 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1171
1172 /* Get auto-negotiation status */
1173 val = phy_read(phydev, MII_BMCR);
1174 an_enabled = val & BMCR_ANENABLE;
1175
1176 pr_info("%s: aneg: %d\n", __func__, an_enabled);
1177 val = phy_read_paged(phydev, RTL821X_PAGE_MAC, 25);
1178 val &= ~BIT(5); /* Use MAC-based EEE */
1179 phy_write_paged(phydev, RTL821X_PAGE_MAC, 25, val);
1180
1181 /* Enable 100M (bit 1) / 1000M (bit 2) EEE */
1182 phy_write_paged(phydev, 7, MDIO_AN_EEE_ADV, e->eee_enabled ? (MDIO_EEE_100TX | MDIO_EEE_1000T) : 0);
1183
1184 /* 500M EEE ability */
1185 val = phy_read_paged(phydev, RTL821X_PAGE_GPHY, 20);
1186 if (e->eee_enabled)
1187 val |= BIT(7);
1188 else
1189 val &= ~BIT(7);
1190
1191 phy_write_paged(phydev, RTL821X_PAGE_GPHY, 20, val);
1192
1193 /* Restart AN if enabled */
1194 if (an_enabled) {
1195 pr_info("%s: doing aneg\n", __func__);
1196 val = phy_read(phydev, MII_BMCR);
1197 val |= BMCR_ANRESTART;
1198 phy_write(phydev, MII_BMCR, val);
1199 }
1200
1201 /* GPHY page back to auto */
1202 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1203
1204 resume_polling(poll_state);
1205
1206 return 0;
1207 }
1208
1209 static int rtl8214fc_get_eee(struct phy_device *phydev,
1210 struct ethtool_eee *e)
1211 {
1212 int addr = phydev->mdio.addr;
1213
1214 pr_debug("In %s port %d, enabled %d\n", __func__, addr, e->eee_enabled);
1215 if (rtl8214fc_media_is_fibre(phydev)) {
1216 netdev_err(phydev->attached_dev, "Port %d configured for FIBRE", addr);
1217 return -ENOTSUPP;
1218 }
1219
1220 return rtl8218b_get_eee(phydev, e);
1221 }
1222
1223 static int rtl8218b_set_eee(struct phy_device *phydev, struct ethtool_eee *e)
1224 {
1225 int port = phydev->mdio.addr;
1226 u64 poll_state;
1227 u32 val;
1228 bool an_enabled;
1229
1230 pr_info("In %s, port %d, enabled %d\n", __func__, port, e->eee_enabled);
1231
1232 poll_state = disable_polling(port);
1233
1234 /* Set GPHY page to copper */
1235 phy_write(phydev, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1236 val = phy_read(phydev, MII_BMCR);
1237 an_enabled = val & BMCR_ANENABLE;
1238
1239 if (e->eee_enabled) {
1240 /* 100/1000M EEE Capability */
1241 phy_write(phydev, 13, 0x0007);
1242 phy_write(phydev, 14, 0x003C);
1243 phy_write(phydev, 13, 0x4007);
1244 phy_write(phydev, 14, 0x0006);
1245
1246 val = phy_read_paged(phydev, RTL821X_PAGE_MAC, 25);
1247 val |= BIT(4);
1248 phy_write_paged(phydev, RTL821X_PAGE_MAC, 25, val);
1249 } else {
1250 /* 100/1000M EEE Capability */
1251 phy_write(phydev, 13, 0x0007);
1252 phy_write(phydev, 14, 0x003C);
1253 phy_write(phydev, 13, 0x0007);
1254 phy_write(phydev, 14, 0x0000);
1255
1256 val = phy_read_paged(phydev, RTL821X_PAGE_MAC, 25);
1257 val &= ~BIT(4);
1258 phy_write_paged(phydev, RTL821X_PAGE_MAC, 25, val);
1259 }
1260
1261 /* Restart AN if enabled */
1262 if (an_enabled) {
1263 val = phy_read(phydev, MII_BMCR);
1264 val |= BMCR_ANRESTART;
1265 phy_write(phydev, MII_BMCR, val);
1266 }
1267
1268 /* GPHY page back to auto */
1269 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1270
1271 pr_info("%s done\n", __func__);
1272 resume_polling(poll_state);
1273
1274 return 0;
1275 }
1276
1277 static int rtl8218d_set_eee(struct phy_device *phydev, struct ethtool_eee *e)
1278 {
1279 int addr = phydev->mdio.addr;
1280 u64 poll_state;
1281
1282 pr_info("In %s, port %d, enabled %d\n", __func__, addr, e->eee_enabled);
1283
1284 poll_state = disable_polling(addr);
1285
1286 rtl8218d_eee_set(phydev, (bool) e->eee_enabled);
1287
1288 resume_polling(poll_state);
1289
1290 return 0;
1291 }
1292
1293 static int rtl8214c_match_phy_device(struct phy_device *phydev)
1294 {
1295 return phydev->phy_id == PHY_ID_RTL8214C;
1296 }
1297
1298 static int rtl8380_configure_rtl8214c(struct phy_device *phydev)
1299 {
1300 u32 phy_id, val;
1301 int mac = phydev->mdio.addr;
1302
1303 val = phy_read(phydev, 2);
1304 phy_id = val << 16;
1305 val = phy_read(phydev, 3);
1306 phy_id |= val;
1307 pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
1308
1309 phydev_info(phydev, "Detected external RTL8214C\n");
1310
1311 /* GPHY auto conf */
1312 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1313
1314 return 0;
1315 }
1316
1317 static int rtl8380_configure_rtl8214fc(struct phy_device *phydev)
1318 {
1319 int mac = phydev->mdio.addr;
1320 struct fw_header *h;
1321 u32 *rtl8380_rtl8214fc_perchip;
1322 u32 *rtl8380_rtl8214fc_perport;
1323 u32 phy_id;
1324 u32 val;
1325
1326 val = phy_read(phydev, 2);
1327 phy_id = val << 16;
1328 val = phy_read(phydev, 3);
1329 phy_id |= val;
1330 pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
1331
1332 /* Read internal PHY id */
1333 phy_write_paged(phydev, 0, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1334 phy_write_paged(phydev, 0x1f, 0x1b, 0x0002);
1335 val = phy_read_paged(phydev, 0x1f, 0x1c);
1336 if (val != RTL821X_CHIP_ID) {
1337 phydev_err(phydev, "Expected external RTL8214FC, found PHY-ID %x\n", val);
1338 return -1;
1339 }
1340 phydev_info(phydev, "Detected external RTL8214FC\n");
1341
1342 h = rtl838x_request_fw(phydev, &rtl838x_8214fc_fw, FIRMWARE_838X_8214FC_1);
1343 if (!h)
1344 return -1;
1345
1346 if (h->phy != 0x8214fc00) {
1347 phydev_err(phydev, "Wrong firmware file: PHY mismatch.\n");
1348 return -1;
1349 }
1350
1351 rtl8380_rtl8214fc_perchip = (void *)h + sizeof(struct fw_header) + h->parts[0].start;
1352
1353 rtl8380_rtl8214fc_perport = (void *)h + sizeof(struct fw_header) + h->parts[1].start;
1354
1355 /* detect phy version */
1356 phy_write_paged(phydev, RTL83XX_PAGE_RAW, 27, 0x0004);
1357 val = phy_read_paged(phydev, RTL83XX_PAGE_RAW, 28);
1358
1359 val = phy_read(phydev, 16);
1360 if (val & BMCR_PDOWN)
1361 rtl8380_rtl8214fc_on_off(phydev, true);
1362 else
1363 rtl8380_phy_reset(phydev);
1364
1365 msleep(100);
1366 phy_write_paged(phydev, 0, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1367
1368 for (int i = 0; rtl8380_rtl8214fc_perchip[i * 3] &&
1369 rtl8380_rtl8214fc_perchip[i * 3 + 1]; i++) {
1370 u32 page = 0;
1371
1372 if (rtl8380_rtl8214fc_perchip[i * 3 + 1] == 0x1f)
1373 page = rtl8380_rtl8214fc_perchip[i * 3 + 2];
1374 if (rtl8380_rtl8214fc_perchip[i * 3 + 1] == 0x13 && page == 0x260) {
1375 val = phy_read_paged(phydev, 0x260, 13);
1376 val = (val & 0x1f00) | (rtl8380_rtl8214fc_perchip[i * 3 + 2] & 0xe0ff);
1377 phy_write_paged(phydev, RTL83XX_PAGE_RAW,
1378 rtl8380_rtl8214fc_perchip[i * 3 + 1], val);
1379 } else {
1380 phy_write_paged(phydev, RTL83XX_PAGE_RAW,
1381 rtl8380_rtl8214fc_perchip[i * 3 + 1],
1382 rtl8380_rtl8214fc_perchip[i * 3 + 2]);
1383 }
1384 }
1385
1386 /* Force copper medium */
1387 for (int i = 0; i < 4; i++) {
1388 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
1389 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1390 }
1391
1392 /* Enable PHY */
1393 for (int i = 0; i < 4; i++) {
1394 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
1395 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, 0x00, 0x1140);
1396 }
1397 mdelay(100);
1398
1399 /* Disable Autosensing */
1400 for (int i = 0; i < 4; i++) {
1401 int l;
1402
1403 for (l = 0; l < 100; l++) {
1404 val = phy_package_port_read_paged(phydev, i, RTL821X_PAGE_GPHY, 0x10);
1405 if ((val & 0x7) >= 3)
1406 break;
1407 }
1408 if (l >= 100) {
1409 phydev_err(phydev, "Could not disable autosensing\n");
1410 return -1;
1411 }
1412 }
1413
1414 /* Request patch */
1415 for (int i = 0; i < 4; i++) {
1416 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL821X_PAGE_PATCH);
1417 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, 0x10, 0x0010);
1418 }
1419 mdelay(300);
1420
1421 /* Verify patch readiness */
1422 for (int i = 0; i < 4; i++) {
1423 int l;
1424
1425 for (l = 0; l < 100; l++) {
1426 val = phy_package_port_read_paged(phydev, i, RTL821X_PAGE_STATE, 0x10);
1427 if (val & 0x40)
1428 break;
1429 }
1430 if (l >= 100) {
1431 phydev_err(phydev, "Could not patch PHY\n");
1432 return -1;
1433 }
1434 }
1435 /* Use Broadcast ID method for patching */
1436 rtl821x_phy_setup_package_broadcast(phydev, true);
1437
1438 for (int i = 0; rtl8380_rtl8214fc_perport[i * 2]; i++) {
1439 phy_write_paged(phydev, RTL83XX_PAGE_RAW, rtl8380_rtl8214fc_perport[i * 2],
1440 rtl8380_rtl8214fc_perport[i * 2 + 1]);
1441 }
1442
1443 /* Disable broadcast ID */
1444 rtl821x_phy_setup_package_broadcast(phydev, false);
1445
1446 /* Auto medium selection */
1447 for (int i = 0; i < 4; i++) {
1448 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
1449 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1450 }
1451
1452 return 0;
1453 }
1454
1455 static int rtl8214fc_match_phy_device(struct phy_device *phydev)
1456 {
1457 int addr = phydev->mdio.addr;
1458
1459 return phydev->phy_id == PHY_ID_RTL8214FC && addr >= 24;
1460 }
1461
1462 static int rtl8380_configure_serdes(struct phy_device *phydev)
1463 {
1464 u32 v;
1465 u32 sds_conf_value;
1466 int i;
1467 struct fw_header *h;
1468 u32 *rtl8380_sds_take_reset;
1469 u32 *rtl8380_sds_common;
1470 u32 *rtl8380_sds01_qsgmii_6275b;
1471 u32 *rtl8380_sds23_qsgmii_6275b;
1472 u32 *rtl8380_sds4_fiber_6275b;
1473 u32 *rtl8380_sds5_fiber_6275b;
1474 u32 *rtl8380_sds_reset;
1475 u32 *rtl8380_sds_release_reset;
1476
1477 phydev_info(phydev, "Detected internal RTL8380 SERDES\n");
1478
1479 h = rtl838x_request_fw(phydev, &rtl838x_8218b_fw, FIRMWARE_838X_8380_1);
1480 if (!h)
1481 return -1;
1482
1483 if (h->magic != 0x83808380) {
1484 phydev_err(phydev, "Wrong firmware file: magic number mismatch.\n");
1485 return -1;
1486 }
1487
1488 rtl8380_sds_take_reset = (void *)h + sizeof(struct fw_header) + h->parts[0].start;
1489
1490 rtl8380_sds_common = (void *)h + sizeof(struct fw_header) + h->parts[1].start;
1491
1492 rtl8380_sds01_qsgmii_6275b = (void *)h + sizeof(struct fw_header) + h->parts[2].start;
1493
1494 rtl8380_sds23_qsgmii_6275b = (void *)h + sizeof(struct fw_header) + h->parts[3].start;
1495
1496 rtl8380_sds4_fiber_6275b = (void *)h + sizeof(struct fw_header) + h->parts[4].start;
1497
1498 rtl8380_sds5_fiber_6275b = (void *)h + sizeof(struct fw_header) + h->parts[5].start;
1499
1500 rtl8380_sds_reset = (void *)h + sizeof(struct fw_header) + h->parts[6].start;
1501
1502 rtl8380_sds_release_reset = (void *)h + sizeof(struct fw_header) + h->parts[7].start;
1503
1504 /* Back up serdes power off value */
1505 sds_conf_value = sw_r32(RTL838X_SDS_CFG_REG);
1506 pr_info("SDS power down value: %x\n", sds_conf_value);
1507
1508 /* take serdes into reset */
1509 i = 0;
1510 while (rtl8380_sds_take_reset[2 * i]) {
1511 sw_w32(rtl8380_sds_take_reset[2 * i + 1], rtl8380_sds_take_reset[2 * i]);
1512 i++;
1513 udelay(1000);
1514 }
1515
1516 /* apply common serdes patch */
1517 i = 0;
1518 while (rtl8380_sds_common[2 * i]) {
1519 sw_w32(rtl8380_sds_common[2 * i + 1], rtl8380_sds_common[2 * i]);
1520 i++;
1521 udelay(1000);
1522 }
1523
1524 /* internal R/W enable */
1525 sw_w32(3, RTL838X_INT_RW_CTRL);
1526
1527 /* SerDes ports 4 and 5 are FIBRE ports */
1528 sw_w32_mask(0x7 | 0x38, 1 | (1 << 3), RTL838X_INT_MODE_CTRL);
1529
1530 /* SerDes module settings, SerDes 0-3 are QSGMII */
1531 v = 0x6 << 25 | 0x6 << 20 | 0x6 << 15 | 0x6 << 10;
1532 /* SerDes 4 and 5 are 1000BX FIBRE */
1533 v |= 0x4 << 5 | 0x4;
1534 sw_w32(v, RTL838X_SDS_MODE_SEL);
1535
1536 pr_info("PLL control register: %x\n", sw_r32(RTL838X_PLL_CML_CTRL));
1537 sw_w32_mask(0xfffffff0, 0xaaaaaaaf & 0xf, RTL838X_PLL_CML_CTRL);
1538 i = 0;
1539 while (rtl8380_sds01_qsgmii_6275b[2 * i]) {
1540 sw_w32(rtl8380_sds01_qsgmii_6275b[2 * i + 1],
1541 rtl8380_sds01_qsgmii_6275b[2 * i]);
1542 i++;
1543 }
1544
1545 i = 0;
1546 while (rtl8380_sds23_qsgmii_6275b[2 * i]) {
1547 sw_w32(rtl8380_sds23_qsgmii_6275b[2 * i + 1], rtl8380_sds23_qsgmii_6275b[2 * i]);
1548 i++;
1549 }
1550
1551 i = 0;
1552 while (rtl8380_sds4_fiber_6275b[2 * i]) {
1553 sw_w32(rtl8380_sds4_fiber_6275b[2 * i + 1], rtl8380_sds4_fiber_6275b[2 * i]);
1554 i++;
1555 }
1556
1557 i = 0;
1558 while (rtl8380_sds5_fiber_6275b[2 * i]) {
1559 sw_w32(rtl8380_sds5_fiber_6275b[2 * i + 1], rtl8380_sds5_fiber_6275b[2 * i]);
1560 i++;
1561 }
1562
1563 i = 0;
1564 while (rtl8380_sds_reset[2 * i]) {
1565 sw_w32(rtl8380_sds_reset[2 * i + 1], rtl8380_sds_reset[2 * i]);
1566 i++;
1567 }
1568
1569 i = 0;
1570 while (rtl8380_sds_release_reset[2 * i]) {
1571 sw_w32(rtl8380_sds_release_reset[2 * i + 1], rtl8380_sds_release_reset[2 * i]);
1572 i++;
1573 }
1574
1575 pr_info("SDS power down value now: %x\n", sw_r32(RTL838X_SDS_CFG_REG));
1576 sw_w32(sds_conf_value, RTL838X_SDS_CFG_REG);
1577
1578 pr_info("Configuration of SERDES done\n");
1579
1580 return 0;
1581 }
1582
1583 static int rtl8390_configure_serdes(struct phy_device *phydev)
1584 {
1585 phydev_info(phydev, "Detected internal RTL8390 SERDES\n");
1586
1587 /* In autoneg state, force link, set SR4_CFG_EN_LINK_FIB1G */
1588 sw_w32_mask(0, 1 << 18, RTL839X_SDS12_13_XSG0 + 0x0a);
1589
1590 /* Disable EEE: Clear FRE16_EEE_RSG_FIB1G, FRE16_EEE_STD_FIB1G,
1591 * FRE16_C1_PWRSAV_EN_FIB1G, FRE16_C2_PWRSAV_EN_FIB1G
1592 * and FRE16_EEE_QUIET_FIB1G
1593 */
1594 sw_w32_mask(0x1f << 10, 0, RTL839X_SDS12_13_XSG0 + 0xe0);
1595
1596 return 0;
1597 }
1598
1599 void rtl9300_sds_field_w(int sds, u32 page, u32 reg, int end_bit, int start_bit, u32 v)
1600 {
1601 int l = end_bit - start_bit + 1;
1602 u32 data = v;
1603
1604 if (l < 32) {
1605 u32 mask = BIT(l) - 1;
1606
1607 data = rtl930x_read_sds_phy(sds, page, reg);
1608 data &= ~(mask << start_bit);
1609 data |= (v & mask) << start_bit;
1610 }
1611
1612 rtl930x_write_sds_phy(sds, page, reg, data);
1613 }
1614
1615 u32 rtl9300_sds_field_r(int sds, u32 page, u32 reg, int end_bit, int start_bit)
1616 {
1617 int l = end_bit - start_bit + 1;
1618 u32 v = rtl930x_read_sds_phy(sds, page, reg);
1619
1620 if (l >= 32)
1621 return v;
1622
1623 return (v >> start_bit) & (BIT(l) - 1);
1624 }
1625
1626 /* Read the link and speed status of the internal SerDes of the RTL9300
1627 */
1628 static int rtl9300_read_status(struct phy_device *phydev)
1629 {
1630 struct device *dev = &phydev->mdio.dev;
1631 int phy_addr = phydev->mdio.addr;
1632 struct device_node *dn;
1633 u32 sds_num = 0, status, latch_status, mode;
1634
1635 if (dev->of_node) {
1636 dn = dev->of_node;
1637
1638 if (of_property_read_u32(dn, "sds", &sds_num))
1639 sds_num = -1;
1640 pr_info("%s: Port %d, SerDes is %d\n", __func__, phy_addr, sds_num);
1641 } else {
1642 dev_err(dev, "No DT node.\n");
1643 return -EINVAL;
1644 }
1645
1646 if (sds_num < 0)
1647 return 0;
1648
1649 mode = rtl9300_sds_mode_get(sds_num);
1650 pr_info("%s got SDS mode %02x\n", __func__, mode);
1651 if (mode == RTL930X_SDS_OFF)
1652 mode = rtl9300_sds_field_r(sds_num, 0x1f, 9, 11, 7);
1653 if (mode == RTL930X_SDS_MODE_10GBASER) { /* 10GR mode */
1654 status = rtl9300_sds_field_r(sds_num, 0x5, 0, 12, 12);
1655 latch_status = rtl9300_sds_field_r(sds_num, 0x4, 1, 2, 2);
1656 status |= rtl9300_sds_field_r(sds_num, 0x5, 0, 12, 12);
1657 latch_status |= rtl9300_sds_field_r(sds_num, 0x4, 1, 2, 2);
1658 } else {
1659 status = rtl9300_sds_field_r(sds_num, 0x1, 29, 8, 0);
1660 latch_status = rtl9300_sds_field_r(sds_num, 0x1, 30, 8, 0);
1661 status |= rtl9300_sds_field_r(sds_num, 0x1, 29, 8, 0);
1662 latch_status |= rtl9300_sds_field_r(sds_num, 0x1, 30, 8, 0);
1663 }
1664
1665 pr_info("%s link status: status: %d, latch %d\n", __func__, status, latch_status);
1666
1667 if (latch_status) {
1668 phydev->link = true;
1669 if (mode == RTL930X_SDS_MODE_10GBASER) {
1670 phydev->speed = SPEED_10000;
1671 phydev->interface = PHY_INTERFACE_MODE_10GBASER;
1672 } else {
1673 phydev->speed = SPEED_1000;
1674 phydev->interface = PHY_INTERFACE_MODE_1000BASEX;
1675 }
1676
1677 phydev->duplex = DUPLEX_FULL;
1678 }
1679
1680 return 0;
1681 }
1682
1683 void rtl930x_sds_rx_rst(int sds_num, phy_interface_t phy_if)
1684 {
1685 int page = 0x2e; /* 10GR and USXGMII */
1686
1687 if (phy_if == PHY_INTERFACE_MODE_1000BASEX)
1688 page = 0x24;
1689
1690 rtl9300_sds_field_w(sds_num, page, 0x15, 4, 4, 0x1);
1691 mdelay(5);
1692 rtl9300_sds_field_w(sds_num, page, 0x15, 4, 4, 0x0);
1693 }
1694
1695 /* Force PHY modes on 10GBit Serdes
1696 */
1697 void rtl9300_force_sds_mode(int sds, phy_interface_t phy_if)
1698 {
1699 int lc_value;
1700 int sds_mode;
1701 bool lc_on;
1702 int lane_0 = (sds % 2) ? sds - 1 : sds;
1703 u32 v;
1704
1705 pr_info("%s: SDS: %d, mode %d\n", __func__, sds, phy_if);
1706 switch (phy_if) {
1707 case PHY_INTERFACE_MODE_SGMII:
1708 sds_mode = RTL930X_SDS_MODE_SGMII;
1709 lc_on = false;
1710 lc_value = 0x1;
1711 break;
1712
1713 case PHY_INTERFACE_MODE_HSGMII:
1714 sds_mode = RTL930X_SDS_MODE_HSGMII;
1715 lc_value = 0x3;
1716 /* Configure LC */
1717 break;
1718
1719 case PHY_INTERFACE_MODE_1000BASEX:
1720 sds_mode = RTL930X_SDS_MODE_1000BASEX;
1721 lc_on = false;
1722 break;
1723
1724 case PHY_INTERFACE_MODE_2500BASEX:
1725 sds_mode = RTL930X_SDS_MODE_2500BASEX;
1726 lc_value = 0x3;
1727 /* Configure LC */
1728 break;
1729
1730 case PHY_INTERFACE_MODE_10GBASER:
1731 sds_mode = RTL930X_SDS_MODE_10GBASER;
1732 lc_on = true;
1733 lc_value = 0x5;
1734 break;
1735
1736 case PHY_INTERFACE_MODE_NA:
1737 /* This will disable SerDes */
1738 sds_mode = RTL930X_SDS_OFF;
1739 break;
1740
1741 default:
1742 pr_err("%s: unknown serdes mode: %s\n",
1743 __func__, phy_modes(phy_if));
1744 return;
1745 }
1746
1747 pr_info("%s --------------------- serdes %d forcing to %x ...\n", __func__, sds, sds_mode);
1748 /* Power down SerDes */
1749 rtl9300_sds_field_w(sds, 0x20, 0, 7, 6, 0x3);
1750 if (sds == 5) pr_info("%s after %x\n", __func__, rtl930x_read_sds_phy(sds, 0x20, 0));
1751
1752 if (sds == 5) pr_info("%s a %x\n", __func__, rtl930x_read_sds_phy(sds, 0x1f, 9));
1753 /* Force mode enable */
1754 rtl9300_sds_field_w(sds, 0x1f, 9, 6, 6, 0x1);
1755 if (sds == 5) pr_info("%s b %x\n", __func__, rtl930x_read_sds_phy(sds, 0x1f, 9));
1756
1757 /* SerDes off */
1758 rtl9300_sds_field_w(sds, 0x1f, 9, 11, 7, RTL930X_SDS_OFF);
1759
1760 if (phy_if == PHY_INTERFACE_MODE_NA)
1761 return;
1762
1763 if (sds == 5) pr_info("%s c %x\n", __func__, rtl930x_read_sds_phy(sds, 0x20, 18));
1764 /* Enable LC and ring */
1765 rtl9300_sds_field_w(lane_0, 0x20, 18, 3, 0, 0xf);
1766
1767 if (sds == lane_0)
1768 rtl9300_sds_field_w(lane_0, 0x20, 18, 5, 4, 0x1);
1769 else
1770 rtl9300_sds_field_w(lane_0, 0x20, 18, 7, 6, 0x1);
1771
1772 rtl9300_sds_field_w(sds, 0x20, 0, 5, 4, 0x3);
1773
1774 if (lc_on)
1775 rtl9300_sds_field_w(lane_0, 0x20, 18, 11, 8, lc_value);
1776 else
1777 rtl9300_sds_field_w(lane_0, 0x20, 18, 15, 12, lc_value);
1778
1779 /* Force analog LC & ring on */
1780 rtl9300_sds_field_w(lane_0, 0x21, 11, 3, 0, 0xf);
1781
1782 v = lc_on ? 0x3 : 0x1;
1783
1784 if (sds == lane_0)
1785 rtl9300_sds_field_w(lane_0, 0x20, 18, 5, 4, v);
1786 else
1787 rtl9300_sds_field_w(lane_0, 0x20, 18, 7, 6, v);
1788
1789 /* Force SerDes mode */
1790 rtl9300_sds_field_w(sds, 0x1f, 9, 6, 6, 1);
1791 rtl9300_sds_field_w(sds, 0x1f, 9, 11, 7, sds_mode);
1792
1793 /* Toggle LC or Ring */
1794 for (int i = 0; i < 20; i++) {
1795 u32 cr_0, cr_1, cr_2;
1796 u32 m_bit, l_bit;
1797
1798 mdelay(200);
1799
1800 rtl930x_write_sds_phy(lane_0, 0x1f, 2, 53);
1801
1802 m_bit = (lane_0 == sds) ? (4) : (5);
1803 l_bit = (lane_0 == sds) ? (4) : (5);
1804
1805 cr_0 = rtl9300_sds_field_r(lane_0, 0x1f, 20, m_bit, l_bit);
1806 mdelay(10);
1807 cr_1 = rtl9300_sds_field_r(lane_0, 0x1f, 20, m_bit, l_bit);
1808 mdelay(10);
1809 cr_2 = rtl9300_sds_field_r(lane_0, 0x1f, 20, m_bit, l_bit);
1810
1811 if (cr_0 && cr_1 && cr_2) {
1812 u32 t;
1813
1814 if (phy_if != PHY_INTERFACE_MODE_10GBASER)
1815 break;
1816
1817 t = rtl9300_sds_field_r(sds, 0x6, 0x1, 2, 2);
1818 rtl9300_sds_field_w(sds, 0x6, 0x1, 2, 2, 0x1);
1819
1820 /* Reset FSM */
1821 rtl9300_sds_field_w(sds, 0x6, 0x2, 12, 12, 0x1);
1822 mdelay(10);
1823 rtl9300_sds_field_w(sds, 0x6, 0x2, 12, 12, 0x0);
1824 mdelay(10);
1825
1826 /* Need to read this twice */
1827 v = rtl9300_sds_field_r(sds, 0x5, 0, 12, 12);
1828 v = rtl9300_sds_field_r(sds, 0x5, 0, 12, 12);
1829
1830 rtl9300_sds_field_w(sds, 0x6, 0x1, 2, 2, t);
1831
1832 /* Reset FSM again */
1833 rtl9300_sds_field_w(sds, 0x6, 0x2, 12, 12, 0x1);
1834 mdelay(10);
1835 rtl9300_sds_field_w(sds, 0x6, 0x2, 12, 12, 0x0);
1836 mdelay(10);
1837
1838 if (v == 1)
1839 break;
1840 }
1841
1842 m_bit = (phy_if == PHY_INTERFACE_MODE_10GBASER) ? 3 : 1;
1843 l_bit = (phy_if == PHY_INTERFACE_MODE_10GBASER) ? 2 : 0;
1844
1845 rtl9300_sds_field_w(lane_0, 0x21, 11, m_bit, l_bit, 0x2);
1846 mdelay(10);
1847 rtl9300_sds_field_w(lane_0, 0x21, 11, m_bit, l_bit, 0x3);
1848 }
1849
1850 rtl930x_sds_rx_rst(sds, phy_if);
1851
1852 /* Re-enable power */
1853 rtl9300_sds_field_w(sds, 0x20, 0, 7, 6, 0);
1854
1855 pr_info("%s --------------------- serdes %d forced to %x DONE\n", __func__, sds, sds_mode);
1856 }
1857
1858 void rtl9300_sds_tx_config(int sds, phy_interface_t phy_if)
1859 {
1860 /* parameters: rtl9303_80G_txParam_s2 */
1861 int impedance = 0x8;
1862 int pre_amp = 0x2;
1863 int main_amp = 0x9;
1864 int post_amp = 0x2;
1865 int pre_en = 0x1;
1866 int post_en = 0x1;
1867 int page;
1868
1869 switch(phy_if) {
1870 case PHY_INTERFACE_MODE_1000BASEX:
1871 pre_amp = 0x1;
1872 main_amp = 0x9;
1873 post_amp = 0x1;
1874 page = 0x25;
1875 break;
1876 case PHY_INTERFACE_MODE_HSGMII:
1877 case PHY_INTERFACE_MODE_2500BASEX:
1878 pre_amp = 0;
1879 post_amp = 0x8;
1880 pre_en = 0;
1881 page = 0x29;
1882 break;
1883 case PHY_INTERFACE_MODE_10GBASER:
1884 case PHY_INTERFACE_MODE_USXGMII:
1885 case PHY_INTERFACE_MODE_XGMII:
1886 pre_en = 0;
1887 pre_amp = 0;
1888 main_amp = 0x10;
1889 post_amp = 0;
1890 post_en = 0;
1891 page = 0x2f;
1892 break;
1893 default:
1894 pr_err("%s: unsupported PHY mode\n", __func__);
1895 return;
1896 }
1897
1898 rtl9300_sds_field_w(sds, page, 0x01, 15, 11, pre_amp);
1899 rtl9300_sds_field_w(sds, page, 0x06, 4, 0, post_amp);
1900 rtl9300_sds_field_w(sds, page, 0x07, 0, 0, pre_en);
1901 rtl9300_sds_field_w(sds, page, 0x07, 3, 3, post_en);
1902 rtl9300_sds_field_w(sds, page, 0x07, 8, 4, main_amp);
1903 rtl9300_sds_field_w(sds, page, 0x18, 15, 12, impedance);
1904 }
1905
1906 /* Wait for clock ready, this assumes the SerDes is in XGMII mode
1907 * timeout is in ms
1908 */
1909 int rtl9300_sds_clock_wait(int timeout)
1910 {
1911 u32 v;
1912 unsigned long start = jiffies;
1913
1914 do {
1915 rtl9300_sds_field_w(2, 0x1f, 0x2, 15, 0, 53);
1916 v = rtl9300_sds_field_r(2, 0x1f, 20, 5, 4);
1917 if (v == 3)
1918 return 0;
1919 } while (jiffies < start + (HZ / 1000) * timeout);
1920
1921 return 1;
1922 }
1923
1924 void rtl9300_serdes_mac_link_config(int sds, bool tx_normal, bool rx_normal)
1925 {
1926 u32 v10, v1;
1927
1928 v10 = rtl930x_read_sds_phy(sds, 6, 2); /* 10GBit, page 6, reg 2 */
1929 v1 = rtl930x_read_sds_phy(sds, 0, 0); /* 1GBit, page 0, reg 0 */
1930 pr_info("%s: registers before %08x %08x\n", __func__, v10, v1);
1931
1932 v10 &= ~(BIT(13) | BIT(14));
1933 v1 &= ~(BIT(8) | BIT(9));
1934
1935 v10 |= rx_normal ? 0 : BIT(13);
1936 v1 |= rx_normal ? 0 : BIT(9);
1937
1938 v10 |= tx_normal ? 0 : BIT(14);
1939 v1 |= tx_normal ? 0 : BIT(8);
1940
1941 rtl930x_write_sds_phy(sds, 6, 2, v10);
1942 rtl930x_write_sds_phy(sds, 0, 0, v1);
1943
1944 v10 = rtl930x_read_sds_phy(sds, 6, 2);
1945 v1 = rtl930x_read_sds_phy(sds, 0, 0);
1946 pr_info("%s: registers after %08x %08x\n", __func__, v10, v1);
1947 }
1948
1949 void rtl9300_sds_rxcal_dcvs_manual(u32 sds_num, u32 dcvs_id, bool manual, u32 dvcs_list[])
1950 {
1951 if (manual) {
1952 switch(dcvs_id) {
1953 case 0:
1954 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 14, 14, 0x1);
1955 rtl9300_sds_field_w(sds_num, 0x2f, 0x03, 5, 5, dvcs_list[0]);
1956 rtl9300_sds_field_w(sds_num, 0x2f, 0x03, 4, 0, dvcs_list[1]);
1957 break;
1958 case 1:
1959 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 13, 13, 0x1);
1960 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 15, 15, dvcs_list[0]);
1961 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 14, 11, dvcs_list[1]);
1962 break;
1963 case 2:
1964 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 12, 12, 0x1);
1965 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 10, 10, dvcs_list[0]);
1966 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 9, 6, dvcs_list[1]);
1967 break;
1968 case 3:
1969 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 11, 11, 0x1);
1970 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 5, 5, dvcs_list[0]);
1971 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 4, 1, dvcs_list[1]);
1972 break;
1973 case 4:
1974 rtl9300_sds_field_w(sds_num, 0x2e, 0x01, 15, 15, 0x1);
1975 rtl9300_sds_field_w(sds_num, 0x2e, 0x11, 10, 10, dvcs_list[0]);
1976 rtl9300_sds_field_w(sds_num, 0x2e, 0x11, 9, 6, dvcs_list[1]);
1977 break;
1978 case 5:
1979 rtl9300_sds_field_w(sds_num, 0x2e, 0x02, 11, 11, 0x1);
1980 rtl9300_sds_field_w(sds_num, 0x2e, 0x11, 4, 4, dvcs_list[0]);
1981 rtl9300_sds_field_w(sds_num, 0x2e, 0x11, 3, 0, dvcs_list[1]);
1982 break;
1983 default:
1984 break;
1985 }
1986 } else {
1987 switch(dcvs_id) {
1988 case 0:
1989 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 14, 14, 0x0);
1990 break;
1991 case 1:
1992 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 13, 13, 0x0);
1993 break;
1994 case 2:
1995 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 12, 12, 0x0);
1996 break;
1997 case 3:
1998 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 11, 11, 0x0);
1999 break;
2000 case 4:
2001 rtl9300_sds_field_w(sds_num, 0x2e, 0x01, 15, 15, 0x0);
2002 break;
2003 case 5:
2004 rtl9300_sds_field_w(sds_num, 0x2e, 0x02, 11, 11, 0x0);
2005 break;
2006 default:
2007 break;
2008 }
2009 mdelay(1);
2010 }
2011 }
2012
2013 void rtl9300_sds_rxcal_dcvs_get(u32 sds_num, u32 dcvs_id, u32 dcvs_list[])
2014 {
2015 u32 dcvs_sign_out = 0, dcvs_coef_bin = 0;
2016 bool dcvs_manual;
2017
2018 if (!(sds_num % 2))
2019 rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
2020 else
2021 rtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31);
2022
2023 /* ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1] */
2024 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
2025
2026 /* ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x] */
2027 rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x20);
2028
2029 switch(dcvs_id) {
2030 case 0:
2031 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x22);
2032 mdelay(1);
2033
2034 /* ##DCVS0 Read Out */
2035 dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2036 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2037 dcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 14, 14);
2038 break;
2039
2040 case 1:
2041 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x23);
2042 mdelay(1);
2043
2044 /* ##DCVS0 Read Out */
2045 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2046 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2047 dcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 13, 13);
2048 break;
2049
2050 case 2:
2051 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x24);
2052 mdelay(1);
2053
2054 /* ##DCVS0 Read Out */
2055 dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2056 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2057 dcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 12, 12);
2058 break;
2059 case 3:
2060 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x25);
2061 mdelay(1);
2062
2063 /* ##DCVS0 Read Out */
2064 dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2065 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2066 dcvs_manual = rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 11, 11);
2067 break;
2068
2069 case 4:
2070 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x2c);
2071 mdelay(1);
2072
2073 /* ##DCVS0 Read Out */
2074 dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2075 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2076 dcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x01, 15, 15);
2077 break;
2078
2079 case 5:
2080 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x2d);
2081 mdelay(1);
2082
2083 /* ##DCVS0 Read Out */
2084 dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2085 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2086 dcvs_manual = rtl9300_sds_field_r(sds_num, 0x2e, 0x02, 11, 11);
2087 break;
2088
2089 default:
2090 break;
2091 }
2092
2093 if (dcvs_sign_out)
2094 pr_info("%s DCVS %u Sign: -", __func__, dcvs_id);
2095 else
2096 pr_info("%s DCVS %u Sign: +", __func__, dcvs_id);
2097
2098 pr_info("DCVS %u even coefficient = %u", dcvs_id, dcvs_coef_bin);
2099 pr_info("DCVS %u manual = %u", dcvs_id, dcvs_manual);
2100
2101 dcvs_list[0] = dcvs_sign_out;
2102 dcvs_list[1] = dcvs_coef_bin;
2103 }
2104
2105 void rtl9300_sds_rxcal_leq_manual(u32 sds_num, bool manual, u32 leq_gray)
2106 {
2107 if (manual) {
2108 rtl9300_sds_field_w(sds_num, 0x2e, 0x18, 15, 15, 0x1);
2109 rtl9300_sds_field_w(sds_num, 0x2e, 0x16, 14, 10, leq_gray);
2110 } else {
2111 rtl9300_sds_field_w(sds_num, 0x2e, 0x18, 15, 15, 0x0);
2112 mdelay(100);
2113 }
2114 }
2115
2116 void rtl9300_sds_rxcal_leq_offset_manual(u32 sds_num, bool manual, u32 offset)
2117 {
2118 if (manual) {
2119 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 6, 2, offset);
2120 } else {
2121 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 6, 2, offset);
2122 mdelay(1);
2123 }
2124 }
2125
2126 #define GRAY_BITS 5
2127 u32 rtl9300_sds_rxcal_gray_to_binary(u32 gray_code)
2128 {
2129 int i, j, m;
2130 u32 g[GRAY_BITS];
2131 u32 c[GRAY_BITS];
2132 u32 leq_binary = 0;
2133
2134 for(i = 0; i < GRAY_BITS; i++)
2135 g[i] = (gray_code & BIT(i)) >> i;
2136
2137 m = GRAY_BITS - 1;
2138
2139 c[m] = g[m];
2140
2141 for(i = 0; i < m; i++) {
2142 c[i] = g[i];
2143 for(j = i + 1; j < GRAY_BITS; j++)
2144 c[i] = c[i] ^ g[j];
2145 }
2146
2147 for(i = 0; i < GRAY_BITS; i++)
2148 leq_binary += c[i] << i;
2149
2150 return leq_binary;
2151 }
2152
2153 u32 rtl9300_sds_rxcal_leq_read(int sds_num)
2154 {
2155 u32 leq_gray, leq_bin;
2156 bool leq_manual;
2157
2158 if (!(sds_num % 2))
2159 rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
2160 else
2161 rtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31);
2162
2163 /* ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1] */
2164 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
2165
2166 /* ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[0 1 x x x x] */
2167 rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x10);
2168 mdelay(1);
2169
2170 /* ##LEQ Read Out */
2171 leq_gray = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 7, 3);
2172 leq_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x18, 15, 15);
2173 leq_bin = rtl9300_sds_rxcal_gray_to_binary(leq_gray);
2174
2175 pr_info("LEQ_gray: %u, LEQ_bin: %u", leq_gray, leq_bin);
2176 pr_info("LEQ manual: %u", leq_manual);
2177
2178 return leq_bin;
2179 }
2180
2181 void rtl9300_sds_rxcal_vth_manual(u32 sds_num, bool manual, u32 vth_list[])
2182 {
2183 if (manual) {
2184 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, 13, 13, 0x1);
2185 rtl9300_sds_field_w(sds_num, 0x2e, 0x13, 5, 3, vth_list[0]);
2186 rtl9300_sds_field_w(sds_num, 0x2e, 0x13, 2, 0, vth_list[1]);
2187 } else {
2188 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, 13, 13, 0x0);
2189 mdelay(10);
2190 }
2191 }
2192
2193 void rtl9300_sds_rxcal_vth_get(u32 sds_num, u32 vth_list[])
2194 {
2195 u32 vth_manual;
2196
2197 /* ##Page0x1F, Reg0x02[15 0], REG_DBGO_SEL=[0x002F]; */ /* Lane0 */
2198 /* ##Page0x1F, Reg0x02[15 0], REG_DBGO_SEL=[0x0031]; */ /* Lane1 */
2199 if (!(sds_num % 2))
2200 rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
2201 else
2202 rtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31);
2203
2204 /* ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1] */
2205 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
2206 /* ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x] */
2207 rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x20);
2208 /* ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 1 1 0 0] */
2209 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0xc);
2210
2211 mdelay(1);
2212
2213 /* ##VthP & VthN Read Out */
2214 vth_list[0] = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 2, 0); /* v_thp set bin */
2215 vth_list[1] = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 3); /* v_thn set bin */
2216
2217 pr_info("vth_set_bin = %d", vth_list[0]);
2218 pr_info("vth_set_bin = %d", vth_list[1]);
2219
2220 vth_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x0f, 13, 13);
2221 pr_info("Vth Maunal = %d", vth_manual);
2222 }
2223
2224 void rtl9300_sds_rxcal_tap_manual(u32 sds_num, int tap_id, bool manual, u32 tap_list[])
2225 {
2226 if (manual) {
2227 switch(tap_id) {
2228 case 0:
2229 /* ##REG0_LOAD_IN_INIT[0]=1; REG0_TAP0_INIT[5:0]=Tap0_Value */
2230 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);
2231 rtl9300_sds_field_w(sds_num, 0x2f, 0x03, 5, 5, tap_list[0]);
2232 rtl9300_sds_field_w(sds_num, 0x2f, 0x03, 4, 0, tap_list[1]);
2233 break;
2234 case 1:
2235 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);
2236 rtl9300_sds_field_w(sds_num, 0x21, 0x07, 6, 6, tap_list[0]);
2237 rtl9300_sds_field_w(sds_num, 0x2e, 0x09, 11, 6, tap_list[1]);
2238 rtl9300_sds_field_w(sds_num, 0x21, 0x07, 5, 5, tap_list[2]);
2239 rtl9300_sds_field_w(sds_num, 0x2f, 0x12, 5, 0, tap_list[3]);
2240 break;
2241 case 2:
2242 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);
2243 rtl9300_sds_field_w(sds_num, 0x2e, 0x09, 5, 5, tap_list[0]);
2244 rtl9300_sds_field_w(sds_num, 0x2e, 0x09, 4, 0, tap_list[1]);
2245 rtl9300_sds_field_w(sds_num, 0x2e, 0x0a, 11, 11, tap_list[2]);
2246 rtl9300_sds_field_w(sds_num, 0x2e, 0x0a, 10, 6, tap_list[3]);
2247 break;
2248 case 3:
2249 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);
2250 rtl9300_sds_field_w(sds_num, 0x2e, 0x0a, 5, 5, tap_list[0]);
2251 rtl9300_sds_field_w(sds_num, 0x2e, 0x0a, 4, 0, tap_list[1]);
2252 rtl9300_sds_field_w(sds_num, 0x2e, 0x06, 5, 5, tap_list[2]);
2253 rtl9300_sds_field_w(sds_num, 0x2e, 0x06, 4, 0, tap_list[3]);
2254 break;
2255 case 4:
2256 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);
2257 rtl9300_sds_field_w(sds_num, 0x2f, 0x01, 5, 5, tap_list[0]);
2258 rtl9300_sds_field_w(sds_num, 0x2f, 0x01, 4, 0, tap_list[1]);
2259 rtl9300_sds_field_w(sds_num, 0x2e, 0x06, 11, 11, tap_list[2]);
2260 rtl9300_sds_field_w(sds_num, 0x2e, 0x06, 10, 6, tap_list[3]);
2261 break;
2262 default:
2263 break;
2264 }
2265 } else {
2266 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x0);
2267 mdelay(10);
2268 }
2269 }
2270
2271 void rtl9300_sds_rxcal_tap_get(u32 sds_num, u32 tap_id, u32 tap_list[])
2272 {
2273 u32 tap0_sign_out;
2274 u32 tap0_coef_bin;
2275 u32 tap_sign_out_even;
2276 u32 tap_coef_bin_even;
2277 u32 tap_sign_out_odd;
2278 u32 tap_coef_bin_odd;
2279 bool tap_manual;
2280
2281 if (!(sds_num % 2))
2282 rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
2283 else
2284 rtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31);
2285
2286 /* ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1] */
2287 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
2288 /* ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x] */
2289 rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x20);
2290
2291 if (!tap_id) {
2292 /* ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 0 0 0 1] */
2293 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0);
2294 /* ##Tap1 Even Read Out */
2295 mdelay(1);
2296 tap0_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 5);
2297 tap0_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 0);
2298
2299 if (tap0_sign_out == 1)
2300 pr_info("Tap0 Sign : -");
2301 else
2302 pr_info("Tap0 Sign : +");
2303
2304 pr_info("tap0_coef_bin = %d", tap0_coef_bin);
2305
2306 tap_list[0] = tap0_sign_out;
2307 tap_list[1] = tap0_coef_bin;
2308
2309 tap_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x0f, 7, 7);
2310 pr_info("tap0 manual = %u",tap_manual);
2311 } else {
2312 /* ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 0 0 0 1] */
2313 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, tap_id);
2314 mdelay(1);
2315 /* ##Tap1 Even Read Out */
2316 tap_sign_out_even = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 5);
2317 tap_coef_bin_even = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 0);
2318
2319 /* ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 0 1 1 0] */
2320 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, (tap_id + 5));
2321 /* ##Tap1 Odd Read Out */
2322 tap_sign_out_odd = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 5);
2323 tap_coef_bin_odd = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 0);
2324
2325 if (tap_sign_out_even == 1)
2326 pr_info("Tap %u even sign: -", tap_id);
2327 else
2328 pr_info("Tap %u even sign: +", tap_id);
2329
2330 pr_info("Tap %u even coefficient = %u", tap_id, tap_coef_bin_even);
2331
2332 if (tap_sign_out_odd == 1)
2333 pr_info("Tap %u odd sign: -", tap_id);
2334 else
2335 pr_info("Tap %u odd sign: +", tap_id);
2336
2337 pr_info("Tap %u odd coefficient = %u", tap_id,tap_coef_bin_odd);
2338
2339 tap_list[0] = tap_sign_out_even;
2340 tap_list[1] = tap_coef_bin_even;
2341 tap_list[2] = tap_sign_out_odd;
2342 tap_list[3] = tap_coef_bin_odd;
2343
2344 tap_manual = rtl9300_sds_field_r(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7);
2345 pr_info("tap %u manual = %d",tap_id, tap_manual);
2346 }
2347 }
2348
2349 void rtl9300_do_rx_calibration_1(int sds, phy_interface_t phy_mode)
2350 {
2351 /* From both rtl9300_rxCaliConf_serdes_myParam and rtl9300_rxCaliConf_phy_myParam */
2352 int tap0_init_val = 0x1f; /* Initial Decision Fed Equalizer 0 tap */
2353 int vth_min = 0x0;
2354
2355 pr_info("start_1.1.1 initial value for sds %d\n", sds);
2356 rtl930x_write_sds_phy(sds, 6, 0, 0);
2357
2358 /* FGCAL */
2359 rtl9300_sds_field_w(sds, 0x2e, 0x01, 14, 14, 0x00);
2360 rtl9300_sds_field_w(sds, 0x2e, 0x1c, 10, 5, 0x20);
2361 rtl9300_sds_field_w(sds, 0x2f, 0x02, 0, 0, 0x01);
2362
2363 /* DCVS */
2364 rtl9300_sds_field_w(sds, 0x2e, 0x1e, 14, 11, 0x00);
2365 rtl9300_sds_field_w(sds, 0x2e, 0x01, 15, 15, 0x00);
2366 rtl9300_sds_field_w(sds, 0x2e, 0x02, 11, 11, 0x00);
2367 rtl9300_sds_field_w(sds, 0x2e, 0x1c, 4, 0, 0x00);
2368 rtl9300_sds_field_w(sds, 0x2e, 0x1d, 15, 11, 0x00);
2369 rtl9300_sds_field_w(sds, 0x2e, 0x1d, 10, 6, 0x00);
2370 rtl9300_sds_field_w(sds, 0x2e, 0x1d, 5, 1, 0x00);
2371 rtl9300_sds_field_w(sds, 0x2e, 0x02, 10, 6, 0x00);
2372 rtl9300_sds_field_w(sds, 0x2e, 0x11, 4, 0, 0x00);
2373 rtl9300_sds_field_w(sds, 0x2f, 0x00, 3, 0, 0x0f);
2374 rtl9300_sds_field_w(sds, 0x2e, 0x04, 6, 6, 0x01);
2375 rtl9300_sds_field_w(sds, 0x2e, 0x04, 7, 7, 0x01);
2376
2377 /* LEQ (Long Term Equivalent signal level) */
2378 rtl9300_sds_field_w(sds, 0x2e, 0x16, 14, 8, 0x00);
2379
2380 /* DFE (Decision Fed Equalizer) */
2381 rtl9300_sds_field_w(sds, 0x2f, 0x03, 5, 0, tap0_init_val);
2382 rtl9300_sds_field_w(sds, 0x2e, 0x09, 11, 6, 0x00);
2383 rtl9300_sds_field_w(sds, 0x2e, 0x09, 5, 0, 0x00);
2384 rtl9300_sds_field_w(sds, 0x2e, 0x0a, 5, 0, 0x00);
2385 rtl9300_sds_field_w(sds, 0x2f, 0x01, 5, 0, 0x00);
2386 rtl9300_sds_field_w(sds, 0x2f, 0x12, 5, 0, 0x00);
2387 rtl9300_sds_field_w(sds, 0x2e, 0x0a, 11, 6, 0x00);
2388 rtl9300_sds_field_w(sds, 0x2e, 0x06, 5, 0, 0x00);
2389 rtl9300_sds_field_w(sds, 0x2f, 0x01, 5, 0, 0x00);
2390
2391 /* Vth */
2392 rtl9300_sds_field_w(sds, 0x2e, 0x13, 5, 3, 0x07);
2393 rtl9300_sds_field_w(sds, 0x2e, 0x13, 2, 0, 0x07);
2394 rtl9300_sds_field_w(sds, 0x2f, 0x0b, 5, 3, vth_min);
2395
2396 pr_info("end_1.1.1 --\n");
2397
2398 pr_info("start_1.1.2 Load DFE init. value\n");
2399
2400 rtl9300_sds_field_w(sds, 0x2e, 0x0f, 13, 7, 0x7f);
2401
2402 pr_info("end_1.1.2\n");
2403
2404 pr_info("start_1.1.3 disable LEQ training,enable DFE clock\n");
2405
2406 rtl9300_sds_field_w(sds, 0x2e, 0x17, 7, 7, 0x00);
2407 rtl9300_sds_field_w(sds, 0x2e, 0x17, 6, 2, 0x00);
2408 rtl9300_sds_field_w(sds, 0x2e, 0x0c, 8, 8, 0x00);
2409 rtl9300_sds_field_w(sds, 0x2e, 0x0b, 4, 4, 0x01);
2410 rtl9300_sds_field_w(sds, 0x2e, 0x12, 14, 14, 0x00);
2411 rtl9300_sds_field_w(sds, 0x2f, 0x02, 15, 15, 0x00);
2412
2413 pr_info("end_1.1.3 --\n");
2414
2415 pr_info("start_1.1.4 offset cali setting\n");
2416
2417 rtl9300_sds_field_w(sds, 0x2e, 0x0f, 15, 14, 0x03);
2418
2419 pr_info("end_1.1.4\n");
2420
2421 pr_info("start_1.1.5 LEQ and DFE setting\n");
2422
2423 /* TODO: make this work for DAC cables of different lengths */
2424 /* For a 10GBit serdes wit Fibre, SDS 8 or 9 */
2425 if (phy_mode == PHY_INTERFACE_MODE_10GBASER || PHY_INTERFACE_MODE_1000BASEX)
2426 rtl9300_sds_field_w(sds, 0x2e, 0x16, 3, 2, 0x02);
2427 else
2428 pr_err("%s not PHY-based or SerDes, implement DAC!\n", __func__);
2429
2430 /* No serdes, check for Aquantia PHYs */
2431 rtl9300_sds_field_w(sds, 0x2e, 0x16, 3, 2, 0x02);
2432
2433 rtl9300_sds_field_w(sds, 0x2e, 0x0f, 6, 0, 0x5f);
2434 rtl9300_sds_field_w(sds, 0x2f, 0x05, 7, 2, 0x1f);
2435 rtl9300_sds_field_w(sds, 0x2e, 0x19, 9, 5, 0x1f);
2436 rtl9300_sds_field_w(sds, 0x2f, 0x0b, 15, 9, 0x3c);
2437 rtl9300_sds_field_w(sds, 0x2e, 0x0b, 1, 0, 0x03);
2438
2439 pr_info("end_1.1.5\n");
2440 }
2441
2442 void rtl9300_do_rx_calibration_2_1(u32 sds_num)
2443 {
2444 pr_info("start_1.2.1 ForegroundOffsetCal_Manual\n");
2445
2446 /* Gray config endis to 1 */
2447 rtl9300_sds_field_w(sds_num, 0x2f, 0x02, 2, 2, 0x01);
2448
2449 /* ForegroundOffsetCal_Manual(auto mode) */
2450 rtl9300_sds_field_w(sds_num, 0x2e, 0x01, 14, 14, 0x00);
2451
2452 pr_info("end_1.2.1");
2453 }
2454
2455 void rtl9300_do_rx_calibration_2_2(int sds_num)
2456 {
2457 /* Force Rx-Run = 0 */
2458 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 8, 8, 0x0);
2459
2460 rtl930x_sds_rx_rst(sds_num, PHY_INTERFACE_MODE_10GBASER);
2461 }
2462
2463 void rtl9300_do_rx_calibration_2_3(int sds_num)
2464 {
2465 u32 fgcal_binary, fgcal_gray;
2466 u32 offset_range;
2467
2468 pr_info("start_1.2.3 Foreground Calibration\n");
2469
2470 while(1) {
2471 if (!(sds_num % 2))
2472 rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
2473 else
2474 rtl930x_write_sds_phy(sds_num -1 , 0x1f, 0x2, 0x31);
2475
2476 /* ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1] */
2477 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
2478 /* ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x] */
2479 rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x20);
2480 /* ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 1 1 1 1] */
2481 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0xf);
2482 /* ##FGCAL read gray */
2483 fgcal_gray = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 0);
2484 /* ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 1 1 1 0] */
2485 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0xe);
2486 /* ##FGCAL read binary */
2487 fgcal_binary = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 0);
2488
2489 pr_info("%s: fgcal_gray: %d, fgcal_binary %d\n",
2490 __func__, fgcal_gray, fgcal_binary);
2491
2492 offset_range = rtl9300_sds_field_r(sds_num, 0x2e, 0x15, 15, 14);
2493
2494 if (fgcal_binary > 60 || fgcal_binary < 3) {
2495 if (offset_range == 3) {
2496 pr_info("%s: Foreground Calibration result marginal!", __func__);
2497 break;
2498 } else {
2499 offset_range++;
2500 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 15, 14, offset_range);
2501 rtl9300_do_rx_calibration_2_2(sds_num);
2502 }
2503 } else {
2504 break;
2505 }
2506 }
2507 pr_info("%s: end_1.2.3\n", __func__);
2508 }
2509
2510 void rtl9300_do_rx_calibration_2(int sds)
2511 {
2512 rtl930x_sds_rx_rst(sds, PHY_INTERFACE_MODE_10GBASER);
2513 rtl9300_do_rx_calibration_2_1(sds);
2514 rtl9300_do_rx_calibration_2_2(sds);
2515 rtl9300_do_rx_calibration_2_3(sds);
2516 }
2517
2518 void rtl9300_sds_rxcal_3_1(int sds_num, phy_interface_t phy_mode)
2519 {
2520 pr_info("start_1.3.1");
2521
2522 /* ##1.3.1 */
2523 if (phy_mode != PHY_INTERFACE_MODE_10GBASER && phy_mode != PHY_INTERFACE_MODE_1000BASEX)
2524 rtl9300_sds_field_w(sds_num, 0x2e, 0xc, 8, 8, 0);
2525
2526 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 7, 7, 0x0);
2527 rtl9300_sds_rxcal_leq_manual(sds_num, false, 0);
2528
2529 pr_info("end_1.3.1");
2530 }
2531
2532 void rtl9300_sds_rxcal_3_2(int sds_num, phy_interface_t phy_mode)
2533 {
2534 u32 sum10 = 0, avg10, int10;
2535 int dac_long_cable_offset;
2536 bool eq_hold_enabled;
2537 int i;
2538
2539 if (phy_mode == PHY_INTERFACE_MODE_10GBASER || phy_mode == PHY_INTERFACE_MODE_1000BASEX) {
2540 /* rtl9300_rxCaliConf_serdes_myParam */
2541 dac_long_cable_offset = 3;
2542 eq_hold_enabled = true;
2543 } else {
2544 /* rtl9300_rxCaliConf_phy_myParam */
2545 dac_long_cable_offset = 0;
2546 eq_hold_enabled = false;
2547 }
2548
2549 if (phy_mode == PHY_INTERFACE_MODE_1000BASEX)
2550 pr_warn("%s: LEQ only valid for 10GR!\n", __func__);
2551
2552 pr_info("start_1.3.2");
2553
2554 for(i = 0; i < 10; i++) {
2555 sum10 += rtl9300_sds_rxcal_leq_read(sds_num);
2556 mdelay(10);
2557 }
2558
2559 avg10 = (sum10 / 10) + (((sum10 % 10) >= 5) ? 1 : 0);
2560 int10 = sum10 / 10;
2561
2562 pr_info("sum10:%u, avg10:%u, int10:%u", sum10, avg10, int10);
2563
2564 if (phy_mode == PHY_INTERFACE_MODE_10GBASER || phy_mode == PHY_INTERFACE_MODE_1000BASEX) {
2565 if (dac_long_cable_offset) {
2566 rtl9300_sds_rxcal_leq_offset_manual(sds_num, 1, dac_long_cable_offset);
2567 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 7, 7, eq_hold_enabled);
2568 if (phy_mode == PHY_INTERFACE_MODE_10GBASER)
2569 rtl9300_sds_rxcal_leq_manual(sds_num, true, avg10);
2570 } else {
2571 if (sum10 >= 5) {
2572 rtl9300_sds_rxcal_leq_offset_manual(sds_num, 1, 3);
2573 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 7, 7, 0x1);
2574 if (phy_mode == PHY_INTERFACE_MODE_10GBASER)
2575 rtl9300_sds_rxcal_leq_manual(sds_num, true, avg10);
2576 } else {
2577 rtl9300_sds_rxcal_leq_offset_manual(sds_num, 1, 0);
2578 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 7, 7, 0x1);
2579 if (phy_mode == PHY_INTERFACE_MODE_10GBASER)
2580 rtl9300_sds_rxcal_leq_manual(sds_num, true, avg10);
2581 }
2582 }
2583 }
2584
2585 pr_info("Sds:%u LEQ = %u",sds_num, rtl9300_sds_rxcal_leq_read(sds_num));
2586
2587 pr_info("end_1.3.2");
2588 }
2589
2590 void rtl9300_do_rx_calibration_3(int sds_num, phy_interface_t phy_mode)
2591 {
2592 rtl9300_sds_rxcal_3_1(sds_num, phy_mode);
2593
2594 if (phy_mode == PHY_INTERFACE_MODE_10GBASER || phy_mode == PHY_INTERFACE_MODE_1000BASEX)
2595 rtl9300_sds_rxcal_3_2(sds_num, phy_mode);
2596 }
2597
2598 void rtl9300_do_rx_calibration_4_1(int sds_num)
2599 {
2600 u32 vth_list[2] = {0, 0};
2601 u32 tap0_list[4] = {0, 0, 0, 0};
2602
2603 pr_info("start_1.4.1");
2604
2605 /* ##1.4.1 */
2606 rtl9300_sds_rxcal_vth_manual(sds_num, false, vth_list);
2607 rtl9300_sds_rxcal_tap_manual(sds_num, 0, false, tap0_list);
2608 mdelay(200);
2609
2610 pr_info("end_1.4.1");
2611 }
2612
2613 void rtl9300_do_rx_calibration_4_2(u32 sds_num)
2614 {
2615 u32 vth_list[2];
2616 u32 tap_list[4];
2617
2618 pr_info("start_1.4.2");
2619
2620 rtl9300_sds_rxcal_vth_get(sds_num, vth_list);
2621 rtl9300_sds_rxcal_vth_manual(sds_num, true, vth_list);
2622
2623 mdelay(100);
2624
2625 rtl9300_sds_rxcal_tap_get(sds_num, 0, tap_list);
2626 rtl9300_sds_rxcal_tap_manual(sds_num, 0, true, tap_list);
2627
2628 pr_info("end_1.4.2");
2629 }
2630
2631 void rtl9300_do_rx_calibration_4(u32 sds_num)
2632 {
2633 rtl9300_do_rx_calibration_4_1(sds_num);
2634 rtl9300_do_rx_calibration_4_2(sds_num);
2635 }
2636
2637 void rtl9300_do_rx_calibration_5_2(u32 sds_num)
2638 {
2639 u32 tap1_list[4] = {0};
2640 u32 tap2_list[4] = {0};
2641 u32 tap3_list[4] = {0};
2642 u32 tap4_list[4] = {0};
2643
2644 pr_info("start_1.5.2");
2645
2646 rtl9300_sds_rxcal_tap_manual(sds_num, 1, false, tap1_list);
2647 rtl9300_sds_rxcal_tap_manual(sds_num, 2, false, tap2_list);
2648 rtl9300_sds_rxcal_tap_manual(sds_num, 3, false, tap3_list);
2649 rtl9300_sds_rxcal_tap_manual(sds_num, 4, false, tap4_list);
2650
2651 mdelay(30);
2652
2653 pr_info("end_1.5.2");
2654 }
2655
2656 void rtl9300_do_rx_calibration_5(u32 sds_num, phy_interface_t phy_mode)
2657 {
2658 if (phy_mode == PHY_INTERFACE_MODE_10GBASER) /* dfeTap1_4Enable true */
2659 rtl9300_do_rx_calibration_5_2(sds_num);
2660 }
2661
2662
2663 void rtl9300_do_rx_calibration_dfe_disable(u32 sds_num)
2664 {
2665 u32 tap1_list[4] = {0};
2666 u32 tap2_list[4] = {0};
2667 u32 tap3_list[4] = {0};
2668 u32 tap4_list[4] = {0};
2669
2670 rtl9300_sds_rxcal_tap_manual(sds_num, 1, true, tap1_list);
2671 rtl9300_sds_rxcal_tap_manual(sds_num, 2, true, tap2_list);
2672 rtl9300_sds_rxcal_tap_manual(sds_num, 3, true, tap3_list);
2673 rtl9300_sds_rxcal_tap_manual(sds_num, 4, true, tap4_list);
2674
2675 mdelay(10);
2676 }
2677
2678 void rtl9300_do_rx_calibration(int sds, phy_interface_t phy_mode)
2679 {
2680 u32 latch_sts;
2681
2682 rtl9300_do_rx_calibration_1(sds, phy_mode);
2683 rtl9300_do_rx_calibration_2(sds);
2684 rtl9300_do_rx_calibration_4(sds);
2685 rtl9300_do_rx_calibration_5(sds, phy_mode);
2686 mdelay(20);
2687
2688 /* Do this only for 10GR mode, SDS active in mode 0x1a */
2689 if (rtl9300_sds_field_r(sds, 0x1f, 9, 11, 7) == RTL930X_SDS_MODE_10GBASER) {
2690 pr_info("%s: SDS enabled\n", __func__);
2691 latch_sts = rtl9300_sds_field_r(sds, 0x4, 1, 2, 2);
2692 mdelay(1);
2693 latch_sts = rtl9300_sds_field_r(sds, 0x4, 1, 2, 2);
2694 if (latch_sts) {
2695 rtl9300_do_rx_calibration_dfe_disable(sds);
2696 rtl9300_do_rx_calibration_4(sds);
2697 rtl9300_do_rx_calibration_5(sds, phy_mode);
2698 }
2699 }
2700 }
2701
2702 int rtl9300_sds_sym_err_reset(int sds_num, phy_interface_t phy_mode)
2703 {
2704 switch (phy_mode) {
2705 case PHY_INTERFACE_MODE_XGMII:
2706 break;
2707
2708 case PHY_INTERFACE_MODE_10GBASER:
2709 /* Read twice to clear */
2710 rtl930x_read_sds_phy(sds_num, 5, 1);
2711 rtl930x_read_sds_phy(sds_num, 5, 1);
2712 break;
2713
2714 case PHY_INTERFACE_MODE_1000BASEX:
2715 rtl9300_sds_field_w(sds_num, 0x1, 24, 2, 0, 0);
2716 rtl9300_sds_field_w(sds_num, 0x1, 3, 15, 8, 0);
2717 rtl9300_sds_field_w(sds_num, 0x1, 2, 15, 0, 0);
2718 break;
2719
2720 default:
2721 pr_info("%s unsupported phy mode\n", __func__);
2722 return -1;
2723 }
2724
2725 return 0;
2726 }
2727
2728 u32 rtl9300_sds_sym_err_get(int sds_num, phy_interface_t phy_mode)
2729 {
2730 u32 v = 0;
2731
2732 switch (phy_mode) {
2733 case PHY_INTERFACE_MODE_XGMII:
2734 break;
2735
2736 case PHY_INTERFACE_MODE_1000BASEX:
2737 case PHY_INTERFACE_MODE_10GBASER:
2738 v = rtl930x_read_sds_phy(sds_num, 5, 1);
2739 return v & 0xff;
2740
2741 default:
2742 pr_info("%s unsupported PHY-mode\n", __func__);
2743 }
2744
2745 return v;
2746 }
2747
2748 int rtl9300_sds_check_calibration(int sds_num, phy_interface_t phy_mode)
2749 {
2750 u32 errors1, errors2;
2751
2752 rtl9300_sds_sym_err_reset(sds_num, phy_mode);
2753 rtl9300_sds_sym_err_reset(sds_num, phy_mode);
2754
2755 /* Count errors during 1ms */
2756 errors1 = rtl9300_sds_sym_err_get(sds_num, phy_mode);
2757 mdelay(1);
2758 errors2 = rtl9300_sds_sym_err_get(sds_num, phy_mode);
2759
2760 switch (phy_mode) {
2761 case PHY_INTERFACE_MODE_1000BASEX:
2762 case PHY_INTERFACE_MODE_XGMII:
2763 if ((errors2 - errors1 > 100) ||
2764 (errors1 >= 0xffff00) || (errors2 >= 0xffff00)) {
2765 pr_info("%s XSGMII error rate too high\n", __func__);
2766 return 1;
2767 }
2768 break;
2769 case PHY_INTERFACE_MODE_10GBASER:
2770 if (errors2 > 0) {
2771 pr_info("%s 10GBASER error rate too high\n", __func__);
2772 return 1;
2773 }
2774 break;
2775 default:
2776 return 1;
2777 }
2778
2779 return 0;
2780 }
2781
2782 void rtl9300_phy_enable_10g_1g(int sds_num)
2783 {
2784 u32 v;
2785
2786 /* Enable 1GBit PHY */
2787 v = rtl930x_read_sds_phy(sds_num, PHY_PAGE_2, MII_BMCR);
2788 pr_info("%s 1gbit phy: %08x\n", __func__, v);
2789 v &= ~BMCR_PDOWN;
2790 rtl930x_write_sds_phy(sds_num, PHY_PAGE_2, MII_BMCR, v);
2791 pr_info("%s 1gbit phy enabled: %08x\n", __func__, v);
2792
2793 /* Enable 10GBit PHY */
2794 v = rtl930x_read_sds_phy(sds_num, PHY_PAGE_4, MII_BMCR);
2795 pr_info("%s 10gbit phy: %08x\n", __func__, v);
2796 v &= ~BMCR_PDOWN;
2797 rtl930x_write_sds_phy(sds_num, PHY_PAGE_4, MII_BMCR, v);
2798 pr_info("%s 10gbit phy after: %08x\n", __func__, v);
2799
2800 /* dal_longan_construct_mac_default_10gmedia_fiber */
2801 v = rtl930x_read_sds_phy(sds_num, 0x1f, 11);
2802 pr_info("%s set medium: %08x\n", __func__, v);
2803 v |= BIT(1);
2804 rtl930x_write_sds_phy(sds_num, 0x1f, 11, v);
2805 pr_info("%s set medium after: %08x\n", __func__, v);
2806 }
2807
2808 static int rtl9300_sds_10g_idle(int sds_num);
2809 static void rtl9300_serdes_patch(int sds_num);
2810
2811 #define RTL930X_MAC_FORCE_MODE_CTRL (0xCA1C)
2812 int rtl9300_serdes_setup(int port, int sds_num, phy_interface_t phy_mode)
2813 {
2814 int calib_tries = 0;
2815
2816 /* Turn Off Serdes */
2817 rtl9300_sds_rst(sds_num, RTL930X_SDS_OFF);
2818
2819 /* Apply serdes patches */
2820 rtl9300_serdes_patch(sds_num);
2821
2822 /* Maybe use dal_longan_sds_init */
2823
2824 /* dal_longan_construct_serdesConfig_init */ /* Serdes Construct */
2825 rtl9300_phy_enable_10g_1g(sds_num);
2826
2827 /* Disable MAC */
2828 sw_w32_mask(0, 1, RTL930X_MAC_FORCE_MODE_CTRL + 4 * port);
2829 mdelay(20);
2830
2831 /* ----> dal_longan_sds_mode_set */
2832 pr_info("%s: Configuring RTL9300 SERDES %d\n", __func__, sds_num);
2833
2834 /* Configure link to MAC */
2835 rtl9300_serdes_mac_link_config(sds_num, true, true); /* MAC Construct */
2836
2837 /* Re-Enable MAC */
2838 sw_w32_mask(1, 0, RTL930X_MAC_FORCE_MODE_CTRL + 4 * port);
2839
2840 /* Enable SDS in desired mode */
2841 rtl9300_force_sds_mode(sds_num, phy_mode);
2842
2843 /* Enable Fiber RX */
2844 rtl9300_sds_field_w(sds_num, 0x20, 2, 12, 12, 0);
2845
2846 /* Calibrate SerDes receiver in loopback mode */
2847 rtl9300_sds_10g_idle(sds_num);
2848 do {
2849 rtl9300_do_rx_calibration(sds_num, phy_mode);
2850 calib_tries++;
2851 mdelay(50);
2852 } while (rtl9300_sds_check_calibration(sds_num, phy_mode) && calib_tries < 3);
2853 if (calib_tries >= 3)
2854 pr_warn("%s: SerDes RX calibration failed\n", __func__);
2855
2856 /* Leave loopback mode */
2857 rtl9300_sds_tx_config(sds_num, phy_mode);
2858
2859 return 0;
2860 }
2861
2862 static int rtl9300_sds_10g_idle(int sds_num)
2863 {
2864 bool busy;
2865 int i = 0;
2866
2867 do {
2868 if (sds_num % 2) {
2869 rtl9300_sds_field_w(sds_num - 1, 0x1f, 0x2, 15, 0, 53);
2870 busy = !!rtl9300_sds_field_r(sds_num - 1, 0x1f, 0x14, 1, 1);
2871 } else {
2872 rtl9300_sds_field_w(sds_num, 0x1f, 0x2, 15, 0, 53);
2873 busy = !!rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 0, 0);
2874 }
2875 i++;
2876 } while (busy && i < 100);
2877
2878 if (i < 100)
2879 return 0;
2880
2881 pr_warn("%s WARNING: Waiting for RX idle timed out, SDS %d\n", __func__, sds_num);
2882 return -EIO;
2883 }
2884
2885 typedef struct {
2886 u8 page;
2887 u8 reg;
2888 u16 data;
2889 } sds_config;
2890
2891 sds_config rtl9300_a_sds_10gr_lane0[] =
2892 {
2893 /* 1G */
2894 {0x00, 0x0E, 0x3053}, {0x01, 0x14, 0x0100}, {0x21, 0x03, 0x8206},
2895 {0x21, 0x05, 0x40B0}, {0x21, 0x06, 0x0010}, {0x21, 0x07, 0xF09F},
2896 {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009}, {0x21, 0x0E, 0x0000},
2897 {0x21, 0x0F, 0x0008}, {0x24, 0x00, 0x0668}, {0x24, 0x02, 0xD020},
2898 {0x24, 0x06, 0xC000}, {0x24, 0x0B, 0x1892}, {0x24, 0x0F, 0xFFDF},
2899 {0x24, 0x12, 0x03C4}, {0x24, 0x13, 0x027F}, {0x24, 0x14, 0x1311},
2900 {0x24, 0x16, 0x00C9}, {0x24, 0x17, 0xA100}, {0x24, 0x1A, 0x0001},
2901 {0x24, 0x1C, 0x0400}, {0x25, 0x01, 0x0300}, {0x25, 0x02, 0x1017},
2902 {0x25, 0x03, 0xFFDF}, {0x25, 0x05, 0x7F7C}, {0x25, 0x07, 0x8100},
2903 {0x25, 0x08, 0x0001}, {0x25, 0x09, 0xFFD4}, {0x25, 0x0A, 0x7C2F},
2904 {0x25, 0x0E, 0x003F}, {0x25, 0x0F, 0x0121}, {0x25, 0x10, 0x0020},
2905 {0x25, 0x11, 0x8840}, {0x2B, 0x13, 0x0050}, {0x2B, 0x18, 0x8E88},
2906 {0x2B, 0x19, 0x4902}, {0x2B, 0x1D, 0x2501}, {0x2D, 0x13, 0x0050},
2907 {0x2D, 0x18, 0x8E88}, {0x2D, 0x19, 0x4902}, {0x2D, 0x1D, 0x2641},
2908 {0x2F, 0x13, 0x0050}, {0x2F, 0x18, 0x8E88}, {0x2F, 0x19, 0x4902},
2909 {0x2F, 0x1D, 0x66E1},
2910 /* 3.125G */
2911 {0x28, 0x00, 0x0668}, {0x28, 0x02, 0xD020}, {0x28, 0x06, 0xC000},
2912 {0x28, 0x0B, 0x1892}, {0x28, 0x0F, 0xFFDF}, {0x28, 0x12, 0x01C4},
2913 {0x28, 0x13, 0x027F}, {0x28, 0x14, 0x1311}, {0x28, 0x16, 0x00C9},
2914 {0x28, 0x17, 0xA100}, {0x28, 0x1A, 0x0001}, {0x28, 0x1C, 0x0400},
2915 {0x29, 0x01, 0x0300}, {0x29, 0x02, 0x1017}, {0x29, 0x03, 0xFFDF},
2916 {0x29, 0x05, 0x7F7C}, {0x29, 0x07, 0x8100}, {0x29, 0x08, 0x0001},
2917 {0x29, 0x09, 0xFFD4}, {0x29, 0x0A, 0x7C2F}, {0x29, 0x0E, 0x003F},
2918 {0x29, 0x0F, 0x0121}, {0x29, 0x10, 0x0020}, {0x29, 0x11, 0x8840},
2919 /* 10G */
2920 {0x06, 0x0D, 0x0F00}, {0x06, 0x00, 0x0000}, {0x06, 0x01, 0xC800},
2921 {0x21, 0x03, 0x8206}, {0x21, 0x05, 0x40B0}, {0x21, 0x06, 0x0010},
2922 {0x21, 0x07, 0xF09F}, {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009},
2923 {0x21, 0x0E, 0x0000}, {0x21, 0x0F, 0x0008}, {0x2E, 0x00, 0xA668},
2924 {0x2E, 0x02, 0xD020}, {0x2E, 0x06, 0xC000}, {0x2E, 0x0B, 0x1892},
2925 {0x2E, 0x0F, 0xFFDF}, {0x2E, 0x11, 0x8280}, {0x2E, 0x12, 0x0044},
2926 {0x2E, 0x13, 0x027F}, {0x2E, 0x14, 0x1311}, {0x2E, 0x17, 0xA100},
2927 {0x2E, 0x1A, 0x0001}, {0x2E, 0x1C, 0x0400}, {0x2F, 0x01, 0x0300},
2928 {0x2F, 0x02, 0x1217}, {0x2F, 0x03, 0xFFDF}, {0x2F, 0x05, 0x7F7C},
2929 {0x2F, 0x07, 0x80C4}, {0x2F, 0x08, 0x0001}, {0x2F, 0x09, 0xFFD4},
2930 {0x2F, 0x0A, 0x7C2F}, {0x2F, 0x0E, 0x003F}, {0x2F, 0x0F, 0x0121},
2931 {0x2F, 0x10, 0x0020}, {0x2F, 0x11, 0x8840}, {0x2F, 0x14, 0xE008},
2932 {0x2B, 0x13, 0x0050}, {0x2B, 0x18, 0x8E88}, {0x2B, 0x19, 0x4902},
2933 {0x2B, 0x1D, 0x2501}, {0x2D, 0x13, 0x0050}, {0x2D, 0x17, 0x4109},
2934 {0x2D, 0x18, 0x8E88}, {0x2D, 0x19, 0x4902}, {0x2D, 0x1C, 0x1109},
2935 {0x2D, 0x1D, 0x2641}, {0x2F, 0x13, 0x0050}, {0x2F, 0x18, 0x8E88},
2936 {0x2F, 0x19, 0x4902}, {0x2F, 0x1D, 0x76E1},
2937 };
2938
2939 sds_config rtl9300_a_sds_10gr_lane1[] =
2940 {
2941 /* 1G */
2942 {0x00, 0x0E, 0x3053}, {0x01, 0x14, 0x0100}, {0x21, 0x03, 0x8206},
2943 {0x21, 0x06, 0x0010}, {0x21, 0x07, 0xF09F}, {0x21, 0x0A, 0x0003},
2944 {0x21, 0x0B, 0x0005}, {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009},
2945 {0x21, 0x0E, 0x0000}, {0x21, 0x0F, 0x0008}, {0x24, 0x00, 0x0668},
2946 {0x24, 0x02, 0xD020}, {0x24, 0x06, 0xC000}, {0x24, 0x0B, 0x1892},
2947 {0x24, 0x0F, 0xFFDF}, {0x24, 0x12, 0x03C4}, {0x24, 0x13, 0x027F},
2948 {0x24, 0x14, 0x1311}, {0x24, 0x16, 0x00C9}, {0x24, 0x17, 0xA100},
2949 {0x24, 0x1A, 0x0001}, {0x24, 0x1C, 0x0400}, {0x25, 0x00, 0x820F},
2950 {0x25, 0x01, 0x0300}, {0x25, 0x02, 0x1017}, {0x25, 0x03, 0xFFDF},
2951 {0x25, 0x05, 0x7F7C}, {0x25, 0x07, 0x8100}, {0x25, 0x08, 0x0001},
2952 {0x25, 0x09, 0xFFD4}, {0x25, 0x0A, 0x7C2F}, {0x25, 0x0E, 0x003F},
2953 {0x25, 0x0F, 0x0121}, {0x25, 0x10, 0x0020}, {0x25, 0x11, 0x8840},
2954 {0x2B, 0x13, 0x3D87}, {0x2B, 0x14, 0x3108}, {0x2D, 0x13, 0x3C87},
2955 {0x2D, 0x14, 0x1808},
2956 /* 3.125G */
2957 {0x28, 0x00, 0x0668}, {0x28, 0x02, 0xD020}, {0x28, 0x06, 0xC000},
2958 {0x28, 0x0B, 0x1892}, {0x28, 0x0F, 0xFFDF}, {0x28, 0x12, 0x01C4},
2959 {0x28, 0x13, 0x027F}, {0x28, 0x14, 0x1311}, {0x28, 0x16, 0x00C9},
2960 {0x28, 0x17, 0xA100}, {0x28, 0x1A, 0x0001}, {0x28, 0x1C, 0x0400},
2961 {0x29, 0x00, 0x820F}, {0x29, 0x01, 0x0300}, {0x29, 0x02, 0x1017},
2962 {0x29, 0x03, 0xFFDF}, {0x29, 0x05, 0x7F7C}, {0x29, 0x07, 0x8100},
2963 {0x29, 0x08, 0x0001}, {0x29, 0x0A, 0x7C2F}, {0x29, 0x0E, 0x003F},
2964 {0x29, 0x0F, 0x0121}, {0x29, 0x10, 0x0020}, {0x29, 0x11, 0x8840},
2965 /* 10G */
2966 {0x06, 0x0D, 0x0F00}, {0x06, 0x00, 0x0000}, {0x06, 0x01, 0xC800},
2967 {0x21, 0x03, 0x8206}, {0x21, 0x05, 0x40B0}, {0x21, 0x06, 0x0010},
2968 {0x21, 0x07, 0xF09F}, {0x21, 0x0A, 0x0003}, {0x21, 0x0B, 0x0005},
2969 {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009}, {0x21, 0x0E, 0x0000},
2970 {0x21, 0x0F, 0x0008}, {0x2E, 0x00, 0xA668}, {0x2E, 0x02, 0xD020},
2971 {0x2E, 0x06, 0xC000}, {0x2E, 0x0B, 0x1892}, {0x2E, 0x0F, 0xFFDF},
2972 {0x2E, 0x11, 0x8280}, {0x2E, 0x12, 0x0044}, {0x2E, 0x13, 0x027F},
2973 {0x2E, 0x14, 0x1311}, {0x2E, 0x17, 0xA100}, {0x2E, 0x1A, 0x0001},
2974 {0x2E, 0x1C, 0x0400}, {0x2F, 0x00, 0x820F}, {0x2F, 0x01, 0x0300},
2975 {0x2F, 0x02, 0x1217}, {0x2F, 0x03, 0xFFDF}, {0x2F, 0x05, 0x7F7C},
2976 {0x2F, 0x07, 0x80C4}, {0x2F, 0x08, 0x0001}, {0x2F, 0x09, 0xFFD4},
2977 {0x2F, 0x0A, 0x7C2F}, {0x2F, 0x0E, 0x003F}, {0x2F, 0x0F, 0x0121},
2978 {0x2F, 0x10, 0x0020}, {0x2F, 0x11, 0x8840}, {0x2B, 0x13, 0x3D87},
2979 {0x2B, 0x14, 0x3108}, {0x2D, 0x13, 0x3C87}, {0x2D, 0x14, 0x1808},
2980 };
2981
2982 static void rtl9300_serdes_patch(int sds_num)
2983 {
2984 if (sds_num % 2) {
2985 for (int i = 0; i < sizeof(rtl9300_a_sds_10gr_lane1) / sizeof(sds_config); ++i) {
2986 rtl930x_write_sds_phy(sds_num, rtl9300_a_sds_10gr_lane1[i].page,
2987 rtl9300_a_sds_10gr_lane1[i].reg,
2988 rtl9300_a_sds_10gr_lane1[i].data);
2989 }
2990 } else {
2991 for (int i = 0; i < sizeof(rtl9300_a_sds_10gr_lane0) / sizeof(sds_config); ++i) {
2992 rtl930x_write_sds_phy(sds_num, rtl9300_a_sds_10gr_lane0[i].page,
2993 rtl9300_a_sds_10gr_lane0[i].reg,
2994 rtl9300_a_sds_10gr_lane0[i].data);
2995 }
2996 }
2997 }
2998
2999 int rtl9300_sds_cmu_band_get(int sds)
3000 {
3001 u32 page;
3002 u32 en;
3003 u32 cmu_band;
3004
3005 /* page = rtl9300_sds_cmu_page_get(sds); */
3006 page = 0x25; /* 10GR and 1000BX */
3007 sds = (sds % 2) ? (sds - 1) : (sds);
3008
3009 rtl9300_sds_field_w(sds, page, 0x1c, 15, 15, 1);
3010 rtl9300_sds_field_w(sds + 1, page, 0x1c, 15, 15, 1);
3011
3012 en = rtl9300_sds_field_r(sds, page, 27, 1, 1);
3013 if(!en) { /* Auto mode */
3014 rtl930x_write_sds_phy(sds, 0x1f, 0x02, 31);
3015
3016 cmu_band = rtl9300_sds_field_r(sds, 0x1f, 0x15, 5, 1);
3017 } else {
3018 cmu_band = rtl9300_sds_field_r(sds, page, 30, 4, 0);
3019 }
3020
3021 return cmu_band;
3022 }
3023
3024 void rtl9310_sds_field_w(int sds, u32 page, u32 reg, int end_bit, int start_bit, u32 v)
3025 {
3026 int l = end_bit - start_bit + 1;
3027 u32 data = v;
3028
3029 if (l < 32) {
3030 u32 mask = BIT(l) - 1;
3031
3032 data = rtl930x_read_sds_phy(sds, page, reg);
3033 data &= ~(mask << start_bit);
3034 data |= (v & mask) << start_bit;
3035 }
3036
3037 rtl931x_write_sds_phy(sds, page, reg, data);
3038 }
3039
3040 u32 rtl9310_sds_field_r(int sds, u32 page, u32 reg, int end_bit, int start_bit)
3041 {
3042 int l = end_bit - start_bit + 1;
3043 u32 v = rtl931x_read_sds_phy(sds, page, reg);
3044
3045 if (l >= 32)
3046 return v;
3047
3048 return (v >> start_bit) & (BIT(l) - 1);
3049 }
3050
3051 static void rtl931x_sds_rst(u32 sds)
3052 {
3053 u32 o, v, o_mode;
3054 int shift = ((sds & 0x3) << 3);
3055
3056 /* TODO: We need to lock this! */
3057
3058 o = sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3059 v = o | BIT(sds);
3060 sw_w32(v, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3061
3062 o_mode = sw_r32(RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3063 v = BIT(7) | 0x1F;
3064 sw_w32_mask(0xff << shift, v << shift, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3065 sw_w32(o_mode, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3066
3067 sw_w32(o, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3068 }
3069
3070 static void rtl931x_symerr_clear(u32 sds, phy_interface_t mode)
3071 {
3072
3073 switch (mode) {
3074 case PHY_INTERFACE_MODE_NA:
3075 break;
3076 case PHY_INTERFACE_MODE_XGMII:
3077 u32 xsg_sdsid_0, xsg_sdsid_1;
3078
3079 if (sds < 2)
3080 xsg_sdsid_0 = sds;
3081 else
3082 xsg_sdsid_0 = (sds - 1) * 2;
3083 xsg_sdsid_1 = xsg_sdsid_0 + 1;
3084
3085 for (int i = 0; i < 4; ++i) {
3086 rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 24, 2, 0, i);
3087 rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 3, 15, 8, 0x0);
3088 rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 2, 15, 0, 0x0);
3089 }
3090
3091 for (int i = 0; i < 4; ++i) {
3092 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 24, 2, 0, i);
3093 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 3, 15, 8, 0x0);
3094 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 2, 15, 0, 0x0);
3095 }
3096
3097 rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 0, 15, 0, 0x0);
3098 rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 1, 15, 8, 0x0);
3099 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 0, 15, 0, 0x0);
3100 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 1, 15, 8, 0x0);
3101 break;
3102 default:
3103 break;
3104 }
3105
3106 return;
3107 }
3108
3109 static u32 rtl931x_get_analog_sds(u32 sds)
3110 {
3111 u32 sds_map[] = { 0, 1, 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23 };
3112
3113 if (sds < 14)
3114 return sds_map[sds];
3115
3116 return sds;
3117 }
3118
3119 void rtl931x_sds_fiber_disable(u32 sds)
3120 {
3121 u32 v = 0x3F;
3122 u32 asds = rtl931x_get_analog_sds(sds);
3123
3124 rtl9310_sds_field_w(asds, 0x1F, 0x9, 11, 6, v);
3125 }
3126
3127 static void rtl931x_sds_fiber_mode_set(u32 sds, phy_interface_t mode)
3128 {
3129 u32 val, asds = rtl931x_get_analog_sds(sds);
3130
3131 /* clear symbol error count before changing mode */
3132 rtl931x_symerr_clear(sds, mode);
3133
3134 val = 0x9F;
3135 sw_w32(val, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3136
3137 switch (mode) {
3138 case PHY_INTERFACE_MODE_SGMII:
3139 val = 0x5;
3140 break;
3141
3142 case PHY_INTERFACE_MODE_1000BASEX:
3143 /* serdes mode FIBER1G */
3144 val = 0x9;
3145 break;
3146
3147 case PHY_INTERFACE_MODE_10GBASER:
3148 case PHY_INTERFACE_MODE_10GKR:
3149 val = 0x35;
3150 break;
3151 /* case MII_10GR1000BX_AUTO:
3152 val = 0x39;
3153 break; */
3154
3155
3156 case PHY_INTERFACE_MODE_USXGMII:
3157 val = 0x1B;
3158 break;
3159 default:
3160 val = 0x25;
3161 }
3162
3163 pr_info("%s writing analog SerDes Mode value %02x\n", __func__, val);
3164 rtl9310_sds_field_w(asds, 0x1F, 0x9, 11, 6, val);
3165
3166 return;
3167 }
3168
3169 static int rtl931x_sds_cmu_page_get(phy_interface_t mode)
3170 {
3171 switch (mode) {
3172 case PHY_INTERFACE_MODE_SGMII:
3173 case PHY_INTERFACE_MODE_1000BASEX: /* MII_1000BX_FIBER / 100BX_FIBER / 1000BX100BX_AUTO */
3174 return 0x24;
3175 case PHY_INTERFACE_MODE_HSGMII:
3176 case PHY_INTERFACE_MODE_2500BASEX: /* MII_2500Base_X: */
3177 return 0x28;
3178 /* case MII_HISGMII_5G: */
3179 /* return 0x2a; */
3180 case PHY_INTERFACE_MODE_QSGMII:
3181 return 0x2a; /* Code also has 0x34 */
3182 case PHY_INTERFACE_MODE_XAUI: /* MII_RXAUI_LITE: */
3183 return 0x2c;
3184 case PHY_INTERFACE_MODE_XGMII: /* MII_XSGMII */
3185 case PHY_INTERFACE_MODE_10GKR:
3186 case PHY_INTERFACE_MODE_10GBASER: /* MII_10GR */
3187 return 0x2e;
3188 default:
3189 return -1;
3190 }
3191
3192 return -1;
3193 }
3194
3195 static void rtl931x_cmu_type_set(u32 asds, phy_interface_t mode, int chiptype)
3196 {
3197 int cmu_type = 0; /* Clock Management Unit */
3198 u32 cmu_page = 0;
3199 u32 frc_cmu_spd;
3200 u32 evenSds;
3201 u32 lane, frc_lc_mode_bitnum, frc_lc_mode_val_bitnum;
3202
3203 switch (mode) {
3204 case PHY_INTERFACE_MODE_NA:
3205 case PHY_INTERFACE_MODE_10GKR:
3206 case PHY_INTERFACE_MODE_XGMII:
3207 case PHY_INTERFACE_MODE_10GBASER:
3208 case PHY_INTERFACE_MODE_USXGMII:
3209 return;
3210
3211 /* case MII_10GR1000BX_AUTO:
3212 if (chiptype)
3213 rtl9310_sds_field_w(asds, 0x24, 0xd, 14, 14, 0);
3214 return; */
3215
3216 case PHY_INTERFACE_MODE_QSGMII:
3217 cmu_type = 1;
3218 frc_cmu_spd = 0;
3219 break;
3220
3221 case PHY_INTERFACE_MODE_HSGMII:
3222 cmu_type = 1;
3223 frc_cmu_spd = 1;
3224 break;
3225
3226 case PHY_INTERFACE_MODE_1000BASEX:
3227 cmu_type = 1;
3228 frc_cmu_spd = 0;
3229 break;
3230
3231 /* case MII_1000BX100BX_AUTO:
3232 cmu_type = 1;
3233 frc_cmu_spd = 0;
3234 break; */
3235
3236 case PHY_INTERFACE_MODE_SGMII:
3237 cmu_type = 1;
3238 frc_cmu_spd = 0;
3239 break;
3240
3241 case PHY_INTERFACE_MODE_2500BASEX:
3242 cmu_type = 1;
3243 frc_cmu_spd = 1;
3244 break;
3245
3246 default:
3247 pr_info("SerDes %d mode is invalid\n", asds);
3248 return;
3249 }
3250
3251 if (cmu_type == 1)
3252 cmu_page = rtl931x_sds_cmu_page_get(mode);
3253
3254 lane = asds % 2;
3255
3256 if (!lane) {
3257 frc_lc_mode_bitnum = 4;
3258 frc_lc_mode_val_bitnum = 5;
3259 } else {
3260 frc_lc_mode_bitnum = 6;
3261 frc_lc_mode_val_bitnum = 7;
3262 }
3263
3264 evenSds = asds - lane;
3265
3266 pr_info("%s: cmu_type %0d cmu_page %x frc_cmu_spd %d lane %d asds %d\n",
3267 __func__, cmu_type, cmu_page, frc_cmu_spd, lane, asds);
3268
3269 if (cmu_type == 1) {
3270 pr_info("%s A CMU page 0x28 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x28, 0x7));
3271 rtl9310_sds_field_w(asds, cmu_page, 0x7, 15, 15, 0);
3272 pr_info("%s B CMU page 0x28 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x28, 0x7));
3273 if (chiptype) {
3274 rtl9310_sds_field_w(asds, cmu_page, 0xd, 14, 14, 0);
3275 }
3276
3277 rtl9310_sds_field_w(evenSds, 0x20, 0x12, 3, 2, 0x3);
3278 rtl9310_sds_field_w(evenSds, 0x20, 0x12, frc_lc_mode_bitnum, frc_lc_mode_bitnum, 1);
3279 rtl9310_sds_field_w(evenSds, 0x20, 0x12, frc_lc_mode_val_bitnum, frc_lc_mode_val_bitnum, 0);
3280 rtl9310_sds_field_w(evenSds, 0x20, 0x12, 12, 12, 1);
3281 rtl9310_sds_field_w(evenSds, 0x20, 0x12, 15, 13, frc_cmu_spd);
3282 }
3283
3284 pr_info("%s CMU page 0x28 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x28, 0x7));
3285 return;
3286 }
3287
3288 static void rtl931x_sds_rx_rst(u32 sds)
3289 {
3290 u32 asds = rtl931x_get_analog_sds(sds);
3291
3292 if (sds < 2)
3293 return;
3294
3295 rtl931x_write_sds_phy(asds, 0x2e, 0x12, 0x2740);
3296 rtl931x_write_sds_phy(asds, 0x2f, 0x0, 0x0);
3297 rtl931x_write_sds_phy(asds, 0x2f, 0x2, 0x2010);
3298 rtl931x_write_sds_phy(asds, 0x20, 0x0, 0xc10);
3299
3300 rtl931x_write_sds_phy(asds, 0x2e, 0x12, 0x27c0);
3301 rtl931x_write_sds_phy(asds, 0x2f, 0x0, 0xc000);
3302 rtl931x_write_sds_phy(asds, 0x2f, 0x2, 0x6010);
3303 rtl931x_write_sds_phy(asds, 0x20, 0x0, 0xc30);
3304
3305 mdelay(50);
3306 }
3307
3308 // Currently not used
3309 // static void rtl931x_sds_disable(u32 sds)
3310 // {
3311 // u32 v = 0x1f;
3312
3313 // v |= BIT(7);
3314 // sw_w32(v, RTL931X_SERDES_MODE_CTRL + (sds >> 2) * 4);
3315 // }
3316
3317 static void rtl931x_sds_mii_mode_set(u32 sds, phy_interface_t mode)
3318 {
3319 u32 val;
3320
3321 switch (mode) {
3322 case PHY_INTERFACE_MODE_QSGMII:
3323 val = 0x6;
3324 break;
3325 case PHY_INTERFACE_MODE_XGMII:
3326 val = 0x10; /* serdes mode XSGMII */
3327 break;
3328 case PHY_INTERFACE_MODE_USXGMII:
3329 case PHY_INTERFACE_MODE_2500BASEX:
3330 val = 0xD;
3331 break;
3332 case PHY_INTERFACE_MODE_HSGMII:
3333 val = 0x12;
3334 break;
3335 case PHY_INTERFACE_MODE_SGMII:
3336 val = 0x2;
3337 break;
3338 default:
3339 return;
3340 }
3341
3342 val |= (1 << 7);
3343
3344 sw_w32(val, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3345 }
3346
3347 static sds_config sds_config_10p3125g_type1[] = {
3348 { 0x2E, 0x00, 0x0107 }, { 0x2E, 0x01, 0x01A3 }, { 0x2E, 0x02, 0x6A24 },
3349 { 0x2E, 0x03, 0xD10D }, { 0x2E, 0x04, 0x8000 }, { 0x2E, 0x05, 0xA17E },
3350 { 0x2E, 0x06, 0xE31D }, { 0x2E, 0x07, 0x800E }, { 0x2E, 0x08, 0x0294 },
3351 { 0x2E, 0x09, 0x0CE4 }, { 0x2E, 0x0A, 0x7FC8 }, { 0x2E, 0x0B, 0xE0E7 },
3352 { 0x2E, 0x0C, 0x0200 }, { 0x2E, 0x0D, 0xDF80 }, { 0x2E, 0x0E, 0x0000 },
3353 { 0x2E, 0x0F, 0x1FC2 }, { 0x2E, 0x10, 0x0C3F }, { 0x2E, 0x11, 0x0000 },
3354 { 0x2E, 0x12, 0x27C0 }, { 0x2E, 0x13, 0x7E1D }, { 0x2E, 0x14, 0x1300 },
3355 { 0x2E, 0x15, 0x003F }, { 0x2E, 0x16, 0xBE7F }, { 0x2E, 0x17, 0x0090 },
3356 { 0x2E, 0x18, 0x0000 }, { 0x2E, 0x19, 0x4000 }, { 0x2E, 0x1A, 0x0000 },
3357 { 0x2E, 0x1B, 0x8000 }, { 0x2E, 0x1C, 0x011F }, { 0x2E, 0x1D, 0x0000 },
3358 { 0x2E, 0x1E, 0xC8FF }, { 0x2E, 0x1F, 0x0000 }, { 0x2F, 0x00, 0xC000 },
3359 { 0x2F, 0x01, 0xF000 }, { 0x2F, 0x02, 0x6010 }, { 0x2F, 0x12, 0x0EE7 },
3360 { 0x2F, 0x13, 0x0000 }
3361 };
3362
3363 static sds_config sds_config_10p3125g_cmu_type1[] = {
3364 { 0x2F, 0x03, 0x4210 }, { 0x2F, 0x04, 0x0000 }, { 0x2F, 0x05, 0x0019 },
3365 { 0x2F, 0x06, 0x18A6 }, { 0x2F, 0x07, 0x2990 }, { 0x2F, 0x08, 0xFFF4 },
3366 { 0x2F, 0x09, 0x1F08 }, { 0x2F, 0x0A, 0x0000 }, { 0x2F, 0x0B, 0x8000 },
3367 { 0x2F, 0x0C, 0x4224 }, { 0x2F, 0x0D, 0x0000 }, { 0x2F, 0x0E, 0x0000 },
3368 { 0x2F, 0x0F, 0xA470 }, { 0x2F, 0x10, 0x8000 }, { 0x2F, 0x11, 0x037B }
3369 };
3370
3371 void rtl931x_sds_init(u32 sds, phy_interface_t mode)
3372 {
3373 u32 board_sds_tx_type1[] = {
3374 0x01c3, 0x01c3, 0x01c3, 0x01a3, 0x01a3, 0x01a3,
3375 0x0143, 0x0143, 0x0143, 0x0143, 0x0163, 0x0163,
3376 };
3377 u32 board_sds_tx[] = {
3378 0x1a00, 0x1a00, 0x0200, 0x0200, 0x0200, 0x0200,
3379 0x01a3, 0x01a3, 0x01a3, 0x01a3, 0x01e3, 0x01e3
3380 };
3381 u32 board_sds_tx2[] = {
3382 0x0dc0, 0x01c0, 0x0200, 0x0180, 0x0160, 0x0123,
3383 0x0123, 0x0163, 0x01a3, 0x01a0, 0x01c3, 0x09c3,
3384 };
3385 u32 asds, dSds, ori, model_info, val;
3386 int chiptype = 0;
3387
3388 asds = rtl931x_get_analog_sds(sds);
3389
3390 if (sds > 13)
3391 return;
3392
3393 pr_info("%s: set sds %d to mode %d\n", __func__, sds, mode);
3394 val = rtl9310_sds_field_r(asds, 0x1F, 0x9, 11, 6);
3395
3396 pr_info("%s: fibermode %08X stored mode 0x%x analog SDS %d", __func__,
3397 rtl931x_read_sds_phy(asds, 0x1f, 0x9), val, asds);
3398 pr_info("%s: SGMII mode %08X in 0x24 0x9 analog SDS %d", __func__,
3399 rtl931x_read_sds_phy(asds, 0x24, 0x9), asds);
3400 pr_info("%s: CMU mode %08X stored even SDS %d", __func__,
3401 rtl931x_read_sds_phy(asds & ~1, 0x20, 0x12), asds & ~1);
3402 pr_info("%s: serdes_mode_ctrl %08X", __func__, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3403 pr_info("%s CMU page 0x24 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x24, 0x7));
3404 pr_info("%s CMU page 0x26 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x26, 0x7));
3405 pr_info("%s CMU page 0x28 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x28, 0x7));
3406 pr_info("%s XSG page 0x0 0xe %08x\n", __func__, rtl931x_read_sds_phy(dSds, 0x0, 0xe));
3407 pr_info("%s XSG2 page 0x0 0xe %08x\n", __func__, rtl931x_read_sds_phy(dSds + 1, 0x0, 0xe));
3408
3409 model_info = sw_r32(RTL93XX_MODEL_NAME_INFO);
3410 if ((model_info >> 4) & 0x1) {
3411 pr_info("detected chiptype 1\n");
3412 chiptype = 1;
3413 } else {
3414 pr_info("detected chiptype 0\n");
3415 }
3416
3417 if (sds < 2)
3418 dSds = sds;
3419 else
3420 dSds = (sds - 1) * 2;
3421
3422 pr_info("%s: 2.5gbit %08X dsds %d", __func__,
3423 rtl931x_read_sds_phy(dSds, 0x1, 0x14), dSds);
3424
3425 pr_info("%s: RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR 0x%08X\n", __func__, sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR));
3426 ori = sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3427 val = ori | (1 << sds);
3428 sw_w32(val, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3429
3430 switch (mode) {
3431 case PHY_INTERFACE_MODE_NA:
3432 break;
3433
3434 case PHY_INTERFACE_MODE_XGMII: /* MII_XSGMII */
3435
3436 if (chiptype) {
3437 u32 xsg_sdsid_1;
3438 xsg_sdsid_1 = dSds + 1;
3439 /* fifo inv clk */
3440 rtl9310_sds_field_w(dSds, 0x1, 0x1, 7, 4, 0xf);
3441 rtl9310_sds_field_w(dSds, 0x1, 0x1, 3, 0, 0xf);
3442
3443 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 0x1, 7, 4, 0xf);
3444 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 0x1, 3, 0, 0xf);
3445
3446 }
3447
3448 rtl9310_sds_field_w(dSds, 0x0, 0xE, 12, 12, 1);
3449 rtl9310_sds_field_w(dSds + 1, 0x0, 0xE, 12, 12, 1);
3450 break;
3451
3452 case PHY_INTERFACE_MODE_USXGMII: /* MII_USXGMII_10GSXGMII/10GDXGMII/10GQXGMII: */
3453 u32 op_code = 0x6003;
3454 u32 evenSds;
3455
3456 if (chiptype) {
3457 rtl9310_sds_field_w(asds, 0x6, 0x2, 12, 12, 1);
3458
3459 for (int i = 0; i < sizeof(sds_config_10p3125g_type1) / sizeof(sds_config); ++i) {
3460 rtl931x_write_sds_phy(asds, sds_config_10p3125g_type1[i].page - 0x4, sds_config_10p3125g_type1[i].reg, sds_config_10p3125g_type1[i].data);
3461 }
3462
3463 evenSds = asds - (asds % 2);
3464
3465 for (int i = 0; i < sizeof(sds_config_10p3125g_cmu_type1) / sizeof(sds_config); ++i) {
3466 rtl931x_write_sds_phy(evenSds,
3467 sds_config_10p3125g_cmu_type1[i].page - 0x4, sds_config_10p3125g_cmu_type1[i].reg, sds_config_10p3125g_cmu_type1[i].data);
3468 }
3469
3470 rtl9310_sds_field_w(asds, 0x6, 0x2, 12, 12, 0);
3471 } else {
3472
3473 rtl9310_sds_field_w(asds, 0x2e, 0xd, 6, 0, 0x0);
3474 rtl9310_sds_field_w(asds, 0x2e, 0xd, 7, 7, 0x1);
3475
3476 rtl9310_sds_field_w(asds, 0x2e, 0x1c, 5, 0, 0x1E);
3477 rtl9310_sds_field_w(asds, 0x2e, 0x1d, 11, 0, 0x00);
3478 rtl9310_sds_field_w(asds, 0x2e, 0x1f, 11, 0, 0x00);
3479 rtl9310_sds_field_w(asds, 0x2f, 0x0, 11, 0, 0x00);
3480 rtl9310_sds_field_w(asds, 0x2f, 0x1, 11, 0, 0x00);
3481
3482 rtl9310_sds_field_w(asds, 0x2e, 0xf, 12, 6, 0x7F);
3483 rtl931x_write_sds_phy(asds, 0x2f, 0x12, 0xaaa);
3484
3485 rtl931x_sds_rx_rst(sds);
3486
3487 rtl931x_write_sds_phy(asds, 0x7, 0x10, op_code);
3488 rtl931x_write_sds_phy(asds, 0x6, 0x1d, 0x0480);
3489 rtl931x_write_sds_phy(asds, 0x6, 0xe, 0x0400);
3490 }
3491 break;
3492
3493 case PHY_INTERFACE_MODE_10GBASER: /* MII_10GR / MII_10GR1000BX_AUTO: */
3494 /* configure 10GR fiber mode=1 */
3495 rtl9310_sds_field_w(asds, 0x1f, 0xb, 1, 1, 1);
3496
3497 /* init fiber_1g */
3498 rtl9310_sds_field_w(dSds, 0x3, 0x13, 15, 14, 0);
3499
3500 rtl9310_sds_field_w(dSds, 0x2, 0x0, 12, 12, 1);
3501 rtl9310_sds_field_w(dSds, 0x2, 0x0, 6, 6, 1);
3502 rtl9310_sds_field_w(dSds, 0x2, 0x0, 13, 13, 0);
3503
3504 /* init auto */
3505 rtl9310_sds_field_w(asds, 0x1f, 13, 15, 0, 0x109e);
3506 rtl9310_sds_field_w(asds, 0x1f, 0x6, 14, 10, 0x8);
3507 rtl9310_sds_field_w(asds, 0x1f, 0x7, 10, 4, 0x7f);
3508 break;
3509
3510 case PHY_INTERFACE_MODE_HSGMII:
3511 rtl9310_sds_field_w(dSds, 0x1, 0x14, 8, 8, 1);
3512 break;
3513
3514 case PHY_INTERFACE_MODE_1000BASEX: /* MII_1000BX_FIBER */
3515 rtl9310_sds_field_w(dSds, 0x3, 0x13, 15, 14, 0);
3516
3517 rtl9310_sds_field_w(dSds, 0x2, 0x0, 12, 12, 1);
3518 rtl9310_sds_field_w(dSds, 0x2, 0x0, 6, 6, 1);
3519 rtl9310_sds_field_w(dSds, 0x2, 0x0, 13, 13, 0);
3520 break;
3521
3522 case PHY_INTERFACE_MODE_SGMII:
3523 rtl9310_sds_field_w(asds, 0x24, 0x9, 15, 15, 0);
3524 break;
3525
3526 case PHY_INTERFACE_MODE_2500BASEX:
3527 rtl9310_sds_field_w(dSds, 0x1, 0x14, 8, 8, 1);
3528 break;
3529
3530 case PHY_INTERFACE_MODE_QSGMII:
3531 default:
3532 pr_info("%s: PHY mode %s not supported by SerDes %d\n",
3533 __func__, phy_modes(mode), sds);
3534 return;
3535 }
3536
3537 rtl931x_cmu_type_set(asds, mode, chiptype);
3538
3539 if (sds >= 2 && sds <= 13) {
3540 if (chiptype)
3541 rtl931x_write_sds_phy(asds, 0x2E, 0x1, board_sds_tx_type1[sds - 2]);
3542 else {
3543 val = 0xa0000;
3544 sw_w32(val, RTL931X_CHIP_INFO_ADDR);
3545 val = sw_r32(RTL931X_CHIP_INFO_ADDR);
3546 if (val & BIT(28)) /* consider 9311 etc. RTL9313_CHIP_ID == HWP_CHIP_ID(unit)) */
3547 {
3548 rtl931x_write_sds_phy(asds, 0x2E, 0x1, board_sds_tx2[sds - 2]);
3549 } else {
3550 rtl931x_write_sds_phy(asds, 0x2E, 0x1, board_sds_tx[sds - 2]);
3551 }
3552 val = 0;
3553 sw_w32(val, RTL931X_CHIP_INFO_ADDR);
3554 }
3555 }
3556
3557 val = ori & ~BIT(sds);
3558 sw_w32(val, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3559 pr_debug("%s: RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR 0x%08X\n", __func__, sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR));
3560
3561 if (mode == PHY_INTERFACE_MODE_XGMII ||
3562 mode == PHY_INTERFACE_MODE_QSGMII ||
3563 mode == PHY_INTERFACE_MODE_HSGMII ||
3564 mode == PHY_INTERFACE_MODE_SGMII ||
3565 mode == PHY_INTERFACE_MODE_USXGMII) {
3566 if (mode == PHY_INTERFACE_MODE_XGMII)
3567 rtl931x_sds_mii_mode_set(sds, mode);
3568 else
3569 rtl931x_sds_fiber_mode_set(sds, mode);
3570 }
3571 }
3572
3573 int rtl931x_sds_cmu_band_set(int sds, bool enable, u32 band, phy_interface_t mode)
3574 {
3575 u32 asds;
3576 int page = rtl931x_sds_cmu_page_get(mode);
3577
3578 sds -= (sds % 2);
3579 sds = sds & ~1;
3580 asds = rtl931x_get_analog_sds(sds);
3581 page += 1;
3582
3583 if (enable) {
3584 rtl9310_sds_field_w(asds, page, 0x7, 13, 13, 0);
3585 rtl9310_sds_field_w(asds, page, 0x7, 11, 11, 0);
3586 } else {
3587 rtl9310_sds_field_w(asds, page, 0x7, 13, 13, 0);
3588 rtl9310_sds_field_w(asds, page, 0x7, 11, 11, 0);
3589 }
3590
3591 rtl9310_sds_field_w(asds, page, 0x7, 4, 0, band);
3592
3593 rtl931x_sds_rst(sds);
3594
3595 return 0;
3596 }
3597
3598 int rtl931x_sds_cmu_band_get(int sds, phy_interface_t mode)
3599 {
3600 int page = rtl931x_sds_cmu_page_get(mode);
3601 u32 asds, band;
3602
3603 sds -= (sds % 2);
3604 asds = rtl931x_get_analog_sds(sds);
3605 page += 1;
3606 rtl931x_write_sds_phy(asds, 0x1f, 0x02, 73);
3607
3608 rtl9310_sds_field_w(asds, page, 0x5, 15, 15, 1);
3609 band = rtl9310_sds_field_r(asds, 0x1f, 0x15, 8, 3);
3610 pr_info("%s band is: %d\n", __func__, band);
3611
3612 return band;
3613 }
3614
3615
3616 int rtl931x_link_sts_get(u32 sds)
3617 {
3618 u32 sts, sts1, latch_sts, latch_sts1;
3619 if (0){
3620 u32 xsg_sdsid_0, xsg_sdsid_1;
3621
3622 xsg_sdsid_0 = sds < 2 ? sds : (sds - 1) * 2;
3623 xsg_sdsid_1 = xsg_sdsid_0 + 1;
3624
3625 sts = rtl9310_sds_field_r(xsg_sdsid_0, 0x1, 29, 8, 0);
3626 sts1 = rtl9310_sds_field_r(xsg_sdsid_1, 0x1, 29, 8, 0);
3627 latch_sts = rtl9310_sds_field_r(xsg_sdsid_0, 0x1, 30, 8, 0);
3628 latch_sts1 = rtl9310_sds_field_r(xsg_sdsid_1, 0x1, 30, 8, 0);
3629 } else {
3630 u32 asds, dsds;
3631
3632 asds = rtl931x_get_analog_sds(sds);
3633 sts = rtl9310_sds_field_r(asds, 0x5, 0, 12, 12);
3634 latch_sts = rtl9310_sds_field_r(asds, 0x4, 1, 2, 2);
3635
3636 dsds = sds < 2 ? sds : (sds - 1) * 2;
3637 latch_sts1 = rtl9310_sds_field_r(dsds, 0x2, 1, 2, 2);
3638 sts1 = rtl9310_sds_field_r(dsds, 0x2, 1, 2, 2);
3639 }
3640
3641 pr_info("%s: serdes %d sts %d, sts1 %d, latch_sts %d, latch_sts1 %d\n", __func__,
3642 sds, sts, sts1, latch_sts, latch_sts1);
3643
3644 return sts1;
3645 }
3646
3647 static int rtl8214fc_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)
3648 {
3649 struct phy_device *phydev = upstream;
3650
3651 rtl8214fc_media_set(phydev, true);
3652
3653 return 0;
3654 }
3655
3656 static void rtl8214fc_sfp_remove(void *upstream)
3657 {
3658 struct phy_device *phydev = upstream;
3659
3660 rtl8214fc_media_set(phydev, false);
3661 }
3662
3663 static const struct sfp_upstream_ops rtl8214fc_sfp_ops = {
3664 .attach = phy_sfp_attach,
3665 .detach = phy_sfp_detach,
3666 .module_insert = rtl8214fc_sfp_insert,
3667 .module_remove = rtl8214fc_sfp_remove,
3668 };
3669
3670 static int rtl8214fc_phy_probe(struct phy_device *phydev)
3671 {
3672 struct device *dev = &phydev->mdio.dev;
3673 int addr = phydev->mdio.addr;
3674 int ret = 0;
3675
3676 /* 839x has internal SerDes */
3677 if (soc_info.id == 0x8393)
3678 return -ENODEV;
3679
3680 /* All base addresses of the PHYs start at multiples of 8 */
3681 devm_phy_package_join(dev, phydev, addr & (~7),
3682 sizeof(struct rtl83xx_shared_private));
3683
3684 if (!(addr % 8)) {
3685 struct rtl83xx_shared_private *shared = phydev->shared->priv;
3686 shared->name = "RTL8214FC";
3687 /* Configuration must be done while patching still possible */
3688 ret = rtl8380_configure_rtl8214fc(phydev);
3689 if (ret)
3690 return ret;
3691 }
3692
3693 return phy_sfp_probe(phydev, &rtl8214fc_sfp_ops);
3694 }
3695
3696 static int rtl8214c_phy_probe(struct phy_device *phydev)
3697 {
3698 struct device *dev = &phydev->mdio.dev;
3699 int addr = phydev->mdio.addr;
3700
3701 /* All base addresses of the PHYs start at multiples of 8 */
3702 devm_phy_package_join(dev, phydev, addr & (~7),
3703 sizeof(struct rtl83xx_shared_private));
3704
3705 if (!(addr % 8)) {
3706 struct rtl83xx_shared_private *shared = phydev->shared->priv;
3707 shared->name = "RTL8214C";
3708 /* Configuration must be done whil patching still possible */
3709 return rtl8380_configure_rtl8214c(phydev);
3710 }
3711
3712 return 0;
3713 }
3714
3715 static int rtl8218b_ext_phy_probe(struct phy_device *phydev)
3716 {
3717 struct device *dev = &phydev->mdio.dev;
3718 int addr = phydev->mdio.addr;
3719
3720 /* All base addresses of the PHYs start at multiples of 8 */
3721 devm_phy_package_join(dev, phydev, addr & (~7),
3722 sizeof(struct rtl83xx_shared_private));
3723
3724 if (!(addr % 8)) {
3725 struct rtl83xx_shared_private *shared = phydev->shared->priv;
3726 shared->name = "RTL8218B (external)";
3727 if (soc_info.family == RTL8380_FAMILY_ID) {
3728 /* Configuration must be done while patching still possible */
3729 return rtl8380_configure_ext_rtl8218b(phydev);
3730 }
3731 }
3732
3733 return 0;
3734 }
3735
3736 static int rtl8218b_int_phy_probe(struct phy_device *phydev)
3737 {
3738 struct device *dev = &phydev->mdio.dev;
3739 int addr = phydev->mdio.addr;
3740
3741 if (soc_info.family != RTL8380_FAMILY_ID)
3742 return -ENODEV;
3743 if (addr >= 24)
3744 return -ENODEV;
3745
3746 pr_debug("%s: id: %d\n", __func__, addr);
3747 /* All base addresses of the PHYs start at multiples of 8 */
3748 devm_phy_package_join(dev, phydev, addr & (~7),
3749 sizeof(struct rtl83xx_shared_private));
3750
3751 if (!(addr % 8)) {
3752 struct rtl83xx_shared_private *shared = phydev->shared->priv;
3753 shared->name = "RTL8218B (internal)";
3754 /* Configuration must be done while patching still possible */
3755 return rtl8380_configure_int_rtl8218b(phydev);
3756 }
3757
3758 return 0;
3759 }
3760
3761 static int rtl8218d_phy_probe(struct phy_device *phydev)
3762 {
3763 struct device *dev = &phydev->mdio.dev;
3764 int addr = phydev->mdio.addr;
3765
3766 pr_debug("%s: id: %d\n", __func__, addr);
3767 /* All base addresses of the PHYs start at multiples of 8 */
3768 devm_phy_package_join(dev, phydev, addr & (~7),
3769 sizeof(struct rtl83xx_shared_private));
3770
3771 /* All base addresses of the PHYs start at multiples of 8 */
3772 if (!(addr % 8)) {
3773 struct rtl83xx_shared_private *shared = phydev->shared->priv;
3774 shared->name = "RTL8218D";
3775 /* Configuration must be done while patching still possible */
3776 /* TODO: return configure_rtl8218d(phydev); */
3777 }
3778
3779 return 0;
3780 }
3781
3782 static int rtl838x_serdes_probe(struct phy_device *phydev)
3783 {
3784 int addr = phydev->mdio.addr;
3785
3786 if (soc_info.family != RTL8380_FAMILY_ID)
3787 return -ENODEV;
3788 if (addr < 24)
3789 return -ENODEV;
3790
3791 /* On the RTL8380M, PHYs 24-27 connect to the internal SerDes */
3792 if (soc_info.id == 0x8380) {
3793 if (addr == 24)
3794 return rtl8380_configure_serdes(phydev);
3795 return 0;
3796 }
3797
3798 return -ENODEV;
3799 }
3800
3801 static int rtl8393_serdes_probe(struct phy_device *phydev)
3802 {
3803 int addr = phydev->mdio.addr;
3804
3805 pr_info("%s: id: %d\n", __func__, addr);
3806 if (soc_info.family != RTL8390_FAMILY_ID)
3807 return -ENODEV;
3808
3809 if (addr < 24)
3810 return -ENODEV;
3811
3812 return rtl8390_configure_serdes(phydev);
3813 }
3814
3815 static int rtl8390_serdes_probe(struct phy_device *phydev)
3816 {
3817 int addr = phydev->mdio.addr;
3818
3819 if (soc_info.family != RTL8390_FAMILY_ID)
3820 return -ENODEV;
3821
3822 if (addr < 24)
3823 return -ENODEV;
3824
3825 return rtl8390_configure_generic(phydev);
3826 }
3827
3828 static int rtl9300_serdes_probe(struct phy_device *phydev)
3829 {
3830 if (soc_info.family != RTL9300_FAMILY_ID)
3831 return -ENODEV;
3832
3833 phydev_info(phydev, "Detected internal RTL9300 Serdes\n");
3834
3835 return 0;
3836 }
3837
3838 static struct phy_driver rtl83xx_phy_driver[] = {
3839 {
3840 PHY_ID_MATCH_MODEL(PHY_ID_RTL8214C),
3841 .name = "Realtek RTL8214C",
3842 .features = PHY_GBIT_FEATURES,
3843 .flags = PHY_HAS_REALTEK_PAGES,
3844 .match_phy_device = rtl8214c_match_phy_device,
3845 .probe = rtl8214c_phy_probe,
3846 .suspend = genphy_suspend,
3847 .resume = genphy_resume,
3848 .set_loopback = genphy_loopback,
3849 },
3850 {
3851 PHY_ID_MATCH_MODEL(PHY_ID_RTL8214FC),
3852 .name = "Realtek RTL8214FC",
3853 .features = PHY_GBIT_FIBRE_FEATURES,
3854 .flags = PHY_HAS_REALTEK_PAGES,
3855 .match_phy_device = rtl8214fc_match_phy_device,
3856 .probe = rtl8214fc_phy_probe,
3857 .suspend = rtl8214fc_suspend,
3858 .resume = rtl8214fc_resume,
3859 .set_loopback = genphy_loopback,
3860 .set_port = rtl8214fc_set_port,
3861 .get_port = rtl8214fc_get_port,
3862 .set_eee = rtl8214fc_set_eee,
3863 .get_eee = rtl8214fc_get_eee,
3864 },
3865 {
3866 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_E),
3867 .name = "Realtek RTL8218B (external)",
3868 .features = PHY_GBIT_FEATURES,
3869 .flags = PHY_HAS_REALTEK_PAGES,
3870 .match_phy_device = rtl8218b_ext_match_phy_device,
3871 .probe = rtl8218b_ext_phy_probe,
3872 .suspend = genphy_suspend,
3873 .resume = genphy_resume,
3874 .set_loopback = genphy_loopback,
3875 .set_eee = rtl8218b_set_eee,
3876 .get_eee = rtl8218b_get_eee,
3877 },
3878 {
3879 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218D),
3880 .name = "REALTEK RTL8218D",
3881 .features = PHY_GBIT_FEATURES,
3882 .flags = PHY_HAS_REALTEK_PAGES,
3883 .probe = rtl8218d_phy_probe,
3884 .suspend = genphy_suspend,
3885 .resume = genphy_resume,
3886 .set_loopback = genphy_loopback,
3887 .set_eee = rtl8218d_set_eee,
3888 .get_eee = rtl8218d_get_eee,
3889 },
3890 {
3891 PHY_ID_MATCH_MODEL(PHY_ID_RTL8221B),
3892 .name = "REALTEK RTL8221B",
3893 .features = PHY_GBIT_FEATURES,
3894 .flags = PHY_HAS_REALTEK_PAGES,
3895 .suspend = genphy_suspend,
3896 .resume = genphy_resume,
3897 .set_loopback = genphy_loopback,
3898 .read_page = rtl8226_read_page,
3899 .write_page = rtl8226_write_page,
3900 .read_status = rtl8226_read_status,
3901 .config_aneg = rtl8226_config_aneg,
3902 .set_eee = rtl8226_set_eee,
3903 .get_eee = rtl8226_get_eee,
3904 },
3905 {
3906 PHY_ID_MATCH_MODEL(PHY_ID_RTL8226),
3907 .name = "REALTEK RTL8226",
3908 .features = PHY_GBIT_FEATURES,
3909 .flags = PHY_HAS_REALTEK_PAGES,
3910 .suspend = genphy_suspend,
3911 .resume = genphy_resume,
3912 .set_loopback = genphy_loopback,
3913 .read_page = rtl8226_read_page,
3914 .write_page = rtl8226_write_page,
3915 .read_status = rtl8226_read_status,
3916 .config_aneg = rtl8226_config_aneg,
3917 .set_eee = rtl8226_set_eee,
3918 .get_eee = rtl8226_get_eee,
3919 },
3920 {
3921 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_I),
3922 .name = "Realtek RTL8218B (internal)",
3923 .features = PHY_GBIT_FEATURES,
3924 .flags = PHY_HAS_REALTEK_PAGES,
3925 .probe = rtl8218b_int_phy_probe,
3926 .suspend = genphy_suspend,
3927 .resume = genphy_resume,
3928 .set_loopback = genphy_loopback,
3929 .set_eee = rtl8218b_set_eee,
3930 .get_eee = rtl8218b_get_eee,
3931 },
3932 {
3933 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_I),
3934 .name = "Realtek RTL8380 SERDES",
3935 .features = PHY_GBIT_FIBRE_FEATURES,
3936 .flags = PHY_HAS_REALTEK_PAGES,
3937 .probe = rtl838x_serdes_probe,
3938 .suspend = genphy_suspend,
3939 .resume = genphy_resume,
3940 .set_loopback = genphy_loopback,
3941 .read_status = rtl8380_read_status,
3942 },
3943 {
3944 PHY_ID_MATCH_MODEL(PHY_ID_RTL8393_I),
3945 .name = "Realtek RTL8393 SERDES",
3946 .features = PHY_GBIT_FIBRE_FEATURES,
3947 .flags = PHY_HAS_REALTEK_PAGES,
3948 .probe = rtl8393_serdes_probe,
3949 .suspend = genphy_suspend,
3950 .resume = genphy_resume,
3951 .set_loopback = genphy_loopback,
3952 .read_status = rtl8393_read_status,
3953 },
3954 {
3955 PHY_ID_MATCH_MODEL(PHY_ID_RTL8390_GENERIC),
3956 .name = "Realtek RTL8390 Generic",
3957 .features = PHY_GBIT_FIBRE_FEATURES,
3958 .flags = PHY_HAS_REALTEK_PAGES,
3959 .probe = rtl8390_serdes_probe,
3960 .suspend = genphy_suspend,
3961 .resume = genphy_resume,
3962 .set_loopback = genphy_loopback,
3963 },
3964 {
3965 PHY_ID_MATCH_MODEL(PHY_ID_RTL9300_I),
3966 .name = "REALTEK RTL9300 SERDES",
3967 .features = PHY_GBIT_FIBRE_FEATURES,
3968 .flags = PHY_HAS_REALTEK_PAGES,
3969 .probe = rtl9300_serdes_probe,
3970 .suspend = genphy_suspend,
3971 .resume = genphy_resume,
3972 .set_loopback = genphy_loopback,
3973 .read_status = rtl9300_read_status,
3974 },
3975 };
3976
3977 module_phy_driver(rtl83xx_phy_driver);
3978
3979 static struct mdio_device_id __maybe_unused rtl83xx_tbl[] = {
3980 { PHY_ID_MATCH_MODEL(PHY_ID_RTL8214FC) },
3981 { }
3982 };
3983
3984 MODULE_DEVICE_TABLE(mdio, rtl83xx_tbl);
3985
3986 MODULE_AUTHOR("B. Koblitz");
3987 MODULE_DESCRIPTION("RTL83xx PHY driver");
3988 MODULE_LICENSE("GPL");
Staging tree of Stijn Tintel