target/linux/realtek/files-5.15/drivers/net/ethernet/rtl838x_eth.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef _RTL838X_ETH_H
   4 #define _RTL838X_ETH_H
   5
   6 /* Register definition */
   7
   8 /* Per port MAC control */
   9 #define RTL838X_MAC_PORT_CTRL                   (0xd560)
  10 #define RTL839X_MAC_PORT_CTRL                   (0x8004)
  11 #define RTL930X_MAC_L2_PORT_CTRL                (0x3268)
  12 #define RTL930X_MAC_PORT_CTRL                   (0x3260)
  13 #define RTL931X_MAC_L2_PORT_CTRL                (0x6000)
  14 #define RTL931X_MAC_PORT_CTRL                   (0x6004)
  15
  16 /* DMA interrupt control and status registers */
  17 #define RTL838X_DMA_IF_CTRL                     (0x9f58)
  18 #define RTL838X_DMA_IF_INTR_STS                 (0x9f54)
  19 #define RTL838X_DMA_IF_INTR_MSK                 (0x9f50)
  20
  21 #define RTL839X_DMA_IF_CTRL                     (0x786c)
  22 #define RTL839X_DMA_IF_INTR_STS                 (0x7868)
  23 #define RTL839X_DMA_IF_INTR_MSK                 (0x7864)
  24
  25 #define RTL930X_DMA_IF_CTRL                     (0xe028)
  26 #define RTL930X_DMA_IF_INTR_RX_RUNOUT_STS       (0xe01C)
  27 #define RTL930X_DMA_IF_INTR_RX_DONE_STS         (0xe020)
  28 #define RTL930X_DMA_IF_INTR_TX_DONE_STS         (0xe024)
  29 #define RTL930X_DMA_IF_INTR_RX_RUNOUT_MSK       (0xe010)
  30 #define RTL930X_DMA_IF_INTR_RX_DONE_MSK         (0xe014)
  31 #define RTL930X_DMA_IF_INTR_TX_DONE_MSK         (0xe018)
  32 #define RTL930X_L2_NTFY_IF_INTR_MSK             (0xe04C)
  33 #define RTL930X_L2_NTFY_IF_INTR_STS             (0xe050)
  34
  35 /* TODO: RTL931X_DMA_IF_CTRL has different bits meanings */
  36 #define RTL931X_DMA_IF_CTRL                     (0x0928)
  37 #define RTL931X_DMA_IF_INTR_RX_RUNOUT_STS       (0x091c)
  38 #define RTL931X_DMA_IF_INTR_RX_DONE_STS         (0x0920)
  39 #define RTL931X_DMA_IF_INTR_TX_DONE_STS         (0x0924)
  40 #define RTL931X_DMA_IF_INTR_RX_RUNOUT_MSK       (0x0910)
  41 #define RTL931X_DMA_IF_INTR_RX_DONE_MSK         (0x0914)
  42 #define RTL931X_DMA_IF_INTR_TX_DONE_MSK         (0x0918)
  43 #define RTL931X_L2_NTFY_IF_INTR_MSK             (0x09E4)
  44 #define RTL931X_L2_NTFY_IF_INTR_STS             (0x09E8)
  45
  46 #define RTL838X_MAC_FORCE_MODE_CTRL             (0xa104)
  47 #define RTL839X_MAC_FORCE_MODE_CTRL             (0x02bc)
  48 #define RTL930X_MAC_FORCE_MODE_CTRL             (0xCA1C)
  49 #define RTL931X_MAC_FORCE_MODE_CTRL             (0x0ddc)
  50
  51 /* MAC address settings */
  52 #define RTL838X_MAC                             (0xa9ec)
  53 #define RTL839X_MAC                             (0x02b4)
  54 #define RTL838X_MAC_ALE                         (0x6b04)
  55 #define RTL838X_MAC2                            (0xa320)
  56 #define RTL930X_MAC_L2_ADDR_CTRL                (0xC714)
  57 #define RTL931X_MAC_L2_ADDR_CTRL                (0x135c)
  58
  59 /* Ringbuffer setup */
  60 #define RTL838X_DMA_RX_BASE                     (0x9f00)
  61 #define RTL839X_DMA_RX_BASE                     (0x780c)
  62 #define RTL930X_DMA_RX_BASE                     (0xdf00)
  63 #define RTL931X_DMA_RX_BASE                     (0x0800)
  64
  65 #define RTL838X_DMA_TX_BASE                     (0x9f40)
  66 #define RTL839X_DMA_TX_BASE                     (0x784c)
  67 #define RTL930X_DMA_TX_BASE                     (0xe000)
  68 #define RTL931X_DMA_TX_BASE                     (0x0900)
  69
  70 #define RTL838X_DMA_IF_RX_RING_SIZE             (0xB7E4)
  71 #define RTL839X_DMA_IF_RX_RING_SIZE             (0x6038)
  72 #define RTL930X_DMA_IF_RX_RING_SIZE             (0x7C60)
  73 #define RTL931X_DMA_IF_RX_RING_SIZE             (0x2080)
  74
  75 #define RTL838X_DMA_IF_RX_RING_CNTR             (0xB7E8)
  76 #define RTL839X_DMA_IF_RX_RING_CNTR             (0x603c)
  77 #define RTL930X_DMA_IF_RX_RING_CNTR             (0x7C8C)
  78 #define RTL931X_DMA_IF_RX_RING_CNTR             (0x20AC)
  79
  80 #define RTL838X_DMA_IF_RX_CUR                   (0x9F20)
  81 #define RTL839X_DMA_IF_RX_CUR                   (0x782c)
  82 #define RTL930X_DMA_IF_RX_CUR                   (0xdf80)
  83 #define RTL931X_DMA_IF_RX_CUR                   (0x0880)
  84
  85 #define RTL838X_DMA_IF_TX_CUR_DESC_ADDR_CTRL    (0x9F48)
  86 #define RTL930X_DMA_IF_TX_CUR_DESC_ADDR_CTRL    (0xE008)
  87
  88 #define RTL838X_DMY_REG31                       (0x3b28)
  89 #define RTL838X_SDS_MODE_SEL                    (0x0028)
  90 #define RTL838X_SDS_CFG_REG                     (0x0034)
  91 #define RTL838X_INT_MODE_CTRL                   (0x005c)
  92 #define RTL838X_CHIP_INFO                       (0x00d8)
  93 #define RTL838X_SDS4_REG28                      (0xef80)
  94 #define RTL838X_SDS4_DUMMY0                     (0xef8c)
  95 #define RTL838X_SDS5_EXT_REG6                   (0xf18c)
  96
  97 /* L2 features */
  98 #define RTL839X_TBL_ACCESS_L2_CTRL              (0x1180)
  99 #define RTL839X_TBL_ACCESS_L2_DATA(idx)         (0x1184 + ((idx) << 2))
 100 #define RTL838X_TBL_ACCESS_CTRL_0               (0x6914)
 101 #define RTL838X_TBL_ACCESS_DATA_0(idx)          (0x6918 + ((idx) << 2))
 102
 103 /* MAC-side link state handling */
 104 #define RTL838X_MAC_LINK_STS                    (0xa188)
 105 #define RTL839X_MAC_LINK_STS                    (0x0390)
 106 #define RTL930X_MAC_LINK_STS                    (0xCB10)
 107 #define RTL931X_MAC_LINK_STS                    (0x0ec0)
 108
 109 #define RTL838X_MAC_LINK_SPD_STS                (0xa190)
 110 #define RTL839X_MAC_LINK_SPD_STS                (0x03a0)
 111 #define RTL930X_MAC_LINK_SPD_STS                (0xCB18)
 112 #define RTL931X_MAC_LINK_SPD_STS                (0x0ed0)
 113
 114 #define RTL838X_MAC_LINK_DUP_STS                (0xa19c)
 115 #define RTL839X_MAC_LINK_DUP_STS                (0x03b0)
 116 #define RTL930X_MAC_LINK_DUP_STS                (0xCB28)
 117 #define RTL931X_MAC_LINK_DUP_STS                (0x0ef0)
 118
 119 // TODO: RTL8390_MAC_LINK_MEDIA_STS_ADDR ???
 120
 121 #define RTL838X_MAC_TX_PAUSE_STS                (0xa1a0)
 122 #define RTL839X_MAC_TX_PAUSE_STS                (0x03b8)
 123 #define RTL930X_MAC_TX_PAUSE_STS                (0xCB2C)
 124 #define RTL931X_MAC_TX_PAUSE_STS                (0x0ef8)
 125
 126 #define RTL838X_MAC_RX_PAUSE_STS                (0xa1a4)
 127 #define RTL839X_MAC_RX_PAUSE_STS                (0xCB30)
 128 #define RTL930X_MAC_RX_PAUSE_STS                (0xC2F8)
 129 #define RTL931X_MAC_RX_PAUSE_STS                (0x0f00)
 130
 131 #define RTL838X_EEE_TX_TIMER_GIGA_CTRL          (0xaa04)
 132 #define RTL838X_EEE_TX_TIMER_GELITE_CTRL        (0xaa08)
 133
 134 #define RTL930X_L2_UNKN_UC_FLD_PMSK             (0x9064)
 135 #define RTL931X_L2_UNKN_UC_FLD_PMSK             (0xC8F4)
 136
 137 #define RTL839X_MAC_GLB_CTRL                    (0x02a8)
 138 #define RTL839X_SCHED_LB_TICK_TKN_CTRL          (0x60f8)
 139
 140 #define RTL838X_L2_TBL_FLUSH_CTRL               (0x3370)
 141 #define RTL839X_L2_TBL_FLUSH_CTRL               (0x3ba0)
 142 #define RTL930X_L2_TBL_FLUSH_CTRL               (0x9404)
 143 #define RTL931X_L2_TBL_FLUSH_CTRL               (0xCD9C)
 144
 145 #define RTL930X_L2_PORT_SABLK_CTRL              (0x905c)
 146 #define RTL930X_L2_PORT_DABLK_CTRL              (0x9060)
 147
 148 /* MAC link state bits */
 149 #define FORCE_EN                                (1 << 0)
 150 #define FORCE_LINK_EN                           (1 << 1)
 151 #define NWAY_EN                                 (1 << 2)
 152 #define DUPLX_MODE                              (1 << 3)
 153 #define TX_PAUSE_EN                             (1 << 6)
 154 #define RX_PAUSE_EN                             (1 << 7)
 155
 156 /* L2 Notification DMA interface */
 157 #define RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL (0x785C)
 158 #define RTL839X_L2_NOTIFICATION_CTRL            (0x7808)
 159 #define RTL931X_L2_NTFY_RING_BASE_ADDR          (0x09DC)
 160 #define RTL931X_L2_NTFY_RING_CUR_ADDR           (0x09E0)
 161 #define RTL839X_L2_NOTIFICATION_CTRL            (0x7808)
 162 #define RTL931X_L2_NTFY_CTRL                    (0xCDC8)
 163 #define RTL838X_L2_CTRL_0                       (0x3200)
 164 #define RTL839X_L2_CTRL_0                       (0x3800)
 165 #define RTL930X_L2_CTRL                         (0x8FD8)
 166 #define RTL931X_L2_CTRL                         (0xC800)
 167
 168 /* TRAPPING to CPU-PORT */
 169 #define RTL838X_SPCL_TRAP_IGMP_CTRL             (0x6984)
 170 #define RTL838X_RMA_CTRL_0                      (0x4300)
 171 #define RTL838X_RMA_CTRL_1                      (0x4304)
 172 #define RTL839X_RMA_CTRL_0                      (0x1200)
 173
 174 #define RTL839X_SPCL_TRAP_IGMP_CTRL             (0x1058)
 175 #define RTL839X_RMA_CTRL_1                      (0x1204)
 176 #define RTL839X_RMA_CTRL_2                      (0x1208)
 177 #define RTL839X_RMA_CTRL_3                      (0x120C)
 178
 179 #define RTL930X_VLAN_APP_PKT_CTRL               (0xA23C)
 180 #define RTL930X_RMA_CTRL_0                      (0x9E60)
 181 #define RTL930X_RMA_CTRL_1                      (0x9E64)
 182 #define RTL930X_RMA_CTRL_2                      (0x9E68)
 183
 184 #define RTL931X_VLAN_APP_PKT_CTRL               (0x96b0)
 185 #define RTL931X_RMA_CTRL_0                      (0x8800)
 186 #define RTL931X_RMA_CTRL_1                      (0x8804)
 187 #define RTL931X_RMA_CTRL_2                      (0x8808)
 188
 189 /* Advanced SMI control for clause 45 PHYs */
 190 #define RTL930X_SMI_MAC_TYPE_CTRL               (0xCA04)
 191 #define RTL930X_SMI_PORT24_27_ADDR_CTRL         (0xCB90)
 192 #define RTL930X_SMI_PORT0_15_POLLING_SEL        (0xCA08)
 193 #define RTL930X_SMI_PORT16_27_POLLING_SEL       (0xCA0C)
 194
 195 #define RTL930X_SMI_10GPHY_POLLING_REG0_CFG     (0xCBB4)
 196 #define RTL930X_SMI_10GPHY_POLLING_REG9_CFG     (0xCBB8)
 197 #define RTL930X_SMI_10GPHY_POLLING_REG10_CFG    (0xCBBC)
 198 #define RTL930X_SMI_PRVTE_POLLING_CTRL          (0xCA10)
 199
 200 /* Registers of the internal Serdes of the 8390 */
 201 #define RTL839X_SDS12_13_XSG0                   (0xB800)
 202
 203 /* Chip configuration registers of the RTL9310 */
 204 #define RTL931X_MEM_ENCAP_INIT                  (0x4854)
 205 #define RTL931X_MEM_MIB_INIT                    (0x7E18)
 206 #define RTL931X_MEM_ACL_INIT                    (0x40BC)
 207 #define RTL931X_MEM_ALE_INIT_0                  (0x83F0)
 208 #define RTL931X_MEM_ALE_INIT_1                  (0x83F4)
 209 #define RTL931X_MEM_ALE_INIT_2                  (0x82E4)
 210 #define RTL931X_MDX_CTRL_RSVD                   (0x0fcc)
 211 #define RTL931X_PS_SOC_CTRL                     (0x13f8)
 212 #define RTL931X_SMI_10GPHY_POLLING_SEL2         (0xCF8)
 213 #define RTL931X_SMI_10GPHY_POLLING_SEL3         (0xCFC)
 214 #define RTL931X_SMI_10GPHY_POLLING_SEL4         (0xD00)
 215
 216 /* Registers of the internal Serdes of the 8380 */
 217 #define RTL838X_SDS4_FIB_REG0                   (0xF800)
 218
 219 inline int rtl838x_mac_port_ctrl(int p)
 220 {
 221         return RTL838X_MAC_PORT_CTRL + (p << 7);
 222 }
 223
 224 inline int rtl839x_mac_port_ctrl(int p)
 225 {
 226         return RTL839X_MAC_PORT_CTRL + (p << 7);
 227 }
 228
 229 /* On the RTL931XX, the functionality of the MAC port control register is split up
 230  * into RTL931X_MAC_L2_PORT_CTRL and RTL931X_MAC_PORT_CTRL the functionality used
 231  * by the Ethernet driver is in the same bits now in RTL931X_MAC_L2_PORT_CTRL
 232  */
 233
 234 inline int rtl930x_mac_port_ctrl(int p)
 235 {
 236         return RTL930X_MAC_L2_PORT_CTRL + (p << 6);
 237 }
 238
 239 inline int rtl931x_mac_port_ctrl(int p)
 240 {
 241         return RTL931X_MAC_L2_PORT_CTRL + (p << 7);
 242 }
 243
 244 inline int rtl838x_dma_if_rx_ring_size(int i)
 245 {
 246         return RTL838X_DMA_IF_RX_RING_SIZE + ((i >> 3) << 2);
 247 }
 248
 249 inline int rtl839x_dma_if_rx_ring_size(int i)
 250 {
 251         return RTL839X_DMA_IF_RX_RING_SIZE + ((i >> 3) << 2);
 252 }
 253
 254 inline int rtl930x_dma_if_rx_ring_size(int i)
 255 {
 256         return RTL930X_DMA_IF_RX_RING_SIZE + ((i / 3) << 2);
 257 }
 258
 259 inline int rtl931x_dma_if_rx_ring_size(int i)
 260 {
 261         return RTL931X_DMA_IF_RX_RING_SIZE + ((i / 3) << 2);
 262 }
 263
 264 inline int rtl838x_dma_if_rx_ring_cntr(int i)
 265 {
 266         return RTL838X_DMA_IF_RX_RING_CNTR + ((i >> 3) << 2);
 267 }
 268
 269 inline int rtl839x_dma_if_rx_ring_cntr(int i)
 270 {
 271         return RTL839X_DMA_IF_RX_RING_CNTR + ((i >> 3) << 2);
 272 }
 273
 274 inline int rtl930x_dma_if_rx_ring_cntr(int i)
 275 {
 276         return RTL930X_DMA_IF_RX_RING_CNTR + ((i / 3) << 2);
 277 }
 278
 279 inline int rtl931x_dma_if_rx_ring_cntr(int i)
 280 {
 281         return RTL931X_DMA_IF_RX_RING_CNTR + ((i / 3) << 2);
 282 }
 283
 284 inline u32 rtl838x_get_mac_link_sts(int port)
 285 {
 286         return (sw_r32(RTL838X_MAC_LINK_STS) & BIT(port));
 287 }
 288
 289 inline u32 rtl839x_get_mac_link_sts(int p)
 290 {
 291         return (sw_r32(RTL839X_MAC_LINK_STS + ((p >> 5) << 2)) & BIT(p % 32));
 292 }
 293
 294 inline u32 rtl930x_get_mac_link_sts(int port)
 295 {
 296         u32 link = sw_r32(RTL930X_MAC_LINK_STS);
 297
 298         link = sw_r32(RTL930X_MAC_LINK_STS);
 299         pr_info("%s link state is %08x\n", __func__, link);
 300         return link & BIT(port);
 301 }
 302
 303 inline u32 rtl931x_get_mac_link_sts(int p)
 304 {
 305         return (sw_r32(RTL931X_MAC_LINK_STS + ((p >> 5) << 2)) & BIT(p % 32));
 306 }
 307
 308 inline u32 rtl838x_get_mac_link_dup_sts(int port)
 309 {
 310         return (sw_r32(RTL838X_MAC_LINK_DUP_STS) & BIT(port));
 311 }
 312
 313 inline u32 rtl839x_get_mac_link_dup_sts(int p)
 314 {
 315         return (sw_r32(RTL839X_MAC_LINK_DUP_STS + ((p >> 5) << 2)) & BIT(p % 32));
 316 }
 317
 318 inline u32 rtl930x_get_mac_link_dup_sts(int port)
 319 {
 320         return (sw_r32(RTL930X_MAC_LINK_DUP_STS) & BIT(port));
 321 }
 322
 323 inline u32 rtl931x_get_mac_link_dup_sts(int p)
 324 {
 325         return (sw_r32(RTL931X_MAC_LINK_DUP_STS + ((p >> 5) << 2)) & BIT(p % 32));
 326 }
 327
 328 inline u32 rtl838x_get_mac_link_spd_sts(int port)
 329 {
 330         int r = RTL838X_MAC_LINK_SPD_STS + ((port >> 4) << 2);
 331         u32 speed = sw_r32(r);
 332
 333         speed >>= (port % 16) << 1;
 334         return (speed & 0x3);
 335 }
 336
 337 inline u32 rtl839x_get_mac_link_spd_sts(int port)
 338 {
 339         int r = RTL839X_MAC_LINK_SPD_STS + ((port >> 4) << 2);
 340         u32 speed = sw_r32(r);
 341
 342         speed >>= (port % 16) << 1;
 343         return (speed & 0x3);
 344 }
 345
 346
 347 inline u32 rtl930x_get_mac_link_spd_sts(int port)
 348 {
 349         int r = RTL930X_MAC_LINK_SPD_STS + ((port >> 3) << 2);
 350         u32 speed = sw_r32(r);
 351
 352         speed >>= (port % 8) << 2;
 353         return (speed & 0xf);
 354 }
 355
 356 inline u32 rtl931x_get_mac_link_spd_sts(int port)
 357 {
 358         int r = RTL931X_MAC_LINK_SPD_STS + ((port >> 3) << 2);
 359         u32 speed = sw_r32(r);
 360
 361         speed >>= (port % 8) << 2;
 362         return (speed & 0xf);
 363 }
 364
 365 inline u32 rtl838x_get_mac_rx_pause_sts(int port)
 366 {
 367         return (sw_r32(RTL838X_MAC_RX_PAUSE_STS) & (1 << port));
 368 }
 369
 370 inline u32 rtl839x_get_mac_rx_pause_sts(int p)
 371 {
 372         return (sw_r32(RTL839X_MAC_RX_PAUSE_STS + ((p >> 5) << 2)) & BIT(p % 32));
 373 }
 374
 375 inline u32 rtl930x_get_mac_rx_pause_sts(int port)
 376 {
 377         return (sw_r32(RTL930X_MAC_RX_PAUSE_STS) & (1 << port));
 378 }
 379
 380 inline u32 rtl931x_get_mac_rx_pause_sts(int p)
 381 {
 382         return (sw_r32(RTL931X_MAC_RX_PAUSE_STS + ((p >> 5) << 2)) & BIT(p % 32));
 383 }
 384
 385 inline u32 rtl838x_get_mac_tx_pause_sts(int port)
 386 {
 387         return (sw_r32(RTL838X_MAC_TX_PAUSE_STS) & (1 << port));
 388 }
 389
 390 inline u32 rtl839x_get_mac_tx_pause_sts(int p)
 391 {
 392         return (sw_r32(RTL839X_MAC_TX_PAUSE_STS + ((p >> 5) << 2)) & BIT(p % 32));
 393 }
 394
 395 inline u32 rtl930x_get_mac_tx_pause_sts(int port)
 396 {
 397         return (sw_r32(RTL930X_MAC_TX_PAUSE_STS) & (1 << port));
 398 }
 399
 400 inline u32 rtl931x_get_mac_tx_pause_sts(int p)
 401 {
 402         return (sw_r32(RTL931X_MAC_TX_PAUSE_STS + ((p >> 5) << 2)) & BIT(p % 32));
 403 }
 404
 405 struct p_hdr;
 406 struct dsa_tag;
 407
 408 struct rtl838x_eth_reg {
 409         irqreturn_t (*net_irq)(int irq, void *dev_id);
 410         int (*mac_port_ctrl)(int port);
 411         int dma_if_intr_sts;
 412         int dma_if_intr_msk;
 413         int dma_if_intr_rx_runout_sts;
 414         int dma_if_intr_rx_done_sts;
 415         int dma_if_intr_tx_done_sts;
 416         int dma_if_intr_rx_runout_msk;
 417         int dma_if_intr_rx_done_msk;
 418         int dma_if_intr_tx_done_msk;
 419         int l2_ntfy_if_intr_sts;
 420         int l2_ntfy_if_intr_msk;
 421         int dma_if_ctrl;
 422         int mac_force_mode_ctrl;
 423         int dma_rx_base;
 424         int dma_tx_base;
 425         int (*dma_if_rx_ring_size)(int ring);
 426         int (*dma_if_rx_ring_cntr)(int ring);
 427         int dma_if_rx_cur;
 428         int rst_glb_ctrl;
 429         u32 (*get_mac_link_sts)(int port);
 430         u32 (*get_mac_link_dup_sts)(int port);
 431         u32 (*get_mac_link_spd_sts)(int port);
 432         u32 (*get_mac_rx_pause_sts)(int port);
 433         u32 (*get_mac_tx_pause_sts)(int port);
 434         int mac;
 435         int l2_tbl_flush_ctrl;
 436         void (*update_cntr)(int r, int work_done);
 437         void (*create_tx_header)(struct p_hdr *h, unsigned int dest_port, int prio);
 438         bool (*decode_tag)(struct p_hdr *h, struct dsa_tag *tag);
 439 };
 440
 441 int rtl838x_write_phy(u32 port, u32 page, u32 reg, u32 val);
 442 int rtl838x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
 443 int rtl838x_write_mmd_phy(u32 port, u32 addr, u32 reg, u32 val);
 444 int rtl838x_read_mmd_phy(u32 port, u32 addr, u32 reg, u32 *val);
 445 int rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val);
 446 int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
 447 int rtl839x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val);
 448 int rtl839x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val);
 449 int rtl930x_write_phy(u32 port, u32 page, u32 reg, u32 val);
 450 int rtl930x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
 451 int rtl931x_write_phy(u32 port, u32 page, u32 reg, u32 val);
 452 int rtl931x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
 453 int rtl83xx_setup_tc(struct net_device *dev, enum tc_setup_type type, void *type_data);
 454
 455 #endif /* _RTL838X_ETH_H */