1 // SPDX-License-Identifier: GPL-2.0-only
3 #include <asm/mach-rtl838x/mach-rtl83xx.h>
7 #define RTL931X_VLAN_PORT_TAG_STS_INTERNAL 0x0
8 #define RTL931X_VLAN_PORT_TAG_STS_UNTAG 0x1
9 #define RTL931X_VLAN_PORT_TAG_STS_TAGGED 0x2
10 #define RTL931X_VLAN_PORT_TAG_STS_PRIORITY_TAGGED 0x3
12 #define RTL931X_VLAN_PORT_TAG_CTRL_BASE 0x4860
14 #define RTL931X_VLAN_PORT_TAG_CTRL(port) \
15 RTL931X_VLAN_PORT_TAG_CTRL_BASE + (port << 2)
16 #define RTL931X_VLAN_PORT_TAG_EGR_OTAG_STS_MASK GENMASK(13,12)
17 #define RTL931X_VLAN_PORT_TAG_EGR_ITAG_STS_MASK GENMASK(11,10)
18 #define RTL931X_VLAN_PORT_TAG_EGR_OTAG_KEEP_MASK GENMASK(9,9)
19 #define RTL931X_VLAN_PORT_TAG_EGR_ITAG_KEEP_MASK GENMASK(8,8)
20 #define RTL931X_VLAN_PORT_TAG_IGR_OTAG_KEEP_MASK GENMASK(7,7)
21 #define RTL931X_VLAN_PORT_TAG_IGR_ITAG_KEEP_MASK GENMASK(6,6)
22 #define RTL931X_VLAN_PORT_TAG_OTPID_IDX_MASK GENMASK(5,4)
23 #define RTL931X_VLAN_PORT_TAG_OTPID_KEEP_MASK GENMASK(3,3)
24 #define RTL931X_VLAN_PORT_TAG_ITPID_IDX_MASK GENMASK(2,1)
25 #define RTL931X_VLAN_PORT_TAG_ITPID_KEEP_MASK GENMASK(0,0)
27 extern struct mutex smi_lock
;
28 extern struct rtl83xx_soc_info soc_info
;
30 /* Definition of the RTL931X-specific template field IDs as used in the PIE */
31 enum template_field_id
{
32 TEMPLATE_FIELD_SPM0
= 1,
33 TEMPLATE_FIELD_SPM1
= 2,
34 TEMPLATE_FIELD_SPM2
= 3,
35 TEMPLATE_FIELD_SPM3
= 4,
36 TEMPLATE_FIELD_DMAC0
= 9,
37 TEMPLATE_FIELD_DMAC1
= 10,
38 TEMPLATE_FIELD_DMAC2
= 11,
39 TEMPLATE_FIELD_SMAC0
= 12,
40 TEMPLATE_FIELD_SMAC1
= 13,
41 TEMPLATE_FIELD_SMAC2
= 14,
42 TEMPLATE_FIELD_ETHERTYPE
= 15,
43 TEMPLATE_FIELD_OTAG
= 16,
44 TEMPLATE_FIELD_ITAG
= 17,
45 TEMPLATE_FIELD_SIP0
= 18,
46 TEMPLATE_FIELD_SIP1
= 19,
47 TEMPLATE_FIELD_DIP0
= 20,
48 TEMPLATE_FIELD_DIP1
= 21,
49 TEMPLATE_FIELD_IP_TOS_PROTO
= 22,
50 TEMPLATE_FIELD_L4_SPORT
= 23,
51 TEMPLATE_FIELD_L4_DPORT
= 24,
52 TEMPLATE_FIELD_L34_HEADER
= 25,
53 TEMPLATE_FIELD_TCP_INFO
= 26,
54 TEMPLATE_FIELD_SIP2
= 34,
55 TEMPLATE_FIELD_SIP3
= 35,
56 TEMPLATE_FIELD_SIP4
= 36,
57 TEMPLATE_FIELD_SIP5
= 37,
58 TEMPLATE_FIELD_SIP6
= 38,
59 TEMPLATE_FIELD_SIP7
= 39,
60 TEMPLATE_FIELD_DIP2
= 42,
61 TEMPLATE_FIELD_DIP3
= 43,
62 TEMPLATE_FIELD_DIP4
= 44,
63 TEMPLATE_FIELD_DIP5
= 45,
64 TEMPLATE_FIELD_DIP6
= 46,
65 TEMPLATE_FIELD_DIP7
= 47,
66 TEMPLATE_FIELD_FLOW_LABEL
= 49,
67 TEMPLATE_FIELD_DSAP_SSAP
= 50,
68 TEMPLATE_FIELD_FWD_VID
= 52,
69 TEMPLATE_FIELD_RANGE_CHK
= 53,
70 TEMPLATE_FIELD_SLP
= 55,
71 TEMPLATE_FIELD_DLP
= 56,
72 TEMPLATE_FIELD_META_DATA
= 57,
73 TEMPLATE_FIELD_FIRST_MPLS1
= 60,
74 TEMPLATE_FIELD_FIRST_MPLS2
= 61,
75 TEMPLATE_FIELD_DPM3
= 8,
78 /* The meaning of TEMPLATE_FIELD_VLAN depends on phase and the configuration in
79 * RTL931X_PIE_CTRL. We use always the same definition and map to the inner VLAN tag:
81 #define TEMPLATE_FIELD_VLAN TEMPLATE_FIELD_ITAG
83 // Number of fixed templates predefined in the RTL9300 SoC
84 #define N_FIXED_TEMPLATES 5
85 // RTL931x specific predefined templates
86 static enum template_field_id fixed_templates
[N_FIXED_TEMPLATES
][N_FIXED_FIELDS_RTL931X
] =
89 TEMPLATE_FIELD_DMAC0
, TEMPLATE_FIELD_DMAC1
, TEMPLATE_FIELD_DMAC2
,
90 TEMPLATE_FIELD_SMAC0
, TEMPLATE_FIELD_SMAC1
, TEMPLATE_FIELD_SMAC2
,
91 TEMPLATE_FIELD_VLAN
, TEMPLATE_FIELD_IP_TOS_PROTO
, TEMPLATE_FIELD_DSAP_SSAP
,
92 TEMPLATE_FIELD_ETHERTYPE
, TEMPLATE_FIELD_SPM0
, TEMPLATE_FIELD_SPM1
,
93 TEMPLATE_FIELD_SPM2
, TEMPLATE_FIELD_SPM3
95 TEMPLATE_FIELD_SIP0
, TEMPLATE_FIELD_SIP1
, TEMPLATE_FIELD_DIP0
,
96 TEMPLATE_FIELD_DIP1
, TEMPLATE_FIELD_IP_TOS_PROTO
, TEMPLATE_FIELD_TCP_INFO
,
97 TEMPLATE_FIELD_L4_SPORT
, TEMPLATE_FIELD_L4_DPORT
, TEMPLATE_FIELD_VLAN
,
98 TEMPLATE_FIELD_RANGE_CHK
, TEMPLATE_FIELD_SPM0
, TEMPLATE_FIELD_SPM1
,
99 TEMPLATE_FIELD_SPM2
, TEMPLATE_FIELD_SPM3
101 TEMPLATE_FIELD_DMAC0
, TEMPLATE_FIELD_DMAC1
, TEMPLATE_FIELD_DMAC2
,
102 TEMPLATE_FIELD_VLAN
, TEMPLATE_FIELD_ETHERTYPE
, TEMPLATE_FIELD_IP_TOS_PROTO
,
103 TEMPLATE_FIELD_SIP0
, TEMPLATE_FIELD_SIP1
, TEMPLATE_FIELD_DIP0
,
104 TEMPLATE_FIELD_DIP1
, TEMPLATE_FIELD_L4_SPORT
, TEMPLATE_FIELD_L4_DPORT
,
105 TEMPLATE_FIELD_META_DATA
, TEMPLATE_FIELD_SLP
107 TEMPLATE_FIELD_DIP0
, TEMPLATE_FIELD_DIP1
, TEMPLATE_FIELD_DIP2
,
108 TEMPLATE_FIELD_DIP3
, TEMPLATE_FIELD_DIP4
, TEMPLATE_FIELD_DIP5
,
109 TEMPLATE_FIELD_DIP6
, TEMPLATE_FIELD_DIP7
, TEMPLATE_FIELD_IP_TOS_PROTO
,
110 TEMPLATE_FIELD_TCP_INFO
, TEMPLATE_FIELD_L4_SPORT
, TEMPLATE_FIELD_L4_DPORT
,
111 TEMPLATE_FIELD_RANGE_CHK
, TEMPLATE_FIELD_SLP
113 TEMPLATE_FIELD_SIP0
, TEMPLATE_FIELD_SIP1
, TEMPLATE_FIELD_SIP2
,
114 TEMPLATE_FIELD_SIP3
, TEMPLATE_FIELD_SIP4
, TEMPLATE_FIELD_SIP5
,
115 TEMPLATE_FIELD_SIP6
, TEMPLATE_FIELD_SIP7
, TEMPLATE_FIELD_META_DATA
,
116 TEMPLATE_FIELD_VLAN
, TEMPLATE_FIELD_SPM0
, TEMPLATE_FIELD_SPM1
,
117 TEMPLATE_FIELD_SPM2
, TEMPLATE_FIELD_SPM3
121 inline void rtl931x_exec_tbl0_cmd(u32 cmd
)
123 sw_w32(cmd
, RTL931X_TBL_ACCESS_CTRL_0
);
124 do { } while (sw_r32(RTL931X_TBL_ACCESS_CTRL_0
) & (1 << 20));
127 inline void rtl931x_exec_tbl1_cmd(u32 cmd
)
129 sw_w32(cmd
, RTL931X_TBL_ACCESS_CTRL_1
);
130 do { } while (sw_r32(RTL931X_TBL_ACCESS_CTRL_1
) & (1 << 17));
133 inline int rtl931x_tbl_access_data_0(int i
)
135 return RTL931X_TBL_ACCESS_DATA_0(i
);
138 void rtl931x_vlan_profile_dump(int index
)
142 if (index
< 0 || index
> 15)
145 profile
[0] = sw_r32(RTL931X_VLAN_PROFILE_SET(index
));
146 profile
[1] = (sw_r32(RTL931X_VLAN_PROFILE_SET(index
) + 4) & 0x1FFFFFFFULL
) << 32 |
147 (sw_r32(RTL931X_VLAN_PROFILE_SET(index
) + 8) & 0xFFFFFFFF);
148 profile
[2] = (sw_r32(RTL931X_VLAN_PROFILE_SET(index
) + 16) & 0x1FFFFFFFULL
) << 32 |
149 (sw_r32(RTL931X_VLAN_PROFILE_SET(index
) + 12) & 0xFFFFFFFF);
150 profile
[3] = (sw_r32(RTL931X_VLAN_PROFILE_SET(index
) + 20) & 0x1FFFFFFFULL
) << 32 |
151 (sw_r32(RTL931X_VLAN_PROFILE_SET(index
) + 24) & 0xFFFFFFFF);
153 pr_info("VLAN %d: L2 learning: %d, L2 Unknown MultiCast Field %llx, \
154 IPv4 Unknown MultiCast Field %llx, IPv6 Unknown MultiCast Field: %llx",
155 index
, (u32
) (profile
[0] & (3 << 14)), profile
[1], profile
[2], profile
[3]);
158 static void rtl931x_stp_get(struct rtl838x_switch_priv
*priv
, u16 msti
, u32 port_state
[])
161 u32 cmd
= 1 << 20 | /* Execute cmd */
163 5 << 15 | /* Table type 0b101 */
165 priv
->r
->exec_tbl0_cmd(cmd
);
167 for (i
= 0; i
< 4; i
++)
168 port_state
[i
] = sw_r32(priv
->r
->tbl_access_data_0(i
));
171 static void rtl931x_stp_set(struct rtl838x_switch_priv
*priv
, u16 msti
, u32 port_state
[])
174 u32 cmd
= 1 << 20 | /* Execute cmd */
175 1 << 19 | /* Write */
176 5 << 15 | /* Table type 0b101 */
178 for (i
= 0; i
< 4; i
++)
179 sw_w32(port_state
[i
], priv
->r
->tbl_access_data_0(i
));
180 priv
->r
->exec_tbl0_cmd(cmd
);
183 inline static int rtl931x_trk_mbr_ctr(int group
)
185 return RTL931X_TRK_MBR_CTRL
+ (group
<< 2);
188 static void rtl931x_vlan_tables_read(u32 vlan
, struct rtl838x_vlan_info
*info
)
191 // Read VLAN table (3) via register 0
192 struct table_reg
*r
= rtl_table_get(RTL9310_TBL_0
, 3);
194 rtl_table_read(r
, vlan
);
195 v
= sw_r32(rtl_table_data(r
, 0));
196 w
= sw_r32(rtl_table_data(r
, 1));
197 x
= sw_r32(rtl_table_data(r
, 2));
198 y
= sw_r32(rtl_table_data(r
, 3));
199 rtl_table_release(r
);
201 pr_debug("VLAN_READ %d: %08x %08x %08x %08x\n", vlan
, v
, w
, x
, y
);
202 info
->tagged_ports
= ((u64
) v
) << 25 | (w
>> 7);
203 info
->profile_id
= (x
>> 16) & 0xf;
204 info
->fid
= w
& 0x7f; // AKA MSTI depending on context
205 info
->hash_uc_fid
= !!(x
& BIT(31));
206 info
->hash_mc_fid
= !!(x
& BIT(30));
207 info
->if_id
= (x
>> 20) & 0x3ff;
208 info
->profile_id
= (x
>> 16) & 0xf;
209 info
->multicast_grp_mask
= x
& 0xffff;
211 info
->l2_tunnel_list_id
= y
>> 18;
213 info
->l2_tunnel_list_id
= -1;
214 pr_debug("%s read tagged %016llx, profile-id %d, uc %d, mc %d, intf-id %d\n", __func__
,
215 info
->tagged_ports
, info
->profile_id
, info
->hash_uc_fid
, info
->hash_mc_fid
,
218 // Read UNTAG table via table register 3
219 r
= rtl_table_get(RTL9310_TBL_3
, 0);
220 rtl_table_read(r
, vlan
);
221 v
= ((u64
)sw_r32(rtl_table_data(r
, 0))) << 25;
222 v
|= sw_r32(rtl_table_data(r
, 1)) >> 7;
223 rtl_table_release(r
);
225 info
->untagged_ports
= v
;
228 static void rtl931x_vlan_set_tagged(u32 vlan
, struct rtl838x_vlan_info
*info
)
231 // Access VLAN table (1) via register 0
232 struct table_reg
*r
= rtl_table_get(RTL9310_TBL_0
, 3);
234 v
= info
->tagged_ports
>> 25;
235 w
= (info
->tagged_ports
& 0x1fffff) << 7;
236 w
|= info
->fid
& 0x7f;
237 x
= info
->hash_uc_fid
? BIT(31) : 0;
238 x
|= info
->hash_mc_fid
? BIT(30) : 0;
239 x
|= info
->if_id
& 0x3ff << 20;
240 x
|= (info
->profile_id
& 0xf) << 16;
241 x
|= info
->multicast_grp_mask
& 0xffff;
242 if (info
->l2_tunnel_list_id
>= 0) {
243 y
= info
->l2_tunnel_list_id
<< 18;
249 sw_w32(v
, rtl_table_data(r
, 0));
250 sw_w32(w
, rtl_table_data(r
, 1));
251 sw_w32(x
, rtl_table_data(r
, 2));
252 sw_w32(y
, rtl_table_data(r
, 3));
254 rtl_table_write(r
, vlan
);
255 rtl_table_release(r
);
258 static void rtl931x_vlan_set_untagged(u32 vlan
, u64 portmask
)
260 struct table_reg
*r
= rtl_table_get(RTL9310_TBL_3
, 0);
262 rtl839x_set_port_reg_be(portmask
<< 7, rtl_table_data(r
, 0));
263 rtl_table_write(r
, vlan
);
264 rtl_table_release(r
);
267 static inline int rtl931x_mac_force_mode_ctrl(int p
)
269 return RTL931X_MAC_FORCE_MODE_CTRL
+ (p
<< 2);
272 static inline int rtl931x_mac_link_spd_sts(int p
)
274 return RTL931X_MAC_LINK_SPD_STS
+ (((p
>> 3) << 2));
277 static inline int rtl931x_mac_port_ctrl(int p
)
279 return RTL931X_MAC_L2_PORT_CTRL
+ (p
<< 7);
282 static inline int rtl931x_l2_port_new_salrn(int p
)
284 return RTL931X_L2_PORT_NEW_SALRN(p
);
287 static inline int rtl931x_l2_port_new_sa_fwd(int p
)
289 return RTL931X_L2_PORT_NEW_SA_FWD(p
);
292 irqreturn_t
rtl931x_switch_irq(int irq
, void *dev_id
)
294 struct dsa_switch
*ds
= dev_id
;
295 u32 status
= sw_r32(RTL931X_ISR_GLB_SRC
);
296 u64 ports
= rtl839x_get_port_reg_le(RTL931X_ISR_PORT_LINK_STS_CHG
);
301 rtl839x_set_port_reg_le(ports
, RTL931X_ISR_PORT_LINK_STS_CHG
);
302 pr_debug("RTL931X Link change: status: %x, ports %016llx\n", status
, ports
);
304 link
= rtl839x_get_port_reg_le(RTL931X_MAC_LINK_STS
);
305 // Must re-read this to get correct status
306 link
= rtl839x_get_port_reg_le(RTL931X_MAC_LINK_STS
);
307 pr_debug("RTL931X Link change: status: %x, link status %016llx\n", status
, link
);
309 for (i
= 0; i
< 56; i
++) {
310 if (ports
& BIT_ULL(i
)) {
311 if (link
& BIT_ULL(i
)) {
312 pr_info("%s port %d up\n", __func__
, i
);
313 dsa_port_phylink_mac_change(ds
, i
, true);
315 pr_info("%s port %d down\n", __func__
, i
);
316 dsa_port_phylink_mac_change(ds
, i
, false);
324 int rtl931x_write_phy(u32 port
, u32 page
, u32 reg
, u32 val
)
330 if (port
> 63 || page
> 4095 || reg
> 31)
333 mutex_lock(&smi_lock
);
334 pr_debug("%s: writing to phy %d %d %d %d\n", __func__
, port
, page
, reg
, val
);
335 /* Clear both port registers */
336 sw_w32(0, RTL931X_SMI_INDRT_ACCESS_CTRL_2
);
337 sw_w32(0, RTL931X_SMI_INDRT_ACCESS_CTRL_2
+ 4);
338 sw_w32_mask(0, BIT(port
% 32), RTL931X_SMI_INDRT_ACCESS_CTRL_2
+ (port
/ 32) * 4);
340 sw_w32_mask(0xffff, val
, RTL931X_SMI_INDRT_ACCESS_CTRL_3
);
342 v
= reg
<< 6 | page
<< 11 ;
343 sw_w32(v
, RTL931X_SMI_INDRT_ACCESS_CTRL_0
);
345 sw_w32(0x1ff, RTL931X_SMI_INDRT_ACCESS_CTRL_1
);
347 v
|= BIT(4) | 1; /* Write operation and execute */
348 sw_w32(v
, RTL931X_SMI_INDRT_ACCESS_CTRL_0
);
351 } while (sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_0
) & 0x1);
353 if (sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_0
) & 0x2)
356 mutex_unlock(&smi_lock
);
361 int rtl931x_read_phy(u32 port
, u32 page
, u32 reg
, u32
*val
)
365 if (port
> 63 || page
> 4095 || reg
> 31)
368 mutex_lock(&smi_lock
);
370 sw_w32(port
<< 5, RTL931X_SMI_INDRT_ACCESS_BC_PHYID_CTRL
);
372 v
= reg
<< 6 | page
<< 11 | 1;
373 sw_w32(v
, RTL931X_SMI_INDRT_ACCESS_CTRL_0
);
376 } while (sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_0
) & 0x1);
378 v
= sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_0
);
379 *val
= sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_3
);
380 *val
= (*val
& 0xffff0000) >> 16;
382 pr_debug("%s: port %d, page: %d, reg: %x, val: %x, v: %08x\n",
383 __func__
, port
, page
, reg
, *val
, v
);
385 mutex_unlock(&smi_lock
);
390 /* Read an mmd register of the PHY */
391 int rtl931x_read_mmd_phy(u32 port
, u32 devnum
, u32 regnum
, u32
*val
)
395 /* Select PHY register type
396 * If select 1G/10G MMD register type, registers EXT_PAGE, MAIN_PAGE and REG settings are don’t care.
397 * 0x0 Normal register (Clause 22)
398 * 0x1: 1G MMD register (MMD via Clause 22 registers 13 and 14)
399 * 0x2: 10G MMD register (MMD via Clause 45)
401 int type
= (regnum
& MII_ADDR_C45
)?2:1;
403 mutex_lock(&smi_lock
);
405 // Set PHY to access via port-number
406 sw_w32(port
<< 5, RTL931X_SMI_INDRT_ACCESS_BC_PHYID_CTRL
);
408 // Set MMD device number and register to write to
409 sw_w32(devnum
<< 16 | mdiobus_c45_regad(regnum
), RTL931X_SMI_INDRT_ACCESS_MMD_CTRL
);
411 v
= type
<< 2 | BIT(0); // MMD-access-type | EXEC
412 sw_w32(v
, RTL931X_SMI_INDRT_ACCESS_CTRL_0
);
415 v
= sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_0
);
416 } while (v
& BIT(0));
418 // Check for error condition
422 *val
= sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_3
) >> 16;
424 pr_debug("%s: port %d, dev: %x, regnum: %x, val: %x (err %d)\n", __func__
,
425 port
, devnum
, mdiobus_c45_regad(regnum
), *val
, err
);
427 mutex_unlock(&smi_lock
);
432 /* Write to an mmd register of the PHY */
433 int rtl931x_write_mmd_phy(u32 port
, u32 devnum
, u32 regnum
, u32 val
)
437 int type
= (regnum
& MII_ADDR_C45
)?2:1;
440 mutex_lock(&smi_lock
);
442 // Set PHY to access via port-mask
444 sw_w32((u32
)pm
, RTL931X_SMI_INDRT_ACCESS_CTRL_2
);
445 sw_w32((u32
)(pm
>> 32), RTL931X_SMI_INDRT_ACCESS_CTRL_2
+ 4);
448 sw_w32_mask(0xffff, val
, RTL931X_SMI_INDRT_ACCESS_CTRL_3
);
450 // Set MMD device number and register to write to
451 sw_w32(devnum
<< 16 | mdiobus_c45_regad(regnum
), RTL931X_SMI_INDRT_ACCESS_MMD_CTRL
);
453 v
= BIT(4) | type
<< 2 | BIT(0); // WRITE | MMD-access-type | EXEC
454 sw_w32(v
, RTL931X_SMI_INDRT_ACCESS_CTRL_0
);
457 v
= sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_0
);
458 } while (v
& BIT(0));
460 pr_debug("%s: port %d, dev: %x, regnum: %x, val: %x (err %d)\n", __func__
,
461 port
, devnum
, mdiobus_c45_regad(regnum
), val
, err
);
462 mutex_unlock(&smi_lock
);
467 void rtl931x_print_matrix(void)
469 volatile u64
*ptr
= RTL838X_SW_BASE
+ RTL839X_PORT_ISO_CTRL(0);
472 for (i
= 0; i
< 52; i
+= 4)
473 pr_info("> %16llx %16llx %16llx %16llx\n",
474 ptr
[i
+ 0], ptr
[i
+ 1], ptr
[i
+ 2], ptr
[i
+ 3]);
475 pr_info("CPU_PORT> %16llx\n", ptr
[52]);
478 void rtl931x_set_receive_management_action(int port
, rma_ctrl_t type
, action_type_t action
)
482 /* hack for value mapping */
483 if (type
== GRATARP
&& action
== COPY2CPU
)
484 action
= TRAP2MASTERCPU
;
508 sw_w32_mask(7 << ((port
% 10) * 3), value
<< ((port
% 10) * 3), RTL931X_RMA_BPDU_CTRL
+ ((port
/ 10) << 2));
512 sw_w32_mask(3 << 2, value
<< 2, RTL931X_RMA_PTP_CTRL
+ (port
<< 2));
514 sw_w32_mask(3, value
, RTL931X_RMA_PTP_CTRL
+ (port
<< 2));
517 sw_w32_mask(3 << 2, value
<< 2, RTL931X_RMA_PTP_CTRL
+ (port
<< 2));
520 sw_w32_mask(3, value
, RTL931X_RMA_PTP_CTRL
+ (port
<< 2));
523 sw_w32_mask(7 << ((port
% 10) * 3), value
<< ((port
% 10) * 3), RTL931X_RMA_LLTP_CTRL
+ ((port
/ 10) << 2));
526 sw_w32_mask(7 << ((port
% 10) * 3), value
<< ((port
% 10) * 3), RTL931X_RMA_EAPOL_CTRL
+ ((port
/ 10) << 2));
529 sw_w32_mask(3 << ((port
& 0xf) << 1), value
<< ((port
& 0xf) << 1), RTL931X_TRAP_ARP_GRAT_PORT_ACT
+ ((port
>> 4) << 2));
534 u64
rtl931x_traffic_get(int source
)
537 struct table_reg
*r
= rtl_table_get(RTL9310_TBL_0
, 6);
539 rtl_table_read(r
, source
);
540 v
= sw_r32(rtl_table_data(r
, 0));
541 rtl_table_release(r
);
547 /* Enable traffic between a source port and a destination port matrix */
548 void rtl931x_traffic_set(int source
, u64 dest_matrix
)
550 struct table_reg
*r
= rtl_table_get(RTL9310_TBL_0
, 6);
552 sw_w32((dest_matrix
<< 3), rtl_table_data(r
, 0));
553 rtl_table_write(r
, source
);
554 rtl_table_release(r
);
557 void rtl931x_traffic_enable(int source
, int dest
)
559 struct table_reg
*r
= rtl_table_get(RTL9310_TBL_0
, 6);
560 rtl_table_read(r
, source
);
561 sw_w32_mask(0, BIT(dest
+ 3), rtl_table_data(r
, 0));
562 rtl_table_write(r
, source
);
563 rtl_table_release(r
);
566 void rtl931x_traffic_disable(int source
, int dest
)
568 struct table_reg
*r
= rtl_table_get(RTL9310_TBL_0
, 6);
569 rtl_table_read(r
, source
);
570 sw_w32_mask(BIT(dest
+ 3), 0, rtl_table_data(r
, 0));
571 rtl_table_write(r
, source
);
572 rtl_table_release(r
);
575 static u64
rtl931x_l2_hash_seed(u64 mac
, u32 vid
)
585 /* Calculate both the block 0 and the block 1 hash by applyingthe same hash
586 * algorithm as the one used currently by the ASIC to the seed, and return
587 * both hashes in the lower and higher word of the return value since only 12 bit of
588 * the hash are significant.
590 static u32
rtl931x_l2_hash_key(struct rtl838x_switch_priv
*priv
, u64 seed
)
592 u32 h
, h0
, h1
, h2
, h3
, h4
, k0
, k1
;
595 h1
= (seed
>> 12) & 0xfff;
596 h2
= (seed
>> 24) & 0xfff;
597 h3
= (seed
>> 36) & 0xfff;
598 h4
= (seed
>> 48) & 0xfff;
599 h4
= ((h4
& 0x7) << 9) | ((h4
>> 3) & 0x1ff);
600 k0
= h0
^ h1
^ h2
^ h3
^ h4
;
603 h0
= ((h0
& 0x1ff) << 3) | ((h0
>> 9) & 0x7);
604 h1
= (seed
>> 12) & 0xfff;
605 h1
= ((h1
& 0x3f) << 6) | ((h1
>> 6) & 0x3f);
606 h2
= (seed
>> 24) & 0xfff;
607 h3
= (seed
>> 36) & 0xfff;
608 h3
= ((h3
& 0x3f) << 6) | ((h3
>> 6) & 0x3f);
609 h4
= (seed
>> 48) & 0xfff;
610 k1
= h0
^ h1
^ h2
^ h3
^ h4
;
612 // Algorithm choice for block 0
613 if (sw_r32(RTL931X_L2_CTRL
) & BIT(0))
618 /* Algorithm choice for block 1
619 * Since k0 and k1 are < 4096, adding 4096 will offset the hash into the second
621 * 4096 is in fact the hash-table size 32768 divided by 4 hashes per bucket
622 * divided by 2 to divide the hash space in 2
624 if (sw_r32(RTL931X_L2_CTRL
) & BIT(1))
625 h
|= (k1
+ 4096) << 16;
627 h
|= (k0
+ 4096) << 16;
632 /* Fills an L2 entry structure from the SoC registers */
633 static void rtl931x_fill_l2_entry(u32 r
[], struct rtl838x_l2_entry
*e
)
635 pr_debug("In %s valid?\n", __func__
);
636 e
->valid
= !!(r
[0] & BIT(31));
640 pr_debug("%s: entry valid, raw: %08x %08x %08x %08x\n", __func__
, r
[0], r
[1], r
[2], r
[3]);
642 e
->is_ipv6_mc
= false;
644 e
->mac
[0] = r
[0] >> 8;
646 e
->mac
[2] = r
[1] >> 24;
647 e
->mac
[3] = r
[1] >> 16;
648 e
->mac
[4] = r
[1] >> 8;
651 e
->is_open_flow
= !!(r
[0] & BIT(30));
652 e
->is_pe_forward
= !!(r
[0] & BIT(29));
653 e
->next_hop
= !!(r
[2] & BIT(30));
654 e
->rvid
= (r
[0] >> 16) & 0xfff;
656 /* Is it a unicast entry? check multicast bit */
657 if (!(e
->mac
[0] & 1)) {
658 e
->type
= L2_UNICAST
;
659 e
->is_l2_tunnel
= !!(r
[2] & BIT(31));
660 e
->is_static
= !!(r
[2] & BIT(13));
661 e
->port
= (r
[2] >> 19) & 0x3ff;
662 // Check for trunk port
663 if (r
[2] & BIT(29)) {
665 e
->stack_dev
= (e
->port
>> 9) & 1;
666 e
->trunk
= e
->port
& 0x3f;
669 e
->stack_dev
= (e
->port
>> 6) & 0xf;
670 e
->port
= e
->port
& 0x3f;
673 e
->block_da
= !!(r
[2] & BIT(14));
674 e
->block_sa
= !!(r
[2] & BIT(15));
675 e
->suspended
= !!(r
[2] & BIT(12));
676 e
->age
= (r
[2] >> 16) & 3;
678 // the UC_VID field in hardware is used for the VID or for the route id
680 e
->nh_route_id
= r
[2] & 0x7ff;
683 e
->vid
= r
[2] & 0xfff;
687 e
->l2_tunnel_id
= ((r
[2] & 0xff) << 4) | (r
[3] >> 28);
688 // TODO: Implement VLAN conversion
690 e
->type
= L2_MULTICAST
;
691 e
->is_local_forward
= !!(r
[2] & BIT(31));
692 e
->is_remote_forward
= !!(r
[2] & BIT(17));
693 e
->mc_portmask_index
= (r
[2] >> 18) & 0xfff;
694 e
->l2_tunnel_list_id
= (r
[2] >> 4) & 0x1fff;
698 /* Fills the 3 SoC table registers r[] with the information of in the rtl838x_l2_entry */
699 static void rtl931x_fill_l2_row(u32 r
[], struct rtl838x_l2_entry
*e
)
704 r
[0] = r
[1] = r
[2] = 0;
708 r
[2] = BIT(31); // Set valid bit
710 r
[0] = ((u32
)e
->mac
[0]) << 24 |
711 ((u32
)e
->mac
[1]) << 16 |
712 ((u32
)e
->mac
[2]) << 8 |
714 r
[1] = ((u32
)e
->mac
[4]) << 24 |
715 ((u32
)e
->mac
[5]) << 16;
717 r
[2] |= e
->next_hop
? BIT(12) : 0;
719 if (e
->type
== L2_UNICAST
) {
720 r
[2] |= e
->is_static
? BIT(14) : 0;
721 r
[1] |= e
->rvid
& 0xfff;
722 r
[2] |= (e
->port
& 0x3ff) << 20;
725 port
= e
->stack_dev
<< 9 | (e
->port
& 0x3f);
727 port
= (e
->stack_dev
& 0xf) << 6;
728 port
|= e
->port
& 0x3f;
731 r
[2] |= e
->block_da
? BIT(15) : 0;
732 r
[2] |= e
->block_sa
? BIT(17) : 0;
733 r
[2] |= e
->suspended
? BIT(13) : 0;
734 r
[2] |= (e
->age
& 0x3) << 17;
735 // the UC_VID field in hardware is used for the VID or for the route id
737 r
[2] |= e
->nh_route_id
& 0x7ff;
739 r
[2] |= e
->vid
& 0xfff;
740 } else { // L2_MULTICAST
741 r
[2] |= (e
->mc_portmask_index
& 0x3ff) << 16;
742 r
[2] |= e
->mc_mac_index
& 0x7ff;
746 /* Read an L2 UC or MC entry out of a hash bucket of the L2 forwarding table
747 * hash is the id of the bucket and pos is the position of the entry in that bucket
748 * The data read from the SoC is filled into rtl838x_l2_entry
750 static u64
rtl931x_read_l2_entry_using_hash(u32 hash
, u32 pos
, struct rtl838x_l2_entry
*e
)
753 struct table_reg
*q
= rtl_table_get(RTL9310_TBL_0
, 0);
759 pr_debug("%s: hash %08x, pos: %d\n", __func__
, hash
, pos
);
761 /* On the RTL93xx, 2 different hash algorithms are used making it a total of
762 * 8 buckets that need to be searched, 4 for each hash-half
763 * Use second hash space when bucket is between 4 and 8
772 idx
= (0 << 14) | (hash
<< 2) | pos
; // Search SRAM, with hash and at pos in bucket
773 pr_debug("%s: NOW hash %08x, pos: %d\n", __func__
, hash
, pos
);
775 rtl_table_read(q
, idx
);
776 for (i
= 0; i
< 4; i
++)
777 r
[i
] = sw_r32(rtl_table_data(q
, i
));
779 rtl_table_release(q
);
781 rtl931x_fill_l2_entry(r
, e
);
783 pr_debug("%s: valid: %d, nh: %d\n", __func__
, e
->valid
, e
->next_hop
);
787 mac
= ((u64
)e
->mac
[0]) << 40 |
788 ((u64
)e
->mac
[1]) << 32 |
789 ((u64
)e
->mac
[2]) << 24 |
790 ((u64
)e
->mac
[3]) << 16 |
791 ((u64
)e
->mac
[4]) << 8 |
794 seed
= rtl931x_l2_hash_seed(mac
, e
->rvid
);
795 pr_debug("%s: mac %016llx, seed %016llx\n", __func__
, mac
, seed
);
797 // return vid with concatenated mac as unique id
801 static u64
rtl931x_read_cam(int idx
, struct rtl838x_l2_entry
*e
)
806 static void rtl931x_write_cam(int idx
, struct rtl838x_l2_entry
*e
)
810 static void rtl931x_write_l2_entry_using_hash(u32 hash
, u32 pos
, struct rtl838x_l2_entry
*e
)
813 struct table_reg
*q
= rtl_table_get(RTL9310_TBL_0
, 0);
814 u32 idx
= (0 << 14) | (hash
<< 2) | pos
; // Access SRAM, with hash and at pos in bucket
817 pr_info("%s: hash %d, pos %d\n", __func__
, hash
, pos
);
818 pr_info("%s: index %d -> mac %02x:%02x:%02x:%02x:%02x:%02x\n", __func__
, idx
,
819 e
->mac
[0], e
->mac
[1], e
->mac
[2], e
->mac
[3],e
->mac
[4],e
->mac
[5]);
821 rtl931x_fill_l2_row(r
, e
);
822 pr_info("%s: %d: %08x %08x %08x\n", __func__
, idx
, r
[0], r
[1], r
[2]);
824 for (i
= 0; i
< 4; i
++)
825 sw_w32(r
[i
], rtl_table_data(q
, i
));
827 rtl_table_write(q
, idx
);
828 rtl_table_release(q
);
831 static void rtl931x_vlan_fwd_on_inner(int port
, bool is_set
)
833 // Always set all tag modes to fwd based on either inner or outer tag
835 sw_w32_mask(0, 0xf, RTL931X_VLAN_PORT_FWD
+ (port
<< 2));
837 sw_w32_mask(0xf, 0, RTL931X_VLAN_PORT_FWD
+ (port
<< 2));
840 static void rtl931x_vlan_profile_setup(int profile
)
845 pr_info("In %s\n", __func__
);
850 p
[0] = sw_r32(RTL931X_VLAN_PROFILE_SET(profile
));
852 // Enable routing of Ipv4/6 Unicast and IPv4/6 Multicast traffic
853 //p[0] |= BIT(17) | BIT(16) | BIT(13) | BIT(12);
854 p
[0] |= 0x3 << 11; // COPY2CPU
856 p
[1] = 0x1FFFFFF; // L2 unknwon MC flooding portmask all ports, including the CPU-port
858 p
[3] = 0x1FFFFFF; // IPv4 unknwon MC flooding portmask
860 p
[5] = 0x1FFFFFF; // IPv6 unknwon MC flooding portmask
863 for (int i
= 0; i
< 7; i
++)
864 sw_w32(p
[i
], RTL931X_VLAN_PROFILE_SET(profile
) + i
* 4);
865 pr_info("Leaving %s\n", __func__
);
868 static void rtl931x_l2_learning_setup(void)
870 // Portmask for flooding broadcast traffic
871 rtl839x_set_port_reg_be(0x1FFFFFFFFFFFFFF, RTL931X_L2_BC_FLD_PMSK
);
873 // Portmask for flooding unicast traffic with unknown destination
874 rtl839x_set_port_reg_be(0x1FFFFFFFFFFFFFF, RTL931X_L2_UNKN_UC_FLD_PMSK
);
876 // Limit learning to maximum: 64k entries, after that just flood (bits 0-2)
877 sw_w32((0xffff << 3) | FORWARD
, RTL931X_L2_LRN_CONSTRT_CTRL
);
880 static u64
rtl931x_read_mcast_pmask(int idx
)
883 // Read MC_PMSK (2) via register RTL9310_TBL_0
884 struct table_reg
*q
= rtl_table_get(RTL9310_TBL_0
, 2);
886 rtl_table_read(q
, idx
);
887 portmask
= sw_r32(rtl_table_data(q
, 0));
889 portmask
|= sw_r32(rtl_table_data(q
, 1));
891 rtl_table_release(q
);
893 pr_debug("%s: Index idx %d has portmask %016llx\n", __func__
, idx
, portmask
);
898 static void rtl931x_write_mcast_pmask(int idx
, u64 portmask
)
902 // Access MC_PMSK (2) via register RTL9310_TBL_0
903 struct table_reg
*q
= rtl_table_get(RTL9310_TBL_0
, 2);
905 pr_debug("%s: Index idx %d has portmask %016llx\n", __func__
, idx
, pm
);
907 sw_w32((u32
)(pm
>> 32), rtl_table_data(q
, 0));
908 sw_w32((u32
)pm
, rtl_table_data(q
, 1));
909 rtl_table_write(q
, idx
);
910 rtl_table_release(q
);
914 static int rtl931x_set_ageing_time(unsigned long msec
)
916 int t
= sw_r32(RTL931X_L2_AGE_CTRL
);
920 pr_debug("L2 AGING time: %d sec\n", t
);
922 t
= (msec
/ 100 + 7) / 8;
923 t
= t
> 0x1FFFFF ? 0x1FFFFF : t
;
924 sw_w32_mask(0x1FFFFF, t
, RTL931X_L2_AGE_CTRL
);
925 pr_debug("Dynamic aging for ports: %x\n", sw_r32(RTL931X_L2_PORT_AGE_CTRL
));
929 void rtl931x_sw_init(struct rtl838x_switch_priv
*priv
)
931 // rtl931x_sds_init(priv);
934 static void rtl931x_pie_lookup_enable(struct rtl838x_switch_priv
*priv
, int index
)
936 int block
= index
/ PIE_BLOCK_SIZE
;
938 sw_w32_mask(0, BIT(block
), RTL931X_PIE_BLK_LOOKUP_CTRL
);
941 /* Fills the data in the intermediate representation in the pie_rule structure
942 * into a data field for a given template field field_type
943 * TODO: This function looks very similar to the function of the rtl9300, but
944 * since it uses the physical template_field_id, which are different for each
945 * SoC and there are other field types, it is actually not. If we would also use
946 * an intermediate representation for a field type, we would could have one
947 * pie_data_fill function for all SoCs, provided we have also for each SoC a
948 * function to map between physical and intermediate field type
950 int rtl931x_pie_data_fill(enum template_field_id field_type
, struct pie_rule
*pr
, u16
*data
, u16
*data_m
)
954 switch (field_type
) {
955 case TEMPLATE_FIELD_SPM0
:
959 case TEMPLATE_FIELD_SPM1
:
960 *data
= pr
->spm
>> 16;
961 *data_m
= pr
->spm_m
>> 16;
963 case TEMPLATE_FIELD_OTAG
:
965 *data_m
= pr
->otag_m
;
967 case TEMPLATE_FIELD_SMAC0
:
969 *data
= (*data
<< 8) | pr
->smac
[5];
970 *data_m
= pr
->smac_m
[4];
971 *data_m
= (*data_m
<< 8) | pr
->smac_m
[5];
973 case TEMPLATE_FIELD_SMAC1
:
975 *data
= (*data
<< 8) | pr
->smac
[3];
976 *data_m
= pr
->smac_m
[2];
977 *data_m
= (*data_m
<< 8) | pr
->smac_m
[3];
979 case TEMPLATE_FIELD_SMAC2
:
981 *data
= (*data
<< 8) | pr
->smac
[1];
982 *data_m
= pr
->smac_m
[0];
983 *data_m
= (*data_m
<< 8) | pr
->smac_m
[1];
985 case TEMPLATE_FIELD_DMAC0
:
987 *data
= (*data
<< 8) | pr
->dmac
[5];
988 *data_m
= pr
->dmac_m
[4];
989 *data_m
= (*data_m
<< 8) | pr
->dmac_m
[5];
991 case TEMPLATE_FIELD_DMAC1
:
993 *data
= (*data
<< 8) | pr
->dmac
[3];
994 *data_m
= pr
->dmac_m
[2];
995 *data_m
= (*data_m
<< 8) | pr
->dmac_m
[3];
997 case TEMPLATE_FIELD_DMAC2
:
999 *data
= (*data
<< 8) | pr
->dmac
[1];
1000 *data_m
= pr
->dmac_m
[0];
1001 *data_m
= (*data_m
<< 8) | pr
->dmac_m
[1];
1003 case TEMPLATE_FIELD_ETHERTYPE
:
1004 *data
= pr
->ethertype
;
1005 *data_m
= pr
->ethertype_m
;
1007 case TEMPLATE_FIELD_ITAG
:
1009 *data_m
= pr
->itag_m
;
1011 case TEMPLATE_FIELD_SIP0
:
1013 *data
= pr
->sip6
.s6_addr16
[7];
1014 *data_m
= pr
->sip6_m
.s6_addr16
[7];
1017 *data_m
= pr
->sip_m
;
1020 case TEMPLATE_FIELD_SIP1
:
1022 *data
= pr
->sip6
.s6_addr16
[6];
1023 *data_m
= pr
->sip6_m
.s6_addr16
[6];
1025 *data
= pr
->sip
>> 16;
1026 *data_m
= pr
->sip_m
>> 16;
1029 case TEMPLATE_FIELD_SIP2
:
1030 case TEMPLATE_FIELD_SIP3
:
1031 case TEMPLATE_FIELD_SIP4
:
1032 case TEMPLATE_FIELD_SIP5
:
1033 case TEMPLATE_FIELD_SIP6
:
1034 case TEMPLATE_FIELD_SIP7
:
1035 *data
= pr
->sip6
.s6_addr16
[5 - (field_type
- TEMPLATE_FIELD_SIP2
)];
1036 *data_m
= pr
->sip6_m
.s6_addr16
[5 - (field_type
- TEMPLATE_FIELD_SIP2
)];
1038 case TEMPLATE_FIELD_DIP0
:
1040 *data
= pr
->dip6
.s6_addr16
[7];
1041 *data_m
= pr
->dip6_m
.s6_addr16
[7];
1044 *data_m
= pr
->dip_m
;
1047 case TEMPLATE_FIELD_DIP1
:
1049 *data
= pr
->dip6
.s6_addr16
[6];
1050 *data_m
= pr
->dip6_m
.s6_addr16
[6];
1052 *data
= pr
->dip
>> 16;
1053 *data_m
= pr
->dip_m
>> 16;
1056 case TEMPLATE_FIELD_DIP2
:
1057 case TEMPLATE_FIELD_DIP3
:
1058 case TEMPLATE_FIELD_DIP4
:
1059 case TEMPLATE_FIELD_DIP5
:
1060 case TEMPLATE_FIELD_DIP6
:
1061 case TEMPLATE_FIELD_DIP7
:
1062 *data
= pr
->dip6
.s6_addr16
[5 - (field_type
- TEMPLATE_FIELD_DIP2
)];
1063 *data_m
= pr
->dip6_m
.s6_addr16
[5 - (field_type
- TEMPLATE_FIELD_DIP2
)];
1065 case TEMPLATE_FIELD_IP_TOS_PROTO
:
1066 *data
= pr
->tos_proto
;
1067 *data_m
= pr
->tos_proto_m
;
1069 case TEMPLATE_FIELD_L4_SPORT
:
1071 *data_m
= pr
->sport_m
;
1073 case TEMPLATE_FIELD_L4_DPORT
:
1075 *data_m
= pr
->dport_m
;
1077 case TEMPLATE_FIELD_DSAP_SSAP
:
1078 *data
= pr
->dsap_ssap
;
1079 *data_m
= pr
->dsap_ssap_m
;
1081 case TEMPLATE_FIELD_TCP_INFO
:
1082 *data
= pr
->tcp_info
;
1083 *data_m
= pr
->tcp_info_m
;
1085 case TEMPLATE_FIELD_RANGE_CHK
:
1086 pr_info("TEMPLATE_FIELD_RANGE_CHK: not configured\n");
1089 pr_info("%s: unknown field %d\n", __func__
, field_type
);
1096 /* Reads the intermediate representation of the templated match-fields of the
1097 * PIE rule in the pie_rule structure and fills in the raw data fields in the
1098 * raw register space r[].
1099 * The register space configuration size is identical for the RTL8380/90 and RTL9300,
1100 * however the RTL931X has 2 more registers / fields and the physical field-ids are different
1102 * On the RTL9300 the mask fields are not word-aligend!
1104 static void rtl931x_write_pie_templated(u32 r
[], struct pie_rule
*pr
, enum template_field_id t
[])
1109 for (i
= 0; i
< N_FIXED_FIELDS
; i
++) {
1110 rtl931x_pie_data_fill(t
[i
], pr
, &data
, &data_m
);
1112 // On the RTL9300, the mask fields are not word aligned!
1114 r
[5 - i
/ 2] = data
;
1115 r
[12 - i
/ 2] |= ((u32
)data_m
<< 8);
1117 r
[5 - i
/ 2] |= ((u32
)data
) << 16;
1118 r
[12 - i
/ 2] |= ((u32
)data_m
) << 24;
1119 r
[11 - i
/ 2] |= ((u32
)data_m
) >> 8;
1124 static void rtl931x_read_pie_fixed_fields(u32 r
[], struct pie_rule
*pr
)
1126 pr
->mgnt_vlan
= r
[7] & BIT(31);
1127 if (pr
->phase
== PHASE_IACL
)
1128 pr
->dmac_hit_sw
= r
[7] & BIT(30);
1129 else // TODO: EACL/VACL phase handling
1130 pr
->content_too_deep
= r
[7] & BIT(30);
1131 pr
->not_first_frag
= r
[7] & BIT(29);
1132 pr
->frame_type_l4
= (r
[7] >> 26) & 7;
1133 pr
->frame_type
= (r
[7] >> 24) & 3;
1134 pr
->otag_fmt
= (r
[7] >> 23) & 1;
1135 pr
->itag_fmt
= (r
[7] >> 22) & 1;
1136 pr
->otag_exist
= (r
[7] >> 21) & 1;
1137 pr
->itag_exist
= (r
[7] >> 20) & 1;
1138 pr
->frame_type_l2
= (r
[7] >> 18) & 3;
1139 pr
->igr_normal_port
= (r
[7] >> 17) & 1;
1140 pr
->tid
= (r
[7] >> 16) & 1;
1142 pr
->mgnt_vlan_m
= r
[14] & BIT(15);
1143 if (pr
->phase
== PHASE_IACL
)
1144 pr
->dmac_hit_sw_m
= r
[14] & BIT(14);
1146 pr
->content_too_deep_m
= r
[14] & BIT(14);
1147 pr
->not_first_frag_m
= r
[14] & BIT(13);
1148 pr
->frame_type_l4_m
= (r
[14] >> 10) & 7;
1149 pr
->frame_type_m
= (r
[14] >> 8) & 3;
1150 pr
->otag_fmt_m
= r
[14] & BIT(7);
1151 pr
->itag_fmt_m
= r
[14] & BIT(6);
1152 pr
->otag_exist_m
= r
[14] & BIT(5);
1153 pr
->itag_exist_m
= r
[14] & BIT (4);
1154 pr
->frame_type_l2_m
= (r
[14] >> 2) & 3;
1155 pr
->igr_normal_port_m
= r
[14] & BIT(1);
1156 pr
->tid_m
= r
[14] & 1;
1158 pr
->valid
= r
[15] & BIT(31);
1159 pr
->cond_not
= r
[15] & BIT(30);
1160 pr
->cond_and1
= r
[15] & BIT(29);
1161 pr
->cond_and2
= r
[15] & BIT(28);
1164 static void rtl931x_write_pie_fixed_fields(u32 r
[], struct pie_rule
*pr
)
1166 r
[7] |= pr
->mgnt_vlan
? BIT(31) : 0;
1167 if (pr
->phase
== PHASE_IACL
)
1168 r
[7] |= pr
->dmac_hit_sw
? BIT(30) : 0;
1170 r
[7] |= pr
->content_too_deep
? BIT(30) : 0;
1171 r
[7] |= pr
->not_first_frag
? BIT(29) : 0;
1172 r
[7] |= ((u32
) (pr
->frame_type_l4
& 0x7)) << 26;
1173 r
[7] |= ((u32
) (pr
->frame_type
& 0x3)) << 24;
1174 r
[7] |= pr
->otag_fmt
? BIT(23) : 0;
1175 r
[7] |= pr
->itag_fmt
? BIT(22) : 0;
1176 r
[7] |= pr
->otag_exist
? BIT(21) : 0;
1177 r
[7] |= pr
->itag_exist
? BIT(20) : 0;
1178 r
[7] |= ((u32
) (pr
->frame_type_l2
& 0x3)) << 18;
1179 r
[7] |= pr
->igr_normal_port
? BIT(17) : 0;
1180 r
[7] |= ((u32
) (pr
->tid
& 0x1)) << 16;
1182 r
[14] |= pr
->mgnt_vlan_m
? BIT(15) : 0;
1183 if (pr
->phase
== PHASE_IACL
)
1184 r
[14] |= pr
->dmac_hit_sw_m
? BIT(14) : 0;
1186 r
[14] |= pr
->content_too_deep_m
? BIT(14) : 0;
1187 r
[14] |= pr
->not_first_frag_m
? BIT(13) : 0;
1188 r
[14] |= ((u32
) (pr
->frame_type_l4_m
& 0x7)) << 10;
1189 r
[14] |= ((u32
) (pr
->frame_type_m
& 0x3)) << 8;
1190 r
[14] |= pr
->otag_fmt_m
? BIT(7) : 0;
1191 r
[14] |= pr
->itag_fmt_m
? BIT(6) : 0;
1192 r
[14] |= pr
->otag_exist_m
? BIT(5) : 0;
1193 r
[14] |= pr
->itag_exist_m
? BIT(4) : 0;
1194 r
[14] |= ((u32
) (pr
->frame_type_l2_m
& 0x3)) << 2;
1195 r
[14] |= pr
->igr_normal_port_m
? BIT(1) : 0;
1196 r
[14] |= (u32
) (pr
->tid_m
& 0x1);
1198 r
[15] |= pr
->valid
? BIT(31) : 0;
1199 r
[15] |= pr
->cond_not
? BIT(30) : 0;
1200 r
[15] |= pr
->cond_and1
? BIT(29) : 0;
1201 r
[15] |= pr
->cond_and2
? BIT(28) : 0;
1204 static void rtl931x_write_pie_action(u32 r
[], struct pie_rule
*pr
)
1206 // Either drop or forward
1208 r
[15] |= BIT(11) | BIT(12) | BIT(13); // Do Green, Yellow and Red drops
1209 // Actually DROP, not PERMIT in Green / Yellow / Red
1210 r
[16] |= BIT(27) | BIT(28) | BIT(29);
1212 r
[15] |= pr
->fwd_sel
? BIT(14) : 0;
1213 r
[16] |= pr
->fwd_act
<< 24;
1214 r
[16] |= BIT(21); // We overwrite any drop
1216 if (pr
->phase
== PHASE_VACL
)
1217 r
[16] |= pr
->fwd_sa_lrn
? BIT(22) : 0;
1218 r
[15] |= pr
->bypass_sel
? BIT(10) : 0;
1219 r
[15] |= pr
->nopri_sel
? BIT(21) : 0;
1220 r
[15] |= pr
->tagst_sel
? BIT(20) : 0;
1221 r
[15] |= pr
->ovid_sel
? BIT(18) : 0;
1222 r
[15] |= pr
->ivid_sel
? BIT(16) : 0;
1223 r
[15] |= pr
->meter_sel
? BIT(27) : 0;
1224 r
[15] |= pr
->mir_sel
? BIT(15) : 0;
1225 r
[15] |= pr
->log_sel
? BIT(26) : 0;
1227 r
[16] |= ((u32
)(pr
->fwd_data
& 0xfff)) << 9;
1228 // r[15] |= pr->log_octets ? BIT(31) : 0;
1229 r
[15] |= (u32
)(pr
->meter_data
) >> 2;
1230 r
[16] |= (((u32
)(pr
->meter_data
) >> 7) & 0x3) << 29;
1232 r
[16] |= ((u32
)(pr
->ivid_act
& 0x3)) << 21;
1233 r
[15] |= ((u32
)(pr
->ivid_data
& 0xfff)) << 9;
1234 r
[16] |= ((u32
)(pr
->ovid_act
& 0x3)) << 30;
1235 r
[16] |= ((u32
)(pr
->ovid_data
& 0xfff)) << 16;
1236 r
[16] |= ((u32
)(pr
->mir_data
& 0x3)) << 6;
1237 r
[17] |= ((u32
)(pr
->tagst_data
& 0xf)) << 28;
1238 r
[17] |= ((u32
)(pr
->nopri_data
& 0x7)) << 25;
1239 r
[17] |= pr
->bypass_ibc_sc
? BIT(16) : 0;
1242 void rtl931x_pie_rule_dump_raw(u32 r
[])
1244 pr_info("Raw IACL table entry:\n");
1245 pr_info("r 0 - 7: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1246 r
[0], r
[1], r
[2], r
[3], r
[4], r
[5], r
[6], r
[7]);
1247 pr_info("r 8 - 15: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1248 r
[8], r
[9], r
[10], r
[11], r
[12], r
[13], r
[14], r
[15]);
1249 pr_info("r 16 - 18: %08x %08x %08x\n", r
[16], r
[17], r
[18]);
1250 pr_info("Match : %08x %08x %08x %08x %08x %08x\n", r
[0], r
[1], r
[2], r
[3], r
[4], r
[5]);
1251 pr_info("Fixed : %06x\n", r
[6] >> 8);
1252 pr_info("Match M: %08x %08x %08x %08x %08x %08x\n",
1253 (r
[6] << 24) | (r
[7] >> 8), (r
[7] << 24) | (r
[8] >> 8), (r
[8] << 24) | (r
[9] >> 8),
1254 (r
[9] << 24) | (r
[10] >> 8), (r
[10] << 24) | (r
[11] >> 8),
1255 (r
[11] << 24) | (r
[12] >> 8));
1256 pr_info("R[13]: %08x\n", r
[13]);
1257 pr_info("Fixed M: %06x\n", ((r
[12] << 16) | (r
[13] >> 16)) & 0xffffff);
1258 pr_info("Valid / not / and1 / and2 : %1x\n", (r
[13] >> 12) & 0xf);
1259 pr_info("r 13-16: %08x %08x %08x %08x\n", r
[13], r
[14], r
[15], r
[16]);
1262 static int rtl931x_pie_rule_write(struct rtl838x_switch_priv
*priv
, int idx
, struct pie_rule
*pr
)
1264 // Access IACL table (0) via register 1, the table size is 4096
1265 struct table_reg
*q
= rtl_table_get(RTL9310_TBL_1
, 0);
1268 int block
= idx
/ PIE_BLOCK_SIZE
;
1269 u32 t_select
= sw_r32(RTL931X_PIE_BLK_TMPLTE_CTRL(block
));
1271 pr_info("%s: %d, t_select: %08x\n", __func__
, idx
, t_select
);
1273 for (i
= 0; i
< 22; i
++)
1277 rtl_table_write(q
, idx
);
1278 rtl_table_release(q
);
1281 rtl931x_write_pie_fixed_fields(r
, pr
);
1283 pr_info("%s: template %d\n", __func__
, (t_select
>> (pr
->tid
* 4)) & 0xf);
1284 rtl931x_write_pie_templated(r
, pr
, fixed_templates
[(t_select
>> (pr
->tid
* 4)) & 0xf]);
1286 rtl931x_write_pie_action(r
, pr
);
1288 rtl931x_pie_rule_dump_raw(r
);
1290 for (i
= 0; i
< 22; i
++)
1291 sw_w32(r
[i
], rtl_table_data(q
, i
));
1293 rtl_table_write(q
, idx
);
1294 rtl_table_release(q
);
1299 static bool rtl931x_pie_templ_has(int t
, enum template_field_id field_type
)
1302 enum template_field_id ft
;
1304 for (i
= 0; i
< N_FIXED_FIELDS_RTL931X
; i
++) {
1305 ft
= fixed_templates
[t
][i
];
1306 if (field_type
== ft
)
1313 /* Verify that the rule pr is compatible with a given template t in block block
1314 * Note that this function is SoC specific since the values of e.g. TEMPLATE_FIELD_SIP0
1317 static int rtl931x_pie_verify_template(struct rtl838x_switch_priv
*priv
,
1318 struct pie_rule
*pr
, int t
, int block
)
1322 if (!pr
->is_ipv6
&& pr
->sip_m
&& !rtl931x_pie_templ_has(t
, TEMPLATE_FIELD_SIP0
))
1325 if (!pr
->is_ipv6
&& pr
->dip_m
&& !rtl931x_pie_templ_has(t
, TEMPLATE_FIELD_DIP0
))
1329 if ((pr
->sip6_m
.s6_addr32
[0] ||
1330 pr
->sip6_m
.s6_addr32
[1] ||
1331 pr
->sip6_m
.s6_addr32
[2] ||
1332 pr
->sip6_m
.s6_addr32
[3]) &&
1333 !rtl931x_pie_templ_has(t
, TEMPLATE_FIELD_SIP2
))
1335 if ((pr
->dip6_m
.s6_addr32
[0] ||
1336 pr
->dip6_m
.s6_addr32
[1] ||
1337 pr
->dip6_m
.s6_addr32
[2] ||
1338 pr
->dip6_m
.s6_addr32
[3]) &&
1339 !rtl931x_pie_templ_has(t
, TEMPLATE_FIELD_DIP2
))
1343 if (ether_addr_to_u64(pr
->smac
) && !rtl931x_pie_templ_has(t
, TEMPLATE_FIELD_SMAC0
))
1346 if (ether_addr_to_u64(pr
->dmac
) && !rtl931x_pie_templ_has(t
, TEMPLATE_FIELD_DMAC0
))
1351 i
= find_first_zero_bit(&priv
->pie_use_bm
[block
* 4], PIE_BLOCK_SIZE
);
1353 if (i
>= PIE_BLOCK_SIZE
)
1356 return i
+ PIE_BLOCK_SIZE
* block
;
1359 static int rtl931x_pie_rule_add(struct rtl838x_switch_priv
*priv
, struct pie_rule
*pr
)
1361 int idx
, block
, j
, t
;
1363 int max_block
= priv
->n_pie_blocks
/ 2;
1365 if (pr
->is_egress
) {
1366 min_block
= max_block
;
1367 max_block
= priv
->n_pie_blocks
;
1369 pr_info("In %s\n", __func__
);
1371 mutex_lock(&priv
->pie_mutex
);
1373 for (block
= min_block
; block
< max_block
; block
++) {
1374 for (j
= 0; j
< 2; j
++) {
1375 t
= (sw_r32(RTL931X_PIE_BLK_TMPLTE_CTRL(block
)) >> (j
* 4)) & 0xf;
1376 pr_info("Testing block %d, template %d, template id %d\n", block
, j
, t
);
1377 pr_info("%s: %08x\n",
1378 __func__
, sw_r32(RTL931X_PIE_BLK_TMPLTE_CTRL(block
)));
1379 idx
= rtl931x_pie_verify_template(priv
, pr
, t
, block
);
1387 if (block
>= priv
->n_pie_blocks
) {
1388 mutex_unlock(&priv
->pie_mutex
);
1392 pr_info("Using block: %d, index %d, template-id %d\n", block
, idx
, j
);
1393 set_bit(idx
, priv
->pie_use_bm
);
1396 pr
->tid
= j
; // Mapped to template number
1400 rtl931x_pie_lookup_enable(priv
, idx
);
1401 rtl931x_pie_rule_write(priv
, idx
, pr
);
1403 mutex_unlock(&priv
->pie_mutex
);
1408 /* Delete a range of Packet Inspection Engine rules */
1409 static int rtl931x_pie_rule_del(struct rtl838x_switch_priv
*priv
, int index_from
, int index_to
)
1411 u32 v
= (index_from
<< 1)| (index_to
<< 13 ) | BIT(0);
1413 pr_info("%s: from %d to %d\n", __func__
, index_from
, index_to
);
1414 mutex_lock(&priv
->reg_mutex
);
1416 // Write from-to and execute bit into control register
1417 sw_w32(v
, RTL931X_PIE_CLR_CTRL
);
1419 // Wait until command has completed
1421 } while (sw_r32(RTL931X_PIE_CLR_CTRL
) & BIT(0));
1423 mutex_unlock(&priv
->reg_mutex
);
1428 static void rtl931x_pie_rule_rm(struct rtl838x_switch_priv
*priv
, struct pie_rule
*pr
)
1432 rtl931x_pie_rule_del(priv
, idx
, idx
);
1433 clear_bit(idx
, priv
->pie_use_bm
);
1436 static void rtl931x_pie_init(struct rtl838x_switch_priv
*priv
)
1439 u32 template_selectors
;
1441 mutex_init(&priv
->pie_mutex
);
1443 pr_info("%s\n", __func__
);
1444 // Enable ACL lookup on all ports, including CPU_PORT
1445 for (i
= 0; i
<= priv
->cpu_port
; i
++)
1446 sw_w32(1, RTL931X_ACL_PORT_LOOKUP_CTRL(i
));
1448 // Include IPG in metering
1449 sw_w32_mask(0, 1, RTL931X_METER_GLB_CTRL
);
1451 // Delete all present rules, block size is 128 on all SoC families
1452 rtl931x_pie_rule_del(priv
, 0, priv
->n_pie_blocks
* 128 - 1);
1454 // Assign first half blocks 0-7 to VACL phase, second half to IACL
1455 // 3 bits are used for each block, values for PIE blocks are
1456 // 6: Disabled, 0: VACL, 1: IACL, 2: EACL
1457 // And for OpenFlow Flow blocks: 3: Ingress Flow table 0,
1458 // 4: Ingress Flow Table 3, 5: Egress flow table 0
1459 for (i
= 0; i
< priv
->n_pie_blocks
; i
++) {
1460 int pos
= (i
% 10) * 3;
1461 u32 r
= RTL931X_PIE_BLK_PHASE_CTRL
+ 4 * (i
/ 10);
1463 if (i
< priv
->n_pie_blocks
/ 2)
1464 sw_w32_mask(0x7 << pos
, 0, r
);
1466 sw_w32_mask(0x7 << pos
, 1 << pos
, r
);
1469 // Enable predefined templates 0, 1 for first quarter of all blocks
1470 template_selectors
= 0 | (1 << 4);
1471 for (i
= 0; i
< priv
->n_pie_blocks
/ 4; i
++)
1472 sw_w32(template_selectors
, RTL931X_PIE_BLK_TMPLTE_CTRL(i
));
1474 // Enable predefined templates 2, 3 for second quarter of all blocks
1475 template_selectors
= 2 | (3 << 4);
1476 for (i
= priv
->n_pie_blocks
/ 4; i
< priv
->n_pie_blocks
/ 2; i
++)
1477 sw_w32(template_selectors
, RTL931X_PIE_BLK_TMPLTE_CTRL(i
));
1479 // Enable predefined templates 0, 1 for third quater of all blocks
1480 template_selectors
= 0 | (1 << 4);
1481 for (i
= priv
->n_pie_blocks
/ 2; i
< priv
->n_pie_blocks
* 3 / 4; i
++)
1482 sw_w32(template_selectors
, RTL931X_PIE_BLK_TMPLTE_CTRL(i
));
1484 // Enable predefined templates 2, 3 for fourth quater of all blocks
1485 template_selectors
= 2 | (3 << 4);
1486 for (i
= priv
->n_pie_blocks
* 3 / 4; i
< priv
->n_pie_blocks
; i
++)
1487 sw_w32(template_selectors
, RTL931X_PIE_BLK_TMPLTE_CTRL(i
));
1491 int rtl931x_l3_setup(struct rtl838x_switch_priv
*priv
)
1496 void rtl931x_vlan_port_keep_tag_set(int port
, bool keep_outer
, bool keep_inner
)
1498 sw_w32(FIELD_PREP(RTL931X_VLAN_PORT_TAG_EGR_OTAG_STS_MASK
,
1499 keep_outer
? RTL931X_VLAN_PORT_TAG_STS_TAGGED
: RTL931X_VLAN_PORT_TAG_STS_UNTAG
) |
1500 FIELD_PREP(RTL931X_VLAN_PORT_TAG_EGR_ITAG_STS_MASK
,
1501 keep_inner
? RTL931X_VLAN_PORT_TAG_STS_TAGGED
: RTL931X_VLAN_PORT_TAG_STS_UNTAG
),
1502 RTL931X_VLAN_PORT_TAG_CTRL(port
));
1505 void rtl931x_vlan_port_pvidmode_set(int port
, enum pbvlan_type type
, enum pbvlan_mode mode
)
1507 if (type
== PBVLAN_TYPE_INNER
)
1508 sw_w32_mask(0x3 << 12, mode
<< 12, RTL931X_VLAN_PORT_IGR_CTRL
+ (port
<< 2));
1510 sw_w32_mask(0x3 << 26, mode
<< 26, RTL931X_VLAN_PORT_IGR_CTRL
+ (port
<< 2));
1513 void rtl931x_vlan_port_pvid_set(int port
, enum pbvlan_type type
, int pvid
)
1515 if (type
== PBVLAN_TYPE_INNER
)
1516 sw_w32_mask(0xfff, pvid
, RTL931X_VLAN_PORT_IGR_CTRL
+ (port
<< 2));
1518 sw_w32_mask(0xfff << 14, pvid
<< 14, RTL931X_VLAN_PORT_IGR_CTRL
+ (port
<< 2));
1521 static void rtl931x_set_igr_filter(int port
, enum igr_filter state
)
1523 sw_w32_mask(0x3 << ((port
& 0xf)<<1), state
<< ((port
& 0xf)<<1),
1524 RTL931X_VLAN_PORT_IGR_FLTR
+ (((port
>> 4) << 2)));
1527 static void rtl931x_set_egr_filter(int port
, enum egr_filter state
)
1529 sw_w32_mask(0x1 << (port
% 0x20), state
<< (port
% 0x20),
1530 RTL931X_VLAN_PORT_EGR_FLTR
+ (((port
>> 5) << 2)));
1533 void rtl931x_set_distribution_algorithm(int group
, int algoidx
, u32 algomsk
)
1538 /* TODO: for now we set algoidx to 0 */
1541 if (algomsk
& TRUNK_DISTRIBUTION_ALGO_SIP_BIT
) {
1543 newmask
|= TRUNK_DISTRIBUTION_ALGO_L3_SIP_BIT
;
1545 if (algomsk
& TRUNK_DISTRIBUTION_ALGO_DIP_BIT
) {
1547 newmask
|= TRUNK_DISTRIBUTION_ALGO_L3_DIP_BIT
;
1549 if (algomsk
& TRUNK_DISTRIBUTION_ALGO_SRC_L4PORT_BIT
) {
1551 newmask
|= TRUNK_DISTRIBUTION_ALGO_L3_SRC_L4PORT_BIT
;
1553 if (algomsk
& TRUNK_DISTRIBUTION_ALGO_SRC_L4PORT_BIT
) {
1555 newmask
|= TRUNK_DISTRIBUTION_ALGO_L3_SRC_L4PORT_BIT
;
1559 if (algomsk
& TRUNK_DISTRIBUTION_ALGO_SMAC_BIT
)
1560 newmask
|= TRUNK_DISTRIBUTION_ALGO_L3_SMAC_BIT
;
1561 if (algomsk
& TRUNK_DISTRIBUTION_ALGO_DMAC_BIT
)
1562 newmask
|= TRUNK_DISTRIBUTION_ALGO_L3_DMAC_BIT
;
1564 if (algomsk
& TRUNK_DISTRIBUTION_ALGO_SMAC_BIT
)
1565 newmask
|= TRUNK_DISTRIBUTION_ALGO_L2_SMAC_BIT
;
1566 if (algomsk
& TRUNK_DISTRIBUTION_ALGO_DMAC_BIT
)
1567 newmask
|= TRUNK_DISTRIBUTION_ALGO_L2_DMAC_BIT
;
1570 sw_w32(newmask
<< l3shift
, RTL931X_TRK_HASH_CTRL
+ (algoidx
<< 2));
1573 static void rtl931x_led_init(struct rtl838x_switch_priv
*priv
)
1577 u64 pm_copper
= 0, pm_fiber
= 0;
1579 const __be32
*led_set
;
1581 struct device_node
*node
;
1583 pr_info("%s called\n", __func__
);
1584 node
= of_find_compatible_node(NULL
, NULL
, "realtek,rtl9300-leds");
1586 pr_info("%s No compatible LED node found\n", __func__
);
1590 for (i
= 0; i
< priv
->cpu_port
; i
++) {
1591 pos
= (i
<< 1) % 32;
1592 sw_w32_mask(0x3 << pos
, 0, RTL931X_LED_PORT_FIB_SET_SEL_CTRL(i
));
1593 sw_w32_mask(0x3 << pos
, 0, RTL931X_LED_PORT_COPR_SET_SEL_CTRL(i
));
1595 if (!priv
->ports
[i
].phy
)
1598 v
= 0x1; // Found on the EdgeCore, but we do not have any HW description
1599 sw_w32_mask(0x3 << pos
, v
<< pos
, RTL931X_LED_PORT_NUM_CTRL(i
));
1601 if (priv
->ports
[i
].phy_is_integrated
)
1602 pm_fiber
|= BIT_ULL(i
);
1604 pm_copper
|= BIT_ULL(i
);
1606 set
= priv
->ports
[i
].led_set
;
1607 sw_w32_mask(0, set
<< pos
, RTL931X_LED_PORT_COPR_SET_SEL_CTRL(i
));
1608 sw_w32_mask(0, set
<< pos
, RTL931X_LED_PORT_FIB_SET_SEL_CTRL(i
));
1611 for (i
= 0; i
< 4; i
++) {
1612 sprintf(set_name
, "led_set%d", i
);
1613 pr_info(">%s<\n", set_name
);
1614 led_set
= of_get_property(node
, set_name
, &setlen
);
1615 if (!led_set
|| setlen
!= 16)
1617 v
= be32_to_cpup(led_set
) << 16 | be32_to_cpup(led_set
+ 1);
1618 sw_w32(v
, RTL931X_LED_SET0_0_CTRL
- 4 - i
* 8);
1619 v
= be32_to_cpup(led_set
+ 2) << 16 | be32_to_cpup(led_set
+ 3);
1620 sw_w32(v
, RTL931X_LED_SET0_0_CTRL
- i
* 8);
1623 // Set LED mode to serial (0x1)
1624 sw_w32_mask(0x3, 0x1, RTL931X_LED_GLB_CTRL
);
1626 rtl839x_set_port_reg_le(pm_copper
, RTL931X_LED_PORT_COPR_MASK_CTRL
);
1627 rtl839x_set_port_reg_le(pm_fiber
, RTL931X_LED_PORT_FIB_MASK_CTRL
);
1628 rtl839x_set_port_reg_le(pm_copper
| pm_fiber
, RTL931X_LED_PORT_COMBO_MASK_CTRL
);
1630 for (i
= 0; i
< 32; i
++)
1631 pr_info("%s %08x: %08x\n",__func__
, 0xbb000600 + i
* 4, sw_r32(0x0600 + i
* 4));
1634 const struct rtl838x_reg rtl931x_reg
= {
1635 .mask_port_reg_be
= rtl839x_mask_port_reg_be
,
1636 .set_port_reg_be
= rtl839x_set_port_reg_be
,
1637 .get_port_reg_be
= rtl839x_get_port_reg_be
,
1638 .mask_port_reg_le
= rtl839x_mask_port_reg_le
,
1639 .set_port_reg_le
= rtl839x_set_port_reg_le
,
1640 .get_port_reg_le
= rtl839x_get_port_reg_le
,
1641 .stat_port_rst
= RTL931X_STAT_PORT_RST
,
1642 .stat_rst
= RTL931X_STAT_RST
,
1643 .stat_port_std_mib
= 0, // Not defined
1644 .traffic_enable
= rtl931x_traffic_enable
,
1645 .traffic_disable
= rtl931x_traffic_disable
,
1646 .traffic_get
= rtl931x_traffic_get
,
1647 .traffic_set
= rtl931x_traffic_set
,
1648 .l2_ctrl_0
= RTL931X_L2_CTRL
,
1649 .l2_ctrl_1
= RTL931X_L2_AGE_CTRL
,
1650 .l2_port_aging_out
= RTL931X_L2_PORT_AGE_CTRL
,
1651 .set_ageing_time
= rtl931x_set_ageing_time
,
1652 // .smi_poll_ctrl does not exist
1653 .l2_tbl_flush_ctrl
= RTL931X_L2_TBL_FLUSH_CTRL
,
1654 .exec_tbl0_cmd
= rtl931x_exec_tbl0_cmd
,
1655 .exec_tbl1_cmd
= rtl931x_exec_tbl1_cmd
,
1656 .tbl_access_data_0
= rtl931x_tbl_access_data_0
,
1657 .isr_glb_src
= RTL931X_ISR_GLB_SRC
,
1658 .isr_port_link_sts_chg
= RTL931X_ISR_PORT_LINK_STS_CHG
,
1659 .imr_port_link_sts_chg
= RTL931X_IMR_PORT_LINK_STS_CHG
,
1660 // imr_glb does not exist on RTL931X
1661 .vlan_tables_read
= rtl931x_vlan_tables_read
,
1662 .vlan_set_tagged
= rtl931x_vlan_set_tagged
,
1663 .vlan_set_untagged
= rtl931x_vlan_set_untagged
,
1664 .vlan_profile_dump
= rtl931x_vlan_profile_dump
,
1665 .vlan_profile_setup
= rtl931x_vlan_profile_setup
,
1666 .vlan_fwd_on_inner
= rtl931x_vlan_fwd_on_inner
,
1667 .stp_get
= rtl931x_stp_get
,
1668 .stp_set
= rtl931x_stp_set
,
1669 .mac_force_mode_ctrl
= rtl931x_mac_force_mode_ctrl
,
1670 .mac_port_ctrl
= rtl931x_mac_port_ctrl
,
1671 .l2_port_new_salrn
= rtl931x_l2_port_new_salrn
,
1672 .l2_port_new_sa_fwd
= rtl931x_l2_port_new_sa_fwd
,
1673 .mir_ctrl
= RTL931X_MIR_CTRL
,
1674 .mir_dpm
= RTL931X_MIR_DPM_CTRL
,
1675 .mir_spm
= RTL931X_MIR_SPM_CTRL
,
1676 .mac_link_sts
= RTL931X_MAC_LINK_STS
,
1677 .mac_link_dup_sts
= RTL931X_MAC_LINK_DUP_STS
,
1678 .mac_link_spd_sts
= rtl931x_mac_link_spd_sts
,
1679 .mac_rx_pause_sts
= RTL931X_MAC_RX_PAUSE_STS
,
1680 .mac_tx_pause_sts
= RTL931X_MAC_TX_PAUSE_STS
,
1681 .read_l2_entry_using_hash
= rtl931x_read_l2_entry_using_hash
,
1682 .write_l2_entry_using_hash
= rtl931x_write_l2_entry_using_hash
,
1683 .read_cam
= rtl931x_read_cam
,
1684 .write_cam
= rtl931x_write_cam
,
1685 .vlan_port_keep_tag_set
= rtl931x_vlan_port_keep_tag_set
,
1686 .vlan_port_pvidmode_set
= rtl931x_vlan_port_pvidmode_set
,
1687 .vlan_port_pvid_set
= rtl931x_vlan_port_pvid_set
,
1688 .trk_mbr_ctr
= rtl931x_trk_mbr_ctr
,
1689 .set_vlan_igr_filter
= rtl931x_set_igr_filter
,
1690 .set_vlan_egr_filter
= rtl931x_set_egr_filter
,
1691 .set_distribution_algorithm
= rtl931x_set_distribution_algorithm
,
1692 .l2_hash_key
= rtl931x_l2_hash_key
,
1693 .read_mcast_pmask
= rtl931x_read_mcast_pmask
,
1694 .write_mcast_pmask
= rtl931x_write_mcast_pmask
,
1695 .pie_init
= rtl931x_pie_init
,
1696 .pie_rule_write
= rtl931x_pie_rule_write
,
1697 .pie_rule_add
= rtl931x_pie_rule_add
,
1698 .pie_rule_rm
= rtl931x_pie_rule_rm
,
1699 .l2_learning_setup
= rtl931x_l2_learning_setup
,
1700 .l3_setup
= rtl931x_l3_setup
,
1701 .led_init
= rtl931x_led_init
,