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[openwrt/staging/jow.git] / target / linux / realtek / files-5.15 / drivers / net / dsa / rtl83xx / rtl931x.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <asm/mach-rtl838x/mach-rtl83xx.h>
4
5 #include "rtl83xx.h"
6
7 #define RTL931X_VLAN_PORT_TAG_STS_INTERNAL 0x0
8 #define RTL931X_VLAN_PORT_TAG_STS_UNTAG 0x1
9 #define RTL931X_VLAN_PORT_TAG_STS_TAGGED 0x2
10 #define RTL931X_VLAN_PORT_TAG_STS_PRIORITY_TAGGED 0x3
11
12 #define RTL931X_VLAN_PORT_TAG_CTRL_BASE 0x4860
13 /* port 0-56 */
14 #define RTL931X_VLAN_PORT_TAG_CTRL(port) \
15 RTL931X_VLAN_PORT_TAG_CTRL_BASE + (port << 2)
16 #define RTL931X_VLAN_PORT_TAG_EGR_OTAG_STS_MASK GENMASK(13,12)
17 #define RTL931X_VLAN_PORT_TAG_EGR_ITAG_STS_MASK GENMASK(11,10)
18 #define RTL931X_VLAN_PORT_TAG_EGR_OTAG_KEEP_MASK GENMASK(9,9)
19 #define RTL931X_VLAN_PORT_TAG_EGR_ITAG_KEEP_MASK GENMASK(8,8)
20 #define RTL931X_VLAN_PORT_TAG_IGR_OTAG_KEEP_MASK GENMASK(7,7)
21 #define RTL931X_VLAN_PORT_TAG_IGR_ITAG_KEEP_MASK GENMASK(6,6)
22 #define RTL931X_VLAN_PORT_TAG_OTPID_IDX_MASK GENMASK(5,4)
23 #define RTL931X_VLAN_PORT_TAG_OTPID_KEEP_MASK GENMASK(3,3)
24 #define RTL931X_VLAN_PORT_TAG_ITPID_IDX_MASK GENMASK(2,1)
25 #define RTL931X_VLAN_PORT_TAG_ITPID_KEEP_MASK GENMASK(0,0)
26
27 extern struct mutex smi_lock;
28 extern struct rtl83xx_soc_info soc_info;
29
30 /* Definition of the RTL931X-specific template field IDs as used in the PIE */
31 enum template_field_id {
32 TEMPLATE_FIELD_SPM0 = 1,
33 TEMPLATE_FIELD_SPM1 = 2,
34 TEMPLATE_FIELD_SPM2 = 3,
35 TEMPLATE_FIELD_SPM3 = 4,
36 TEMPLATE_FIELD_DMAC0 = 9,
37 TEMPLATE_FIELD_DMAC1 = 10,
38 TEMPLATE_FIELD_DMAC2 = 11,
39 TEMPLATE_FIELD_SMAC0 = 12,
40 TEMPLATE_FIELD_SMAC1 = 13,
41 TEMPLATE_FIELD_SMAC2 = 14,
42 TEMPLATE_FIELD_ETHERTYPE = 15,
43 TEMPLATE_FIELD_OTAG = 16,
44 TEMPLATE_FIELD_ITAG = 17,
45 TEMPLATE_FIELD_SIP0 = 18,
46 TEMPLATE_FIELD_SIP1 = 19,
47 TEMPLATE_FIELD_DIP0 = 20,
48 TEMPLATE_FIELD_DIP1 = 21,
49 TEMPLATE_FIELD_IP_TOS_PROTO = 22,
50 TEMPLATE_FIELD_L4_SPORT = 23,
51 TEMPLATE_FIELD_L4_DPORT = 24,
52 TEMPLATE_FIELD_L34_HEADER = 25,
53 TEMPLATE_FIELD_TCP_INFO = 26,
54 TEMPLATE_FIELD_SIP2 = 34,
55 TEMPLATE_FIELD_SIP3 = 35,
56 TEMPLATE_FIELD_SIP4 = 36,
57 TEMPLATE_FIELD_SIP5 = 37,
58 TEMPLATE_FIELD_SIP6 = 38,
59 TEMPLATE_FIELD_SIP7 = 39,
60 TEMPLATE_FIELD_DIP2 = 42,
61 TEMPLATE_FIELD_DIP3 = 43,
62 TEMPLATE_FIELD_DIP4 = 44,
63 TEMPLATE_FIELD_DIP5 = 45,
64 TEMPLATE_FIELD_DIP6 = 46,
65 TEMPLATE_FIELD_DIP7 = 47,
66 TEMPLATE_FIELD_FLOW_LABEL = 49,
67 TEMPLATE_FIELD_DSAP_SSAP = 50,
68 TEMPLATE_FIELD_FWD_VID = 52,
69 TEMPLATE_FIELD_RANGE_CHK = 53,
70 TEMPLATE_FIELD_SLP = 55,
71 TEMPLATE_FIELD_DLP = 56,
72 TEMPLATE_FIELD_META_DATA = 57,
73 TEMPLATE_FIELD_FIRST_MPLS1 = 60,
74 TEMPLATE_FIELD_FIRST_MPLS2 = 61,
75 TEMPLATE_FIELD_DPM3 = 8,
76 };
77
78 /* The meaning of TEMPLATE_FIELD_VLAN depends on phase and the configuration in
79 * RTL931X_PIE_CTRL. We use always the same definition and map to the inner VLAN tag:
80 */
81 #define TEMPLATE_FIELD_VLAN TEMPLATE_FIELD_ITAG
82
83 /* Number of fixed templates predefined in the RTL9300 SoC */
84 #define N_FIXED_TEMPLATES 5
85 /* RTL931x specific predefined templates */
86 static enum template_field_id fixed_templates[N_FIXED_TEMPLATES][N_FIXED_FIELDS_RTL931X] =
87 {
88 {
89 TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2,
90 TEMPLATE_FIELD_SMAC0, TEMPLATE_FIELD_SMAC1, TEMPLATE_FIELD_SMAC2,
91 TEMPLATE_FIELD_VLAN, TEMPLATE_FIELD_IP_TOS_PROTO, TEMPLATE_FIELD_DSAP_SSAP,
92 TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1,
93 TEMPLATE_FIELD_SPM2, TEMPLATE_FIELD_SPM3
94 }, {
95 TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0,
96 TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_IP_TOS_PROTO, TEMPLATE_FIELD_TCP_INFO,
97 TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_L4_DPORT, TEMPLATE_FIELD_VLAN,
98 TEMPLATE_FIELD_RANGE_CHK, TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1,
99 TEMPLATE_FIELD_SPM2, TEMPLATE_FIELD_SPM3
100 }, {
101 TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2,
102 TEMPLATE_FIELD_VLAN, TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_IP_TOS_PROTO,
103 TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0,
104 TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_L4_DPORT,
105 TEMPLATE_FIELD_META_DATA, TEMPLATE_FIELD_SLP
106 }, {
107 TEMPLATE_FIELD_DIP0, TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_DIP2,
108 TEMPLATE_FIELD_DIP3, TEMPLATE_FIELD_DIP4, TEMPLATE_FIELD_DIP5,
109 TEMPLATE_FIELD_DIP6, TEMPLATE_FIELD_DIP7, TEMPLATE_FIELD_IP_TOS_PROTO,
110 TEMPLATE_FIELD_TCP_INFO, TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_L4_DPORT,
111 TEMPLATE_FIELD_RANGE_CHK, TEMPLATE_FIELD_SLP
112 }, {
113 TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_SIP2,
114 TEMPLATE_FIELD_SIP3, TEMPLATE_FIELD_SIP4, TEMPLATE_FIELD_SIP5,
115 TEMPLATE_FIELD_SIP6, TEMPLATE_FIELD_SIP7, TEMPLATE_FIELD_META_DATA,
116 TEMPLATE_FIELD_VLAN, TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1,
117 TEMPLATE_FIELD_SPM2, TEMPLATE_FIELD_SPM3
118 },
119 };
120
121 inline void rtl931x_exec_tbl0_cmd(u32 cmd)
122 {
123 sw_w32(cmd, RTL931X_TBL_ACCESS_CTRL_0);
124 do { } while (sw_r32(RTL931X_TBL_ACCESS_CTRL_0) & (1 << 20));
125 }
126
127 inline void rtl931x_exec_tbl1_cmd(u32 cmd)
128 {
129 sw_w32(cmd, RTL931X_TBL_ACCESS_CTRL_1);
130 do { } while (sw_r32(RTL931X_TBL_ACCESS_CTRL_1) & (1 << 17));
131 }
132
133 inline int rtl931x_tbl_access_data_0(int i)
134 {
135 return RTL931X_TBL_ACCESS_DATA_0(i);
136 }
137
138 void rtl931x_vlan_profile_dump(int index)
139 {
140 u64 profile[4];
141
142 if (index < 0 || index > 15)
143 return;
144
145 profile[0] = sw_r32(RTL931X_VLAN_PROFILE_SET(index));
146 profile[1] = (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 4) & 0x1FFFFFFFULL) << 32 |
147 (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 8) & 0xFFFFFFFF);
148 profile[2] = (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 16) & 0x1FFFFFFFULL) << 32 |
149 (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 12) & 0xFFFFFFFF);
150 profile[3] = (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 20) & 0x1FFFFFFFULL) << 32 |
151 (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 24) & 0xFFFFFFFF);
152
153 pr_info("VLAN %d: L2 learning: %d, L2 Unknown MultiCast Field %llx, \
154 IPv4 Unknown MultiCast Field %llx, IPv6 Unknown MultiCast Field: %llx",
155 index, (u32) (profile[0] & (3 << 14)), profile[1], profile[2], profile[3]);
156 }
157
158 static void rtl931x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
159 {
160 u32 cmd = 1 << 20 | /* Execute cmd */
161 0 << 19 | /* Read */
162 5 << 15 | /* Table type 0b101 */
163 (msti & 0x3fff);
164 priv->r->exec_tbl0_cmd(cmd);
165
166 for (int i = 0; i < 4; i++)
167 port_state[i] = sw_r32(priv->r->tbl_access_data_0(i));
168 }
169
170 static void rtl931x_stp_set(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
171 {
172 u32 cmd = 1 << 20 | /* Execute cmd */
173 1 << 19 | /* Write */
174 5 << 15 | /* Table type 0b101 */
175 (msti & 0x3fff);
176 for (int i = 0; i < 4; i++)
177 sw_w32(port_state[i], priv->r->tbl_access_data_0(i));
178 priv->r->exec_tbl0_cmd(cmd);
179 }
180
181 inline static int rtl931x_trk_mbr_ctr(int group)
182 {
183 return RTL931X_TRK_MBR_CTRL + (group << 2);
184 }
185
186 static void rtl931x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info)
187 {
188 u32 v, w, x, y;
189 /* Read VLAN table (3) via register 0 */
190 struct table_reg *r = rtl_table_get(RTL9310_TBL_0, 3);
191
192 rtl_table_read(r, vlan);
193 v = sw_r32(rtl_table_data(r, 0));
194 w = sw_r32(rtl_table_data(r, 1));
195 x = sw_r32(rtl_table_data(r, 2));
196 y = sw_r32(rtl_table_data(r, 3));
197 rtl_table_release(r);
198
199 pr_debug("VLAN_READ %d: %08x %08x %08x %08x\n", vlan, v, w, x, y);
200 info->tagged_ports = ((u64) v) << 25 | (w >> 7);
201 info->profile_id = (x >> 16) & 0xf;
202 info->fid = w & 0x7f; /* AKA MSTI depending on context */
203 info->hash_uc_fid = !!(x & BIT(31));
204 info->hash_mc_fid = !!(x & BIT(30));
205 info->if_id = (x >> 20) & 0x3ff;
206 info->profile_id = (x >> 16) & 0xf;
207 info->multicast_grp_mask = x & 0xffff;
208 if (x & BIT(31))
209 info->l2_tunnel_list_id = y >> 18;
210 else
211 info->l2_tunnel_list_id = -1;
212 pr_debug("%s read tagged %016llx, profile-id %d, uc %d, mc %d, intf-id %d\n", __func__,
213 info->tagged_ports, info->profile_id, info->hash_uc_fid, info->hash_mc_fid,
214 info->if_id);
215
216 /* Read UNTAG table via table register 3 */
217 r = rtl_table_get(RTL9310_TBL_3, 0);
218 rtl_table_read(r, vlan);
219 v = ((u64)sw_r32(rtl_table_data(r, 0))) << 25;
220 v |= sw_r32(rtl_table_data(r, 1)) >> 7;
221 rtl_table_release(r);
222
223 info->untagged_ports = v;
224 }
225
226 static void rtl931x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info)
227 {
228 u32 v, w, x, y;
229 /* Access VLAN table (1) via register 0 */
230 struct table_reg *r = rtl_table_get(RTL9310_TBL_0, 3);
231
232 v = info->tagged_ports >> 25;
233 w = (info->tagged_ports & 0x1fffff) << 7;
234 w |= info->fid & 0x7f;
235 x = info->hash_uc_fid ? BIT(31) : 0;
236 x |= info->hash_mc_fid ? BIT(30) : 0;
237 x |= info->if_id & 0x3ff << 20;
238 x |= (info->profile_id & 0xf) << 16;
239 x |= info->multicast_grp_mask & 0xffff;
240 if (info->l2_tunnel_list_id >= 0) {
241 y = info->l2_tunnel_list_id << 18;
242 y |= BIT(31);
243 } else {
244 y = 0;
245 }
246
247 sw_w32(v, rtl_table_data(r, 0));
248 sw_w32(w, rtl_table_data(r, 1));
249 sw_w32(x, rtl_table_data(r, 2));
250 sw_w32(y, rtl_table_data(r, 3));
251
252 rtl_table_write(r, vlan);
253 rtl_table_release(r);
254 }
255
256 static void rtl931x_vlan_set_untagged(u32 vlan, u64 portmask)
257 {
258 struct table_reg *r = rtl_table_get(RTL9310_TBL_3, 0);
259
260 rtl839x_set_port_reg_be(portmask << 7, rtl_table_data(r, 0));
261 rtl_table_write(r, vlan);
262 rtl_table_release(r);
263 }
264
265 static inline int rtl931x_mac_force_mode_ctrl(int p)
266 {
267 return RTL931X_MAC_FORCE_MODE_CTRL + (p << 2);
268 }
269
270 static inline int rtl931x_mac_link_spd_sts(int p)
271 {
272 return RTL931X_MAC_LINK_SPD_STS + (((p >> 3) << 2));
273 }
274
275 static inline int rtl931x_mac_port_ctrl(int p)
276 {
277 return RTL931X_MAC_L2_PORT_CTRL + (p << 7);
278 }
279
280 static inline int rtl931x_l2_port_new_salrn(int p)
281 {
282 return RTL931X_L2_PORT_NEW_SALRN(p);
283 }
284
285 static inline int rtl931x_l2_port_new_sa_fwd(int p)
286 {
287 return RTL931X_L2_PORT_NEW_SA_FWD(p);
288 }
289
290 irqreturn_t rtl931x_switch_irq(int irq, void *dev_id)
291 {
292 struct dsa_switch *ds = dev_id;
293 u32 status = sw_r32(RTL931X_ISR_GLB_SRC);
294 u64 ports = rtl839x_get_port_reg_le(RTL931X_ISR_PORT_LINK_STS_CHG);
295 u64 link;
296
297 /* Clear status */
298 rtl839x_set_port_reg_le(ports, RTL931X_ISR_PORT_LINK_STS_CHG);
299 pr_debug("RTL931X Link change: status: %x, ports %016llx\n", status, ports);
300
301 link = rtl839x_get_port_reg_le(RTL931X_MAC_LINK_STS);
302 /* Must re-read this to get correct status */
303 link = rtl839x_get_port_reg_le(RTL931X_MAC_LINK_STS);
304 pr_debug("RTL931X Link change: status: %x, link status %016llx\n", status, link);
305
306 for (int i = 0; i < 56; i++) {
307 if (ports & BIT_ULL(i)) {
308 if (link & BIT_ULL(i)) {
309 pr_info("%s port %d up\n", __func__, i);
310 dsa_port_phylink_mac_change(ds, i, true);
311 } else {
312 pr_info("%s port %d down\n", __func__, i);
313 dsa_port_phylink_mac_change(ds, i, false);
314 }
315 }
316 }
317
318 return IRQ_HANDLED;
319 }
320
321 int rtl931x_write_phy(u32 port, u32 page, u32 reg, u32 val)
322 {
323 u32 v;
324 int err = 0;
325
326 val &= 0xffff;
327 if (port > 63 || page > 4095 || reg > 31)
328 return -ENOTSUPP;
329
330 mutex_lock(&smi_lock);
331 pr_debug("%s: writing to phy %d %d %d %d\n", __func__, port, page, reg, val);
332 /* Clear both port registers */
333 sw_w32(0, RTL931X_SMI_INDRT_ACCESS_CTRL_2);
334 sw_w32(0, RTL931X_SMI_INDRT_ACCESS_CTRL_2 + 4);
335 sw_w32_mask(0, BIT(port % 32), RTL931X_SMI_INDRT_ACCESS_CTRL_2 + (port / 32) * 4);
336
337 sw_w32_mask(0xffff, val, RTL931X_SMI_INDRT_ACCESS_CTRL_3);
338
339 v = reg << 6 | page << 11 ;
340 sw_w32(v, RTL931X_SMI_INDRT_ACCESS_CTRL_0);
341
342 sw_w32(0x1ff, RTL931X_SMI_INDRT_ACCESS_CTRL_1);
343
344 v |= BIT(4) | 1; /* Write operation and execute */
345 sw_w32(v, RTL931X_SMI_INDRT_ACCESS_CTRL_0);
346
347 do {
348 } while (sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_0) & 0x1);
349
350 if (sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_0) & 0x2)
351 err = -EIO;
352
353 mutex_unlock(&smi_lock);
354
355 return err;
356 }
357
358 int rtl931x_read_phy(u32 port, u32 page, u32 reg, u32 *val)
359 {
360 u32 v;
361
362 if (port > 63 || page > 4095 || reg > 31)
363 return -ENOTSUPP;
364
365 mutex_lock(&smi_lock);
366
367 sw_w32(port << 5, RTL931X_SMI_INDRT_ACCESS_BC_PHYID_CTRL);
368
369 v = reg << 6 | page << 11 | 1;
370 sw_w32(v, RTL931X_SMI_INDRT_ACCESS_CTRL_0);
371
372 do {
373 } while (sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_0) & 0x1);
374
375 v = sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_0);
376 *val = sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_3);
377 *val = (*val & 0xffff0000) >> 16;
378
379 pr_debug("%s: port %d, page: %d, reg: %x, val: %x, v: %08x\n",
380 __func__, port, page, reg, *val, v);
381
382 mutex_unlock(&smi_lock);
383
384 return 0;
385 }
386
387 /* Read an mmd register of the PHY */
388 int rtl931x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val)
389 {
390 int err = 0;
391 u32 v;
392 /* Select PHY register type
393 * If select 1G/10G MMD register type, registers EXT_PAGE, MAIN_PAGE and REG settings are don’t care.
394 * 0x0 Normal register (Clause 22)
395 * 0x1: 1G MMD register (MMD via Clause 22 registers 13 and 14)
396 * 0x2: 10G MMD register (MMD via Clause 45)
397 */
398 int type = (regnum & MII_ADDR_C45)?2:1;
399
400 mutex_lock(&smi_lock);
401
402 /* Set PHY to access via port-number */
403 sw_w32(port << 5, RTL931X_SMI_INDRT_ACCESS_BC_PHYID_CTRL);
404
405 /* Set MMD device number and register to write to */
406 sw_w32(devnum << 16 | mdiobus_c45_regad(regnum), RTL931X_SMI_INDRT_ACCESS_MMD_CTRL);
407
408 v = type << 2 | BIT(0); /* MMD-access-type | EXEC */
409 sw_w32(v, RTL931X_SMI_INDRT_ACCESS_CTRL_0);
410
411 do {
412 v = sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_0);
413 } while (v & BIT(0));
414
415 /* Check for error condition */
416 if (v & BIT(1))
417 err = -EIO;
418
419 *val = sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_3) >> 16;
420
421 pr_debug("%s: port %d, dev: %x, regnum: %x, val: %x (err %d)\n", __func__,
422 port, devnum, mdiobus_c45_regad(regnum), *val, err);
423
424 mutex_unlock(&smi_lock);
425
426 return err;
427 }
428
429 /* Write to an mmd register of the PHY */
430 int rtl931x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val)
431 {
432 int err = 0;
433 u32 v;
434 int type = (regnum & MII_ADDR_C45)?2:1;
435 u64 pm;
436
437 mutex_lock(&smi_lock);
438
439 /* Set PHY to access via port-mask */
440 pm = (u64)1 << port;
441 sw_w32((u32)pm, RTL931X_SMI_INDRT_ACCESS_CTRL_2);
442 sw_w32((u32)(pm >> 32), RTL931X_SMI_INDRT_ACCESS_CTRL_2 + 4);
443
444 /* Set data to write */
445 sw_w32_mask(0xffff, val, RTL931X_SMI_INDRT_ACCESS_CTRL_3);
446
447 /* Set MMD device number and register to write to */
448 sw_w32(devnum << 16 | mdiobus_c45_regad(regnum), RTL931X_SMI_INDRT_ACCESS_MMD_CTRL);
449
450 v = BIT(4) | type << 2 | BIT(0); /* WRITE | MMD-access-type | EXEC */
451 sw_w32(v, RTL931X_SMI_INDRT_ACCESS_CTRL_0);
452
453 do {
454 v = sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_0);
455 } while (v & BIT(0));
456
457 pr_debug("%s: port %d, dev: %x, regnum: %x, val: %x (err %d)\n", __func__,
458 port, devnum, mdiobus_c45_regad(regnum), val, err);
459 mutex_unlock(&smi_lock);
460
461 return err;
462 }
463
464 void rtl931x_print_matrix(void)
465 {
466 volatile u64 *ptr = RTL838X_SW_BASE + RTL839X_PORT_ISO_CTRL(0);
467
468 for (int i = 0; i < 52; i += 4)
469 pr_info("> %16llx %16llx %16llx %16llx\n",
470 ptr[i + 0], ptr[i + 1], ptr[i + 2], ptr[i + 3]);
471 pr_info("CPU_PORT> %16llx\n", ptr[52]);
472 }
473
474 void rtl931x_set_receive_management_action(int port, rma_ctrl_t type, action_type_t action)
475 {
476 u32 value = 0;
477
478 /* hack for value mapping */
479 if (type == GRATARP && action == COPY2CPU)
480 action = TRAP2MASTERCPU;
481
482 switch(action) {
483 case FORWARD:
484 value = 0;
485 break;
486 case DROP:
487 value = 1;
488 break;
489 case TRAP2CPU:
490 value = 2;
491 break;
492 case TRAP2MASTERCPU:
493 value = 3;
494 break;
495 case FLOODALL:
496 value = 4;
497 break;
498 default:
499 break;
500 }
501
502 switch(type) {
503 case BPDU:
504 sw_w32_mask(7 << ((port % 10) * 3), value << ((port % 10) * 3), RTL931X_RMA_BPDU_CTRL + ((port / 10) << 2));
505 break;
506 case PTP:
507 /* udp */
508 sw_w32_mask(3 << 2, value << 2, RTL931X_RMA_PTP_CTRL + (port << 2));
509 /* eth2 */
510 sw_w32_mask(3, value, RTL931X_RMA_PTP_CTRL + (port << 2));
511 break;
512 case PTP_UDP:
513 sw_w32_mask(3 << 2, value << 2, RTL931X_RMA_PTP_CTRL + (port << 2));
514 break;
515 case PTP_ETH2:
516 sw_w32_mask(3, value, RTL931X_RMA_PTP_CTRL + (port << 2));
517 break;
518 case LLTP:
519 sw_w32_mask(7 << ((port % 10) * 3), value << ((port % 10) * 3), RTL931X_RMA_LLTP_CTRL + ((port / 10) << 2));
520 break;
521 case EAPOL:
522 sw_w32_mask(7 << ((port % 10) * 3), value << ((port % 10) * 3), RTL931X_RMA_EAPOL_CTRL + ((port / 10) << 2));
523 break;
524 case GRATARP:
525 sw_w32_mask(3 << ((port & 0xf) << 1), value << ((port & 0xf) << 1), RTL931X_TRAP_ARP_GRAT_PORT_ACT + ((port >> 4) << 2));
526 break;
527 }
528 }
529
530 u64 rtl931x_traffic_get(int source)
531 {
532 u32 v;
533 struct table_reg *r = rtl_table_get(RTL9310_TBL_0, 6);
534
535 rtl_table_read(r, source);
536 v = sw_r32(rtl_table_data(r, 0));
537 rtl_table_release(r);
538 v = v >> 3;
539
540 return v;
541 }
542
543 /* Enable traffic between a source port and a destination port matrix */
544 void rtl931x_traffic_set(int source, u64 dest_matrix)
545 {
546 struct table_reg *r = rtl_table_get(RTL9310_TBL_0, 6);
547
548 sw_w32((dest_matrix << 3), rtl_table_data(r, 0));
549 rtl_table_write(r, source);
550 rtl_table_release(r);
551 }
552
553 void rtl931x_traffic_enable(int source, int dest)
554 {
555 struct table_reg *r = rtl_table_get(RTL9310_TBL_0, 6);
556 rtl_table_read(r, source);
557 sw_w32_mask(0, BIT(dest + 3), rtl_table_data(r, 0));
558 rtl_table_write(r, source);
559 rtl_table_release(r);
560 }
561
562 void rtl931x_traffic_disable(int source, int dest)
563 {
564 struct table_reg *r = rtl_table_get(RTL9310_TBL_0, 6);
565 rtl_table_read(r, source);
566 sw_w32_mask(BIT(dest + 3), 0, rtl_table_data(r, 0));
567 rtl_table_write(r, source);
568 rtl_table_release(r);
569 }
570
571 static u64 rtl931x_l2_hash_seed(u64 mac, u32 vid)
572 {
573 u64 v = vid;
574
575 v <<= 48;
576 v |= mac;
577
578 return v;
579 }
580
581 /* Calculate both the block 0 and the block 1 hash by applyingthe same hash
582 * algorithm as the one used currently by the ASIC to the seed, and return
583 * both hashes in the lower and higher word of the return value since only 12 bit of
584 * the hash are significant.
585 */
586 static u32 rtl931x_l2_hash_key(struct rtl838x_switch_priv *priv, u64 seed)
587 {
588 u32 h, h0, h1, h2, h3, h4, k0, k1;
589
590 h0 = seed & 0xfff;
591 h1 = (seed >> 12) & 0xfff;
592 h2 = (seed >> 24) & 0xfff;
593 h3 = (seed >> 36) & 0xfff;
594 h4 = (seed >> 48) & 0xfff;
595 h4 = ((h4 & 0x7) << 9) | ((h4 >> 3) & 0x1ff);
596 k0 = h0 ^ h1 ^ h2 ^ h3 ^ h4;
597
598 h0 = seed & 0xfff;
599 h0 = ((h0 & 0x1ff) << 3) | ((h0 >> 9) & 0x7);
600 h1 = (seed >> 12) & 0xfff;
601 h1 = ((h1 & 0x3f) << 6) | ((h1 >> 6) & 0x3f);
602 h2 = (seed >> 24) & 0xfff;
603 h3 = (seed >> 36) & 0xfff;
604 h3 = ((h3 & 0x3f) << 6) | ((h3 >> 6) & 0x3f);
605 h4 = (seed >> 48) & 0xfff;
606 k1 = h0 ^ h1 ^ h2 ^ h3 ^ h4;
607
608 /* Algorithm choice for block 0 */
609 if (sw_r32(RTL931X_L2_CTRL) & BIT(0))
610 h = k1;
611 else
612 h = k0;
613
614 /* Algorithm choice for block 1
615 * Since k0 and k1 are < 4096, adding 4096 will offset the hash into the second
616 * half of hash-space
617 * 4096 is in fact the hash-table size 32768 divided by 4 hashes per bucket
618 * divided by 2 to divide the hash space in 2
619 */
620 if (sw_r32(RTL931X_L2_CTRL) & BIT(1))
621 h |= (k1 + 4096) << 16;
622 else
623 h |= (k0 + 4096) << 16;
624
625 return h;
626 }
627
628 /* Fills an L2 entry structure from the SoC registers */
629 static void rtl931x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e)
630 {
631 pr_debug("In %s valid?\n", __func__);
632 e->valid = !!(r[0] & BIT(31));
633 if (!e->valid)
634 return;
635
636 pr_debug("%s: entry valid, raw: %08x %08x %08x %08x\n", __func__, r[0], r[1], r[2], r[3]);
637 e->is_ip_mc = false;
638 e->is_ipv6_mc = false;
639
640 e->mac[0] = r[0] >> 8;
641 e->mac[1] = r[0];
642 e->mac[2] = r[1] >> 24;
643 e->mac[3] = r[1] >> 16;
644 e->mac[4] = r[1] >> 8;
645 e->mac[5] = r[1];
646
647 e->is_open_flow = !!(r[0] & BIT(30));
648 e->is_pe_forward = !!(r[0] & BIT(29));
649 e->next_hop = !!(r[2] & BIT(30));
650 e->rvid = (r[0] >> 16) & 0xfff;
651
652 /* Is it a unicast entry? check multicast bit */
653 if (!(e->mac[0] & 1)) {
654 e->type = L2_UNICAST;
655 e->is_l2_tunnel = !!(r[2] & BIT(31));
656 e->is_static = !!(r[2] & BIT(13));
657 e->port = (r[2] >> 19) & 0x3ff;
658 /* Check for trunk port */
659 if (r[2] & BIT(29)) {
660 e->is_trunk = true;
661 e->stack_dev = (e->port >> 9) & 1;
662 e->trunk = e->port & 0x3f;
663 } else {
664 e->is_trunk = false;
665 e->stack_dev = (e->port >> 6) & 0xf;
666 e->port = e->port & 0x3f;
667 }
668
669 e->block_da = !!(r[2] & BIT(14));
670 e->block_sa = !!(r[2] & BIT(15));
671 e->suspended = !!(r[2] & BIT(12));
672 e->age = (r[2] >> 16) & 3;
673
674 /* the UC_VID field in hardware is used for the VID or for the route id */
675 if (e->next_hop) {
676 e->nh_route_id = r[2] & 0x7ff;
677 e->vid = 0;
678 } else {
679 e->vid = r[2] & 0xfff;
680 e->nh_route_id = 0;
681 }
682 if (e->is_l2_tunnel)
683 e->l2_tunnel_id = ((r[2] & 0xff) << 4) | (r[3] >> 28);
684 /* TODO: Implement VLAN conversion */
685 } else {
686 e->type = L2_MULTICAST;
687 e->is_local_forward = !!(r[2] & BIT(31));
688 e->is_remote_forward = !!(r[2] & BIT(17));
689 e->mc_portmask_index = (r[2] >> 18) & 0xfff;
690 e->l2_tunnel_list_id = (r[2] >> 4) & 0x1fff;
691 }
692 }
693
694 /* Fills the 3 SoC table registers r[] with the information of in the rtl838x_l2_entry */
695 static void rtl931x_fill_l2_row(u32 r[], struct rtl838x_l2_entry *e)
696 {
697 u32 port;
698
699 if (!e->valid) {
700 r[0] = r[1] = r[2] = 0;
701 return;
702 }
703
704 r[2] = BIT(31); /* Set valid bit */
705
706 r[0] = ((u32)e->mac[0]) << 24 |
707 ((u32)e->mac[1]) << 16 |
708 ((u32)e->mac[2]) << 8 |
709 ((u32)e->mac[3]);
710 r[1] = ((u32)e->mac[4]) << 24 |
711 ((u32)e->mac[5]) << 16;
712
713 r[2] |= e->next_hop ? BIT(12) : 0;
714
715 if (e->type == L2_UNICAST) {
716 r[2] |= e->is_static ? BIT(14) : 0;
717 r[1] |= e->rvid & 0xfff;
718 r[2] |= (e->port & 0x3ff) << 20;
719 if (e->is_trunk) {
720 r[2] |= BIT(30);
721 port = e->stack_dev << 9 | (e->port & 0x3f);
722 } else {
723 port = (e->stack_dev & 0xf) << 6;
724 port |= e->port & 0x3f;
725 }
726 r[2] |= port << 20;
727 r[2] |= e->block_da ? BIT(15) : 0;
728 r[2] |= e->block_sa ? BIT(17) : 0;
729 r[2] |= e->suspended ? BIT(13) : 0;
730 r[2] |= (e->age & 0x3) << 17;
731 /* the UC_VID field in hardware is used for the VID or for the route id */
732 if (e->next_hop)
733 r[2] |= e->nh_route_id & 0x7ff;
734 else
735 r[2] |= e->vid & 0xfff;
736 } else { /* L2_MULTICAST */
737 r[2] |= (e->mc_portmask_index & 0x3ff) << 16;
738 r[2] |= e->mc_mac_index & 0x7ff;
739 }
740 }
741
742 /* Read an L2 UC or MC entry out of a hash bucket of the L2 forwarding table
743 * hash is the id of the bucket and pos is the position of the entry in that bucket
744 * The data read from the SoC is filled into rtl838x_l2_entry
745 */
746 static u64 rtl931x_read_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e)
747 {
748 u32 r[4];
749 struct table_reg *q = rtl_table_get(RTL9310_TBL_0, 0);
750 u32 idx;
751 u64 mac;
752 u64 seed;
753
754 pr_debug("%s: hash %08x, pos: %d\n", __func__, hash, pos);
755
756 /* On the RTL93xx, 2 different hash algorithms are used making it a total of
757 * 8 buckets that need to be searched, 4 for each hash-half
758 * Use second hash space when bucket is between 4 and 8
759 */
760 if (pos >= 4) {
761 pos -= 4;
762 hash >>= 16;
763 } else {
764 hash &= 0xffff;
765 }
766
767 idx = (0 << 14) | (hash << 2) | pos; /* Search SRAM, with hash and at pos in bucket */
768 pr_debug("%s: NOW hash %08x, pos: %d\n", __func__, hash, pos);
769
770 rtl_table_read(q, idx);
771 for (int i = 0; i < 4; i++)
772 r[i] = sw_r32(rtl_table_data(q, i));
773
774 rtl_table_release(q);
775
776 rtl931x_fill_l2_entry(r, e);
777
778 pr_debug("%s: valid: %d, nh: %d\n", __func__, e->valid, e->next_hop);
779 if (!e->valid)
780 return 0;
781
782 mac = ((u64)e->mac[0]) << 40 |
783 ((u64)e->mac[1]) << 32 |
784 ((u64)e->mac[2]) << 24 |
785 ((u64)e->mac[3]) << 16 |
786 ((u64)e->mac[4]) << 8 |
787 ((u64)e->mac[5]);
788
789 seed = rtl931x_l2_hash_seed(mac, e->rvid);
790 pr_debug("%s: mac %016llx, seed %016llx\n", __func__, mac, seed);
791
792 /* return vid with concatenated mac as unique id */
793 return seed;
794 }
795
796 static u64 rtl931x_read_cam(int idx, struct rtl838x_l2_entry *e)
797 {
798 return 0;
799 }
800
801 static void rtl931x_write_cam(int idx, struct rtl838x_l2_entry *e)
802 {
803 }
804
805 static void rtl931x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e)
806 {
807 u32 r[4];
808 struct table_reg *q = rtl_table_get(RTL9310_TBL_0, 0);
809 u32 idx = (0 << 14) | (hash << 2) | pos; /* Access SRAM, with hash and at pos in bucket */
810
811 pr_info("%s: hash %d, pos %d\n", __func__, hash, pos);
812 pr_info("%s: index %d -> mac %02x:%02x:%02x:%02x:%02x:%02x\n", __func__, idx,
813 e->mac[0], e->mac[1], e->mac[2], e->mac[3],e->mac[4],e->mac[5]);
814
815 rtl931x_fill_l2_row(r, e);
816 pr_info("%s: %d: %08x %08x %08x\n", __func__, idx, r[0], r[1], r[2]);
817
818 for (int i = 0; i < 4; i++)
819 sw_w32(r[i], rtl_table_data(q, i));
820
821 rtl_table_write(q, idx);
822 rtl_table_release(q);
823 }
824
825 static void rtl931x_vlan_fwd_on_inner(int port, bool is_set)
826 {
827 /* Always set all tag modes to fwd based on either inner or outer tag */
828 if (is_set)
829 sw_w32_mask(0, 0xf, RTL931X_VLAN_PORT_FWD + (port << 2));
830 else
831 sw_w32_mask(0xf, 0, RTL931X_VLAN_PORT_FWD + (port << 2));
832 }
833
834 static void rtl931x_vlan_profile_setup(int profile)
835 {
836 u32 p[7];
837
838 pr_info("In %s\n", __func__);
839
840 if (profile > 15)
841 return;
842
843 p[0] = sw_r32(RTL931X_VLAN_PROFILE_SET(profile));
844
845 /* Enable routing of Ipv4/6 Unicast and IPv4/6 Multicast traffic */
846 /* p[0] |= BIT(17) | BIT(16) | BIT(13) | BIT(12); */
847 p[0] |= 0x3 << 11; /* COPY2CPU */
848
849 p[1] = 0x1FFFFFF; /* L2 unknwon MC flooding portmask all ports, including the CPU-port */
850 p[2] = 0xFFFFFFFF;
851 p[3] = 0x1FFFFFF; /* IPv4 unknwon MC flooding portmask */
852 p[4] = 0xFFFFFFFF;
853 p[5] = 0x1FFFFFF; /* IPv6 unknwon MC flooding portmask */
854 p[6] = 0xFFFFFFFF;
855
856 for (int i = 0; i < 7; i++)
857 sw_w32(p[i], RTL931X_VLAN_PROFILE_SET(profile) + i * 4);
858 pr_info("Leaving %s\n", __func__);
859 }
860
861 static void rtl931x_l2_learning_setup(void)
862 {
863 /* Portmask for flooding broadcast traffic */
864 rtl839x_set_port_reg_be(0x1FFFFFFFFFFFFFF, RTL931X_L2_BC_FLD_PMSK);
865
866 /* Portmask for flooding unicast traffic with unknown destination */
867 rtl839x_set_port_reg_be(0x1FFFFFFFFFFFFFF, RTL931X_L2_UNKN_UC_FLD_PMSK);
868
869 /* Limit learning to maximum: 64k entries, after that just flood (bits 0-2) */
870 sw_w32((0xffff << 3) | FORWARD, RTL931X_L2_LRN_CONSTRT_CTRL);
871 }
872
873 static u64 rtl931x_read_mcast_pmask(int idx)
874 {
875 u64 portmask;
876 /* Read MC_PMSK (2) via register RTL9310_TBL_0 */
877 struct table_reg *q = rtl_table_get(RTL9310_TBL_0, 2);
878
879 rtl_table_read(q, idx);
880 portmask = sw_r32(rtl_table_data(q, 0));
881 portmask <<= 32;
882 portmask |= sw_r32(rtl_table_data(q, 1));
883 portmask >>= 7;
884 rtl_table_release(q);
885
886 pr_debug("%s: Index idx %d has portmask %016llx\n", __func__, idx, portmask);
887
888 return portmask;
889 }
890
891 static void rtl931x_write_mcast_pmask(int idx, u64 portmask)
892 {
893 u64 pm = portmask;
894
895 /* Access MC_PMSK (2) via register RTL9310_TBL_0 */
896 struct table_reg *q = rtl_table_get(RTL9310_TBL_0, 2);
897
898 pr_debug("%s: Index idx %d has portmask %016llx\n", __func__, idx, pm);
899 pm <<= 7;
900 sw_w32((u32)(pm >> 32), rtl_table_data(q, 0));
901 sw_w32((u32)pm, rtl_table_data(q, 1));
902 rtl_table_write(q, idx);
903 rtl_table_release(q);
904 }
905
906
907 static int rtl931x_set_ageing_time(unsigned long msec)
908 {
909 int t = sw_r32(RTL931X_L2_AGE_CTRL);
910
911 t &= 0x1FFFFF;
912 t = (t * 8) / 10;
913 pr_debug("L2 AGING time: %d sec\n", t);
914
915 t = (msec / 100 + 7) / 8;
916 t = t > 0x1FFFFF ? 0x1FFFFF : t;
917 sw_w32_mask(0x1FFFFF, t, RTL931X_L2_AGE_CTRL);
918 pr_debug("Dynamic aging for ports: %x\n", sw_r32(RTL931X_L2_PORT_AGE_CTRL));
919
920 return 0;
921 }
922 void rtl931x_sw_init(struct rtl838x_switch_priv *priv)
923 {
924 /* rtl931x_sds_init(priv); */
925 }
926
927 static void rtl931x_pie_lookup_enable(struct rtl838x_switch_priv *priv, int index)
928 {
929 int block = index / PIE_BLOCK_SIZE;
930
931 sw_w32_mask(0, BIT(block), RTL931X_PIE_BLK_LOOKUP_CTRL);
932 }
933
934 /* Fills the data in the intermediate representation in the pie_rule structure
935 * into a data field for a given template field field_type
936 * TODO: This function looks very similar to the function of the rtl9300, but
937 * since it uses the physical template_field_id, which are different for each
938 * SoC and there are other field types, it is actually not. If we would also use
939 * an intermediate representation for a field type, we would could have one
940 * pie_data_fill function for all SoCs, provided we have also for each SoC a
941 * function to map between physical and intermediate field type
942 */
943 int rtl931x_pie_data_fill(enum template_field_id field_type, struct pie_rule *pr, u16 *data, u16 *data_m)
944 {
945 *data = *data_m = 0;
946
947 switch (field_type) {
948 case TEMPLATE_FIELD_SPM0:
949 *data = pr->spm;
950 *data_m = pr->spm_m;
951 break;
952 case TEMPLATE_FIELD_SPM1:
953 *data = pr->spm >> 16;
954 *data_m = pr->spm_m >> 16;
955 break;
956 case TEMPLATE_FIELD_OTAG:
957 *data = pr->otag;
958 *data_m = pr->otag_m;
959 break;
960 case TEMPLATE_FIELD_SMAC0:
961 *data = pr->smac[4];
962 *data = (*data << 8) | pr->smac[5];
963 *data_m = pr->smac_m[4];
964 *data_m = (*data_m << 8) | pr->smac_m[5];
965 break;
966 case TEMPLATE_FIELD_SMAC1:
967 *data = pr->smac[2];
968 *data = (*data << 8) | pr->smac[3];
969 *data_m = pr->smac_m[2];
970 *data_m = (*data_m << 8) | pr->smac_m[3];
971 break;
972 case TEMPLATE_FIELD_SMAC2:
973 *data = pr->smac[0];
974 *data = (*data << 8) | pr->smac[1];
975 *data_m = pr->smac_m[0];
976 *data_m = (*data_m << 8) | pr->smac_m[1];
977 break;
978 case TEMPLATE_FIELD_DMAC0:
979 *data = pr->dmac[4];
980 *data = (*data << 8) | pr->dmac[5];
981 *data_m = pr->dmac_m[4];
982 *data_m = (*data_m << 8) | pr->dmac_m[5];
983 break;
984 case TEMPLATE_FIELD_DMAC1:
985 *data = pr->dmac[2];
986 *data = (*data << 8) | pr->dmac[3];
987 *data_m = pr->dmac_m[2];
988 *data_m = (*data_m << 8) | pr->dmac_m[3];
989 break;
990 case TEMPLATE_FIELD_DMAC2:
991 *data = pr->dmac[0];
992 *data = (*data << 8) | pr->dmac[1];
993 *data_m = pr->dmac_m[0];
994 *data_m = (*data_m << 8) | pr->dmac_m[1];
995 break;
996 case TEMPLATE_FIELD_ETHERTYPE:
997 *data = pr->ethertype;
998 *data_m = pr->ethertype_m;
999 break;
1000 case TEMPLATE_FIELD_ITAG:
1001 *data = pr->itag;
1002 *data_m = pr->itag_m;
1003 break;
1004 case TEMPLATE_FIELD_SIP0:
1005 if (pr->is_ipv6) {
1006 *data = pr->sip6.s6_addr16[7];
1007 *data_m = pr->sip6_m.s6_addr16[7];
1008 } else {
1009 *data = pr->sip;
1010 *data_m = pr->sip_m;
1011 }
1012 break;
1013 case TEMPLATE_FIELD_SIP1:
1014 if (pr->is_ipv6) {
1015 *data = pr->sip6.s6_addr16[6];
1016 *data_m = pr->sip6_m.s6_addr16[6];
1017 } else {
1018 *data = pr->sip >> 16;
1019 *data_m = pr->sip_m >> 16;
1020 }
1021 break;
1022 case TEMPLATE_FIELD_SIP2:
1023 case TEMPLATE_FIELD_SIP3:
1024 case TEMPLATE_FIELD_SIP4:
1025 case TEMPLATE_FIELD_SIP5:
1026 case TEMPLATE_FIELD_SIP6:
1027 case TEMPLATE_FIELD_SIP7:
1028 *data = pr->sip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)];
1029 *data_m = pr->sip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)];
1030 break;
1031 case TEMPLATE_FIELD_DIP0:
1032 if (pr->is_ipv6) {
1033 *data = pr->dip6.s6_addr16[7];
1034 *data_m = pr->dip6_m.s6_addr16[7];
1035 } else {
1036 *data = pr->dip;
1037 *data_m = pr->dip_m;
1038 }
1039 break;
1040 case TEMPLATE_FIELD_DIP1:
1041 if (pr->is_ipv6) {
1042 *data = pr->dip6.s6_addr16[6];
1043 *data_m = pr->dip6_m.s6_addr16[6];
1044 } else {
1045 *data = pr->dip >> 16;
1046 *data_m = pr->dip_m >> 16;
1047 }
1048 break;
1049 case TEMPLATE_FIELD_DIP2:
1050 case TEMPLATE_FIELD_DIP3:
1051 case TEMPLATE_FIELD_DIP4:
1052 case TEMPLATE_FIELD_DIP5:
1053 case TEMPLATE_FIELD_DIP6:
1054 case TEMPLATE_FIELD_DIP7:
1055 *data = pr->dip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)];
1056 *data_m = pr->dip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)];
1057 break;
1058 case TEMPLATE_FIELD_IP_TOS_PROTO:
1059 *data = pr->tos_proto;
1060 *data_m = pr->tos_proto_m;
1061 break;
1062 case TEMPLATE_FIELD_L4_SPORT:
1063 *data = pr->sport;
1064 *data_m = pr->sport_m;
1065 break;
1066 case TEMPLATE_FIELD_L4_DPORT:
1067 *data = pr->dport;
1068 *data_m = pr->dport_m;
1069 break;
1070 case TEMPLATE_FIELD_DSAP_SSAP:
1071 *data = pr->dsap_ssap;
1072 *data_m = pr->dsap_ssap_m;
1073 break;
1074 case TEMPLATE_FIELD_TCP_INFO:
1075 *data = pr->tcp_info;
1076 *data_m = pr->tcp_info_m;
1077 break;
1078 case TEMPLATE_FIELD_RANGE_CHK:
1079 pr_info("TEMPLATE_FIELD_RANGE_CHK: not configured\n");
1080 break;
1081 default:
1082 pr_info("%s: unknown field %d\n", __func__, field_type);
1083 return -1;
1084 }
1085
1086 return 0;
1087 }
1088
1089 /* Reads the intermediate representation of the templated match-fields of the
1090 * PIE rule in the pie_rule structure and fills in the raw data fields in the
1091 * raw register space r[].
1092 * The register space configuration size is identical for the RTL8380/90 and RTL9300,
1093 * however the RTL931X has 2 more registers / fields and the physical field-ids are different
1094 * on all SoCs
1095 * On the RTL9300 the mask fields are not word-aligend!
1096 */
1097 static void rtl931x_write_pie_templated(u32 r[], struct pie_rule *pr, enum template_field_id t[])
1098 {
1099 for (int i = 0; i < N_FIXED_FIELDS; i++) {
1100 u16 data, data_m;
1101
1102 rtl931x_pie_data_fill(t[i], pr, &data, &data_m);
1103
1104 /* On the RTL9300, the mask fields are not word aligned! */
1105 if (!(i % 2)) {
1106 r[5 - i / 2] = data;
1107 r[12 - i / 2] |= ((u32)data_m << 8);
1108 } else {
1109 r[5 - i / 2] |= ((u32)data) << 16;
1110 r[12 - i / 2] |= ((u32)data_m) << 24;
1111 r[11 - i / 2] |= ((u32)data_m) >> 8;
1112 }
1113 }
1114 }
1115
1116 // Currently unused
1117 // static void rtl931x_read_pie_fixed_fields(u32 r[], struct pie_rule *pr)
1118 // {
1119 // pr->mgnt_vlan = r[7] & BIT(31);
1120 // if (pr->phase == PHASE_IACL)
1121 // pr->dmac_hit_sw = r[7] & BIT(30);
1122 // else /* TODO: EACL/VACL phase handling */
1123 // pr->content_too_deep = r[7] & BIT(30);
1124 // pr->not_first_frag = r[7] & BIT(29);
1125 // pr->frame_type_l4 = (r[7] >> 26) & 7;
1126 // pr->frame_type = (r[7] >> 24) & 3;
1127 // pr->otag_fmt = (r[7] >> 23) & 1;
1128 // pr->itag_fmt = (r[7] >> 22) & 1;
1129 // pr->otag_exist = (r[7] >> 21) & 1;
1130 // pr->itag_exist = (r[7] >> 20) & 1;
1131 // pr->frame_type_l2 = (r[7] >> 18) & 3;
1132 // pr->igr_normal_port = (r[7] >> 17) & 1;
1133 // pr->tid = (r[7] >> 16) & 1;
1134
1135 // pr->mgnt_vlan_m = r[14] & BIT(15);
1136 // if (pr->phase == PHASE_IACL)
1137 // pr->dmac_hit_sw_m = r[14] & BIT(14);
1138 // else
1139 // pr->content_too_deep_m = r[14] & BIT(14);
1140 // pr->not_first_frag_m = r[14] & BIT(13);
1141 // pr->frame_type_l4_m = (r[14] >> 10) & 7;
1142 // pr->frame_type_m = (r[14] >> 8) & 3;
1143 // pr->otag_fmt_m = r[14] & BIT(7);
1144 // pr->itag_fmt_m = r[14] & BIT(6);
1145 // pr->otag_exist_m = r[14] & BIT(5);
1146 // pr->itag_exist_m = r[14] & BIT (4);
1147 // pr->frame_type_l2_m = (r[14] >> 2) & 3;
1148 // pr->igr_normal_port_m = r[14] & BIT(1);
1149 // pr->tid_m = r[14] & 1;
1150
1151 // pr->valid = r[15] & BIT(31);
1152 // pr->cond_not = r[15] & BIT(30);
1153 // pr->cond_and1 = r[15] & BIT(29);
1154 // pr->cond_and2 = r[15] & BIT(28);
1155 // }
1156
1157 static void rtl931x_write_pie_fixed_fields(u32 r[], struct pie_rule *pr)
1158 {
1159 r[7] |= pr->mgnt_vlan ? BIT(31) : 0;
1160 if (pr->phase == PHASE_IACL)
1161 r[7] |= pr->dmac_hit_sw ? BIT(30) : 0;
1162 else
1163 r[7] |= pr->content_too_deep ? BIT(30) : 0;
1164 r[7] |= pr->not_first_frag ? BIT(29) : 0;
1165 r[7] |= ((u32) (pr->frame_type_l4 & 0x7)) << 26;
1166 r[7] |= ((u32) (pr->frame_type & 0x3)) << 24;
1167 r[7] |= pr->otag_fmt ? BIT(23) : 0;
1168 r[7] |= pr->itag_fmt ? BIT(22) : 0;
1169 r[7] |= pr->otag_exist ? BIT(21) : 0;
1170 r[7] |= pr->itag_exist ? BIT(20) : 0;
1171 r[7] |= ((u32) (pr->frame_type_l2 & 0x3)) << 18;
1172 r[7] |= pr->igr_normal_port ? BIT(17) : 0;
1173 r[7] |= ((u32) (pr->tid & 0x1)) << 16;
1174
1175 r[14] |= pr->mgnt_vlan_m ? BIT(15) : 0;
1176 if (pr->phase == PHASE_IACL)
1177 r[14] |= pr->dmac_hit_sw_m ? BIT(14) : 0;
1178 else
1179 r[14] |= pr->content_too_deep_m ? BIT(14) : 0;
1180 r[14] |= pr->not_first_frag_m ? BIT(13) : 0;
1181 r[14] |= ((u32) (pr->frame_type_l4_m & 0x7)) << 10;
1182 r[14] |= ((u32) (pr->frame_type_m & 0x3)) << 8;
1183 r[14] |= pr->otag_fmt_m ? BIT(7) : 0;
1184 r[14] |= pr->itag_fmt_m ? BIT(6) : 0;
1185 r[14] |= pr->otag_exist_m ? BIT(5) : 0;
1186 r[14] |= pr->itag_exist_m ? BIT(4) : 0;
1187 r[14] |= ((u32) (pr->frame_type_l2_m & 0x3)) << 2;
1188 r[14] |= pr->igr_normal_port_m ? BIT(1) : 0;
1189 r[14] |= (u32) (pr->tid_m & 0x1);
1190
1191 r[15] |= pr->valid ? BIT(31) : 0;
1192 r[15] |= pr->cond_not ? BIT(30) : 0;
1193 r[15] |= pr->cond_and1 ? BIT(29) : 0;
1194 r[15] |= pr->cond_and2 ? BIT(28) : 0;
1195 }
1196
1197 static void rtl931x_write_pie_action(u32 r[], struct pie_rule *pr)
1198 {
1199 /* Either drop or forward */
1200 if (pr->drop) {
1201 r[15] |= BIT(11) | BIT(12) | BIT(13); /* Do Green, Yellow and Red drops */
1202 /* Actually DROP, not PERMIT in Green / Yellow / Red */
1203 r[16] |= BIT(27) | BIT(28) | BIT(29);
1204 } else {
1205 r[15] |= pr->fwd_sel ? BIT(14) : 0;
1206 r[16] |= pr->fwd_act << 24;
1207 r[16] |= BIT(21); /* We overwrite any drop */
1208 }
1209 if (pr->phase == PHASE_VACL)
1210 r[16] |= pr->fwd_sa_lrn ? BIT(22) : 0;
1211 r[15] |= pr->bypass_sel ? BIT(10) : 0;
1212 r[15] |= pr->nopri_sel ? BIT(21) : 0;
1213 r[15] |= pr->tagst_sel ? BIT(20) : 0;
1214 r[15] |= pr->ovid_sel ? BIT(18) : 0;
1215 r[15] |= pr->ivid_sel ? BIT(16) : 0;
1216 r[15] |= pr->meter_sel ? BIT(27) : 0;
1217 r[15] |= pr->mir_sel ? BIT(15) : 0;
1218 r[15] |= pr->log_sel ? BIT(26) : 0;
1219
1220 r[16] |= ((u32)(pr->fwd_data & 0xfff)) << 9;
1221 /* r[15] |= pr->log_octets ? BIT(31) : 0; */
1222 r[15] |= (u32)(pr->meter_data) >> 2;
1223 r[16] |= (((u32)(pr->meter_data) >> 7) & 0x3) << 29;
1224
1225 r[16] |= ((u32)(pr->ivid_act & 0x3)) << 21;
1226 r[15] |= ((u32)(pr->ivid_data & 0xfff)) << 9;
1227 r[16] |= ((u32)(pr->ovid_act & 0x3)) << 30;
1228 r[16] |= ((u32)(pr->ovid_data & 0xfff)) << 16;
1229 r[16] |= ((u32)(pr->mir_data & 0x3)) << 6;
1230 r[17] |= ((u32)(pr->tagst_data & 0xf)) << 28;
1231 r[17] |= ((u32)(pr->nopri_data & 0x7)) << 25;
1232 r[17] |= pr->bypass_ibc_sc ? BIT(16) : 0;
1233 }
1234
1235 void rtl931x_pie_rule_dump_raw(u32 r[])
1236 {
1237 pr_info("Raw IACL table entry:\n");
1238 pr_info("r 0 - 7: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1239 r[0], r[1], r[2], r[3], r[4], r[5], r[6], r[7]);
1240 pr_info("r 8 - 15: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1241 r[8], r[9], r[10], r[11], r[12], r[13], r[14], r[15]);
1242 pr_info("r 16 - 18: %08x %08x %08x\n", r[16], r[17], r[18]);
1243 pr_info("Match : %08x %08x %08x %08x %08x %08x\n", r[0], r[1], r[2], r[3], r[4], r[5]);
1244 pr_info("Fixed : %06x\n", r[6] >> 8);
1245 pr_info("Match M: %08x %08x %08x %08x %08x %08x\n",
1246 (r[6] << 24) | (r[7] >> 8), (r[7] << 24) | (r[8] >> 8), (r[8] << 24) | (r[9] >> 8),
1247 (r[9] << 24) | (r[10] >> 8), (r[10] << 24) | (r[11] >> 8),
1248 (r[11] << 24) | (r[12] >> 8));
1249 pr_info("R[13]: %08x\n", r[13]);
1250 pr_info("Fixed M: %06x\n", ((r[12] << 16) | (r[13] >> 16)) & 0xffffff);
1251 pr_info("Valid / not / and1 / and2 : %1x\n", (r[13] >> 12) & 0xf);
1252 pr_info("r 13-16: %08x %08x %08x %08x\n", r[13], r[14], r[15], r[16]);
1253 }
1254
1255 static int rtl931x_pie_rule_write(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr)
1256 {
1257 /* Access IACL table (0) via register 1, the table size is 4096 */
1258 struct table_reg *q = rtl_table_get(RTL9310_TBL_1, 0);
1259 u32 r[22];
1260 int block = idx / PIE_BLOCK_SIZE;
1261 u32 t_select = sw_r32(RTL931X_PIE_BLK_TMPLTE_CTRL(block));
1262
1263 pr_info("%s: %d, t_select: %08x\n", __func__, idx, t_select);
1264
1265 for (int i = 0; i < 22; i++)
1266 r[i] = 0;
1267
1268 if (!pr->valid) {
1269 rtl_table_write(q, idx);
1270 rtl_table_release(q);
1271 return 0;
1272 }
1273 rtl931x_write_pie_fixed_fields(r, pr);
1274
1275 pr_info("%s: template %d\n", __func__, (t_select >> (pr->tid * 4)) & 0xf);
1276 rtl931x_write_pie_templated(r, pr, fixed_templates[(t_select >> (pr->tid * 4)) & 0xf]);
1277
1278 rtl931x_write_pie_action(r, pr);
1279
1280 rtl931x_pie_rule_dump_raw(r);
1281
1282 for (int i = 0; i < 22; i++)
1283 sw_w32(r[i], rtl_table_data(q, i));
1284
1285 rtl_table_write(q, idx);
1286 rtl_table_release(q);
1287
1288 return 0;
1289 }
1290
1291 static bool rtl931x_pie_templ_has(int t, enum template_field_id field_type)
1292 {
1293 for (int i = 0; i < N_FIXED_FIELDS_RTL931X; i++) {
1294 enum template_field_id ft = fixed_templates[t][i];
1295 if (field_type == ft)
1296 return true;
1297 }
1298
1299 return false;
1300 }
1301
1302 /* Verify that the rule pr is compatible with a given template t in block block
1303 * Note that this function is SoC specific since the values of e.g. TEMPLATE_FIELD_SIP0
1304 * depend on the SoC
1305 */
1306 static int rtl931x_pie_verify_template(struct rtl838x_switch_priv *priv,
1307 struct pie_rule *pr, int t, int block)
1308 {
1309 int i;
1310
1311 if (!pr->is_ipv6 && pr->sip_m && !rtl931x_pie_templ_has(t, TEMPLATE_FIELD_SIP0))
1312 return -1;
1313
1314 if (!pr->is_ipv6 && pr->dip_m && !rtl931x_pie_templ_has(t, TEMPLATE_FIELD_DIP0))
1315 return -1;
1316
1317 if (pr->is_ipv6) {
1318 if ((pr->sip6_m.s6_addr32[0] ||
1319 pr->sip6_m.s6_addr32[1] ||
1320 pr->sip6_m.s6_addr32[2] ||
1321 pr->sip6_m.s6_addr32[3]) &&
1322 !rtl931x_pie_templ_has(t, TEMPLATE_FIELD_SIP2))
1323 return -1;
1324 if ((pr->dip6_m.s6_addr32[0] ||
1325 pr->dip6_m.s6_addr32[1] ||
1326 pr->dip6_m.s6_addr32[2] ||
1327 pr->dip6_m.s6_addr32[3]) &&
1328 !rtl931x_pie_templ_has(t, TEMPLATE_FIELD_DIP2))
1329 return -1;
1330 }
1331
1332 if (ether_addr_to_u64(pr->smac) && !rtl931x_pie_templ_has(t, TEMPLATE_FIELD_SMAC0))
1333 return -1;
1334
1335 if (ether_addr_to_u64(pr->dmac) && !rtl931x_pie_templ_has(t, TEMPLATE_FIELD_DMAC0))
1336 return -1;
1337
1338 /* TODO: Check more */
1339
1340 i = find_first_zero_bit(&priv->pie_use_bm[block * 4], PIE_BLOCK_SIZE);
1341
1342 if (i >= PIE_BLOCK_SIZE)
1343 return -1;
1344
1345 return i + PIE_BLOCK_SIZE * block;
1346 }
1347
1348 static int rtl931x_pie_rule_add(struct rtl838x_switch_priv *priv, struct pie_rule *pr)
1349 {
1350 int idx, block, j;
1351 int min_block = 0;
1352 int max_block = priv->n_pie_blocks / 2;
1353
1354 if (pr->is_egress) {
1355 min_block = max_block;
1356 max_block = priv->n_pie_blocks;
1357 }
1358 pr_info("In %s\n", __func__);
1359
1360 mutex_lock(&priv->pie_mutex);
1361
1362 for (block = min_block; block < max_block; block++) {
1363 for (j = 0; j < 2; j++) {
1364 int t = (sw_r32(RTL931X_PIE_BLK_TMPLTE_CTRL(block)) >> (j * 4)) & 0xf;
1365 pr_info("Testing block %d, template %d, template id %d\n", block, j, t);
1366 pr_info("%s: %08x\n",
1367 __func__, sw_r32(RTL931X_PIE_BLK_TMPLTE_CTRL(block)));
1368 idx = rtl931x_pie_verify_template(priv, pr, t, block);
1369 if (idx >= 0)
1370 break;
1371 }
1372 if (j < 2)
1373 break;
1374 }
1375
1376 if (block >= priv->n_pie_blocks) {
1377 mutex_unlock(&priv->pie_mutex);
1378 return -EOPNOTSUPP;
1379 }
1380
1381 pr_info("Using block: %d, index %d, template-id %d\n", block, idx, j);
1382 set_bit(idx, priv->pie_use_bm);
1383
1384 pr->valid = true;
1385 pr->tid = j; /* Mapped to template number */
1386 pr->tid_m = 0x1;
1387 pr->id = idx;
1388
1389 rtl931x_pie_lookup_enable(priv, idx);
1390 rtl931x_pie_rule_write(priv, idx, pr);
1391
1392 mutex_unlock(&priv->pie_mutex);
1393
1394 return 0;
1395 }
1396
1397 /* Delete a range of Packet Inspection Engine rules */
1398 static int rtl931x_pie_rule_del(struct rtl838x_switch_priv *priv, int index_from, int index_to)
1399 {
1400 u32 v = (index_from << 1)| (index_to << 13 ) | BIT(0);
1401
1402 pr_info("%s: from %d to %d\n", __func__, index_from, index_to);
1403 mutex_lock(&priv->reg_mutex);
1404
1405 /* Write from-to and execute bit into control register */
1406 sw_w32(v, RTL931X_PIE_CLR_CTRL);
1407
1408 /* Wait until command has completed */
1409 do {
1410 } while (sw_r32(RTL931X_PIE_CLR_CTRL) & BIT(0));
1411
1412 mutex_unlock(&priv->reg_mutex);
1413
1414 return 0;
1415 }
1416
1417 static void rtl931x_pie_rule_rm(struct rtl838x_switch_priv *priv, struct pie_rule *pr)
1418 {
1419 int idx = pr->id;
1420
1421 rtl931x_pie_rule_del(priv, idx, idx);
1422 clear_bit(idx, priv->pie_use_bm);
1423 }
1424
1425 static void rtl931x_pie_init(struct rtl838x_switch_priv *priv)
1426 {
1427 u32 template_selectors;
1428
1429 mutex_init(&priv->pie_mutex);
1430
1431 pr_info("%s\n", __func__);
1432 /* Enable ACL lookup on all ports, including CPU_PORT */
1433 for (int i = 0; i <= priv->cpu_port; i++)
1434 sw_w32(1, RTL931X_ACL_PORT_LOOKUP_CTRL(i));
1435
1436 /* Include IPG in metering */
1437 sw_w32_mask(0, 1, RTL931X_METER_GLB_CTRL);
1438
1439 /* Delete all present rules, block size is 128 on all SoC families */
1440 rtl931x_pie_rule_del(priv, 0, priv->n_pie_blocks * 128 - 1);
1441
1442 /* Assign first half blocks 0-7 to VACL phase, second half to IACL */
1443 /* 3 bits are used for each block, values for PIE blocks are */
1444 /* 6: Disabled, 0: VACL, 1: IACL, 2: EACL */
1445 /* And for OpenFlow Flow blocks: 3: Ingress Flow table 0, */
1446 /* 4: Ingress Flow Table 3, 5: Egress flow table 0 */
1447 for (int i = 0; i < priv->n_pie_blocks; i++) {
1448 int pos = (i % 10) * 3;
1449 u32 r = RTL931X_PIE_BLK_PHASE_CTRL + 4 * (i / 10);
1450
1451 if (i < priv->n_pie_blocks / 2)
1452 sw_w32_mask(0x7 << pos, 0, r);
1453 else
1454 sw_w32_mask(0x7 << pos, 1 << pos, r);
1455 }
1456
1457 /* Enable predefined templates 0, 1 for first quarter of all blocks */
1458 template_selectors = 0 | (1 << 4);
1459 for (int i = 0; i < priv->n_pie_blocks / 4; i++)
1460 sw_w32(template_selectors, RTL931X_PIE_BLK_TMPLTE_CTRL(i));
1461
1462 /* Enable predefined templates 2, 3 for second quarter of all blocks */
1463 template_selectors = 2 | (3 << 4);
1464 for (int i = priv->n_pie_blocks / 4; i < priv->n_pie_blocks / 2; i++)
1465 sw_w32(template_selectors, RTL931X_PIE_BLK_TMPLTE_CTRL(i));
1466
1467 /* Enable predefined templates 0, 1 for third quater of all blocks */
1468 template_selectors = 0 | (1 << 4);
1469 for (int i = priv->n_pie_blocks / 2; i < priv->n_pie_blocks * 3 / 4; i++)
1470 sw_w32(template_selectors, RTL931X_PIE_BLK_TMPLTE_CTRL(i));
1471
1472 /* Enable predefined templates 2, 3 for fourth quater of all blocks */
1473 template_selectors = 2 | (3 << 4);
1474 for (int i = priv->n_pie_blocks * 3 / 4; i < priv->n_pie_blocks; i++)
1475 sw_w32(template_selectors, RTL931X_PIE_BLK_TMPLTE_CTRL(i));
1476
1477 }
1478
1479 int rtl931x_l3_setup(struct rtl838x_switch_priv *priv)
1480 {
1481 return 0;
1482 }
1483
1484 void rtl931x_vlan_port_keep_tag_set(int port, bool keep_outer, bool keep_inner)
1485 {
1486 sw_w32(FIELD_PREP(RTL931X_VLAN_PORT_TAG_EGR_OTAG_STS_MASK,
1487 keep_outer ? RTL931X_VLAN_PORT_TAG_STS_TAGGED : RTL931X_VLAN_PORT_TAG_STS_UNTAG) |
1488 FIELD_PREP(RTL931X_VLAN_PORT_TAG_EGR_ITAG_STS_MASK,
1489 keep_inner ? RTL931X_VLAN_PORT_TAG_STS_TAGGED : RTL931X_VLAN_PORT_TAG_STS_UNTAG),
1490 RTL931X_VLAN_PORT_TAG_CTRL(port));
1491 }
1492
1493 void rtl931x_vlan_port_pvidmode_set(int port, enum pbvlan_type type, enum pbvlan_mode mode)
1494 {
1495 if (type == PBVLAN_TYPE_INNER)
1496 sw_w32_mask(0x3 << 12, mode << 12, RTL931X_VLAN_PORT_IGR_CTRL + (port << 2));
1497 else
1498 sw_w32_mask(0x3 << 26, mode << 26, RTL931X_VLAN_PORT_IGR_CTRL + (port << 2));
1499 }
1500
1501 void rtl931x_vlan_port_pvid_set(int port, enum pbvlan_type type, int pvid)
1502 {
1503 if (type == PBVLAN_TYPE_INNER)
1504 sw_w32_mask(0xfff, pvid, RTL931X_VLAN_PORT_IGR_CTRL + (port << 2));
1505 else
1506 sw_w32_mask(0xfff << 14, pvid << 14, RTL931X_VLAN_PORT_IGR_CTRL + (port << 2));
1507 }
1508
1509 static void rtl931x_set_igr_filter(int port, enum igr_filter state)
1510 {
1511 sw_w32_mask(0x3 << ((port & 0xf)<<1), state << ((port & 0xf)<<1),
1512 RTL931X_VLAN_PORT_IGR_FLTR + (((port >> 4) << 2)));
1513 }
1514
1515 static void rtl931x_set_egr_filter(int port, enum egr_filter state)
1516 {
1517 sw_w32_mask(0x1 << (port % 0x20), state << (port % 0x20),
1518 RTL931X_VLAN_PORT_EGR_FLTR + (((port >> 5) << 2)));
1519 }
1520
1521 void rtl931x_set_distribution_algorithm(int group, int algoidx, u32 algomsk)
1522 {
1523 u32 l3shift = 0;
1524 u32 newmask = 0;
1525
1526 /* TODO: for now we set algoidx to 0 */
1527 algoidx = 0;
1528
1529 if (algomsk & TRUNK_DISTRIBUTION_ALGO_SIP_BIT) {
1530 l3shift = 4;
1531 newmask |= TRUNK_DISTRIBUTION_ALGO_L3_SIP_BIT;
1532 }
1533 if (algomsk & TRUNK_DISTRIBUTION_ALGO_DIP_BIT) {
1534 l3shift = 4;
1535 newmask |= TRUNK_DISTRIBUTION_ALGO_L3_DIP_BIT;
1536 }
1537 if (algomsk & TRUNK_DISTRIBUTION_ALGO_SRC_L4PORT_BIT) {
1538 l3shift = 4;
1539 newmask |= TRUNK_DISTRIBUTION_ALGO_L3_SRC_L4PORT_BIT;
1540 }
1541 if (algomsk & TRUNK_DISTRIBUTION_ALGO_SRC_L4PORT_BIT) {
1542 l3shift = 4;
1543 newmask |= TRUNK_DISTRIBUTION_ALGO_L3_SRC_L4PORT_BIT;
1544 }
1545
1546 if (l3shift == 4) {
1547 if (algomsk & TRUNK_DISTRIBUTION_ALGO_SMAC_BIT)
1548 newmask |= TRUNK_DISTRIBUTION_ALGO_L3_SMAC_BIT;
1549 if (algomsk & TRUNK_DISTRIBUTION_ALGO_DMAC_BIT)
1550 newmask |= TRUNK_DISTRIBUTION_ALGO_L3_DMAC_BIT;
1551 } else {
1552 if (algomsk & TRUNK_DISTRIBUTION_ALGO_SMAC_BIT)
1553 newmask |= TRUNK_DISTRIBUTION_ALGO_L2_SMAC_BIT;
1554 if (algomsk & TRUNK_DISTRIBUTION_ALGO_DMAC_BIT)
1555 newmask |= TRUNK_DISTRIBUTION_ALGO_L2_DMAC_BIT;
1556 }
1557
1558 sw_w32(newmask << l3shift, RTL931X_TRK_HASH_CTRL + (algoidx << 2));
1559 }
1560
1561 static void rtl931x_led_init(struct rtl838x_switch_priv *priv)
1562 {
1563 u64 pm_copper = 0, pm_fiber = 0;
1564 struct device_node *node;
1565
1566 pr_info("%s called\n", __func__);
1567 node = of_find_compatible_node(NULL, NULL, "realtek,rtl9300-leds");
1568 if (!node) {
1569 pr_info("%s No compatible LED node found\n", __func__);
1570 return;
1571 }
1572
1573 for (int i = 0; i < priv->cpu_port; i++) {
1574 int pos = (i << 1) % 32;
1575 u32 set;
1576 u32 v;
1577
1578 sw_w32_mask(0x3 << pos, 0, RTL931X_LED_PORT_FIB_SET_SEL_CTRL(i));
1579 sw_w32_mask(0x3 << pos, 0, RTL931X_LED_PORT_COPR_SET_SEL_CTRL(i));
1580
1581 if (!priv->ports[i].phy)
1582 continue;
1583
1584 v = 0x1; /* Found on the EdgeCore, but we do not have any HW description */
1585 sw_w32_mask(0x3 << pos, v << pos, RTL931X_LED_PORT_NUM_CTRL(i));
1586
1587 if (priv->ports[i].phy_is_integrated)
1588 pm_fiber |= BIT_ULL(i);
1589 else
1590 pm_copper |= BIT_ULL(i);
1591
1592 set = priv->ports[i].led_set;
1593 sw_w32_mask(0, set << pos, RTL931X_LED_PORT_COPR_SET_SEL_CTRL(i));
1594 sw_w32_mask(0, set << pos, RTL931X_LED_PORT_FIB_SET_SEL_CTRL(i));
1595 }
1596
1597 for (int i = 0; i < 4; i++) {
1598 const __be32 *led_set;
1599 char set_name[9];
1600 u32 setlen;
1601 u32 v;
1602
1603 sprintf(set_name, "led_set%d", i);
1604 pr_info(">%s<\n", set_name);
1605 led_set = of_get_property(node, set_name, &setlen);
1606 if (!led_set || setlen != 16)
1607 break;
1608 v = be32_to_cpup(led_set) << 16 | be32_to_cpup(led_set + 1);
1609 sw_w32(v, RTL931X_LED_SET0_0_CTRL - 4 - i * 8);
1610 v = be32_to_cpup(led_set + 2) << 16 | be32_to_cpup(led_set + 3);
1611 sw_w32(v, RTL931X_LED_SET0_0_CTRL - i * 8);
1612 }
1613
1614 /* Set LED mode to serial (0x1) */
1615 sw_w32_mask(0x3, 0x1, RTL931X_LED_GLB_CTRL);
1616
1617 rtl839x_set_port_reg_le(pm_copper, RTL931X_LED_PORT_COPR_MASK_CTRL);
1618 rtl839x_set_port_reg_le(pm_fiber, RTL931X_LED_PORT_FIB_MASK_CTRL);
1619 rtl839x_set_port_reg_le(pm_copper | pm_fiber, RTL931X_LED_PORT_COMBO_MASK_CTRL);
1620
1621 for (int i = 0; i < 32; i++)
1622 pr_info("%s %08x: %08x\n",__func__, 0xbb000600 + i * 4, sw_r32(0x0600 + i * 4));
1623 }
1624
1625 const struct rtl838x_reg rtl931x_reg = {
1626 .mask_port_reg_be = rtl839x_mask_port_reg_be,
1627 .set_port_reg_be = rtl839x_set_port_reg_be,
1628 .get_port_reg_be = rtl839x_get_port_reg_be,
1629 .mask_port_reg_le = rtl839x_mask_port_reg_le,
1630 .set_port_reg_le = rtl839x_set_port_reg_le,
1631 .get_port_reg_le = rtl839x_get_port_reg_le,
1632 .stat_port_rst = RTL931X_STAT_PORT_RST,
1633 .stat_rst = RTL931X_STAT_RST,
1634 .stat_port_std_mib = 0, /* Not defined */
1635 .traffic_enable = rtl931x_traffic_enable,
1636 .traffic_disable = rtl931x_traffic_disable,
1637 .traffic_get = rtl931x_traffic_get,
1638 .traffic_set = rtl931x_traffic_set,
1639 .l2_ctrl_0 = RTL931X_L2_CTRL,
1640 .l2_ctrl_1 = RTL931X_L2_AGE_CTRL,
1641 .l2_port_aging_out = RTL931X_L2_PORT_AGE_CTRL,
1642 .set_ageing_time = rtl931x_set_ageing_time,
1643 /* .smi_poll_ctrl does not exist */
1644 .l2_tbl_flush_ctrl = RTL931X_L2_TBL_FLUSH_CTRL,
1645 .exec_tbl0_cmd = rtl931x_exec_tbl0_cmd,
1646 .exec_tbl1_cmd = rtl931x_exec_tbl1_cmd,
1647 .tbl_access_data_0 = rtl931x_tbl_access_data_0,
1648 .isr_glb_src = RTL931X_ISR_GLB_SRC,
1649 .isr_port_link_sts_chg = RTL931X_ISR_PORT_LINK_STS_CHG,
1650 .imr_port_link_sts_chg = RTL931X_IMR_PORT_LINK_STS_CHG,
1651 /* imr_glb does not exist on RTL931X */
1652 .vlan_tables_read = rtl931x_vlan_tables_read,
1653 .vlan_set_tagged = rtl931x_vlan_set_tagged,
1654 .vlan_set_untagged = rtl931x_vlan_set_untagged,
1655 .vlan_profile_dump = rtl931x_vlan_profile_dump,
1656 .vlan_profile_setup = rtl931x_vlan_profile_setup,
1657 .vlan_fwd_on_inner = rtl931x_vlan_fwd_on_inner,
1658 .stp_get = rtl931x_stp_get,
1659 .stp_set = rtl931x_stp_set,
1660 .mac_force_mode_ctrl = rtl931x_mac_force_mode_ctrl,
1661 .mac_port_ctrl = rtl931x_mac_port_ctrl,
1662 .l2_port_new_salrn = rtl931x_l2_port_new_salrn,
1663 .l2_port_new_sa_fwd = rtl931x_l2_port_new_sa_fwd,
1664 .mir_ctrl = RTL931X_MIR_CTRL,
1665 .mir_dpm = RTL931X_MIR_DPM_CTRL,
1666 .mir_spm = RTL931X_MIR_SPM_CTRL,
1667 .mac_link_sts = RTL931X_MAC_LINK_STS,
1668 .mac_link_dup_sts = RTL931X_MAC_LINK_DUP_STS,
1669 .mac_link_spd_sts = rtl931x_mac_link_spd_sts,
1670 .mac_rx_pause_sts = RTL931X_MAC_RX_PAUSE_STS,
1671 .mac_tx_pause_sts = RTL931X_MAC_TX_PAUSE_STS,
1672 .read_l2_entry_using_hash = rtl931x_read_l2_entry_using_hash,
1673 .write_l2_entry_using_hash = rtl931x_write_l2_entry_using_hash,
1674 .read_cam = rtl931x_read_cam,
1675 .write_cam = rtl931x_write_cam,
1676 .vlan_port_keep_tag_set = rtl931x_vlan_port_keep_tag_set,
1677 .vlan_port_pvidmode_set = rtl931x_vlan_port_pvidmode_set,
1678 .vlan_port_pvid_set = rtl931x_vlan_port_pvid_set,
1679 .trk_mbr_ctr = rtl931x_trk_mbr_ctr,
1680 .set_vlan_igr_filter = rtl931x_set_igr_filter,
1681 .set_vlan_egr_filter = rtl931x_set_egr_filter,
1682 .set_distribution_algorithm = rtl931x_set_distribution_algorithm,
1683 .l2_hash_key = rtl931x_l2_hash_key,
1684 .read_mcast_pmask = rtl931x_read_mcast_pmask,
1685 .write_mcast_pmask = rtl931x_write_mcast_pmask,
1686 .pie_init = rtl931x_pie_init,
1687 .pie_rule_write = rtl931x_pie_rule_write,
1688 .pie_rule_add = rtl931x_pie_rule_add,
1689 .pie_rule_rm = rtl931x_pie_rule_rm,
1690 .l2_learning_setup = rtl931x_l2_learning_setup,
1691 .l3_setup = rtl931x_l3_setup,
1692 .led_init = rtl931x_led_init,
1693 };
Staging tree of Jo-Philipp Wich