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realtek: Add missing headers
[openwrt/staging/nbd.git] / target / linux / realtek / files-5.15 / drivers / net / dsa / rtl83xx / rtl931x.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <asm/mach-rtl838x/mach-rtl83xx.h>
4 #include <linux/etherdevice.h>
5
6 #include "rtl83xx.h"
7
8 #define RTL931X_VLAN_PORT_TAG_STS_INTERNAL 0x0
9 #define RTL931X_VLAN_PORT_TAG_STS_UNTAG 0x1
10 #define RTL931X_VLAN_PORT_TAG_STS_TAGGED 0x2
11 #define RTL931X_VLAN_PORT_TAG_STS_PRIORITY_TAGGED 0x3
12
13 #define RTL931X_VLAN_PORT_TAG_CTRL_BASE 0x4860
14 /* port 0-56 */
15 #define RTL931X_VLAN_PORT_TAG_CTRL(port) \
16 RTL931X_VLAN_PORT_TAG_CTRL_BASE + (port << 2)
17 #define RTL931X_VLAN_PORT_TAG_EGR_OTAG_STS_MASK GENMASK(13,12)
18 #define RTL931X_VLAN_PORT_TAG_EGR_ITAG_STS_MASK GENMASK(11,10)
19 #define RTL931X_VLAN_PORT_TAG_EGR_OTAG_KEEP_MASK GENMASK(9,9)
20 #define RTL931X_VLAN_PORT_TAG_EGR_ITAG_KEEP_MASK GENMASK(8,8)
21 #define RTL931X_VLAN_PORT_TAG_IGR_OTAG_KEEP_MASK GENMASK(7,7)
22 #define RTL931X_VLAN_PORT_TAG_IGR_ITAG_KEEP_MASK GENMASK(6,6)
23 #define RTL931X_VLAN_PORT_TAG_OTPID_IDX_MASK GENMASK(5,4)
24 #define RTL931X_VLAN_PORT_TAG_OTPID_KEEP_MASK GENMASK(3,3)
25 #define RTL931X_VLAN_PORT_TAG_ITPID_IDX_MASK GENMASK(2,1)
26 #define RTL931X_VLAN_PORT_TAG_ITPID_KEEP_MASK GENMASK(0,0)
27
28 extern struct mutex smi_lock;
29 extern struct rtl83xx_soc_info soc_info;
30
31 /* Definition of the RTL931X-specific template field IDs as used in the PIE */
32 enum template_field_id {
33 TEMPLATE_FIELD_SPM0 = 1,
34 TEMPLATE_FIELD_SPM1 = 2,
35 TEMPLATE_FIELD_SPM2 = 3,
36 TEMPLATE_FIELD_SPM3 = 4,
37 TEMPLATE_FIELD_DMAC0 = 9,
38 TEMPLATE_FIELD_DMAC1 = 10,
39 TEMPLATE_FIELD_DMAC2 = 11,
40 TEMPLATE_FIELD_SMAC0 = 12,
41 TEMPLATE_FIELD_SMAC1 = 13,
42 TEMPLATE_FIELD_SMAC2 = 14,
43 TEMPLATE_FIELD_ETHERTYPE = 15,
44 TEMPLATE_FIELD_OTAG = 16,
45 TEMPLATE_FIELD_ITAG = 17,
46 TEMPLATE_FIELD_SIP0 = 18,
47 TEMPLATE_FIELD_SIP1 = 19,
48 TEMPLATE_FIELD_DIP0 = 20,
49 TEMPLATE_FIELD_DIP1 = 21,
50 TEMPLATE_FIELD_IP_TOS_PROTO = 22,
51 TEMPLATE_FIELD_L4_SPORT = 23,
52 TEMPLATE_FIELD_L4_DPORT = 24,
53 TEMPLATE_FIELD_L34_HEADER = 25,
54 TEMPLATE_FIELD_TCP_INFO = 26,
55 TEMPLATE_FIELD_SIP2 = 34,
56 TEMPLATE_FIELD_SIP3 = 35,
57 TEMPLATE_FIELD_SIP4 = 36,
58 TEMPLATE_FIELD_SIP5 = 37,
59 TEMPLATE_FIELD_SIP6 = 38,
60 TEMPLATE_FIELD_SIP7 = 39,
61 TEMPLATE_FIELD_DIP2 = 42,
62 TEMPLATE_FIELD_DIP3 = 43,
63 TEMPLATE_FIELD_DIP4 = 44,
64 TEMPLATE_FIELD_DIP5 = 45,
65 TEMPLATE_FIELD_DIP6 = 46,
66 TEMPLATE_FIELD_DIP7 = 47,
67 TEMPLATE_FIELD_FLOW_LABEL = 49,
68 TEMPLATE_FIELD_DSAP_SSAP = 50,
69 TEMPLATE_FIELD_FWD_VID = 52,
70 TEMPLATE_FIELD_RANGE_CHK = 53,
71 TEMPLATE_FIELD_SLP = 55,
72 TEMPLATE_FIELD_DLP = 56,
73 TEMPLATE_FIELD_META_DATA = 57,
74 TEMPLATE_FIELD_FIRST_MPLS1 = 60,
75 TEMPLATE_FIELD_FIRST_MPLS2 = 61,
76 TEMPLATE_FIELD_DPM3 = 8,
77 };
78
79 /* The meaning of TEMPLATE_FIELD_VLAN depends on phase and the configuration in
80 * RTL931X_PIE_CTRL. We use always the same definition and map to the inner VLAN tag:
81 */
82 #define TEMPLATE_FIELD_VLAN TEMPLATE_FIELD_ITAG
83
84 /* Number of fixed templates predefined in the RTL9300 SoC */
85 #define N_FIXED_TEMPLATES 5
86 /* RTL931x specific predefined templates */
87 static enum template_field_id fixed_templates[N_FIXED_TEMPLATES][N_FIXED_FIELDS_RTL931X] =
88 {
89 {
90 TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2,
91 TEMPLATE_FIELD_SMAC0, TEMPLATE_FIELD_SMAC1, TEMPLATE_FIELD_SMAC2,
92 TEMPLATE_FIELD_VLAN, TEMPLATE_FIELD_IP_TOS_PROTO, TEMPLATE_FIELD_DSAP_SSAP,
93 TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1,
94 TEMPLATE_FIELD_SPM2, TEMPLATE_FIELD_SPM3
95 }, {
96 TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0,
97 TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_IP_TOS_PROTO, TEMPLATE_FIELD_TCP_INFO,
98 TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_L4_DPORT, TEMPLATE_FIELD_VLAN,
99 TEMPLATE_FIELD_RANGE_CHK, TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1,
100 TEMPLATE_FIELD_SPM2, TEMPLATE_FIELD_SPM3
101 }, {
102 TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2,
103 TEMPLATE_FIELD_VLAN, TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_IP_TOS_PROTO,
104 TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0,
105 TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_L4_DPORT,
106 TEMPLATE_FIELD_META_DATA, TEMPLATE_FIELD_SLP
107 }, {
108 TEMPLATE_FIELD_DIP0, TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_DIP2,
109 TEMPLATE_FIELD_DIP3, TEMPLATE_FIELD_DIP4, TEMPLATE_FIELD_DIP5,
110 TEMPLATE_FIELD_DIP6, TEMPLATE_FIELD_DIP7, TEMPLATE_FIELD_IP_TOS_PROTO,
111 TEMPLATE_FIELD_TCP_INFO, TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_L4_DPORT,
112 TEMPLATE_FIELD_RANGE_CHK, TEMPLATE_FIELD_SLP
113 }, {
114 TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_SIP2,
115 TEMPLATE_FIELD_SIP3, TEMPLATE_FIELD_SIP4, TEMPLATE_FIELD_SIP5,
116 TEMPLATE_FIELD_SIP6, TEMPLATE_FIELD_SIP7, TEMPLATE_FIELD_META_DATA,
117 TEMPLATE_FIELD_VLAN, TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1,
118 TEMPLATE_FIELD_SPM2, TEMPLATE_FIELD_SPM3
119 },
120 };
121
122 inline void rtl931x_exec_tbl0_cmd(u32 cmd)
123 {
124 sw_w32(cmd, RTL931X_TBL_ACCESS_CTRL_0);
125 do { } while (sw_r32(RTL931X_TBL_ACCESS_CTRL_0) & (1 << 20));
126 }
127
128 inline void rtl931x_exec_tbl1_cmd(u32 cmd)
129 {
130 sw_w32(cmd, RTL931X_TBL_ACCESS_CTRL_1);
131 do { } while (sw_r32(RTL931X_TBL_ACCESS_CTRL_1) & (1 << 17));
132 }
133
134 inline int rtl931x_tbl_access_data_0(int i)
135 {
136 return RTL931X_TBL_ACCESS_DATA_0(i);
137 }
138
139 void rtl931x_vlan_profile_dump(int index)
140 {
141 u64 profile[4];
142
143 if (index < 0 || index > 15)
144 return;
145
146 profile[0] = sw_r32(RTL931X_VLAN_PROFILE_SET(index));
147 profile[1] = (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 4) & 0x1FFFFFFFULL) << 32 |
148 (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 8) & 0xFFFFFFFF);
149 profile[2] = (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 16) & 0x1FFFFFFFULL) << 32 |
150 (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 12) & 0xFFFFFFFF);
151 profile[3] = (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 20) & 0x1FFFFFFFULL) << 32 |
152 (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 24) & 0xFFFFFFFF);
153
154 pr_info("VLAN %d: L2 learning: %d, L2 Unknown MultiCast Field %llx, \
155 IPv4 Unknown MultiCast Field %llx, IPv6 Unknown MultiCast Field: %llx",
156 index, (u32) (profile[0] & (3 << 14)), profile[1], profile[2], profile[3]);
157 }
158
159 static void rtl931x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
160 {
161 u32 cmd = 1 << 20 | /* Execute cmd */
162 0 << 19 | /* Read */
163 5 << 15 | /* Table type 0b101 */
164 (msti & 0x3fff);
165 priv->r->exec_tbl0_cmd(cmd);
166
167 for (int i = 0; i < 4; i++)
168 port_state[i] = sw_r32(priv->r->tbl_access_data_0(i));
169 }
170
171 static void rtl931x_stp_set(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
172 {
173 u32 cmd = 1 << 20 | /* Execute cmd */
174 1 << 19 | /* Write */
175 5 << 15 | /* Table type 0b101 */
176 (msti & 0x3fff);
177 for (int i = 0; i < 4; i++)
178 sw_w32(port_state[i], priv->r->tbl_access_data_0(i));
179 priv->r->exec_tbl0_cmd(cmd);
180 }
181
182 inline static int rtl931x_trk_mbr_ctr(int group)
183 {
184 return RTL931X_TRK_MBR_CTRL + (group << 2);
185 }
186
187 static void rtl931x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info)
188 {
189 u32 v, w, x, y;
190 /* Read VLAN table (3) via register 0 */
191 struct table_reg *r = rtl_table_get(RTL9310_TBL_0, 3);
192
193 rtl_table_read(r, vlan);
194 v = sw_r32(rtl_table_data(r, 0));
195 w = sw_r32(rtl_table_data(r, 1));
196 x = sw_r32(rtl_table_data(r, 2));
197 y = sw_r32(rtl_table_data(r, 3));
198 rtl_table_release(r);
199
200 pr_debug("VLAN_READ %d: %08x %08x %08x %08x\n", vlan, v, w, x, y);
201 info->tagged_ports = ((u64) v) << 25 | (w >> 7);
202 info->profile_id = (x >> 16) & 0xf;
203 info->fid = w & 0x7f; /* AKA MSTI depending on context */
204 info->hash_uc_fid = !!(x & BIT(31));
205 info->hash_mc_fid = !!(x & BIT(30));
206 info->if_id = (x >> 20) & 0x3ff;
207 info->profile_id = (x >> 16) & 0xf;
208 info->multicast_grp_mask = x & 0xffff;
209 if (x & BIT(31))
210 info->l2_tunnel_list_id = y >> 18;
211 else
212 info->l2_tunnel_list_id = -1;
213 pr_debug("%s read tagged %016llx, profile-id %d, uc %d, mc %d, intf-id %d\n", __func__,
214 info->tagged_ports, info->profile_id, info->hash_uc_fid, info->hash_mc_fid,
215 info->if_id);
216
217 /* Read UNTAG table via table register 3 */
218 r = rtl_table_get(RTL9310_TBL_3, 0);
219 rtl_table_read(r, vlan);
220 v = ((u64)sw_r32(rtl_table_data(r, 0))) << 25;
221 v |= sw_r32(rtl_table_data(r, 1)) >> 7;
222 rtl_table_release(r);
223
224 info->untagged_ports = v;
225 }
226
227 static void rtl931x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info)
228 {
229 u32 v, w, x, y;
230 /* Access VLAN table (1) via register 0 */
231 struct table_reg *r = rtl_table_get(RTL9310_TBL_0, 3);
232
233 v = info->tagged_ports >> 25;
234 w = (info->tagged_ports & 0x1fffff) << 7;
235 w |= info->fid & 0x7f;
236 x = info->hash_uc_fid ? BIT(31) : 0;
237 x |= info->hash_mc_fid ? BIT(30) : 0;
238 x |= info->if_id & 0x3ff << 20;
239 x |= (info->profile_id & 0xf) << 16;
240 x |= info->multicast_grp_mask & 0xffff;
241 if (info->l2_tunnel_list_id >= 0) {
242 y = info->l2_tunnel_list_id << 18;
243 y |= BIT(31);
244 } else {
245 y = 0;
246 }
247
248 sw_w32(v, rtl_table_data(r, 0));
249 sw_w32(w, rtl_table_data(r, 1));
250 sw_w32(x, rtl_table_data(r, 2));
251 sw_w32(y, rtl_table_data(r, 3));
252
253 rtl_table_write(r, vlan);
254 rtl_table_release(r);
255 }
256
257 static void rtl931x_vlan_set_untagged(u32 vlan, u64 portmask)
258 {
259 struct table_reg *r = rtl_table_get(RTL9310_TBL_3, 0);
260
261 rtl839x_set_port_reg_be(portmask << 7, rtl_table_data(r, 0));
262 rtl_table_write(r, vlan);
263 rtl_table_release(r);
264 }
265
266 static inline int rtl931x_mac_force_mode_ctrl(int p)
267 {
268 return RTL931X_MAC_FORCE_MODE_CTRL + (p << 2);
269 }
270
271 static inline int rtl931x_mac_link_spd_sts(int p)
272 {
273 return RTL931X_MAC_LINK_SPD_STS + (((p >> 3) << 2));
274 }
275
276 static inline int rtl931x_mac_port_ctrl(int p)
277 {
278 return RTL931X_MAC_L2_PORT_CTRL + (p << 7);
279 }
280
281 static inline int rtl931x_l2_port_new_salrn(int p)
282 {
283 return RTL931X_L2_PORT_NEW_SALRN(p);
284 }
285
286 static inline int rtl931x_l2_port_new_sa_fwd(int p)
287 {
288 return RTL931X_L2_PORT_NEW_SA_FWD(p);
289 }
290
291 irqreturn_t rtl931x_switch_irq(int irq, void *dev_id)
292 {
293 struct dsa_switch *ds = dev_id;
294 u32 status = sw_r32(RTL931X_ISR_GLB_SRC);
295 u64 ports = rtl839x_get_port_reg_le(RTL931X_ISR_PORT_LINK_STS_CHG);
296 u64 link;
297
298 /* Clear status */
299 rtl839x_set_port_reg_le(ports, RTL931X_ISR_PORT_LINK_STS_CHG);
300 pr_debug("RTL931X Link change: status: %x, ports %016llx\n", status, ports);
301
302 link = rtl839x_get_port_reg_le(RTL931X_MAC_LINK_STS);
303 /* Must re-read this to get correct status */
304 link = rtl839x_get_port_reg_le(RTL931X_MAC_LINK_STS);
305 pr_debug("RTL931X Link change: status: %x, link status %016llx\n", status, link);
306
307 for (int i = 0; i < 56; i++) {
308 if (ports & BIT_ULL(i)) {
309 if (link & BIT_ULL(i)) {
310 pr_info("%s port %d up\n", __func__, i);
311 dsa_port_phylink_mac_change(ds, i, true);
312 } else {
313 pr_info("%s port %d down\n", __func__, i);
314 dsa_port_phylink_mac_change(ds, i, false);
315 }
316 }
317 }
318
319 return IRQ_HANDLED;
320 }
321
322 int rtl931x_write_phy(u32 port, u32 page, u32 reg, u32 val)
323 {
324 u32 v;
325 int err = 0;
326
327 val &= 0xffff;
328 if (port > 63 || page > 4095 || reg > 31)
329 return -ENOTSUPP;
330
331 mutex_lock(&smi_lock);
332 pr_debug("%s: writing to phy %d %d %d %d\n", __func__, port, page, reg, val);
333 /* Clear both port registers */
334 sw_w32(0, RTL931X_SMI_INDRT_ACCESS_CTRL_2);
335 sw_w32(0, RTL931X_SMI_INDRT_ACCESS_CTRL_2 + 4);
336 sw_w32_mask(0, BIT(port % 32), RTL931X_SMI_INDRT_ACCESS_CTRL_2 + (port / 32) * 4);
337
338 sw_w32_mask(0xffff, val, RTL931X_SMI_INDRT_ACCESS_CTRL_3);
339
340 v = reg << 6 | page << 11 ;
341 sw_w32(v, RTL931X_SMI_INDRT_ACCESS_CTRL_0);
342
343 sw_w32(0x1ff, RTL931X_SMI_INDRT_ACCESS_CTRL_1);
344
345 v |= BIT(4) | 1; /* Write operation and execute */
346 sw_w32(v, RTL931X_SMI_INDRT_ACCESS_CTRL_0);
347
348 do {
349 } while (sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_0) & 0x1);
350
351 if (sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_0) & 0x2)
352 err = -EIO;
353
354 mutex_unlock(&smi_lock);
355
356 return err;
357 }
358
359 int rtl931x_read_phy(u32 port, u32 page, u32 reg, u32 *val)
360 {
361 u32 v;
362
363 if (port > 63 || page > 4095 || reg > 31)
364 return -ENOTSUPP;
365
366 mutex_lock(&smi_lock);
367
368 sw_w32(port << 5, RTL931X_SMI_INDRT_ACCESS_BC_PHYID_CTRL);
369
370 v = reg << 6 | page << 11 | 1;
371 sw_w32(v, RTL931X_SMI_INDRT_ACCESS_CTRL_0);
372
373 do {
374 } while (sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_0) & 0x1);
375
376 v = sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_0);
377 *val = sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_3);
378 *val = (*val & 0xffff0000) >> 16;
379
380 pr_debug("%s: port %d, page: %d, reg: %x, val: %x, v: %08x\n",
381 __func__, port, page, reg, *val, v);
382
383 mutex_unlock(&smi_lock);
384
385 return 0;
386 }
387
388 /* Read an mmd register of the PHY */
389 int rtl931x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val)
390 {
391 int err = 0;
392 u32 v;
393 /* Select PHY register type
394 * If select 1G/10G MMD register type, registers EXT_PAGE, MAIN_PAGE and REG settings are don’t care.
395 * 0x0 Normal register (Clause 22)
396 * 0x1: 1G MMD register (MMD via Clause 22 registers 13 and 14)
397 * 0x2: 10G MMD register (MMD via Clause 45)
398 */
399 int type = (regnum & MII_ADDR_C45)?2:1;
400
401 mutex_lock(&smi_lock);
402
403 /* Set PHY to access via port-number */
404 sw_w32(port << 5, RTL931X_SMI_INDRT_ACCESS_BC_PHYID_CTRL);
405
406 /* Set MMD device number and register to write to */
407 sw_w32(devnum << 16 | mdiobus_c45_regad(regnum), RTL931X_SMI_INDRT_ACCESS_MMD_CTRL);
408
409 v = type << 2 | BIT(0); /* MMD-access-type | EXEC */
410 sw_w32(v, RTL931X_SMI_INDRT_ACCESS_CTRL_0);
411
412 do {
413 v = sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_0);
414 } while (v & BIT(0));
415
416 /* Check for error condition */
417 if (v & BIT(1))
418 err = -EIO;
419
420 *val = sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_3) >> 16;
421
422 pr_debug("%s: port %d, dev: %x, regnum: %x, val: %x (err %d)\n", __func__,
423 port, devnum, mdiobus_c45_regad(regnum), *val, err);
424
425 mutex_unlock(&smi_lock);
426
427 return err;
428 }
429
430 /* Write to an mmd register of the PHY */
431 int rtl931x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val)
432 {
433 int err = 0;
434 u32 v;
435 int type = (regnum & MII_ADDR_C45)?2:1;
436 u64 pm;
437
438 mutex_lock(&smi_lock);
439
440 /* Set PHY to access via port-mask */
441 pm = (u64)1 << port;
442 sw_w32((u32)pm, RTL931X_SMI_INDRT_ACCESS_CTRL_2);
443 sw_w32((u32)(pm >> 32), RTL931X_SMI_INDRT_ACCESS_CTRL_2 + 4);
444
445 /* Set data to write */
446 sw_w32_mask(0xffff, val, RTL931X_SMI_INDRT_ACCESS_CTRL_3);
447
448 /* Set MMD device number and register to write to */
449 sw_w32(devnum << 16 | mdiobus_c45_regad(regnum), RTL931X_SMI_INDRT_ACCESS_MMD_CTRL);
450
451 v = BIT(4) | type << 2 | BIT(0); /* WRITE | MMD-access-type | EXEC */
452 sw_w32(v, RTL931X_SMI_INDRT_ACCESS_CTRL_0);
453
454 do {
455 v = sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_0);
456 } while (v & BIT(0));
457
458 pr_debug("%s: port %d, dev: %x, regnum: %x, val: %x (err %d)\n", __func__,
459 port, devnum, mdiobus_c45_regad(regnum), val, err);
460 mutex_unlock(&smi_lock);
461
462 return err;
463 }
464
465 void rtl931x_print_matrix(void)
466 {
467 volatile u64 *ptr = RTL838X_SW_BASE + RTL839X_PORT_ISO_CTRL(0);
468
469 for (int i = 0; i < 52; i += 4)
470 pr_info("> %16llx %16llx %16llx %16llx\n",
471 ptr[i + 0], ptr[i + 1], ptr[i + 2], ptr[i + 3]);
472 pr_info("CPU_PORT> %16llx\n", ptr[52]);
473 }
474
475 void rtl931x_set_receive_management_action(int port, rma_ctrl_t type, action_type_t action)
476 {
477 u32 value = 0;
478
479 /* hack for value mapping */
480 if (type == GRATARP && action == COPY2CPU)
481 action = TRAP2MASTERCPU;
482
483 switch(action) {
484 case FORWARD:
485 value = 0;
486 break;
487 case DROP:
488 value = 1;
489 break;
490 case TRAP2CPU:
491 value = 2;
492 break;
493 case TRAP2MASTERCPU:
494 value = 3;
495 break;
496 case FLOODALL:
497 value = 4;
498 break;
499 default:
500 break;
501 }
502
503 switch(type) {
504 case BPDU:
505 sw_w32_mask(7 << ((port % 10) * 3), value << ((port % 10) * 3), RTL931X_RMA_BPDU_CTRL + ((port / 10) << 2));
506 break;
507 case PTP:
508 /* udp */
509 sw_w32_mask(3 << 2, value << 2, RTL931X_RMA_PTP_CTRL + (port << 2));
510 /* eth2 */
511 sw_w32_mask(3, value, RTL931X_RMA_PTP_CTRL + (port << 2));
512 break;
513 case PTP_UDP:
514 sw_w32_mask(3 << 2, value << 2, RTL931X_RMA_PTP_CTRL + (port << 2));
515 break;
516 case PTP_ETH2:
517 sw_w32_mask(3, value, RTL931X_RMA_PTP_CTRL + (port << 2));
518 break;
519 case LLTP:
520 sw_w32_mask(7 << ((port % 10) * 3), value << ((port % 10) * 3), RTL931X_RMA_LLTP_CTRL + ((port / 10) << 2));
521 break;
522 case EAPOL:
523 sw_w32_mask(7 << ((port % 10) * 3), value << ((port % 10) * 3), RTL931X_RMA_EAPOL_CTRL + ((port / 10) << 2));
524 break;
525 case GRATARP:
526 sw_w32_mask(3 << ((port & 0xf) << 1), value << ((port & 0xf) << 1), RTL931X_TRAP_ARP_GRAT_PORT_ACT + ((port >> 4) << 2));
527 break;
528 }
529 }
530
531 u64 rtl931x_traffic_get(int source)
532 {
533 u32 v;
534 struct table_reg *r = rtl_table_get(RTL9310_TBL_0, 6);
535
536 rtl_table_read(r, source);
537 v = sw_r32(rtl_table_data(r, 0));
538 rtl_table_release(r);
539 v = v >> 3;
540
541 return v;
542 }
543
544 /* Enable traffic between a source port and a destination port matrix */
545 void rtl931x_traffic_set(int source, u64 dest_matrix)
546 {
547 struct table_reg *r = rtl_table_get(RTL9310_TBL_0, 6);
548
549 sw_w32((dest_matrix << 3), rtl_table_data(r, 0));
550 rtl_table_write(r, source);
551 rtl_table_release(r);
552 }
553
554 void rtl931x_traffic_enable(int source, int dest)
555 {
556 struct table_reg *r = rtl_table_get(RTL9310_TBL_0, 6);
557 rtl_table_read(r, source);
558 sw_w32_mask(0, BIT(dest + 3), rtl_table_data(r, 0));
559 rtl_table_write(r, source);
560 rtl_table_release(r);
561 }
562
563 void rtl931x_traffic_disable(int source, int dest)
564 {
565 struct table_reg *r = rtl_table_get(RTL9310_TBL_0, 6);
566 rtl_table_read(r, source);
567 sw_w32_mask(BIT(dest + 3), 0, rtl_table_data(r, 0));
568 rtl_table_write(r, source);
569 rtl_table_release(r);
570 }
571
572 static u64 rtl931x_l2_hash_seed(u64 mac, u32 vid)
573 {
574 u64 v = vid;
575
576 v <<= 48;
577 v |= mac;
578
579 return v;
580 }
581
582 /* Calculate both the block 0 and the block 1 hash by applyingthe same hash
583 * algorithm as the one used currently by the ASIC to the seed, and return
584 * both hashes in the lower and higher word of the return value since only 12 bit of
585 * the hash are significant.
586 */
587 static u32 rtl931x_l2_hash_key(struct rtl838x_switch_priv *priv, u64 seed)
588 {
589 u32 h, h0, h1, h2, h3, h4, k0, k1;
590
591 h0 = seed & 0xfff;
592 h1 = (seed >> 12) & 0xfff;
593 h2 = (seed >> 24) & 0xfff;
594 h3 = (seed >> 36) & 0xfff;
595 h4 = (seed >> 48) & 0xfff;
596 h4 = ((h4 & 0x7) << 9) | ((h4 >> 3) & 0x1ff);
597 k0 = h0 ^ h1 ^ h2 ^ h3 ^ h4;
598
599 h0 = seed & 0xfff;
600 h0 = ((h0 & 0x1ff) << 3) | ((h0 >> 9) & 0x7);
601 h1 = (seed >> 12) & 0xfff;
602 h1 = ((h1 & 0x3f) << 6) | ((h1 >> 6) & 0x3f);
603 h2 = (seed >> 24) & 0xfff;
604 h3 = (seed >> 36) & 0xfff;
605 h3 = ((h3 & 0x3f) << 6) | ((h3 >> 6) & 0x3f);
606 h4 = (seed >> 48) & 0xfff;
607 k1 = h0 ^ h1 ^ h2 ^ h3 ^ h4;
608
609 /* Algorithm choice for block 0 */
610 if (sw_r32(RTL931X_L2_CTRL) & BIT(0))
611 h = k1;
612 else
613 h = k0;
614
615 /* Algorithm choice for block 1
616 * Since k0 and k1 are < 4096, adding 4096 will offset the hash into the second
617 * half of hash-space
618 * 4096 is in fact the hash-table size 32768 divided by 4 hashes per bucket
619 * divided by 2 to divide the hash space in 2
620 */
621 if (sw_r32(RTL931X_L2_CTRL) & BIT(1))
622 h |= (k1 + 4096) << 16;
623 else
624 h |= (k0 + 4096) << 16;
625
626 return h;
627 }
628
629 /* Fills an L2 entry structure from the SoC registers */
630 static void rtl931x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e)
631 {
632 pr_debug("In %s valid?\n", __func__);
633 e->valid = !!(r[0] & BIT(31));
634 if (!e->valid)
635 return;
636
637 pr_debug("%s: entry valid, raw: %08x %08x %08x %08x\n", __func__, r[0], r[1], r[2], r[3]);
638 e->is_ip_mc = false;
639 e->is_ipv6_mc = false;
640
641 e->mac[0] = r[0] >> 8;
642 e->mac[1] = r[0];
643 e->mac[2] = r[1] >> 24;
644 e->mac[3] = r[1] >> 16;
645 e->mac[4] = r[1] >> 8;
646 e->mac[5] = r[1];
647
648 e->is_open_flow = !!(r[0] & BIT(30));
649 e->is_pe_forward = !!(r[0] & BIT(29));
650 e->next_hop = !!(r[2] & BIT(30));
651 e->rvid = (r[0] >> 16) & 0xfff;
652
653 /* Is it a unicast entry? check multicast bit */
654 if (!(e->mac[0] & 1)) {
655 e->type = L2_UNICAST;
656 e->is_l2_tunnel = !!(r[2] & BIT(31));
657 e->is_static = !!(r[2] & BIT(13));
658 e->port = (r[2] >> 19) & 0x3ff;
659 /* Check for trunk port */
660 if (r[2] & BIT(29)) {
661 e->is_trunk = true;
662 e->stack_dev = (e->port >> 9) & 1;
663 e->trunk = e->port & 0x3f;
664 } else {
665 e->is_trunk = false;
666 e->stack_dev = (e->port >> 6) & 0xf;
667 e->port = e->port & 0x3f;
668 }
669
670 e->block_da = !!(r[2] & BIT(14));
671 e->block_sa = !!(r[2] & BIT(15));
672 e->suspended = !!(r[2] & BIT(12));
673 e->age = (r[2] >> 16) & 3;
674
675 /* the UC_VID field in hardware is used for the VID or for the route id */
676 if (e->next_hop) {
677 e->nh_route_id = r[2] & 0x7ff;
678 e->vid = 0;
679 } else {
680 e->vid = r[2] & 0xfff;
681 e->nh_route_id = 0;
682 }
683 if (e->is_l2_tunnel)
684 e->l2_tunnel_id = ((r[2] & 0xff) << 4) | (r[3] >> 28);
685 /* TODO: Implement VLAN conversion */
686 } else {
687 e->type = L2_MULTICAST;
688 e->is_local_forward = !!(r[2] & BIT(31));
689 e->is_remote_forward = !!(r[2] & BIT(17));
690 e->mc_portmask_index = (r[2] >> 18) & 0xfff;
691 e->l2_tunnel_list_id = (r[2] >> 4) & 0x1fff;
692 }
693 }
694
695 /* Fills the 3 SoC table registers r[] with the information of in the rtl838x_l2_entry */
696 static void rtl931x_fill_l2_row(u32 r[], struct rtl838x_l2_entry *e)
697 {
698 u32 port;
699
700 if (!e->valid) {
701 r[0] = r[1] = r[2] = 0;
702 return;
703 }
704
705 r[2] = BIT(31); /* Set valid bit */
706
707 r[0] = ((u32)e->mac[0]) << 24 |
708 ((u32)e->mac[1]) << 16 |
709 ((u32)e->mac[2]) << 8 |
710 ((u32)e->mac[3]);
711 r[1] = ((u32)e->mac[4]) << 24 |
712 ((u32)e->mac[5]) << 16;
713
714 r[2] |= e->next_hop ? BIT(12) : 0;
715
716 if (e->type == L2_UNICAST) {
717 r[2] |= e->is_static ? BIT(14) : 0;
718 r[1] |= e->rvid & 0xfff;
719 r[2] |= (e->port & 0x3ff) << 20;
720 if (e->is_trunk) {
721 r[2] |= BIT(30);
722 port = e->stack_dev << 9 | (e->port & 0x3f);
723 } else {
724 port = (e->stack_dev & 0xf) << 6;
725 port |= e->port & 0x3f;
726 }
727 r[2] |= port << 20;
728 r[2] |= e->block_da ? BIT(15) : 0;
729 r[2] |= e->block_sa ? BIT(17) : 0;
730 r[2] |= e->suspended ? BIT(13) : 0;
731 r[2] |= (e->age & 0x3) << 17;
732 /* the UC_VID field in hardware is used for the VID or for the route id */
733 if (e->next_hop)
734 r[2] |= e->nh_route_id & 0x7ff;
735 else
736 r[2] |= e->vid & 0xfff;
737 } else { /* L2_MULTICAST */
738 r[2] |= (e->mc_portmask_index & 0x3ff) << 16;
739 r[2] |= e->mc_mac_index & 0x7ff;
740 }
741 }
742
743 /* Read an L2 UC or MC entry out of a hash bucket of the L2 forwarding table
744 * hash is the id of the bucket and pos is the position of the entry in that bucket
745 * The data read from the SoC is filled into rtl838x_l2_entry
746 */
747 static u64 rtl931x_read_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e)
748 {
749 u32 r[4];
750 struct table_reg *q = rtl_table_get(RTL9310_TBL_0, 0);
751 u32 idx;
752 u64 mac;
753 u64 seed;
754
755 pr_debug("%s: hash %08x, pos: %d\n", __func__, hash, pos);
756
757 /* On the RTL93xx, 2 different hash algorithms are used making it a total of
758 * 8 buckets that need to be searched, 4 for each hash-half
759 * Use second hash space when bucket is between 4 and 8
760 */
761 if (pos >= 4) {
762 pos -= 4;
763 hash >>= 16;
764 } else {
765 hash &= 0xffff;
766 }
767
768 idx = (0 << 14) | (hash << 2) | pos; /* Search SRAM, with hash and at pos in bucket */
769 pr_debug("%s: NOW hash %08x, pos: %d\n", __func__, hash, pos);
770
771 rtl_table_read(q, idx);
772 for (int i = 0; i < 4; i++)
773 r[i] = sw_r32(rtl_table_data(q, i));
774
775 rtl_table_release(q);
776
777 rtl931x_fill_l2_entry(r, e);
778
779 pr_debug("%s: valid: %d, nh: %d\n", __func__, e->valid, e->next_hop);
780 if (!e->valid)
781 return 0;
782
783 mac = ((u64)e->mac[0]) << 40 |
784 ((u64)e->mac[1]) << 32 |
785 ((u64)e->mac[2]) << 24 |
786 ((u64)e->mac[3]) << 16 |
787 ((u64)e->mac[4]) << 8 |
788 ((u64)e->mac[5]);
789
790 seed = rtl931x_l2_hash_seed(mac, e->rvid);
791 pr_debug("%s: mac %016llx, seed %016llx\n", __func__, mac, seed);
792
793 /* return vid with concatenated mac as unique id */
794 return seed;
795 }
796
797 static u64 rtl931x_read_cam(int idx, struct rtl838x_l2_entry *e)
798 {
799 return 0;
800 }
801
802 static void rtl931x_write_cam(int idx, struct rtl838x_l2_entry *e)
803 {
804 }
805
806 static void rtl931x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e)
807 {
808 u32 r[4];
809 struct table_reg *q = rtl_table_get(RTL9310_TBL_0, 0);
810 u32 idx = (0 << 14) | (hash << 2) | pos; /* Access SRAM, with hash and at pos in bucket */
811
812 pr_info("%s: hash %d, pos %d\n", __func__, hash, pos);
813 pr_info("%s: index %d -> mac %02x:%02x:%02x:%02x:%02x:%02x\n", __func__, idx,
814 e->mac[0], e->mac[1], e->mac[2], e->mac[3],e->mac[4],e->mac[5]);
815
816 rtl931x_fill_l2_row(r, e);
817 pr_info("%s: %d: %08x %08x %08x\n", __func__, idx, r[0], r[1], r[2]);
818
819 for (int i = 0; i < 4; i++)
820 sw_w32(r[i], rtl_table_data(q, i));
821
822 rtl_table_write(q, idx);
823 rtl_table_release(q);
824 }
825
826 static void rtl931x_vlan_fwd_on_inner(int port, bool is_set)
827 {
828 /* Always set all tag modes to fwd based on either inner or outer tag */
829 if (is_set)
830 sw_w32_mask(0, 0xf, RTL931X_VLAN_PORT_FWD + (port << 2));
831 else
832 sw_w32_mask(0xf, 0, RTL931X_VLAN_PORT_FWD + (port << 2));
833 }
834
835 static void rtl931x_vlan_profile_setup(int profile)
836 {
837 u32 p[7];
838
839 pr_info("In %s\n", __func__);
840
841 if (profile > 15)
842 return;
843
844 p[0] = sw_r32(RTL931X_VLAN_PROFILE_SET(profile));
845
846 /* Enable routing of Ipv4/6 Unicast and IPv4/6 Multicast traffic */
847 /* p[0] |= BIT(17) | BIT(16) | BIT(13) | BIT(12); */
848 p[0] |= 0x3 << 11; /* COPY2CPU */
849
850 p[1] = 0x1FFFFFF; /* L2 unknwon MC flooding portmask all ports, including the CPU-port */
851 p[2] = 0xFFFFFFFF;
852 p[3] = 0x1FFFFFF; /* IPv4 unknwon MC flooding portmask */
853 p[4] = 0xFFFFFFFF;
854 p[5] = 0x1FFFFFF; /* IPv6 unknwon MC flooding portmask */
855 p[6] = 0xFFFFFFFF;
856
857 for (int i = 0; i < 7; i++)
858 sw_w32(p[i], RTL931X_VLAN_PROFILE_SET(profile) + i * 4);
859 pr_info("Leaving %s\n", __func__);
860 }
861
862 static void rtl931x_l2_learning_setup(void)
863 {
864 /* Portmask for flooding broadcast traffic */
865 rtl839x_set_port_reg_be(0x1FFFFFFFFFFFFFF, RTL931X_L2_BC_FLD_PMSK);
866
867 /* Portmask for flooding unicast traffic with unknown destination */
868 rtl839x_set_port_reg_be(0x1FFFFFFFFFFFFFF, RTL931X_L2_UNKN_UC_FLD_PMSK);
869
870 /* Limit learning to maximum: 64k entries, after that just flood (bits 0-2) */
871 sw_w32((0xffff << 3) | FORWARD, RTL931X_L2_LRN_CONSTRT_CTRL);
872 }
873
874 static u64 rtl931x_read_mcast_pmask(int idx)
875 {
876 u64 portmask;
877 /* Read MC_PMSK (2) via register RTL9310_TBL_0 */
878 struct table_reg *q = rtl_table_get(RTL9310_TBL_0, 2);
879
880 rtl_table_read(q, idx);
881 portmask = sw_r32(rtl_table_data(q, 0));
882 portmask <<= 32;
883 portmask |= sw_r32(rtl_table_data(q, 1));
884 portmask >>= 7;
885 rtl_table_release(q);
886
887 pr_debug("%s: Index idx %d has portmask %016llx\n", __func__, idx, portmask);
888
889 return portmask;
890 }
891
892 static void rtl931x_write_mcast_pmask(int idx, u64 portmask)
893 {
894 u64 pm = portmask;
895
896 /* Access MC_PMSK (2) via register RTL9310_TBL_0 */
897 struct table_reg *q = rtl_table_get(RTL9310_TBL_0, 2);
898
899 pr_debug("%s: Index idx %d has portmask %016llx\n", __func__, idx, pm);
900 pm <<= 7;
901 sw_w32((u32)(pm >> 32), rtl_table_data(q, 0));
902 sw_w32((u32)pm, rtl_table_data(q, 1));
903 rtl_table_write(q, idx);
904 rtl_table_release(q);
905 }
906
907
908 static int rtl931x_set_ageing_time(unsigned long msec)
909 {
910 int t = sw_r32(RTL931X_L2_AGE_CTRL);
911
912 t &= 0x1FFFFF;
913 t = (t * 8) / 10;
914 pr_debug("L2 AGING time: %d sec\n", t);
915
916 t = (msec / 100 + 7) / 8;
917 t = t > 0x1FFFFF ? 0x1FFFFF : t;
918 sw_w32_mask(0x1FFFFF, t, RTL931X_L2_AGE_CTRL);
919 pr_debug("Dynamic aging for ports: %x\n", sw_r32(RTL931X_L2_PORT_AGE_CTRL));
920
921 return 0;
922 }
923 void rtl931x_sw_init(struct rtl838x_switch_priv *priv)
924 {
925 /* rtl931x_sds_init(priv); */
926 }
927
928 static void rtl931x_pie_lookup_enable(struct rtl838x_switch_priv *priv, int index)
929 {
930 int block = index / PIE_BLOCK_SIZE;
931
932 sw_w32_mask(0, BIT(block), RTL931X_PIE_BLK_LOOKUP_CTRL);
933 }
934
935 /* Fills the data in the intermediate representation in the pie_rule structure
936 * into a data field for a given template field field_type
937 * TODO: This function looks very similar to the function of the rtl9300, but
938 * since it uses the physical template_field_id, which are different for each
939 * SoC and there are other field types, it is actually not. If we would also use
940 * an intermediate representation for a field type, we would could have one
941 * pie_data_fill function for all SoCs, provided we have also for each SoC a
942 * function to map between physical and intermediate field type
943 */
944 int rtl931x_pie_data_fill(enum template_field_id field_type, struct pie_rule *pr, u16 *data, u16 *data_m)
945 {
946 *data = *data_m = 0;
947
948 switch (field_type) {
949 case TEMPLATE_FIELD_SPM0:
950 *data = pr->spm;
951 *data_m = pr->spm_m;
952 break;
953 case TEMPLATE_FIELD_SPM1:
954 *data = pr->spm >> 16;
955 *data_m = pr->spm_m >> 16;
956 break;
957 case TEMPLATE_FIELD_OTAG:
958 *data = pr->otag;
959 *data_m = pr->otag_m;
960 break;
961 case TEMPLATE_FIELD_SMAC0:
962 *data = pr->smac[4];
963 *data = (*data << 8) | pr->smac[5];
964 *data_m = pr->smac_m[4];
965 *data_m = (*data_m << 8) | pr->smac_m[5];
966 break;
967 case TEMPLATE_FIELD_SMAC1:
968 *data = pr->smac[2];
969 *data = (*data << 8) | pr->smac[3];
970 *data_m = pr->smac_m[2];
971 *data_m = (*data_m << 8) | pr->smac_m[3];
972 break;
973 case TEMPLATE_FIELD_SMAC2:
974 *data = pr->smac[0];
975 *data = (*data << 8) | pr->smac[1];
976 *data_m = pr->smac_m[0];
977 *data_m = (*data_m << 8) | pr->smac_m[1];
978 break;
979 case TEMPLATE_FIELD_DMAC0:
980 *data = pr->dmac[4];
981 *data = (*data << 8) | pr->dmac[5];
982 *data_m = pr->dmac_m[4];
983 *data_m = (*data_m << 8) | pr->dmac_m[5];
984 break;
985 case TEMPLATE_FIELD_DMAC1:
986 *data = pr->dmac[2];
987 *data = (*data << 8) | pr->dmac[3];
988 *data_m = pr->dmac_m[2];
989 *data_m = (*data_m << 8) | pr->dmac_m[3];
990 break;
991 case TEMPLATE_FIELD_DMAC2:
992 *data = pr->dmac[0];
993 *data = (*data << 8) | pr->dmac[1];
994 *data_m = pr->dmac_m[0];
995 *data_m = (*data_m << 8) | pr->dmac_m[1];
996 break;
997 case TEMPLATE_FIELD_ETHERTYPE:
998 *data = pr->ethertype;
999 *data_m = pr->ethertype_m;
1000 break;
1001 case TEMPLATE_FIELD_ITAG:
1002 *data = pr->itag;
1003 *data_m = pr->itag_m;
1004 break;
1005 case TEMPLATE_FIELD_SIP0:
1006 if (pr->is_ipv6) {
1007 *data = pr->sip6.s6_addr16[7];
1008 *data_m = pr->sip6_m.s6_addr16[7];
1009 } else {
1010 *data = pr->sip;
1011 *data_m = pr->sip_m;
1012 }
1013 break;
1014 case TEMPLATE_FIELD_SIP1:
1015 if (pr->is_ipv6) {
1016 *data = pr->sip6.s6_addr16[6];
1017 *data_m = pr->sip6_m.s6_addr16[6];
1018 } else {
1019 *data = pr->sip >> 16;
1020 *data_m = pr->sip_m >> 16;
1021 }
1022 break;
1023 case TEMPLATE_FIELD_SIP2:
1024 case TEMPLATE_FIELD_SIP3:
1025 case TEMPLATE_FIELD_SIP4:
1026 case TEMPLATE_FIELD_SIP5:
1027 case TEMPLATE_FIELD_SIP6:
1028 case TEMPLATE_FIELD_SIP7:
1029 *data = pr->sip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)];
1030 *data_m = pr->sip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)];
1031 break;
1032 case TEMPLATE_FIELD_DIP0:
1033 if (pr->is_ipv6) {
1034 *data = pr->dip6.s6_addr16[7];
1035 *data_m = pr->dip6_m.s6_addr16[7];
1036 } else {
1037 *data = pr->dip;
1038 *data_m = pr->dip_m;
1039 }
1040 break;
1041 case TEMPLATE_FIELD_DIP1:
1042 if (pr->is_ipv6) {
1043 *data = pr->dip6.s6_addr16[6];
1044 *data_m = pr->dip6_m.s6_addr16[6];
1045 } else {
1046 *data = pr->dip >> 16;
1047 *data_m = pr->dip_m >> 16;
1048 }
1049 break;
1050 case TEMPLATE_FIELD_DIP2:
1051 case TEMPLATE_FIELD_DIP3:
1052 case TEMPLATE_FIELD_DIP4:
1053 case TEMPLATE_FIELD_DIP5:
1054 case TEMPLATE_FIELD_DIP6:
1055 case TEMPLATE_FIELD_DIP7:
1056 *data = pr->dip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)];
1057 *data_m = pr->dip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)];
1058 break;
1059 case TEMPLATE_FIELD_IP_TOS_PROTO:
1060 *data = pr->tos_proto;
1061 *data_m = pr->tos_proto_m;
1062 break;
1063 case TEMPLATE_FIELD_L4_SPORT:
1064 *data = pr->sport;
1065 *data_m = pr->sport_m;
1066 break;
1067 case TEMPLATE_FIELD_L4_DPORT:
1068 *data = pr->dport;
1069 *data_m = pr->dport_m;
1070 break;
1071 case TEMPLATE_FIELD_DSAP_SSAP:
1072 *data = pr->dsap_ssap;
1073 *data_m = pr->dsap_ssap_m;
1074 break;
1075 case TEMPLATE_FIELD_TCP_INFO:
1076 *data = pr->tcp_info;
1077 *data_m = pr->tcp_info_m;
1078 break;
1079 case TEMPLATE_FIELD_RANGE_CHK:
1080 pr_info("TEMPLATE_FIELD_RANGE_CHK: not configured\n");
1081 break;
1082 default:
1083 pr_info("%s: unknown field %d\n", __func__, field_type);
1084 return -1;
1085 }
1086
1087 return 0;
1088 }
1089
1090 /* Reads the intermediate representation of the templated match-fields of the
1091 * PIE rule in the pie_rule structure and fills in the raw data fields in the
1092 * raw register space r[].
1093 * The register space configuration size is identical for the RTL8380/90 and RTL9300,
1094 * however the RTL931X has 2 more registers / fields and the physical field-ids are different
1095 * on all SoCs
1096 * On the RTL9300 the mask fields are not word-aligend!
1097 */
1098 static void rtl931x_write_pie_templated(u32 r[], struct pie_rule *pr, enum template_field_id t[])
1099 {
1100 for (int i = 0; i < N_FIXED_FIELDS; i++) {
1101 u16 data, data_m;
1102
1103 rtl931x_pie_data_fill(t[i], pr, &data, &data_m);
1104
1105 /* On the RTL9300, the mask fields are not word aligned! */
1106 if (!(i % 2)) {
1107 r[5 - i / 2] = data;
1108 r[12 - i / 2] |= ((u32)data_m << 8);
1109 } else {
1110 r[5 - i / 2] |= ((u32)data) << 16;
1111 r[12 - i / 2] |= ((u32)data_m) << 24;
1112 r[11 - i / 2] |= ((u32)data_m) >> 8;
1113 }
1114 }
1115 }
1116
1117 // Currently unused
1118 // static void rtl931x_read_pie_fixed_fields(u32 r[], struct pie_rule *pr)
1119 // {
1120 // pr->mgnt_vlan = r[7] & BIT(31);
1121 // if (pr->phase == PHASE_IACL)
1122 // pr->dmac_hit_sw = r[7] & BIT(30);
1123 // else /* TODO: EACL/VACL phase handling */
1124 // pr->content_too_deep = r[7] & BIT(30);
1125 // pr->not_first_frag = r[7] & BIT(29);
1126 // pr->frame_type_l4 = (r[7] >> 26) & 7;
1127 // pr->frame_type = (r[7] >> 24) & 3;
1128 // pr->otag_fmt = (r[7] >> 23) & 1;
1129 // pr->itag_fmt = (r[7] >> 22) & 1;
1130 // pr->otag_exist = (r[7] >> 21) & 1;
1131 // pr->itag_exist = (r[7] >> 20) & 1;
1132 // pr->frame_type_l2 = (r[7] >> 18) & 3;
1133 // pr->igr_normal_port = (r[7] >> 17) & 1;
1134 // pr->tid = (r[7] >> 16) & 1;
1135
1136 // pr->mgnt_vlan_m = r[14] & BIT(15);
1137 // if (pr->phase == PHASE_IACL)
1138 // pr->dmac_hit_sw_m = r[14] & BIT(14);
1139 // else
1140 // pr->content_too_deep_m = r[14] & BIT(14);
1141 // pr->not_first_frag_m = r[14] & BIT(13);
1142 // pr->frame_type_l4_m = (r[14] >> 10) & 7;
1143 // pr->frame_type_m = (r[14] >> 8) & 3;
1144 // pr->otag_fmt_m = r[14] & BIT(7);
1145 // pr->itag_fmt_m = r[14] & BIT(6);
1146 // pr->otag_exist_m = r[14] & BIT(5);
1147 // pr->itag_exist_m = r[14] & BIT (4);
1148 // pr->frame_type_l2_m = (r[14] >> 2) & 3;
1149 // pr->igr_normal_port_m = r[14] & BIT(1);
1150 // pr->tid_m = r[14] & 1;
1151
1152 // pr->valid = r[15] & BIT(31);
1153 // pr->cond_not = r[15] & BIT(30);
1154 // pr->cond_and1 = r[15] & BIT(29);
1155 // pr->cond_and2 = r[15] & BIT(28);
1156 // }
1157
1158 static void rtl931x_write_pie_fixed_fields(u32 r[], struct pie_rule *pr)
1159 {
1160 r[7] |= pr->mgnt_vlan ? BIT(31) : 0;
1161 if (pr->phase == PHASE_IACL)
1162 r[7] |= pr->dmac_hit_sw ? BIT(30) : 0;
1163 else
1164 r[7] |= pr->content_too_deep ? BIT(30) : 0;
1165 r[7] |= pr->not_first_frag ? BIT(29) : 0;
1166 r[7] |= ((u32) (pr->frame_type_l4 & 0x7)) << 26;
1167 r[7] |= ((u32) (pr->frame_type & 0x3)) << 24;
1168 r[7] |= pr->otag_fmt ? BIT(23) : 0;
1169 r[7] |= pr->itag_fmt ? BIT(22) : 0;
1170 r[7] |= pr->otag_exist ? BIT(21) : 0;
1171 r[7] |= pr->itag_exist ? BIT(20) : 0;
1172 r[7] |= ((u32) (pr->frame_type_l2 & 0x3)) << 18;
1173 r[7] |= pr->igr_normal_port ? BIT(17) : 0;
1174 r[7] |= ((u32) (pr->tid & 0x1)) << 16;
1175
1176 r[14] |= pr->mgnt_vlan_m ? BIT(15) : 0;
1177 if (pr->phase == PHASE_IACL)
1178 r[14] |= pr->dmac_hit_sw_m ? BIT(14) : 0;
1179 else
1180 r[14] |= pr->content_too_deep_m ? BIT(14) : 0;
1181 r[14] |= pr->not_first_frag_m ? BIT(13) : 0;
1182 r[14] |= ((u32) (pr->frame_type_l4_m & 0x7)) << 10;
1183 r[14] |= ((u32) (pr->frame_type_m & 0x3)) << 8;
1184 r[14] |= pr->otag_fmt_m ? BIT(7) : 0;
1185 r[14] |= pr->itag_fmt_m ? BIT(6) : 0;
1186 r[14] |= pr->otag_exist_m ? BIT(5) : 0;
1187 r[14] |= pr->itag_exist_m ? BIT(4) : 0;
1188 r[14] |= ((u32) (pr->frame_type_l2_m & 0x3)) << 2;
1189 r[14] |= pr->igr_normal_port_m ? BIT(1) : 0;
1190 r[14] |= (u32) (pr->tid_m & 0x1);
1191
1192 r[15] |= pr->valid ? BIT(31) : 0;
1193 r[15] |= pr->cond_not ? BIT(30) : 0;
1194 r[15] |= pr->cond_and1 ? BIT(29) : 0;
1195 r[15] |= pr->cond_and2 ? BIT(28) : 0;
1196 }
1197
1198 static void rtl931x_write_pie_action(u32 r[], struct pie_rule *pr)
1199 {
1200 /* Either drop or forward */
1201 if (pr->drop) {
1202 r[15] |= BIT(11) | BIT(12) | BIT(13); /* Do Green, Yellow and Red drops */
1203 /* Actually DROP, not PERMIT in Green / Yellow / Red */
1204 r[16] |= BIT(27) | BIT(28) | BIT(29);
1205 } else {
1206 r[15] |= pr->fwd_sel ? BIT(14) : 0;
1207 r[16] |= pr->fwd_act << 24;
1208 r[16] |= BIT(21); /* We overwrite any drop */
1209 }
1210 if (pr->phase == PHASE_VACL)
1211 r[16] |= pr->fwd_sa_lrn ? BIT(22) : 0;
1212 r[15] |= pr->bypass_sel ? BIT(10) : 0;
1213 r[15] |= pr->nopri_sel ? BIT(21) : 0;
1214 r[15] |= pr->tagst_sel ? BIT(20) : 0;
1215 r[15] |= pr->ovid_sel ? BIT(18) : 0;
1216 r[15] |= pr->ivid_sel ? BIT(16) : 0;
1217 r[15] |= pr->meter_sel ? BIT(27) : 0;
1218 r[15] |= pr->mir_sel ? BIT(15) : 0;
1219 r[15] |= pr->log_sel ? BIT(26) : 0;
1220
1221 r[16] |= ((u32)(pr->fwd_data & 0xfff)) << 9;
1222 /* r[15] |= pr->log_octets ? BIT(31) : 0; */
1223 r[15] |= (u32)(pr->meter_data) >> 2;
1224 r[16] |= (((u32)(pr->meter_data) >> 7) & 0x3) << 29;
1225
1226 r[16] |= ((u32)(pr->ivid_act & 0x3)) << 21;
1227 r[15] |= ((u32)(pr->ivid_data & 0xfff)) << 9;
1228 r[16] |= ((u32)(pr->ovid_act & 0x3)) << 30;
1229 r[16] |= ((u32)(pr->ovid_data & 0xfff)) << 16;
1230 r[16] |= ((u32)(pr->mir_data & 0x3)) << 6;
1231 r[17] |= ((u32)(pr->tagst_data & 0xf)) << 28;
1232 r[17] |= ((u32)(pr->nopri_data & 0x7)) << 25;
1233 r[17] |= pr->bypass_ibc_sc ? BIT(16) : 0;
1234 }
1235
1236 void rtl931x_pie_rule_dump_raw(u32 r[])
1237 {
1238 pr_info("Raw IACL table entry:\n");
1239 pr_info("r 0 - 7: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1240 r[0], r[1], r[2], r[3], r[4], r[5], r[6], r[7]);
1241 pr_info("r 8 - 15: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1242 r[8], r[9], r[10], r[11], r[12], r[13], r[14], r[15]);
1243 pr_info("r 16 - 18: %08x %08x %08x\n", r[16], r[17], r[18]);
1244 pr_info("Match : %08x %08x %08x %08x %08x %08x\n", r[0], r[1], r[2], r[3], r[4], r[5]);
1245 pr_info("Fixed : %06x\n", r[6] >> 8);
1246 pr_info("Match M: %08x %08x %08x %08x %08x %08x\n",
1247 (r[6] << 24) | (r[7] >> 8), (r[7] << 24) | (r[8] >> 8), (r[8] << 24) | (r[9] >> 8),
1248 (r[9] << 24) | (r[10] >> 8), (r[10] << 24) | (r[11] >> 8),
1249 (r[11] << 24) | (r[12] >> 8));
1250 pr_info("R[13]: %08x\n", r[13]);
1251 pr_info("Fixed M: %06x\n", ((r[12] << 16) | (r[13] >> 16)) & 0xffffff);
1252 pr_info("Valid / not / and1 / and2 : %1x\n", (r[13] >> 12) & 0xf);
1253 pr_info("r 13-16: %08x %08x %08x %08x\n", r[13], r[14], r[15], r[16]);
1254 }
1255
1256 static int rtl931x_pie_rule_write(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr)
1257 {
1258 /* Access IACL table (0) via register 1, the table size is 4096 */
1259 struct table_reg *q = rtl_table_get(RTL9310_TBL_1, 0);
1260 u32 r[22];
1261 int block = idx / PIE_BLOCK_SIZE;
1262 u32 t_select = sw_r32(RTL931X_PIE_BLK_TMPLTE_CTRL(block));
1263
1264 pr_info("%s: %d, t_select: %08x\n", __func__, idx, t_select);
1265
1266 for (int i = 0; i < 22; i++)
1267 r[i] = 0;
1268
1269 if (!pr->valid) {
1270 rtl_table_write(q, idx);
1271 rtl_table_release(q);
1272 return 0;
1273 }
1274 rtl931x_write_pie_fixed_fields(r, pr);
1275
1276 pr_info("%s: template %d\n", __func__, (t_select >> (pr->tid * 4)) & 0xf);
1277 rtl931x_write_pie_templated(r, pr, fixed_templates[(t_select >> (pr->tid * 4)) & 0xf]);
1278
1279 rtl931x_write_pie_action(r, pr);
1280
1281 rtl931x_pie_rule_dump_raw(r);
1282
1283 for (int i = 0; i < 22; i++)
1284 sw_w32(r[i], rtl_table_data(q, i));
1285
1286 rtl_table_write(q, idx);
1287 rtl_table_release(q);
1288
1289 return 0;
1290 }
1291
1292 static bool rtl931x_pie_templ_has(int t, enum template_field_id field_type)
1293 {
1294 for (int i = 0; i < N_FIXED_FIELDS_RTL931X; i++) {
1295 enum template_field_id ft = fixed_templates[t][i];
1296 if (field_type == ft)
1297 return true;
1298 }
1299
1300 return false;
1301 }
1302
1303 /* Verify that the rule pr is compatible with a given template t in block block
1304 * Note that this function is SoC specific since the values of e.g. TEMPLATE_FIELD_SIP0
1305 * depend on the SoC
1306 */
1307 static int rtl931x_pie_verify_template(struct rtl838x_switch_priv *priv,
1308 struct pie_rule *pr, int t, int block)
1309 {
1310 int i;
1311
1312 if (!pr->is_ipv6 && pr->sip_m && !rtl931x_pie_templ_has(t, TEMPLATE_FIELD_SIP0))
1313 return -1;
1314
1315 if (!pr->is_ipv6 && pr->dip_m && !rtl931x_pie_templ_has(t, TEMPLATE_FIELD_DIP0))
1316 return -1;
1317
1318 if (pr->is_ipv6) {
1319 if ((pr->sip6_m.s6_addr32[0] ||
1320 pr->sip6_m.s6_addr32[1] ||
1321 pr->sip6_m.s6_addr32[2] ||
1322 pr->sip6_m.s6_addr32[3]) &&
1323 !rtl931x_pie_templ_has(t, TEMPLATE_FIELD_SIP2))
1324 return -1;
1325 if ((pr->dip6_m.s6_addr32[0] ||
1326 pr->dip6_m.s6_addr32[1] ||
1327 pr->dip6_m.s6_addr32[2] ||
1328 pr->dip6_m.s6_addr32[3]) &&
1329 !rtl931x_pie_templ_has(t, TEMPLATE_FIELD_DIP2))
1330 return -1;
1331 }
1332
1333 if (ether_addr_to_u64(pr->smac) && !rtl931x_pie_templ_has(t, TEMPLATE_FIELD_SMAC0))
1334 return -1;
1335
1336 if (ether_addr_to_u64(pr->dmac) && !rtl931x_pie_templ_has(t, TEMPLATE_FIELD_DMAC0))
1337 return -1;
1338
1339 /* TODO: Check more */
1340
1341 i = find_first_zero_bit(&priv->pie_use_bm[block * 4], PIE_BLOCK_SIZE);
1342
1343 if (i >= PIE_BLOCK_SIZE)
1344 return -1;
1345
1346 return i + PIE_BLOCK_SIZE * block;
1347 }
1348
1349 static int rtl931x_pie_rule_add(struct rtl838x_switch_priv *priv, struct pie_rule *pr)
1350 {
1351 int idx, block, j;
1352 int min_block = 0;
1353 int max_block = priv->n_pie_blocks / 2;
1354
1355 if (pr->is_egress) {
1356 min_block = max_block;
1357 max_block = priv->n_pie_blocks;
1358 }
1359 pr_info("In %s\n", __func__);
1360
1361 mutex_lock(&priv->pie_mutex);
1362
1363 for (block = min_block; block < max_block; block++) {
1364 for (j = 0; j < 2; j++) {
1365 int t = (sw_r32(RTL931X_PIE_BLK_TMPLTE_CTRL(block)) >> (j * 4)) & 0xf;
1366 pr_info("Testing block %d, template %d, template id %d\n", block, j, t);
1367 pr_info("%s: %08x\n",
1368 __func__, sw_r32(RTL931X_PIE_BLK_TMPLTE_CTRL(block)));
1369 idx = rtl931x_pie_verify_template(priv, pr, t, block);
1370 if (idx >= 0)
1371 break;
1372 }
1373 if (j < 2)
1374 break;
1375 }
1376
1377 if (block >= priv->n_pie_blocks) {
1378 mutex_unlock(&priv->pie_mutex);
1379 return -EOPNOTSUPP;
1380 }
1381
1382 pr_info("Using block: %d, index %d, template-id %d\n", block, idx, j);
1383 set_bit(idx, priv->pie_use_bm);
1384
1385 pr->valid = true;
1386 pr->tid = j; /* Mapped to template number */
1387 pr->tid_m = 0x1;
1388 pr->id = idx;
1389
1390 rtl931x_pie_lookup_enable(priv, idx);
1391 rtl931x_pie_rule_write(priv, idx, pr);
1392
1393 mutex_unlock(&priv->pie_mutex);
1394
1395 return 0;
1396 }
1397
1398 /* Delete a range of Packet Inspection Engine rules */
1399 static int rtl931x_pie_rule_del(struct rtl838x_switch_priv *priv, int index_from, int index_to)
1400 {
1401 u32 v = (index_from << 1)| (index_to << 13 ) | BIT(0);
1402
1403 pr_info("%s: from %d to %d\n", __func__, index_from, index_to);
1404 mutex_lock(&priv->reg_mutex);
1405
1406 /* Write from-to and execute bit into control register */
1407 sw_w32(v, RTL931X_PIE_CLR_CTRL);
1408
1409 /* Wait until command has completed */
1410 do {
1411 } while (sw_r32(RTL931X_PIE_CLR_CTRL) & BIT(0));
1412
1413 mutex_unlock(&priv->reg_mutex);
1414
1415 return 0;
1416 }
1417
1418 static void rtl931x_pie_rule_rm(struct rtl838x_switch_priv *priv, struct pie_rule *pr)
1419 {
1420 int idx = pr->id;
1421
1422 rtl931x_pie_rule_del(priv, idx, idx);
1423 clear_bit(idx, priv->pie_use_bm);
1424 }
1425
1426 static void rtl931x_pie_init(struct rtl838x_switch_priv *priv)
1427 {
1428 u32 template_selectors;
1429
1430 mutex_init(&priv->pie_mutex);
1431
1432 pr_info("%s\n", __func__);
1433 /* Enable ACL lookup on all ports, including CPU_PORT */
1434 for (int i = 0; i <= priv->cpu_port; i++)
1435 sw_w32(1, RTL931X_ACL_PORT_LOOKUP_CTRL(i));
1436
1437 /* Include IPG in metering */
1438 sw_w32_mask(0, 1, RTL931X_METER_GLB_CTRL);
1439
1440 /* Delete all present rules, block size is 128 on all SoC families */
1441 rtl931x_pie_rule_del(priv, 0, priv->n_pie_blocks * 128 - 1);
1442
1443 /* Assign first half blocks 0-7 to VACL phase, second half to IACL */
1444 /* 3 bits are used for each block, values for PIE blocks are */
1445 /* 6: Disabled, 0: VACL, 1: IACL, 2: EACL */
1446 /* And for OpenFlow Flow blocks: 3: Ingress Flow table 0, */
1447 /* 4: Ingress Flow Table 3, 5: Egress flow table 0 */
1448 for (int i = 0; i < priv->n_pie_blocks; i++) {
1449 int pos = (i % 10) * 3;
1450 u32 r = RTL931X_PIE_BLK_PHASE_CTRL + 4 * (i / 10);
1451
1452 if (i < priv->n_pie_blocks / 2)
1453 sw_w32_mask(0x7 << pos, 0, r);
1454 else
1455 sw_w32_mask(0x7 << pos, 1 << pos, r);
1456 }
1457
1458 /* Enable predefined templates 0, 1 for first quarter of all blocks */
1459 template_selectors = 0 | (1 << 4);
1460 for (int i = 0; i < priv->n_pie_blocks / 4; i++)
1461 sw_w32(template_selectors, RTL931X_PIE_BLK_TMPLTE_CTRL(i));
1462
1463 /* Enable predefined templates 2, 3 for second quarter of all blocks */
1464 template_selectors = 2 | (3 << 4);
1465 for (int i = priv->n_pie_blocks / 4; i < priv->n_pie_blocks / 2; i++)
1466 sw_w32(template_selectors, RTL931X_PIE_BLK_TMPLTE_CTRL(i));
1467
1468 /* Enable predefined templates 0, 1 for third quater of all blocks */
1469 template_selectors = 0 | (1 << 4);
1470 for (int i = priv->n_pie_blocks / 2; i < priv->n_pie_blocks * 3 / 4; i++)
1471 sw_w32(template_selectors, RTL931X_PIE_BLK_TMPLTE_CTRL(i));
1472
1473 /* Enable predefined templates 2, 3 for fourth quater of all blocks */
1474 template_selectors = 2 | (3 << 4);
1475 for (int i = priv->n_pie_blocks * 3 / 4; i < priv->n_pie_blocks; i++)
1476 sw_w32(template_selectors, RTL931X_PIE_BLK_TMPLTE_CTRL(i));
1477
1478 }
1479
1480 int rtl931x_l3_setup(struct rtl838x_switch_priv *priv)
1481 {
1482 return 0;
1483 }
1484
1485 void rtl931x_vlan_port_keep_tag_set(int port, bool keep_outer, bool keep_inner)
1486 {
1487 sw_w32(FIELD_PREP(RTL931X_VLAN_PORT_TAG_EGR_OTAG_STS_MASK,
1488 keep_outer ? RTL931X_VLAN_PORT_TAG_STS_TAGGED : RTL931X_VLAN_PORT_TAG_STS_UNTAG) |
1489 FIELD_PREP(RTL931X_VLAN_PORT_TAG_EGR_ITAG_STS_MASK,
1490 keep_inner ? RTL931X_VLAN_PORT_TAG_STS_TAGGED : RTL931X_VLAN_PORT_TAG_STS_UNTAG),
1491 RTL931X_VLAN_PORT_TAG_CTRL(port));
1492 }
1493
1494 void rtl931x_vlan_port_pvidmode_set(int port, enum pbvlan_type type, enum pbvlan_mode mode)
1495 {
1496 if (type == PBVLAN_TYPE_INNER)
1497 sw_w32_mask(0x3 << 12, mode << 12, RTL931X_VLAN_PORT_IGR_CTRL + (port << 2));
1498 else
1499 sw_w32_mask(0x3 << 26, mode << 26, RTL931X_VLAN_PORT_IGR_CTRL + (port << 2));
1500 }
1501
1502 void rtl931x_vlan_port_pvid_set(int port, enum pbvlan_type type, int pvid)
1503 {
1504 if (type == PBVLAN_TYPE_INNER)
1505 sw_w32_mask(0xfff, pvid, RTL931X_VLAN_PORT_IGR_CTRL + (port << 2));
1506 else
1507 sw_w32_mask(0xfff << 14, pvid << 14, RTL931X_VLAN_PORT_IGR_CTRL + (port << 2));
1508 }
1509
1510 static void rtl931x_set_igr_filter(int port, enum igr_filter state)
1511 {
1512 sw_w32_mask(0x3 << ((port & 0xf)<<1), state << ((port & 0xf)<<1),
1513 RTL931X_VLAN_PORT_IGR_FLTR + (((port >> 4) << 2)));
1514 }
1515
1516 static void rtl931x_set_egr_filter(int port, enum egr_filter state)
1517 {
1518 sw_w32_mask(0x1 << (port % 0x20), state << (port % 0x20),
1519 RTL931X_VLAN_PORT_EGR_FLTR + (((port >> 5) << 2)));
1520 }
1521
1522 void rtl931x_set_distribution_algorithm(int group, int algoidx, u32 algomsk)
1523 {
1524 u32 l3shift = 0;
1525 u32 newmask = 0;
1526
1527 /* TODO: for now we set algoidx to 0 */
1528 algoidx = 0;
1529
1530 if (algomsk & TRUNK_DISTRIBUTION_ALGO_SIP_BIT) {
1531 l3shift = 4;
1532 newmask |= TRUNK_DISTRIBUTION_ALGO_L3_SIP_BIT;
1533 }
1534 if (algomsk & TRUNK_DISTRIBUTION_ALGO_DIP_BIT) {
1535 l3shift = 4;
1536 newmask |= TRUNK_DISTRIBUTION_ALGO_L3_DIP_BIT;
1537 }
1538 if (algomsk & TRUNK_DISTRIBUTION_ALGO_SRC_L4PORT_BIT) {
1539 l3shift = 4;
1540 newmask |= TRUNK_DISTRIBUTION_ALGO_L3_SRC_L4PORT_BIT;
1541 }
1542 if (algomsk & TRUNK_DISTRIBUTION_ALGO_SRC_L4PORT_BIT) {
1543 l3shift = 4;
1544 newmask |= TRUNK_DISTRIBUTION_ALGO_L3_SRC_L4PORT_BIT;
1545 }
1546
1547 if (l3shift == 4) {
1548 if (algomsk & TRUNK_DISTRIBUTION_ALGO_SMAC_BIT)
1549 newmask |= TRUNK_DISTRIBUTION_ALGO_L3_SMAC_BIT;
1550 if (algomsk & TRUNK_DISTRIBUTION_ALGO_DMAC_BIT)
1551 newmask |= TRUNK_DISTRIBUTION_ALGO_L3_DMAC_BIT;
1552 } else {
1553 if (algomsk & TRUNK_DISTRIBUTION_ALGO_SMAC_BIT)
1554 newmask |= TRUNK_DISTRIBUTION_ALGO_L2_SMAC_BIT;
1555 if (algomsk & TRUNK_DISTRIBUTION_ALGO_DMAC_BIT)
1556 newmask |= TRUNK_DISTRIBUTION_ALGO_L2_DMAC_BIT;
1557 }
1558
1559 sw_w32(newmask << l3shift, RTL931X_TRK_HASH_CTRL + (algoidx << 2));
1560 }
1561
1562 static void rtl931x_led_init(struct rtl838x_switch_priv *priv)
1563 {
1564 u64 pm_copper = 0, pm_fiber = 0;
1565 struct device_node *node;
1566
1567 pr_info("%s called\n", __func__);
1568 node = of_find_compatible_node(NULL, NULL, "realtek,rtl9300-leds");
1569 if (!node) {
1570 pr_info("%s No compatible LED node found\n", __func__);
1571 return;
1572 }
1573
1574 for (int i = 0; i < priv->cpu_port; i++) {
1575 int pos = (i << 1) % 32;
1576 u32 set;
1577 u32 v;
1578
1579 sw_w32_mask(0x3 << pos, 0, RTL931X_LED_PORT_FIB_SET_SEL_CTRL(i));
1580 sw_w32_mask(0x3 << pos, 0, RTL931X_LED_PORT_COPR_SET_SEL_CTRL(i));
1581
1582 if (!priv->ports[i].phy)
1583 continue;
1584
1585 v = 0x1; /* Found on the EdgeCore, but we do not have any HW description */
1586 sw_w32_mask(0x3 << pos, v << pos, RTL931X_LED_PORT_NUM_CTRL(i));
1587
1588 if (priv->ports[i].phy_is_integrated)
1589 pm_fiber |= BIT_ULL(i);
1590 else
1591 pm_copper |= BIT_ULL(i);
1592
1593 set = priv->ports[i].led_set;
1594 sw_w32_mask(0, set << pos, RTL931X_LED_PORT_COPR_SET_SEL_CTRL(i));
1595 sw_w32_mask(0, set << pos, RTL931X_LED_PORT_FIB_SET_SEL_CTRL(i));
1596 }
1597
1598 for (int i = 0; i < 4; i++) {
1599 const __be32 *led_set;
1600 char set_name[9];
1601 u32 setlen;
1602 u32 v;
1603
1604 sprintf(set_name, "led_set%d", i);
1605 pr_info(">%s<\n", set_name);
1606 led_set = of_get_property(node, set_name, &setlen);
1607 if (!led_set || setlen != 16)
1608 break;
1609 v = be32_to_cpup(led_set) << 16 | be32_to_cpup(led_set + 1);
1610 sw_w32(v, RTL931X_LED_SET0_0_CTRL - 4 - i * 8);
1611 v = be32_to_cpup(led_set + 2) << 16 | be32_to_cpup(led_set + 3);
1612 sw_w32(v, RTL931X_LED_SET0_0_CTRL - i * 8);
1613 }
1614
1615 /* Set LED mode to serial (0x1) */
1616 sw_w32_mask(0x3, 0x1, RTL931X_LED_GLB_CTRL);
1617
1618 rtl839x_set_port_reg_le(pm_copper, RTL931X_LED_PORT_COPR_MASK_CTRL);
1619 rtl839x_set_port_reg_le(pm_fiber, RTL931X_LED_PORT_FIB_MASK_CTRL);
1620 rtl839x_set_port_reg_le(pm_copper | pm_fiber, RTL931X_LED_PORT_COMBO_MASK_CTRL);
1621
1622 for (int i = 0; i < 32; i++)
1623 pr_info("%s %08x: %08x\n",__func__, 0xbb000600 + i * 4, sw_r32(0x0600 + i * 4));
1624 }
1625
1626 const struct rtl838x_reg rtl931x_reg = {
1627 .mask_port_reg_be = rtl839x_mask_port_reg_be,
1628 .set_port_reg_be = rtl839x_set_port_reg_be,
1629 .get_port_reg_be = rtl839x_get_port_reg_be,
1630 .mask_port_reg_le = rtl839x_mask_port_reg_le,
1631 .set_port_reg_le = rtl839x_set_port_reg_le,
1632 .get_port_reg_le = rtl839x_get_port_reg_le,
1633 .stat_port_rst = RTL931X_STAT_PORT_RST,
1634 .stat_rst = RTL931X_STAT_RST,
1635 .stat_port_std_mib = 0, /* Not defined */
1636 .traffic_enable = rtl931x_traffic_enable,
1637 .traffic_disable = rtl931x_traffic_disable,
1638 .traffic_get = rtl931x_traffic_get,
1639 .traffic_set = rtl931x_traffic_set,
1640 .l2_ctrl_0 = RTL931X_L2_CTRL,
1641 .l2_ctrl_1 = RTL931X_L2_AGE_CTRL,
1642 .l2_port_aging_out = RTL931X_L2_PORT_AGE_CTRL,
1643 .set_ageing_time = rtl931x_set_ageing_time,
1644 /* .smi_poll_ctrl does not exist */
1645 .l2_tbl_flush_ctrl = RTL931X_L2_TBL_FLUSH_CTRL,
1646 .exec_tbl0_cmd = rtl931x_exec_tbl0_cmd,
1647 .exec_tbl1_cmd = rtl931x_exec_tbl1_cmd,
1648 .tbl_access_data_0 = rtl931x_tbl_access_data_0,
1649 .isr_glb_src = RTL931X_ISR_GLB_SRC,
1650 .isr_port_link_sts_chg = RTL931X_ISR_PORT_LINK_STS_CHG,
1651 .imr_port_link_sts_chg = RTL931X_IMR_PORT_LINK_STS_CHG,
1652 /* imr_glb does not exist on RTL931X */
1653 .vlan_tables_read = rtl931x_vlan_tables_read,
1654 .vlan_set_tagged = rtl931x_vlan_set_tagged,
1655 .vlan_set_untagged = rtl931x_vlan_set_untagged,
1656 .vlan_profile_dump = rtl931x_vlan_profile_dump,
1657 .vlan_profile_setup = rtl931x_vlan_profile_setup,
1658 .vlan_fwd_on_inner = rtl931x_vlan_fwd_on_inner,
1659 .stp_get = rtl931x_stp_get,
1660 .stp_set = rtl931x_stp_set,
1661 .mac_force_mode_ctrl = rtl931x_mac_force_mode_ctrl,
1662 .mac_port_ctrl = rtl931x_mac_port_ctrl,
1663 .l2_port_new_salrn = rtl931x_l2_port_new_salrn,
1664 .l2_port_new_sa_fwd = rtl931x_l2_port_new_sa_fwd,
1665 .mir_ctrl = RTL931X_MIR_CTRL,
1666 .mir_dpm = RTL931X_MIR_DPM_CTRL,
1667 .mir_spm = RTL931X_MIR_SPM_CTRL,
1668 .mac_link_sts = RTL931X_MAC_LINK_STS,
1669 .mac_link_dup_sts = RTL931X_MAC_LINK_DUP_STS,
1670 .mac_link_spd_sts = rtl931x_mac_link_spd_sts,
1671 .mac_rx_pause_sts = RTL931X_MAC_RX_PAUSE_STS,
1672 .mac_tx_pause_sts = RTL931X_MAC_TX_PAUSE_STS,
1673 .read_l2_entry_using_hash = rtl931x_read_l2_entry_using_hash,
1674 .write_l2_entry_using_hash = rtl931x_write_l2_entry_using_hash,
1675 .read_cam = rtl931x_read_cam,
1676 .write_cam = rtl931x_write_cam,
1677 .vlan_port_keep_tag_set = rtl931x_vlan_port_keep_tag_set,
1678 .vlan_port_pvidmode_set = rtl931x_vlan_port_pvidmode_set,
1679 .vlan_port_pvid_set = rtl931x_vlan_port_pvid_set,
1680 .trk_mbr_ctr = rtl931x_trk_mbr_ctr,
1681 .set_vlan_igr_filter = rtl931x_set_igr_filter,
1682 .set_vlan_egr_filter = rtl931x_set_egr_filter,
1683 .set_distribution_algorithm = rtl931x_set_distribution_algorithm,
1684 .l2_hash_key = rtl931x_l2_hash_key,
1685 .read_mcast_pmask = rtl931x_read_mcast_pmask,
1686 .write_mcast_pmask = rtl931x_write_mcast_pmask,
1687 .pie_init = rtl931x_pie_init,
1688 .pie_rule_write = rtl931x_pie_rule_write,
1689 .pie_rule_add = rtl931x_pie_rule_add,
1690 .pie_rule_rm = rtl931x_pie_rule_rm,
1691 .l2_learning_setup = rtl931x_l2_learning_setup,
1692 .l3_setup = rtl931x_l3_setup,
1693 .led_init = rtl931x_led_init,
1694 };
Felix Fietkaus staging tree