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realtek: Add missing headers
[openwrt/staging/jow.git] / target / linux / realtek / files-5.15 / drivers / net / dsa / rtl83xx / rtl930x.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <asm/mach-rtl838x/mach-rtl83xx.h>
4 #include <linux/etherdevice.h>
5 #include <linux/inetdevice.h>
6
7 #include "rtl83xx.h"
8
9 #define RTL930X_VLAN_PORT_TAG_STS_INTERNAL 0x0
10 #define RTL930X_VLAN_PORT_TAG_STS_UNTAG 0x1
11 #define RTL930X_VLAN_PORT_TAG_STS_TAGGED 0x2
12 #define RTL930X_VLAN_PORT_TAG_STS_PRIORITY_TAGGED 0x3
13
14 #define RTL930X_VLAN_PORT_TAG_STS_CTRL_BASE 0xCE24
15 /* port 0-28 */
16 #define RTL930X_VLAN_PORT_TAG_STS_CTRL(port) \
17 RTL930X_VLAN_PORT_TAG_STS_CTRL_BASE + (port << 2)
18 #define RTL930X_VLAN_PORT_TAG_STS_CTRL_EGR_OTAG_STS_MASK GENMASK(7,6)
19 #define RTL930X_VLAN_PORT_TAG_STS_CTRL_EGR_ITAG_STS_MASK GENMASK(5,4)
20 #define RTL930X_VLAN_PORT_TAG_STS_CTRL_EGR_P_OTAG_KEEP_MASK GENMASK(3,3)
21 #define RTL930X_VLAN_PORT_TAG_STS_CTRL_EGR_P_ITAG_KEEP_MASK GENMASK(2,2)
22 #define RTL930X_VLAN_PORT_TAG_STS_CTRL_IGR_P_OTAG_KEEP_MASK GENMASK(1,1)
23 #define RTL930X_VLAN_PORT_TAG_STS_CTRL_IGR_P_ITAG_KEEP_MASK GENMASK(0,0)
24
25 #define RTL930X_LED_GLB_ACTIVE_LOW BIT(22)
26
27 extern struct mutex smi_lock;
28 extern struct rtl83xx_soc_info soc_info;
29
30 /* Definition of the RTL930X-specific template field IDs as used in the PIE */
31 enum template_field_id {
32 TEMPLATE_FIELD_SPM0 = 0, /* Source portmask ports 0-15 */
33 TEMPLATE_FIELD_SPM1 = 1, /* Source portmask ports 16-31 */
34 TEMPLATE_FIELD_DMAC0 = 2, /* Destination MAC [15:0] */
35 TEMPLATE_FIELD_DMAC1 = 3, /* Destination MAC [31:16] */
36 TEMPLATE_FIELD_DMAC2 = 4, /* Destination MAC [47:32] */
37 TEMPLATE_FIELD_SMAC0 = 5, /* Source MAC [15:0] */
38 TEMPLATE_FIELD_SMAC1 = 6, /* Source MAC [31:16] */
39 TEMPLATE_FIELD_SMAC2 = 7, /* Source MAC [47:32] */
40 TEMPLATE_FIELD_ETHERTYPE = 8, /* Ethernet frame type field */
41 TEMPLATE_FIELD_OTAG = 9,
42 TEMPLATE_FIELD_ITAG = 10,
43 TEMPLATE_FIELD_SIP0 = 11,
44 TEMPLATE_FIELD_SIP1 = 12,
45 TEMPLATE_FIELD_DIP0 = 13,
46 TEMPLATE_FIELD_DIP1 = 14,
47 TEMPLATE_FIELD_IP_TOS_PROTO = 15,
48 TEMPLATE_FIELD_L4_SPORT = 16,
49 TEMPLATE_FIELD_L4_DPORT = 17,
50 TEMPLATE_FIELD_L34_HEADER = 18,
51 TEMPLATE_FIELD_TCP_INFO = 19,
52 TEMPLATE_FIELD_FIELD_SELECTOR_VALID = 20,
53 TEMPLATE_FIELD_FIELD_SELECTOR_0 = 21,
54 TEMPLATE_FIELD_FIELD_SELECTOR_1 = 22,
55 TEMPLATE_FIELD_FIELD_SELECTOR_2 = 23,
56 TEMPLATE_FIELD_FIELD_SELECTOR_3 = 24,
57 TEMPLATE_FIELD_FIELD_SELECTOR_4 = 25,
58 TEMPLATE_FIELD_FIELD_SELECTOR_5 = 26,
59 TEMPLATE_FIELD_SIP2 = 27,
60 TEMPLATE_FIELD_SIP3 = 28,
61 TEMPLATE_FIELD_SIP4 = 29,
62 TEMPLATE_FIELD_SIP5 = 30,
63 TEMPLATE_FIELD_SIP6 = 31,
64 TEMPLATE_FIELD_SIP7 = 32,
65 TEMPLATE_FIELD_DIP2 = 33,
66 TEMPLATE_FIELD_DIP3 = 34,
67 TEMPLATE_FIELD_DIP4 = 35,
68 TEMPLATE_FIELD_DIP5 = 36,
69 TEMPLATE_FIELD_DIP6 = 37,
70 TEMPLATE_FIELD_DIP7 = 38,
71 TEMPLATE_FIELD_PKT_INFO = 39,
72 TEMPLATE_FIELD_FLOW_LABEL = 40,
73 TEMPLATE_FIELD_DSAP_SSAP = 41,
74 TEMPLATE_FIELD_SNAP_OUI = 42,
75 TEMPLATE_FIELD_FWD_VID = 43,
76 TEMPLATE_FIELD_RANGE_CHK = 44,
77 TEMPLATE_FIELD_VLAN_GMSK = 45, /* VLAN Group Mask/IP range check */
78 TEMPLATE_FIELD_DLP = 46,
79 TEMPLATE_FIELD_META_DATA = 47,
80 TEMPLATE_FIELD_SRC_FWD_VID = 48,
81 TEMPLATE_FIELD_SLP = 49,
82 };
83
84 /* The meaning of TEMPLATE_FIELD_VLAN depends on phase and the configuration in
85 * RTL930X_PIE_CTRL. We use always the same definition and map to the inner VLAN tag:
86 */
87 #define TEMPLATE_FIELD_VLAN TEMPLATE_FIELD_ITAG
88
89 /* Number of fixed templates predefined in the RTL9300 SoC */
90 #define N_FIXED_TEMPLATES 5
91 /* RTL9300 specific predefined templates */
92 static enum template_field_id fixed_templates[N_FIXED_TEMPLATES][N_FIXED_FIELDS] =
93 {
94 {
95 TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2,
96 TEMPLATE_FIELD_SMAC0, TEMPLATE_FIELD_SMAC1, TEMPLATE_FIELD_SMAC2,
97 TEMPLATE_FIELD_VLAN, TEMPLATE_FIELD_IP_TOS_PROTO, TEMPLATE_FIELD_DSAP_SSAP,
98 TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1
99 }, {
100 TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0,
101 TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_IP_TOS_PROTO, TEMPLATE_FIELD_TCP_INFO,
102 TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_L4_DPORT, TEMPLATE_FIELD_VLAN,
103 TEMPLATE_FIELD_RANGE_CHK, TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1
104 }, {
105 TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2,
106 TEMPLATE_FIELD_VLAN, TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_IP_TOS_PROTO,
107 TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0,
108 TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_L4_DPORT
109 }, {
110 TEMPLATE_FIELD_DIP0, TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_DIP2,
111 TEMPLATE_FIELD_DIP3, TEMPLATE_FIELD_DIP4, TEMPLATE_FIELD_DIP5,
112 TEMPLATE_FIELD_DIP6, TEMPLATE_FIELD_DIP7, TEMPLATE_FIELD_IP_TOS_PROTO,
113 TEMPLATE_FIELD_TCP_INFO, TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_L4_DPORT
114 }, {
115 TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_SIP2,
116 TEMPLATE_FIELD_SIP3, TEMPLATE_FIELD_SIP4, TEMPLATE_FIELD_SIP5,
117 TEMPLATE_FIELD_SIP6, TEMPLATE_FIELD_SIP7, TEMPLATE_FIELD_VLAN,
118 TEMPLATE_FIELD_RANGE_CHK, TEMPLATE_FIELD_SPM1, TEMPLATE_FIELD_SPM1
119 },
120 };
121
122 void rtl930x_print_matrix(void)
123 {
124 struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6);
125
126 for (int i = 0; i < 29; i++) {
127 rtl_table_read(r, i);
128 pr_debug("> %08x\n", sw_r32(rtl_table_data(r, 0)));
129 }
130 rtl_table_release(r);
131 }
132
133 inline void rtl930x_exec_tbl0_cmd(u32 cmd)
134 {
135 sw_w32(cmd, RTL930X_TBL_ACCESS_CTRL_0);
136 do { } while (sw_r32(RTL930X_TBL_ACCESS_CTRL_0) & (1 << 17));
137 }
138
139 inline void rtl930x_exec_tbl1_cmd(u32 cmd)
140 {
141 sw_w32(cmd, RTL930X_TBL_ACCESS_CTRL_1);
142 do { } while (sw_r32(RTL930X_TBL_ACCESS_CTRL_1) & (1 << 17));
143 }
144
145 inline int rtl930x_tbl_access_data_0(int i)
146 {
147 return RTL930X_TBL_ACCESS_DATA_0(i);
148 }
149
150 static inline int rtl930x_l2_port_new_salrn(int p)
151 {
152 return RTL930X_L2_PORT_SALRN(p);
153 }
154
155 static inline int rtl930x_l2_port_new_sa_fwd(int p)
156 {
157 /* TODO: The definition of the fields changed, because of the master-cpu in a stack */
158 return RTL930X_L2_PORT_NEW_SA_FWD(p);
159 }
160
161 inline static int rtl930x_trk_mbr_ctr(int group)
162 {
163 return RTL930X_TRK_MBR_CTRL + (group << 2);
164 }
165
166 static void rtl930x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info)
167 {
168 u32 v, w;
169 /* Read VLAN table (1) via register 0 */
170 struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 1);
171
172 rtl_table_read(r, vlan);
173 v = sw_r32(rtl_table_data(r, 0));
174 w = sw_r32(rtl_table_data(r, 1));
175 pr_debug("VLAN_READ %d: %08x %08x\n", vlan, v, w);
176 rtl_table_release(r);
177
178 info->tagged_ports = v >> 3;
179 info->profile_id = (w >> 24) & 7;
180 info->hash_mc_fid = !!(w & BIT(27));
181 info->hash_uc_fid = !!(w & BIT(28));
182 info->fid = ((v & 0x7) << 3) | ((w >> 29) & 0x7);
183
184 /* Read UNTAG table via table register 2 */
185 r = rtl_table_get(RTL9300_TBL_2, 0);
186 rtl_table_read(r, vlan);
187 v = sw_r32(rtl_table_data(r, 0));
188 rtl_table_release(r);
189
190 info->untagged_ports = v >> 3;
191 }
192
193 static void rtl930x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info)
194 {
195 u32 v, w;
196 /* Access VLAN table (1) via register 0 */
197 struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 1);
198
199 v = info->tagged_ports << 3;
200 v |= ((u32)info->fid) >> 3;
201
202 w = ((u32)info->fid) << 29;
203 w |= info->hash_mc_fid ? BIT(27) : 0;
204 w |= info->hash_uc_fid ? BIT(28) : 0;
205 w |= info->profile_id << 24;
206
207 sw_w32(v, rtl_table_data(r, 0));
208 sw_w32(w, rtl_table_data(r, 1));
209
210 rtl_table_write(r, vlan);
211 rtl_table_release(r);
212 }
213
214 void rtl930x_vlan_profile_dump(int profile)
215 {
216 u32 p[5];
217
218 if (profile < 0 || profile > 7)
219 return;
220
221 p[0] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile));
222 p[1] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 4);
223 p[2] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 8) & 0x1FFFFFFF;
224 p[3] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 12) & 0x1FFFFFFF;
225 p[4] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 16) & 0x1FFFFFFF;
226
227 pr_info("VLAN %d: L2 learn: %d; Unknown MC PMasks: L2 %0x, IPv4 %0x, IPv6: %0x",
228 profile, p[0] & (3 << 21), p[2], p[3], p[4]);
229 pr_info(" Routing enabled: IPv4 UC %c, IPv6 UC %c, IPv4 MC %c, IPv6 MC %c\n",
230 p[0] & BIT(17) ? 'y' : 'n', p[0] & BIT(16) ? 'y' : 'n',
231 p[0] & BIT(13) ? 'y' : 'n', p[0] & BIT(12) ? 'y' : 'n');
232 pr_info(" Bridge enabled: IPv4 MC %c, IPv6 MC %c,\n",
233 p[0] & BIT(15) ? 'y' : 'n', p[0] & BIT(14) ? 'y' : 'n');
234 pr_info("VLAN profile %d: raw %08x %08x %08x %08x %08x\n",
235 profile, p[0], p[1], p[2], p[3], p[4]);
236 }
237
238 static void rtl930x_vlan_set_untagged(u32 vlan, u64 portmask)
239 {
240 struct table_reg *r = rtl_table_get(RTL9300_TBL_2, 0);
241
242 sw_w32(portmask << 3, rtl_table_data(r, 0));
243 rtl_table_write(r, vlan);
244 rtl_table_release(r);
245 }
246
247 /* Sets the L2 forwarding to be based on either the inner VLAN tag or the outer */
248 static void rtl930x_vlan_fwd_on_inner(int port, bool is_set)
249 {
250 /* Always set all tag modes to fwd based on either inner or outer tag */
251 if (is_set)
252 sw_w32_mask(0, 0xf, RTL930X_VLAN_PORT_FWD + (port << 2));
253 else
254 sw_w32_mask(0xf, 0, RTL930X_VLAN_PORT_FWD + (port << 2));
255 }
256
257 static void rtl930x_vlan_profile_setup(int profile)
258 {
259 u32 p[5];
260
261 pr_info("In %s\n", __func__);
262 p[0] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile));
263 p[1] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 4);
264
265 /* Enable routing of Ipv4/6 Unicast and IPv4/6 Multicast traffic */
266 p[0] |= BIT(17) | BIT(16) | BIT(13) | BIT(12);
267 p[2] = 0x1fffffff; /* L2 unknown MC flooding portmask all ports, including the CPU-port */
268 p[3] = 0x1fffffff; /* IPv4 unknown MC flooding portmask */
269 p[4] = 0x1fffffff; /* IPv6 unknown MC flooding portmask */
270
271 sw_w32(p[0], RTL930X_VLAN_PROFILE_SET(profile));
272 sw_w32(p[1], RTL930X_VLAN_PROFILE_SET(profile) + 4);
273 sw_w32(p[2], RTL930X_VLAN_PROFILE_SET(profile) + 8);
274 sw_w32(p[3], RTL930X_VLAN_PROFILE_SET(profile) + 12);
275 sw_w32(p[4], RTL930X_VLAN_PROFILE_SET(profile) + 16);
276 }
277
278 static void rtl930x_l2_learning_setup(void)
279 {
280 /* Portmask for flooding broadcast traffic */
281 sw_w32(0x1fffffff, RTL930X_L2_BC_FLD_PMSK);
282
283 /* Portmask for flooding unicast traffic with unknown destination */
284 sw_w32(0x1fffffff, RTL930X_L2_UNKN_UC_FLD_PMSK);
285
286 /* Limit learning to maximum: 32k entries, after that just flood (bits 0-1) */
287 sw_w32((0x7fff << 2) | 0, RTL930X_L2_LRN_CONSTRT_CTRL);
288 }
289
290 static void rtl930x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
291 {
292 u32 cmd = 1 << 17 | /* Execute cmd */
293 0 << 16 | /* Read */
294 4 << 12 | /* Table type 0b10 */
295 (msti & 0xfff);
296 priv->r->exec_tbl0_cmd(cmd);
297
298 for (int i = 0; i < 2; i++)
299 port_state[i] = sw_r32(RTL930X_TBL_ACCESS_DATA_0(i));
300 pr_debug("MSTI: %d STATE: %08x, %08x\n", msti, port_state[0], port_state[1]);
301 }
302
303 static void rtl930x_stp_set(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
304 {
305 u32 cmd = 1 << 17 | /* Execute cmd */
306 1 << 16 | /* Write */
307 4 << 12 | /* Table type 4 */
308 (msti & 0xfff);
309
310 for (int i = 0; i < 2; i++)
311 sw_w32(port_state[i], RTL930X_TBL_ACCESS_DATA_0(i));
312 priv->r->exec_tbl0_cmd(cmd);
313 }
314
315 static inline int rtl930x_mac_force_mode_ctrl(int p)
316 {
317 return RTL930X_MAC_FORCE_MODE_CTRL + (p << 2);
318 }
319
320 static inline int rtl930x_mac_port_ctrl(int p)
321 {
322 return RTL930X_MAC_L2_PORT_CTRL(p);
323 }
324
325 static inline int rtl930x_mac_link_spd_sts(int p)
326 {
327 return RTL930X_MAC_LINK_SPD_STS(p);
328 }
329
330 static u64 rtl930x_l2_hash_seed(u64 mac, u32 vid)
331 {
332 u64 v = vid;
333
334 v <<= 48;
335 v |= mac;
336
337 return v;
338 }
339
340 /* Calculate both the block 0 and the block 1 hash by applyingthe same hash
341 * algorithm as the one used currently by the ASIC to the seed, and return
342 * both hashes in the lower and higher word of the return value since only 12 bit of
343 * the hash are significant
344 */
345 static u32 rtl930x_l2_hash_key(struct rtl838x_switch_priv *priv, u64 seed)
346 {
347 u32 k0, k1, h1, h2, h;
348
349 k0 = (u32) (((seed >> 55) & 0x1f) ^
350 ((seed >> 44) & 0x7ff) ^
351 ((seed >> 33) & 0x7ff) ^
352 ((seed >> 22) & 0x7ff) ^
353 ((seed >> 11) & 0x7ff) ^
354 (seed & 0x7ff));
355
356 h1 = (seed >> 11) & 0x7ff;
357 h1 = ((h1 & 0x1f) << 6) | ((h1 >> 5) & 0x3f);
358
359 h2 = (seed >> 33) & 0x7ff;
360 h2 = ((h2 & 0x3f) << 5)| ((h2 >> 6) & 0x3f);
361
362 k1 = (u32) (((seed << 55) & 0x1f) ^
363 ((seed >> 44) & 0x7ff) ^
364 h2 ^
365 ((seed >> 22) & 0x7ff) ^
366 h1 ^
367 (seed & 0x7ff));
368
369 /* Algorithm choice for block 0 */
370 if (sw_r32(RTL930X_L2_CTRL) & BIT(0))
371 h = k1;
372 else
373 h = k0;
374
375 /* Algorithm choice for block 1
376 * Since k0 and k1 are < 2048, adding 2048 will offset the hash into the second
377 * half of hash-space
378 * 2048 is in fact the hash-table size 16384 divided by 4 hashes per bucket
379 * divided by 2 to divide the hash space in 2
380 */
381 if (sw_r32(RTL930X_L2_CTRL) & BIT(1))
382 h |= (k1 + 2048) << 16;
383 else
384 h |= (k0 + 2048) << 16;
385
386 return h;
387 }
388
389 /* Fills an L2 entry structure from the SoC registers */
390 static void rtl930x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e)
391 {
392 pr_debug("In %s valid?\n", __func__);
393 e->valid = !!(r[2] & BIT(31));
394 if (!e->valid)
395 return;
396
397 pr_debug("In %s is valid\n", __func__);
398 e->is_ip_mc = false;
399 e->is_ipv6_mc = false;
400
401 /* TODO: Is there not a function to copy directly MAC memory? */
402 e->mac[0] = (r[0] >> 24);
403 e->mac[1] = (r[0] >> 16);
404 e->mac[2] = (r[0] >> 8);
405 e->mac[3] = r[0];
406 e->mac[4] = (r[1] >> 24);
407 e->mac[5] = (r[1] >> 16);
408
409 e->next_hop = !!(r[2] & BIT(12));
410 e->rvid = r[1] & 0xfff;
411
412 /* Is it a unicast entry? check multicast bit */
413 if (!(e->mac[0] & 1)) {
414 e->type = L2_UNICAST;
415 e->is_static = !!(r[2] & BIT(14));
416 e->port = (r[2] >> 20) & 0x3ff;
417 /* Check for trunk port */
418 if (r[2] & BIT(30)) {
419 e->is_trunk = true;
420 e->stack_dev = (e->port >> 9) & 1;
421 e->trunk = e->port & 0x3f;
422 } else {
423 e->is_trunk = false;
424 e->stack_dev = (e->port >> 6) & 0xf;
425 e->port = e->port & 0x3f;
426 }
427
428 e->block_da = !!(r[2] & BIT(15));
429 e->block_sa = !!(r[2] & BIT(16));
430 e->suspended = !!(r[2] & BIT(13));
431 e->age = (r[2] >> 17) & 3;
432 e->valid = true;
433 /* the UC_VID field in hardware is used for the VID or for the route id */
434 if (e->next_hop) {
435 e->nh_route_id = r[2] & 0x7ff;
436 e->vid = 0;
437 } else {
438 e->vid = r[2] & 0xfff;
439 e->nh_route_id = 0;
440 }
441 } else {
442 e->valid = true;
443 e->type = L2_MULTICAST;
444 e->mc_portmask_index = (r[2] >> 16) & 0x3ff;
445 }
446 }
447
448 /* Fills the 3 SoC table registers r[] with the information of in the rtl838x_l2_entry */
449 static void rtl930x_fill_l2_row(u32 r[], struct rtl838x_l2_entry *e)
450 {
451 u32 port;
452
453 if (!e->valid) {
454 r[0] = r[1] = r[2] = 0;
455 return;
456 }
457
458 r[2] = BIT(31); /* Set valid bit */
459
460 r[0] = ((u32)e->mac[0]) << 24 |
461 ((u32)e->mac[1]) << 16 |
462 ((u32)e->mac[2]) << 8 |
463 ((u32)e->mac[3]);
464 r[1] = ((u32)e->mac[4]) << 24 |
465 ((u32)e->mac[5]) << 16;
466
467 r[2] |= e->next_hop ? BIT(12) : 0;
468
469 if (e->type == L2_UNICAST) {
470 r[2] |= e->is_static ? BIT(14) : 0;
471 r[1] |= e->rvid & 0xfff;
472 r[2] |= (e->port & 0x3ff) << 20;
473 if (e->is_trunk) {
474 r[2] |= BIT(30);
475 port = e->stack_dev << 9 | (e->port & 0x3f);
476 } else {
477 port = (e->stack_dev & 0xf) << 6;
478 port |= e->port & 0x3f;
479 }
480 r[2] |= port << 20;
481 r[2] |= e->block_da ? BIT(15) : 0;
482 r[2] |= e->block_sa ? BIT(17) : 0;
483 r[2] |= e->suspended ? BIT(13) : 0;
484 r[2] |= (e->age & 0x3) << 17;
485 /* the UC_VID field in hardware is used for the VID or for the route id */
486 if (e->next_hop)
487 r[2] |= e->nh_route_id & 0x7ff;
488 else
489 r[2] |= e->vid & 0xfff;
490 } else { /* L2_MULTICAST */
491 r[2] |= (e->mc_portmask_index & 0x3ff) << 16;
492 r[2] |= e->mc_mac_index & 0x7ff;
493 }
494 }
495
496 /* Read an L2 UC or MC entry out of a hash bucket of the L2 forwarding table
497 * hash is the id of the bucket and pos is the position of the entry in that bucket
498 * The data read from the SoC is filled into rtl838x_l2_entry
499 */
500 static u64 rtl930x_read_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e)
501 {
502 u32 r[3];
503 struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 0);
504 u32 idx;
505 u64 mac;
506 u64 seed;
507
508 pr_debug("%s: hash %08x, pos: %d\n", __func__, hash, pos);
509
510 /* On the RTL93xx, 2 different hash algorithms are used making it a
511 * total of 8 buckets that need to be searched, 4 for each hash-half
512 * Use second hash space when bucket is between 4 and 8
513 */
514 if (pos >= 4) {
515 pos -= 4;
516 hash >>= 16;
517 } else {
518 hash &= 0xffff;
519 }
520
521 idx = (0 << 14) | (hash << 2) | pos; /* Search SRAM, with hash and at pos in bucket */
522 pr_debug("%s: NOW hash %08x, pos: %d\n", __func__, hash, pos);
523
524 rtl_table_read(q, idx);
525 for (int i = 0; i < 3; i++)
526 r[i] = sw_r32(rtl_table_data(q, i));
527
528 rtl_table_release(q);
529
530 rtl930x_fill_l2_entry(r, e);
531
532 pr_debug("%s: valid: %d, nh: %d\n", __func__, e->valid, e->next_hop);
533 if (!e->valid)
534 return 0;
535
536 mac = ((u64)e->mac[0]) << 40 |
537 ((u64)e->mac[1]) << 32 |
538 ((u64)e->mac[2]) << 24 |
539 ((u64)e->mac[3]) << 16 |
540 ((u64)e->mac[4]) << 8 |
541 ((u64)e->mac[5]);
542
543 seed = rtl930x_l2_hash_seed(mac, e->rvid);
544 pr_debug("%s: mac %016llx, seed %016llx\n", __func__, mac, seed);
545
546 /* return vid with concatenated mac as unique id */
547 return seed;
548 }
549
550 static void rtl930x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e)
551 {
552 u32 r[3];
553 struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 0);
554 u32 idx = (0 << 14) | (hash << 2) | pos; /* Access SRAM, with hash and at pos in bucket */
555
556 pr_debug("%s: hash %d, pos %d\n", __func__, hash, pos);
557 pr_debug("%s: index %d -> mac %02x:%02x:%02x:%02x:%02x:%02x\n", __func__, idx,
558 e->mac[0], e->mac[1], e->mac[2], e->mac[3],e->mac[4],e->mac[5]);
559
560 rtl930x_fill_l2_row(r, e);
561
562 for (int i = 0; i < 3; i++)
563 sw_w32(r[i], rtl_table_data(q, i));
564
565 rtl_table_write(q, idx);
566 rtl_table_release(q);
567 }
568
569 static u64 rtl930x_read_cam(int idx, struct rtl838x_l2_entry *e)
570 {
571 u32 r[3];
572 struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 1);
573
574 rtl_table_read(q, idx);
575 for (int i = 0; i < 3; i++)
576 r[i] = sw_r32(rtl_table_data(q, i));
577
578 rtl_table_release(q);
579
580 rtl930x_fill_l2_entry(r, e);
581 if (!e->valid)
582 return 0;
583
584 /* return mac with concatenated vid as unique id */
585 return ((u64)r[0] << 28) | ((r[1] & 0xffff0000) >> 4) | e->vid;
586 }
587
588 static void rtl930x_write_cam(int idx, struct rtl838x_l2_entry *e)
589 {
590 u32 r[3];
591 struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 1); /* Access L2 Table 1 */
592
593 rtl930x_fill_l2_row(r, e);
594
595 for (int i = 0; i < 3; i++)
596 sw_w32(r[i], rtl_table_data(q, i));
597
598 rtl_table_write(q, idx);
599 rtl_table_release(q);
600 }
601
602 static u64 rtl930x_read_mcast_pmask(int idx)
603 {
604 u32 portmask;
605 /* Read MC_PORTMASK (2) via register RTL9300_TBL_L2 */
606 struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 2);
607
608 rtl_table_read(q, idx);
609 portmask = sw_r32(rtl_table_data(q, 0));
610 portmask >>= 3;
611 rtl_table_release(q);
612
613 pr_debug("%s: Index idx %d has portmask %08x\n", __func__, idx, portmask);
614
615 return portmask;
616 }
617
618 static void rtl930x_write_mcast_pmask(int idx, u64 portmask)
619 {
620 u32 pm = portmask;
621
622 /* Access MC_PORTMASK (2) via register RTL9300_TBL_L2 */
623 struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 2);
624
625 pr_debug("%s: Index idx %d has portmask %08x\n", __func__, idx, pm);
626 pm <<= 3;
627 sw_w32(pm, rtl_table_data(q, 0));
628 rtl_table_write(q, idx);
629 rtl_table_release(q);
630 }
631
632 u64 rtl930x_traffic_get(int source)
633 {
634 u32 v;
635 struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6);
636
637 rtl_table_read(r, source);
638 v = sw_r32(rtl_table_data(r, 0));
639 rtl_table_release(r);
640 v = v >> 3;
641
642 return v;
643 }
644
645 /* Enable traffic between a source port and a destination port matrix */
646 void rtl930x_traffic_set(int source, u64 dest_matrix)
647 {
648 struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6);
649
650 sw_w32((dest_matrix << 3), rtl_table_data(r, 0));
651 rtl_table_write(r, source);
652 rtl_table_release(r);
653 }
654
655 void rtl930x_traffic_enable(int source, int dest)
656 {
657 struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6);
658 rtl_table_read(r, source);
659 sw_w32_mask(0, BIT(dest + 3), rtl_table_data(r, 0));
660 rtl_table_write(r, source);
661 rtl_table_release(r);
662 }
663
664 void rtl930x_traffic_disable(int source, int dest)
665 {
666 struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6);
667 rtl_table_read(r, source);
668 sw_w32_mask(BIT(dest + 3), 0, rtl_table_data(r, 0));
669 rtl_table_write(r, source);
670 rtl_table_release(r);
671 }
672
673 void rtl9300_dump_debug(void)
674 {
675 u16 r = RTL930X_STAT_PRVTE_DROP_COUNTER0;
676
677 for (int i = 0; i < 10; i ++) {
678 pr_info("# %d %08x %08x %08x %08x %08x %08x %08x %08x\n", i * 8,
679 sw_r32(r), sw_r32(r + 4), sw_r32(r + 8), sw_r32(r + 12),
680 sw_r32(r + 16), sw_r32(r + 20), sw_r32(r + 24), sw_r32(r + 28));
681 r += 32;
682 }
683 pr_info("# %08x %08x %08x %08x %08x\n",
684 sw_r32(r), sw_r32(r + 4), sw_r32(r + 8), sw_r32(r + 12), sw_r32(r + 16));
685 rtl930x_print_matrix();
686 pr_info("RTL930X_L2_PORT_SABLK_CTRL: %08x, RTL930X_L2_PORT_DABLK_CTRL %08x\n",
687 sw_r32(RTL930X_L2_PORT_SABLK_CTRL), sw_r32(RTL930X_L2_PORT_DABLK_CTRL)
688
689 );
690 }
691
692 irqreturn_t rtl930x_switch_irq(int irq, void *dev_id)
693 {
694 struct dsa_switch *ds = dev_id;
695 u32 ports = sw_r32(RTL930X_ISR_PORT_LINK_STS_CHG);
696 u32 link;
697
698 /* Clear status */
699 sw_w32(ports, RTL930X_ISR_PORT_LINK_STS_CHG);
700
701 for (int i = 0; i < 28; i++) {
702 if (ports & BIT(i)) {
703 /* Read the register twice because of issues with latency at least
704 * with the external RTL8226 PHY on the XGS1210
705 */
706 link = sw_r32(RTL930X_MAC_LINK_STS);
707 link = sw_r32(RTL930X_MAC_LINK_STS);
708 if (link & BIT(i))
709 dsa_port_phylink_mac_change(ds, i, true);
710 else
711 dsa_port_phylink_mac_change(ds, i, false);
712 }
713 }
714
715 return IRQ_HANDLED;
716 }
717
718 int rtl930x_write_phy(u32 port, u32 page, u32 reg, u32 val)
719 {
720 u32 v;
721 int err = 0;
722
723 pr_debug("%s: port %d, page: %d, reg: %x, val: %x\n", __func__, port, page, reg, val);
724
725 if (port > 63 || page > 4095 || reg > 31)
726 return -ENOTSUPP;
727
728 val &= 0xffff;
729 mutex_lock(&smi_lock);
730
731 sw_w32(BIT(port), RTL930X_SMI_ACCESS_PHY_CTRL_0);
732 sw_w32_mask(0xffff << 16, val << 16, RTL930X_SMI_ACCESS_PHY_CTRL_2);
733 v = reg << 20 | page << 3 | 0x1f << 15 | BIT(2) | BIT(0);
734 sw_w32(v, RTL930X_SMI_ACCESS_PHY_CTRL_1);
735
736 do {
737 v = sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_1);
738 } while (v & 0x1);
739
740 if (v & 0x2)
741 err = -EIO;
742
743 mutex_unlock(&smi_lock);
744
745 return err;
746 }
747
748 int rtl930x_read_phy(u32 port, u32 page, u32 reg, u32 *val)
749 {
750 u32 v;
751 int err = 0;
752
753 if (port > 63 || page > 4095 || reg > 31)
754 return -ENOTSUPP;
755
756 mutex_lock(&smi_lock);
757
758 sw_w32_mask(0xffff << 16, port << 16, RTL930X_SMI_ACCESS_PHY_CTRL_2);
759 v = reg << 20 | page << 3 | 0x1f << 15 | 1;
760 sw_w32(v, RTL930X_SMI_ACCESS_PHY_CTRL_1);
761
762 do {
763 v = sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_1);
764 } while ( v & 0x1);
765
766 if (v & BIT(25)) {
767 pr_debug("Error reading phy %d, register %d\n", port, reg);
768 err = -EIO;
769 }
770 *val = (sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_2) & 0xffff);
771
772 pr_debug("%s: port %d, page: %d, reg: %x, val: %x\n", __func__, port, page, reg, *val);
773
774 mutex_unlock(&smi_lock);
775
776 return err;
777 }
778
779 /* Write to an mmd register of the PHY */
780 int rtl930x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val)
781 {
782 int err = 0;
783 u32 v;
784
785 mutex_lock(&smi_lock);
786
787 /* Set PHY to access */
788 sw_w32(BIT(port), RTL930X_SMI_ACCESS_PHY_CTRL_0);
789
790 /* Set data to write */
791 sw_w32_mask(0xffff << 16, val << 16, RTL930X_SMI_ACCESS_PHY_CTRL_2);
792
793 /* Set MMD device number and register to write to */
794 sw_w32(devnum << 16 | (regnum & 0xffff), RTL930X_SMI_ACCESS_PHY_CTRL_3);
795
796 v = BIT(2) | BIT(1) | BIT(0); /* WRITE | MMD-access | EXEC */
797 sw_w32(v, RTL930X_SMI_ACCESS_PHY_CTRL_1);
798
799 do {
800 v = sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_1);
801 } while (v & BIT(0));
802
803 pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__, port, regnum, val, err);
804 mutex_unlock(&smi_lock);
805 return err;
806 }
807
808 /* Read an mmd register of the PHY */
809 int rtl930x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val)
810 {
811 int err = 0;
812 u32 v;
813
814 mutex_lock(&smi_lock);
815
816 /* Set PHY to access */
817 sw_w32_mask(0xffff << 16, port << 16, RTL930X_SMI_ACCESS_PHY_CTRL_2);
818
819 /* Set MMD device number and register to write to */
820 sw_w32(devnum << 16 | (regnum & 0xffff), RTL930X_SMI_ACCESS_PHY_CTRL_3);
821
822 v = BIT(1) | BIT(0); /* MMD-access | EXEC */
823 sw_w32(v, RTL930X_SMI_ACCESS_PHY_CTRL_1);
824
825 do {
826 v = sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_1);
827 } while (v & BIT(0));
828 /* There is no error-checking via BIT 25 of v, as it does not seem to be set correctly */
829 *val = (sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_2) & 0xffff);
830 pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__, port, regnum, *val, err);
831
832 mutex_unlock(&smi_lock);
833
834 return err;
835 }
836
837 /* Calculate both the block 0 and the block 1 hash, and return in
838 * lower and higher word of the return value since only 12 bit of
839 * the hash are significant
840 */
841 u32 rtl930x_hash(struct rtl838x_switch_priv *priv, u64 seed)
842 {
843 u32 k0, k1, h1, h2, h;
844
845 k0 = (u32) (((seed >> 55) & 0x1f) ^
846 ((seed >> 44) & 0x7ff) ^
847 ((seed >> 33) & 0x7ff) ^
848 ((seed >> 22) & 0x7ff) ^
849 ((seed >> 11) & 0x7ff) ^
850 (seed & 0x7ff));
851
852 h1 = (seed >> 11) & 0x7ff;
853 h1 = ((h1 & 0x1f) << 6) | ((h1 >> 5) & 0x3f);
854
855 h2 = (seed >> 33) & 0x7ff;
856 h2 = ((h2 & 0x3f) << 5) | ((h2 >> 6) & 0x3f);
857
858 k1 = (u32) (((seed << 55) & 0x1f) ^
859 ((seed >> 44) & 0x7ff) ^
860 h2 ^
861 ((seed >> 22) & 0x7ff) ^
862 h1 ^
863 (seed & 0x7ff));
864
865 /* Algorithm choice for block 0 */
866 if (sw_r32(RTL930X_L2_CTRL) & BIT(0))
867 h = k1;
868 else
869 h = k0;
870
871 /* Algorithm choice for block 1
872 * Since k0 and k1 are < 2048, adding 2048 will offset the hash into the second
873 * half of hash-space
874 * 2048 is in fact the hash-table size 16384 divided by 4 hashes per bucket
875 * divided by 2 to divide the hash space in 2
876 */
877 if (sw_r32(RTL930X_L2_CTRL) & BIT(1))
878 h |= (k1 + 2048) << 16;
879 else
880 h |= (k0 + 2048) << 16;
881
882 return h;
883 }
884
885 /* Enables or disables the EEE/EEEP capability of a port */
886 void rtl930x_port_eee_set(struct rtl838x_switch_priv *priv, int port, bool enable)
887 {
888 u32 v;
889
890 /* This works only for Ethernet ports, and on the RTL930X, ports from 26 are SFP */
891 if (port >= 26)
892 return;
893
894 pr_debug("In %s: setting port %d to %d\n", __func__, port, enable);
895 v = enable ? 0x3f : 0x0;
896
897 /* Set EEE/EEEP state for 100, 500, 1000MBit and 2.5, 5 and 10GBit */
898 sw_w32_mask(0, v << 10, rtl930x_mac_force_mode_ctrl(port));
899
900 /* Set TX/RX EEE state */
901 v = enable ? 0x3 : 0x0;
902 sw_w32(v, RTL930X_EEE_CTRL(port));
903
904 priv->ports[port].eee_enabled = enable;
905 }
906
907 /* Get EEE own capabilities and negotiation result */
908 int rtl930x_eee_port_ability(struct rtl838x_switch_priv *priv, struct ethtool_eee *e, int port)
909 {
910 u32 link, a;
911
912 if (port >= 26)
913 return -ENOTSUPP;
914
915 pr_info("In %s, port %d\n", __func__, port);
916 link = sw_r32(RTL930X_MAC_LINK_STS);
917 link = sw_r32(RTL930X_MAC_LINK_STS);
918 if (!(link & BIT(port)))
919 return 0;
920
921 pr_info("Setting advertised\n");
922 if (sw_r32(rtl930x_mac_force_mode_ctrl(port)) & BIT(10))
923 e->advertised |= ADVERTISED_100baseT_Full;
924
925 if (sw_r32(rtl930x_mac_force_mode_ctrl(port)) & BIT(12))
926 e->advertised |= ADVERTISED_1000baseT_Full;
927
928 if (priv->ports[port].is2G5 && sw_r32(rtl930x_mac_force_mode_ctrl(port)) & BIT(13)) {
929 pr_info("ADVERTISING 2.5G EEE\n");
930 e->advertised |= ADVERTISED_2500baseX_Full;
931 }
932
933 if (priv->ports[port].is10G && sw_r32(rtl930x_mac_force_mode_ctrl(port)) & BIT(15))
934 e->advertised |= ADVERTISED_10000baseT_Full;
935
936 a = sw_r32(RTL930X_MAC_EEE_ABLTY);
937 a = sw_r32(RTL930X_MAC_EEE_ABLTY);
938 pr_info("Link partner: %08x\n", a);
939 if (a & BIT(port)) {
940 e->lp_advertised = ADVERTISED_100baseT_Full;
941 e->lp_advertised |= ADVERTISED_1000baseT_Full;
942 if (priv->ports[port].is2G5)
943 e->lp_advertised |= ADVERTISED_2500baseX_Full;
944 if (priv->ports[port].is10G)
945 e->lp_advertised |= ADVERTISED_10000baseT_Full;
946 }
947
948 /* Read 2x to clear latched state */
949 a = sw_r32(RTL930X_EEEP_PORT_CTRL(port));
950 a = sw_r32(RTL930X_EEEP_PORT_CTRL(port));
951 pr_info("%s RTL930X_EEEP_PORT_CTRL: %08x\n", __func__, a);
952
953 return 0;
954 }
955
956 static void rtl930x_init_eee(struct rtl838x_switch_priv *priv, bool enable)
957 {
958 pr_info("Setting up EEE, state: %d\n", enable);
959
960 /* Setup EEE on all ports */
961 for (int i = 0; i < priv->cpu_port; i++) {
962 if (priv->ports[i].phy)
963 rtl930x_port_eee_set(priv, i, enable);
964 }
965
966 priv->eee_enabled = enable;
967 }
968 #define HASH_PICK(val, lsb, len) ((val & (((1 << len) - 1) << lsb)) >> lsb)
969
970 static u32 rtl930x_l3_hash4(u32 ip, int algorithm, bool move_dip)
971 {
972 u32 rows[4];
973 u32 hash;
974 u32 s0, s1, pH;
975
976 memset(rows, 0, sizeof(rows));
977
978 rows[0] = HASH_PICK(ip, 27, 5);
979 rows[1] = HASH_PICK(ip, 18, 9);
980 rows[2] = HASH_PICK(ip, 9, 9);
981
982 if (!move_dip)
983 rows[3] = HASH_PICK(ip, 0, 9);
984
985 if (!algorithm) {
986 hash = rows[0] ^ rows[1] ^ rows[2] ^ rows[3];
987 } else {
988 s0 = rows[0] + rows[1] + rows[2];
989 s1 = (s0 & 0x1ff) + ((s0 & (0x1ff << 9)) >> 9);
990 pH = (s1 & 0x1ff) + ((s1 & (0x1ff << 9)) >> 9);
991 hash = pH ^ rows[3];
992 }
993 return hash;
994 }
995
996 // Currently not used
997 // static u32 rtl930x_l3_hash6(struct in6_addr *ip6, int algorithm, bool move_dip)
998 // {
999 // u32 rows[16];
1000 // u32 hash;
1001 // u32 s0, s1, pH;
1002
1003 // rows[0] = (HASH_PICK(ip6->s6_addr[0], 6, 2) << 0);
1004 // rows[1] = (HASH_PICK(ip6->s6_addr[0], 0, 6) << 3) | HASH_PICK(ip6->s6_addr[1], 5, 3);
1005 // rows[2] = (HASH_PICK(ip6->s6_addr[1], 0, 5) << 4) | HASH_PICK(ip6->s6_addr[2], 4, 4);
1006 // rows[3] = (HASH_PICK(ip6->s6_addr[2], 0, 4) << 5) | HASH_PICK(ip6->s6_addr[3], 3, 5);
1007 // rows[4] = (HASH_PICK(ip6->s6_addr[3], 0, 3) << 6) | HASH_PICK(ip6->s6_addr[4], 2, 6);
1008 // rows[5] = (HASH_PICK(ip6->s6_addr[4], 0, 2) << 7) | HASH_PICK(ip6->s6_addr[5], 1, 7);
1009 // rows[6] = (HASH_PICK(ip6->s6_addr[5], 0, 1) << 8) | HASH_PICK(ip6->s6_addr[6], 0, 8);
1010 // rows[7] = (HASH_PICK(ip6->s6_addr[7], 0, 8) << 1) | HASH_PICK(ip6->s6_addr[8], 7, 1);
1011 // rows[8] = (HASH_PICK(ip6->s6_addr[8], 0, 7) << 2) | HASH_PICK(ip6->s6_addr[9], 6, 2);
1012 // rows[9] = (HASH_PICK(ip6->s6_addr[9], 0, 6) << 3) | HASH_PICK(ip6->s6_addr[10], 5, 3);
1013 // rows[10] = (HASH_PICK(ip6->s6_addr[10], 0, 5) << 4) | HASH_PICK(ip6->s6_addr[11], 4, 4);
1014 // if (!algorithm) {
1015 // rows[11] = (HASH_PICK(ip6->s6_addr[11], 0, 4) << 5) |
1016 // (HASH_PICK(ip6->s6_addr[12], 3, 5) << 0);
1017 // rows[12] = (HASH_PICK(ip6->s6_addr[12], 0, 3) << 6) |
1018 // (HASH_PICK(ip6->s6_addr[13], 2, 6) << 0);
1019 // rows[13] = (HASH_PICK(ip6->s6_addr[13], 0, 2) << 7) |
1020 // (HASH_PICK(ip6->s6_addr[14], 1, 7) << 0);
1021 // if (!move_dip) {
1022 // rows[14] = (HASH_PICK(ip6->s6_addr[14], 0, 1) << 8) |
1023 // (HASH_PICK(ip6->s6_addr[15], 0, 8) << 0);
1024 // }
1025 // hash = rows[0] ^ rows[1] ^ rows[2] ^ rows[3] ^ rows[4] ^
1026 // rows[5] ^ rows[6] ^ rows[7] ^ rows[8] ^ rows[9] ^
1027 // rows[10] ^ rows[11] ^ rows[12] ^ rows[13] ^ rows[14];
1028 // } else {
1029 // rows[11] = (HASH_PICK(ip6->s6_addr[11], 0, 4) << 5);
1030 // rows[12] = (HASH_PICK(ip6->s6_addr[12], 3, 5) << 0);
1031 // rows[13] = (HASH_PICK(ip6->s6_addr[12], 0, 3) << 6) |
1032 // HASH_PICK(ip6->s6_addr[13], 2, 6);
1033 // rows[14] = (HASH_PICK(ip6->s6_addr[13], 0, 2) << 7) |
1034 // HASH_PICK(ip6->s6_addr[14], 1, 7);
1035 // if (!move_dip) {
1036 // rows[15] = (HASH_PICK(ip6->s6_addr[14], 0, 1) << 8) |
1037 // (HASH_PICK(ip6->s6_addr[15], 0, 8) << 0);
1038 // }
1039 // s0 = rows[12] + rows[13] + rows[14];
1040 // s1 = (s0 & 0x1ff) + ((s0 & (0x1ff << 9)) >> 9);
1041 // pH = (s1 & 0x1ff) + ((s1 & (0x1ff << 9)) >> 9);
1042 // hash = rows[0] ^ rows[1] ^ rows[2] ^ rows[3] ^ rows[4] ^
1043 // rows[5] ^ rows[6] ^ rows[7] ^ rows[8] ^ rows[9] ^
1044 // rows[10] ^ rows[11] ^ pH ^ rows[15];
1045 // }
1046 // return hash;
1047 // }
1048
1049 /* Read a prefix route entry from the L3_PREFIX_ROUTE_IPUC table
1050 * We currently only support IPv4 and IPv6 unicast route
1051 */
1052 static void rtl930x_route_read(int idx, struct rtl83xx_route *rt)
1053 {
1054 u32 v, ip4_m;
1055 bool host_route, default_route;
1056 struct in6_addr ip6_m;
1057
1058 /* Read L3_PREFIX_ROUTE_IPUC table (2) via register RTL9300_TBL_1 */
1059 struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 2);
1060
1061 rtl_table_read(r, idx);
1062 /* The table has a size of 11 registers */
1063 rt->attr.valid = !!(sw_r32(rtl_table_data(r, 0)) & BIT(31));
1064 if (!rt->attr.valid)
1065 goto out;
1066
1067 rt->attr.type = (sw_r32(rtl_table_data(r, 0)) >> 29) & 0x3;
1068
1069 v = sw_r32(rtl_table_data(r, 10));
1070 host_route = !!(v & BIT(21));
1071 default_route = !!(v & BIT(20));
1072 rt->prefix_len = -1;
1073 pr_info("%s: host route %d, default_route %d\n", __func__, host_route, default_route);
1074
1075 switch (rt->attr.type) {
1076 case 0: /* IPv4 Unicast route */
1077 rt->dst_ip = sw_r32(rtl_table_data(r, 4));
1078 ip4_m = sw_r32(rtl_table_data(r, 9));
1079 pr_info("%s: Read ip4 mask: %08x\n", __func__, ip4_m);
1080 rt->prefix_len = host_route ? 32 : -1;
1081 rt->prefix_len = (rt->prefix_len < 0 && default_route) ? 0 : -1;
1082 if (rt->prefix_len < 0)
1083 rt->prefix_len = inet_mask_len(ip4_m);
1084 break;
1085 case 2: /* IPv6 Unicast route */
1086 ipv6_addr_set(&rt->dst_ip6,
1087 sw_r32(rtl_table_data(r, 1)), sw_r32(rtl_table_data(r, 2)),
1088 sw_r32(rtl_table_data(r, 3)), sw_r32(rtl_table_data(r, 4)));
1089 ipv6_addr_set(&ip6_m,
1090 sw_r32(rtl_table_data(r, 6)), sw_r32(rtl_table_data(r, 7)),
1091 sw_r32(rtl_table_data(r, 8)), sw_r32(rtl_table_data(r, 9)));
1092 rt->prefix_len = host_route ? 128 : 0;
1093 rt->prefix_len = (rt->prefix_len < 0 && default_route) ? 0 : -1;
1094 if (rt->prefix_len < 0)
1095 rt->prefix_len = find_last_bit((unsigned long int *)&ip6_m.s6_addr32,
1096 128);
1097 break;
1098 case 1: /* IPv4 Multicast route */
1099 case 3: /* IPv6 Multicast route */
1100 pr_warn("%s: route type not supported\n", __func__);
1101 goto out;
1102 }
1103
1104 rt->attr.hit = !!(v & BIT(22));
1105 rt->attr.action = (v >> 18) & 3;
1106 rt->nh.id = (v >> 7) & 0x7ff;
1107 rt->attr.ttl_dec = !!(v & BIT(6));
1108 rt->attr.ttl_check = !!(v & BIT(5));
1109 rt->attr.dst_null = !!(v & BIT(4));
1110 rt->attr.qos_as = !!(v & BIT(3));
1111 rt->attr.qos_prio = v & 0x7;
1112 pr_info("%s: index %d is valid: %d\n", __func__, idx, rt->attr.valid);
1113 pr_info("%s: next_hop: %d, hit: %d, action :%d, ttl_dec %d, ttl_check %d, dst_null %d\n",
1114 __func__, rt->nh.id, rt->attr.hit, rt->attr.action,
1115 rt->attr.ttl_dec, rt->attr.ttl_check, rt->attr.dst_null);
1116 pr_info("%s: GW: %pI4, prefix_len: %d\n", __func__, &rt->dst_ip, rt->prefix_len);
1117 out:
1118 rtl_table_release(r);
1119 }
1120
1121 static void rtl930x_net6_mask(int prefix_len, struct in6_addr *ip6_m)
1122 {
1123 int o, b;
1124 /* Define network mask */
1125 o = prefix_len >> 3;
1126 b = prefix_len & 0x7;
1127 memset(ip6_m->s6_addr, 0xff, o);
1128 ip6_m->s6_addr[o] |= b ? 0xff00 >> b : 0x00;
1129 }
1130
1131 /* Read a host route entry from the table using its index
1132 * We currently only support IPv4 and IPv6 unicast route
1133 */
1134 static void rtl930x_host_route_read(int idx, struct rtl83xx_route *rt)
1135 {
1136 u32 v;
1137 /* Read L3_HOST_ROUTE_IPUC table (1) via register RTL9300_TBL_1 */
1138 struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 1);
1139
1140 idx = ((idx / 6) * 8) + (idx % 6);
1141
1142 pr_debug("In %s, physical index %d\n", __func__, idx);
1143 rtl_table_read(r, idx);
1144 /* The table has a size of 5 (for UC, 11 for MC) registers */
1145 v = sw_r32(rtl_table_data(r, 0));
1146 rt->attr.valid = !!(v & BIT(31));
1147 if (!rt->attr.valid)
1148 goto out;
1149 rt->attr.type = (v >> 29) & 0x3;
1150 switch (rt->attr.type) {
1151 case 0: /* IPv4 Unicast route */
1152 rt->dst_ip = sw_r32(rtl_table_data(r, 4));
1153 break;
1154 case 2: /* IPv6 Unicast route */
1155 ipv6_addr_set(&rt->dst_ip6,
1156 sw_r32(rtl_table_data(r, 3)), sw_r32(rtl_table_data(r, 2)),
1157 sw_r32(rtl_table_data(r, 1)), sw_r32(rtl_table_data(r, 0)));
1158 break;
1159 case 1: /* IPv4 Multicast route */
1160 case 3: /* IPv6 Multicast route */
1161 pr_warn("%s: route type not supported\n", __func__);
1162 goto out;
1163 }
1164
1165 rt->attr.hit = !!(v & BIT(20));
1166 rt->attr.dst_null = !!(v & BIT(19));
1167 rt->attr.action = (v >> 17) & 3;
1168 rt->nh.id = (v >> 6) & 0x7ff;
1169 rt->attr.ttl_dec = !!(v & BIT(5));
1170 rt->attr.ttl_check = !!(v & BIT(4));
1171 rt->attr.qos_as = !!(v & BIT(3));
1172 rt->attr.qos_prio = v & 0x7;
1173 pr_debug("%s: index %d is valid: %d\n", __func__, idx, rt->attr.valid);
1174 pr_debug("%s: next_hop: %d, hit: %d, action :%d, ttl_dec %d, ttl_check %d, dst_null %d\n",
1175 __func__, rt->nh.id, rt->attr.hit, rt->attr.action, rt->attr.ttl_dec, rt->attr.ttl_check,
1176 rt->attr.dst_null);
1177 pr_debug("%s: Destination: %pI4\n", __func__, &rt->dst_ip);
1178
1179 out:
1180 rtl_table_release(r);
1181 }
1182
1183 /* Write a host route entry from the table using its index
1184 * We currently only support IPv4 and IPv6 unicast route
1185 */
1186 static void rtl930x_host_route_write(int idx, struct rtl83xx_route *rt)
1187 {
1188 u32 v;
1189 /* Access L3_HOST_ROUTE_IPUC table (1) via register RTL9300_TBL_1 */
1190 struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 1);
1191 /* The table has a size of 5 (for UC, 11 for MC) registers */
1192
1193 idx = ((idx / 6) * 8) + (idx % 6);
1194
1195 pr_debug("%s: index %d is valid: %d\n", __func__, idx, rt->attr.valid);
1196 pr_debug("%s: next_hop: %d, hit: %d, action :%d, ttl_dec %d, ttl_check %d, dst_null %d\n",
1197 __func__, rt->nh.id, rt->attr.hit, rt->attr.action, rt->attr.ttl_dec, rt->attr.ttl_check,
1198 rt->attr.dst_null);
1199 pr_debug("%s: GW: %pI4, prefix_len: %d\n", __func__, &rt->dst_ip, rt->prefix_len);
1200
1201 v = BIT(31); /* Entry is valid */
1202 v |= (rt->attr.type & 0x3) << 29;
1203 v |= rt->attr.hit ? BIT(20) : 0;
1204 v |= rt->attr.dst_null ? BIT(19) : 0;
1205 v |= (rt->attr.action & 0x3) << 17;
1206 v |= (rt->nh.id & 0x7ff) << 6;
1207 v |= rt->attr.ttl_dec ? BIT(5) : 0;
1208 v |= rt->attr.ttl_check ? BIT(4) : 0;
1209 v |= rt->attr.qos_as ? BIT(3) : 0;
1210 v |= rt->attr.qos_prio & 0x7;
1211
1212 sw_w32(v, rtl_table_data(r, 0));
1213 switch (rt->attr.type) {
1214 case 0: /* IPv4 Unicast route */
1215 sw_w32(0, rtl_table_data(r, 1));
1216 sw_w32(0, rtl_table_data(r, 2));
1217 sw_w32(0, rtl_table_data(r, 3));
1218 sw_w32(rt->dst_ip, rtl_table_data(r, 4));
1219 break;
1220 case 2: /* IPv6 Unicast route */
1221 sw_w32(rt->dst_ip6.s6_addr32[0], rtl_table_data(r, 1));
1222 sw_w32(rt->dst_ip6.s6_addr32[1], rtl_table_data(r, 2));
1223 sw_w32(rt->dst_ip6.s6_addr32[2], rtl_table_data(r, 3));
1224 sw_w32(rt->dst_ip6.s6_addr32[3], rtl_table_data(r, 4));
1225 break;
1226 case 1: /* IPv4 Multicast route */
1227 case 3: /* IPv6 Multicast route */
1228 pr_warn("%s: route type not supported\n", __func__);
1229 goto out;
1230 }
1231
1232 rtl_table_write(r, idx);
1233
1234 out:
1235 rtl_table_release(r);
1236 }
1237
1238 /* Look up the index of a prefix route in the routing table CAM for unicast IPv4/6 routes
1239 * using hardware offload.
1240 */
1241 static int rtl930x_route_lookup_hw(struct rtl83xx_route *rt)
1242 {
1243 u32 ip4_m, v;
1244 struct in6_addr ip6_m;
1245
1246 if (rt->attr.type == 1 || rt->attr.type == 3) /* Hardware only supports UC routes */
1247 return -1;
1248
1249 sw_w32_mask(0x3 << 19, rt->attr.type, RTL930X_L3_HW_LU_KEY_CTRL);
1250 if (rt->attr.type) { /* IPv6 */
1251 rtl930x_net6_mask(rt->prefix_len, &ip6_m);
1252 for (int i = 0; i < 4; i++)
1253 sw_w32(rt->dst_ip6.s6_addr32[0] & ip6_m.s6_addr32[0],
1254 RTL930X_L3_HW_LU_KEY_IP_CTRL + (i << 2));
1255 } else { /* IPv4 */
1256 ip4_m = inet_make_mask(rt->prefix_len);
1257 sw_w32(0, RTL930X_L3_HW_LU_KEY_IP_CTRL);
1258 sw_w32(0, RTL930X_L3_HW_LU_KEY_IP_CTRL + 4);
1259 sw_w32(0, RTL930X_L3_HW_LU_KEY_IP_CTRL + 8);
1260 v = rt->dst_ip & ip4_m;
1261 pr_info("%s: searching for %pI4\n", __func__, &v);
1262 sw_w32(v, RTL930X_L3_HW_LU_KEY_IP_CTRL + 12);
1263 }
1264
1265 /* Execute CAM lookup in SoC */
1266 sw_w32(BIT(15), RTL930X_L3_HW_LU_CTRL);
1267
1268 /* Wait until execute bit clears and result is ready */
1269 do {
1270 v = sw_r32(RTL930X_L3_HW_LU_CTRL);
1271 } while (v & BIT(15));
1272
1273 pr_info("%s: found: %d, index: %d\n", __func__, !!(v & BIT(14)), v & 0x1ff);
1274
1275 /* Test if search successful (BIT 14 set) */
1276 if (v & BIT(14))
1277 return v & 0x1ff;
1278
1279 return -1;
1280 }
1281
1282 static int rtl930x_find_l3_slot(struct rtl83xx_route *rt, bool must_exist)
1283 {
1284 int slot_width, algorithm, addr, idx;
1285 u32 hash;
1286 struct rtl83xx_route route_entry;
1287
1288 /* IPv6 entries take up 3 slots */
1289 slot_width = (rt->attr.type == 0) || (rt->attr.type == 2) ? 1 : 3;
1290
1291 for (int t = 0; t < 2; t++) {
1292 algorithm = (sw_r32(RTL930X_L3_HOST_TBL_CTRL) >> (2 + t)) & 0x1;
1293 hash = rtl930x_l3_hash4(rt->dst_ip, algorithm, false);
1294
1295 pr_debug("%s: table %d, algorithm %d, hash %04x\n", __func__, t, algorithm, hash);
1296
1297 for (int s = 0; s < 6; s += slot_width) {
1298 addr = (t << 12) | ((hash & 0x1ff) << 3) | s;
1299 pr_debug("%s physical address %d\n", __func__, addr);
1300 idx = ((addr / 8) * 6) + (addr % 8);
1301 pr_debug("%s logical address %d\n", __func__, idx);
1302
1303 rtl930x_host_route_read(idx, &route_entry);
1304 pr_debug("%s route valid %d, route dest: %pI4, hit %d\n", __func__,
1305 rt->attr.valid, &rt->dst_ip, rt->attr.hit);
1306 if (!must_exist && rt->attr.valid)
1307 return idx;
1308 if (must_exist && route_entry.dst_ip == rt->dst_ip)
1309 return idx;
1310 }
1311 }
1312
1313 return -1;
1314 }
1315
1316 /* Write a prefix route into the routing table CAM at position idx
1317 * Currently only IPv4 and IPv6 unicast routes are supported
1318 */
1319 static void rtl930x_route_write(int idx, struct rtl83xx_route *rt)
1320 {
1321 u32 v, ip4_m;
1322 struct in6_addr ip6_m;
1323 /* Access L3_PREFIX_ROUTE_IPUC table (2) via register RTL9300_TBL_1 */
1324 /* The table has a size of 11 registers (20 for MC) */
1325 struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 2);
1326
1327 pr_debug("%s: index %d is valid: %d\n", __func__, idx, rt->attr.valid);
1328 pr_debug("%s: nexthop: %d, hit: %d, action :%d, ttl_dec %d, ttl_check %d, dst_null %d\n",
1329 __func__, rt->nh.id, rt->attr.hit, rt->attr.action,
1330 rt->attr.ttl_dec, rt->attr.ttl_check, rt->attr.dst_null);
1331 pr_debug("%s: GW: %pI4, prefix_len: %d\n", __func__, &rt->dst_ip, rt->prefix_len);
1332
1333 v = rt->attr.valid ? BIT(31) : 0;
1334 v |= (rt->attr.type & 0x3) << 29;
1335 sw_w32(v, rtl_table_data(r, 0));
1336
1337 v = rt->attr.hit ? BIT(22) : 0;
1338 v |= (rt->attr.action & 0x3) << 18;
1339 v |= (rt->nh.id & 0x7ff) << 7;
1340 v |= rt->attr.ttl_dec ? BIT(6) : 0;
1341 v |= rt->attr.ttl_check ? BIT(5) : 0;
1342 v |= rt->attr.dst_null ? BIT(6) : 0;
1343 v |= rt->attr.qos_as ? BIT(6) : 0;
1344 v |= rt->attr.qos_prio & 0x7;
1345 v |= rt->prefix_len == 0 ? BIT(20) : 0; /* set default route bit */
1346
1347 /* set bit mask for entry type always to 0x3 */
1348 sw_w32(0x3 << 29, rtl_table_data(r, 5));
1349
1350 switch (rt->attr.type) {
1351 case 0: /* IPv4 Unicast route */
1352 sw_w32(0, rtl_table_data(r, 1));
1353 sw_w32(0, rtl_table_data(r, 2));
1354 sw_w32(0, rtl_table_data(r, 3));
1355 sw_w32(rt->dst_ip, rtl_table_data(r, 4));
1356
1357 v |= rt->prefix_len == 32 ? BIT(21) : 0; /* set host-route bit */
1358 ip4_m = inet_make_mask(rt->prefix_len);
1359 sw_w32(0, rtl_table_data(r, 6));
1360 sw_w32(0, rtl_table_data(r, 7));
1361 sw_w32(0, rtl_table_data(r, 8));
1362 sw_w32(ip4_m, rtl_table_data(r, 9));
1363 break;
1364 case 2: /* IPv6 Unicast route */
1365 sw_w32(rt->dst_ip6.s6_addr32[0], rtl_table_data(r, 1));
1366 sw_w32(rt->dst_ip6.s6_addr32[1], rtl_table_data(r, 2));
1367 sw_w32(rt->dst_ip6.s6_addr32[2], rtl_table_data(r, 3));
1368 sw_w32(rt->dst_ip6.s6_addr32[3], rtl_table_data(r, 4));
1369
1370 v |= rt->prefix_len == 128 ? BIT(21) : 0; /* set host-route bit */
1371
1372 rtl930x_net6_mask(rt->prefix_len, &ip6_m);
1373
1374 sw_w32(ip6_m.s6_addr32[0], rtl_table_data(r, 6));
1375 sw_w32(ip6_m.s6_addr32[1], rtl_table_data(r, 7));
1376 sw_w32(ip6_m.s6_addr32[2], rtl_table_data(r, 8));
1377 sw_w32(ip6_m.s6_addr32[3], rtl_table_data(r, 9));
1378 break;
1379 case 1: /* IPv4 Multicast route */
1380 case 3: /* IPv6 Multicast route */
1381 pr_warn("%s: route type not supported\n", __func__);
1382 rtl_table_release(r);
1383 return;
1384 }
1385 sw_w32(v, rtl_table_data(r, 10));
1386
1387 pr_debug("%s: %08x %08x %08x %08x %08x %08x %08x %08x %08x %08x %08x\n", __func__,
1388 sw_r32(rtl_table_data(r, 0)), sw_r32(rtl_table_data(r, 1)), sw_r32(rtl_table_data(r, 2)),
1389 sw_r32(rtl_table_data(r, 3)), sw_r32(rtl_table_data(r, 4)), sw_r32(rtl_table_data(r, 5)),
1390 sw_r32(rtl_table_data(r, 6)), sw_r32(rtl_table_data(r, 7)), sw_r32(rtl_table_data(r, 8)),
1391 sw_r32(rtl_table_data(r, 9)), sw_r32(rtl_table_data(r, 10)));
1392
1393 rtl_table_write(r, idx);
1394 rtl_table_release(r);
1395 }
1396
1397
1398 /* Get the destination MAC and L3 egress interface ID of a nexthop entry from
1399 * the SoC's L3_NEXTHOP table
1400 */
1401 static void rtl930x_get_l3_nexthop(int idx, u16 *dmac_id, u16 *interface)
1402 {
1403 u32 v;
1404 /* Read L3_NEXTHOP table (3) via register RTL9300_TBL_1 */
1405 struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 3);
1406
1407 rtl_table_read(r, idx);
1408 /* The table has a size of 1 register */
1409 v = sw_r32(rtl_table_data(r, 0));
1410 rtl_table_release(r);
1411
1412 *dmac_id = (v >> 7) & 0x7fff;
1413 *interface = v & 0x7f;
1414 }
1415
1416 // Currently not used
1417 // static int rtl930x_l3_mtu_del(struct rtl838x_switch_priv *priv, int mtu)
1418 // {
1419 // int i;
1420
1421 // for (i = 0; i < MAX_INTF_MTUS; i++) {
1422 // if (mtu == priv->intf_mtus[i])
1423 // break;
1424 // }
1425 // if (i >= MAX_INTF_MTUS || !priv->intf_mtu_count[i]) {
1426 // pr_err("%s: No MTU slot found for MTU: %d\n", __func__, mtu);
1427 // return -EINVAL;
1428 // }
1429
1430 // priv->intf_mtu_count[i]--;
1431 // }
1432
1433 // Currently not used
1434 // static int rtl930x_l3_mtu_add(struct rtl838x_switch_priv *priv, int mtu)
1435 // {
1436 // int i, free_mtu;
1437 // int mtu_id;
1438
1439 // /* Try to find an existing mtu-value or a free slot */
1440 // free_mtu = MAX_INTF_MTUS;
1441 // for (i = 0; i < MAX_INTF_MTUS && priv->intf_mtus[i] != mtu; i++) {
1442 // if ((!priv->intf_mtu_count[i]) && (free_mtu == MAX_INTF_MTUS))
1443 // free_mtu = i;
1444 // }
1445 // i = (i < MAX_INTF_MTUS) ? i : free_mtu;
1446 // if (i < MAX_INTF_MTUS) {
1447 // mtu_id = i;
1448 // } else {
1449 // pr_err("%s: No free MTU slot available!\n", __func__);
1450 // return -EINVAL;
1451 // }
1452
1453 // priv->intf_mtus[i] = mtu;
1454 // pr_info("Writing MTU %d to slot %d\n", priv->intf_mtus[i], i);
1455 // /* Set MTU-value of the slot TODO: distinguish between IPv4/IPv6 routes / slots */
1456 // sw_w32_mask(0xffff << ((i % 2) * 16), priv->intf_mtus[i] << ((i % 2) * 16),
1457 // RTL930X_L3_IP_MTU_CTRL(i));
1458 // sw_w32_mask(0xffff << ((i % 2) * 16), priv->intf_mtus[i] << ((i % 2) * 16),
1459 // RTL930X_L3_IP6_MTU_CTRL(i));
1460
1461 // priv->intf_mtu_count[i]++;
1462
1463 // return mtu_id;
1464 // }
1465
1466
1467 // Currently not used
1468 // /* Creates an interface for a route by setting up the HW tables in the SoC
1469 // static int rtl930x_l3_intf_add(struct rtl838x_switch_priv *priv, struct rtl838x_l3_intf *intf)
1470 // {
1471 // int i, intf_id, mtu_id;
1472 // /* number of MTU-values < 16384 *\/
1473
1474 // /* Use the same IPv6 mtu as the ip4 mtu for this route if unset */
1475 // intf->ip6_mtu = intf->ip6_mtu ? intf->ip6_mtu : intf->ip4_mtu;
1476
1477 // mtu_id = rtl930x_l3_mtu_add(priv, intf->ip4_mtu);
1478 // pr_info("%s: added mtu %d with mtu-id %d\n", __func__, intf->ip4_mtu, mtu_id);
1479 // if (mtu_id < 0)
1480 // return -ENOSPC;
1481 // intf->ip4_mtu_id = mtu_id;
1482 // intf->ip6_mtu_id = mtu_id;
1483
1484 // for (i = 0; i < MAX_INTERFACES; i++) {
1485 // if (!priv->interfaces[i])
1486 // break;
1487 // }
1488 // if (i >= MAX_INTERFACES) {
1489 // pr_err("%s: cannot find free interface entry\n", __func__);
1490 // return -EINVAL;
1491 // }
1492 // intf_id = i;
1493 // priv->interfaces[i] = kzalloc(sizeof(struct rtl838x_l3_intf), GFP_KERNEL);
1494 // if (!priv->interfaces[i]) {
1495 // pr_err("%s: no memory to allocate new interface\n", __func__);
1496 // return -ENOMEM;
1497 // }
1498 // }
1499
1500 /* Set the destination MAC and L3 egress interface ID for a nexthop entry in the SoC's
1501 * L3_NEXTHOP table. The nexthop entry is identified by idx.
1502 * dmac_id is the reference to the L2 entry in the L2 forwarding table, special values are
1503 * 0x7ffe: TRAP2CPU
1504 * 0x7ffd: TRAP2MASTERCPU
1505 * 0x7fff: DMAC_ID_DROP
1506 */
1507 static void rtl930x_set_l3_nexthop(int idx, u16 dmac_id, u16 interface)
1508 {
1509 /* Access L3_NEXTHOP table (3) via register RTL9300_TBL_1 */
1510 struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 3);
1511
1512 pr_info("%s: Writing to L3_NEXTHOP table, index %d, dmac_id %d, interface %d\n",
1513 __func__, idx, dmac_id, interface);
1514 sw_w32(((dmac_id & 0x7fff) << 7) | (interface & 0x7f), rtl_table_data(r, 0));
1515
1516 pr_info("%s: %08x\n", __func__, sw_r32(rtl_table_data(r,0)));
1517 rtl_table_write(r, idx);
1518 rtl_table_release(r);
1519 }
1520
1521 static void rtl930x_pie_lookup_enable(struct rtl838x_switch_priv *priv, int index)
1522 {
1523 int block = index / PIE_BLOCK_SIZE;
1524
1525 sw_w32_mask(0, BIT(block), RTL930X_PIE_BLK_LOOKUP_CTRL);
1526 }
1527
1528 /* Reads the intermediate representation of the templated match-fields of the
1529 * PIE rule in the pie_rule structure and fills in the raw data fields in the
1530 * raw register space r[].
1531 * The register space configuration size is identical for the RTL8380/90 and RTL9300,
1532 * however the RTL9310 has 2 more registers / fields and the physical field-ids are different
1533 * on all SoCs
1534 * On the RTL9300 the mask fields are not word-aligend!
1535 */
1536 static void rtl930x_write_pie_templated(u32 r[], struct pie_rule *pr, enum template_field_id t[])
1537 {
1538 for (int i = 0; i < N_FIXED_FIELDS; i++) {
1539 enum template_field_id field_type = t[i];
1540 u16 data = 0, data_m = 0;
1541
1542 switch (field_type) {
1543 case TEMPLATE_FIELD_SPM0:
1544 data = pr->spm;
1545 data_m = pr->spm_m;
1546 break;
1547 case TEMPLATE_FIELD_SPM1:
1548 data = pr->spm >> 16;
1549 data_m = pr->spm_m >> 16;
1550 break;
1551 case TEMPLATE_FIELD_OTAG:
1552 data = pr->otag;
1553 data_m = pr->otag_m;
1554 break;
1555 case TEMPLATE_FIELD_SMAC0:
1556 data = pr->smac[4];
1557 data = (data << 8) | pr->smac[5];
1558 data_m = pr->smac_m[4];
1559 data_m = (data_m << 8) | pr->smac_m[5];
1560 break;
1561 case TEMPLATE_FIELD_SMAC1:
1562 data = pr->smac[2];
1563 data = (data << 8) | pr->smac[3];
1564 data_m = pr->smac_m[2];
1565 data_m = (data_m << 8) | pr->smac_m[3];
1566 break;
1567 case TEMPLATE_FIELD_SMAC2:
1568 data = pr->smac[0];
1569 data = (data << 8) | pr->smac[1];
1570 data_m = pr->smac_m[0];
1571 data_m = (data_m << 8) | pr->smac_m[1];
1572 break;
1573 case TEMPLATE_FIELD_DMAC0:
1574 data = pr->dmac[4];
1575 data = (data << 8) | pr->dmac[5];
1576 data_m = pr->dmac_m[4];
1577 data_m = (data_m << 8) | pr->dmac_m[5];
1578 break;
1579 case TEMPLATE_FIELD_DMAC1:
1580 data = pr->dmac[2];
1581 data = (data << 8) | pr->dmac[3];
1582 data_m = pr->dmac_m[2];
1583 data_m = (data_m << 8) | pr->dmac_m[3];
1584 break;
1585 case TEMPLATE_FIELD_DMAC2:
1586 data = pr->dmac[0];
1587 data = (data << 8) | pr->dmac[1];
1588 data_m = pr->dmac_m[0];
1589 data_m = (data_m << 8) | pr->dmac_m[1];
1590 break;
1591 case TEMPLATE_FIELD_ETHERTYPE:
1592 data = pr->ethertype;
1593 data_m = pr->ethertype_m;
1594 break;
1595 case TEMPLATE_FIELD_ITAG:
1596 data = pr->itag;
1597 data_m = pr->itag_m;
1598 break;
1599 case TEMPLATE_FIELD_SIP0:
1600 if (pr->is_ipv6) {
1601 data = pr->sip6.s6_addr16[7];
1602 data_m = pr->sip6_m.s6_addr16[7];
1603 } else {
1604 data = pr->sip;
1605 data_m = pr->sip_m;
1606 }
1607 break;
1608 case TEMPLATE_FIELD_SIP1:
1609 if (pr->is_ipv6) {
1610 data = pr->sip6.s6_addr16[6];
1611 data_m = pr->sip6_m.s6_addr16[6];
1612 } else {
1613 data = pr->sip >> 16;
1614 data_m = pr->sip_m >> 16;
1615 }
1616 break;
1617 case TEMPLATE_FIELD_SIP2:
1618 case TEMPLATE_FIELD_SIP3:
1619 case TEMPLATE_FIELD_SIP4:
1620 case TEMPLATE_FIELD_SIP5:
1621 case TEMPLATE_FIELD_SIP6:
1622 case TEMPLATE_FIELD_SIP7:
1623 data = pr->sip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)];
1624 data_m = pr->sip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)];
1625 break;
1626 case TEMPLATE_FIELD_DIP0:
1627 if (pr->is_ipv6) {
1628 data = pr->dip6.s6_addr16[7];
1629 data_m = pr->dip6_m.s6_addr16[7];
1630 } else {
1631 data = pr->dip;
1632 data_m = pr->dip_m;
1633 }
1634 break;
1635 case TEMPLATE_FIELD_DIP1:
1636 if (pr->is_ipv6) {
1637 data = pr->dip6.s6_addr16[6];
1638 data_m = pr->dip6_m.s6_addr16[6];
1639 } else {
1640 data = pr->dip >> 16;
1641 data_m = pr->dip_m >> 16;
1642 }
1643 break;
1644 case TEMPLATE_FIELD_DIP2:
1645 case TEMPLATE_FIELD_DIP3:
1646 case TEMPLATE_FIELD_DIP4:
1647 case TEMPLATE_FIELD_DIP5:
1648 case TEMPLATE_FIELD_DIP6:
1649 case TEMPLATE_FIELD_DIP7:
1650 data = pr->dip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)];
1651 data_m = pr->dip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)];
1652 break;
1653 case TEMPLATE_FIELD_IP_TOS_PROTO:
1654 data = pr->tos_proto;
1655 data_m = pr->tos_proto_m;
1656 break;
1657 case TEMPLATE_FIELD_L4_SPORT:
1658 data = pr->sport;
1659 data_m = pr->sport_m;
1660 break;
1661 case TEMPLATE_FIELD_L4_DPORT:
1662 data = pr->dport;
1663 data_m = pr->dport_m;
1664 break;
1665 case TEMPLATE_FIELD_DSAP_SSAP:
1666 data = pr->dsap_ssap;
1667 data_m = pr->dsap_ssap_m;
1668 break;
1669 case TEMPLATE_FIELD_TCP_INFO:
1670 data = pr->tcp_info;
1671 data_m = pr->tcp_info_m;
1672 break;
1673 case TEMPLATE_FIELD_RANGE_CHK:
1674 pr_warn("Warning: TEMPLATE_FIELD_RANGE_CHK: not configured\n");
1675 break;
1676 default:
1677 pr_info("%s: unknown field %d\n", __func__, field_type);
1678 }
1679
1680 /* On the RTL9300, the mask fields are not word aligned! */
1681 if (!(i % 2)) {
1682 r[5 - i / 2] = data;
1683 r[12 - i / 2] |= ((u32)data_m << 8);
1684 } else {
1685 r[5 - i / 2] |= ((u32)data) << 16;
1686 r[12 - i / 2] |= ((u32)data_m) << 24;
1687 r[11 - i / 2] |= ((u32)data_m) >> 8;
1688 }
1689 }
1690 }
1691
1692 // Currently not used
1693 // static void rtl930x_read_pie_fixed_fields(u32 r[], struct pie_rule *pr)
1694 // {
1695 // pr->stacking_port = r[6] & BIT(31);
1696 // pr->spn = (r[6] >> 24) & 0x7f;
1697 // pr->mgnt_vlan = r[6] & BIT(23);
1698 // if (pr->phase == PHASE_IACL)
1699 // pr->dmac_hit_sw = r[6] & BIT(22);
1700 // else
1701 // pr->content_too_deep = r[6] & BIT(22);
1702 // pr->not_first_frag = r[6] & BIT(21);
1703 // pr->frame_type_l4 = (r[6] >> 18) & 7;
1704 // pr->frame_type = (r[6] >> 16) & 3;
1705 // pr->otag_fmt = (r[6] >> 15) & 1;
1706 // pr->itag_fmt = (r[6] >> 14) & 1;
1707 // pr->otag_exist = (r[6] >> 13) & 1;
1708 // pr->itag_exist = (r[6] >> 12) & 1;
1709 // pr->frame_type_l2 = (r[6] >> 10) & 3;
1710 // pr->igr_normal_port = (r[6] >> 9) & 1;
1711 // pr->tid = (r[6] >> 8) & 1;
1712
1713 // pr->stacking_port_m = r[12] & BIT(7);
1714 // pr->spn_m = r[12] & 0x7f;
1715 // pr->mgnt_vlan_m = r[13] & BIT(31);
1716 // if (pr->phase == PHASE_IACL)
1717 // pr->dmac_hit_sw_m = r[13] & BIT(30);
1718 // else
1719 // pr->content_too_deep_m = r[13] & BIT(30);
1720 // pr->not_first_frag_m = r[13] & BIT(29);
1721 // pr->frame_type_l4_m = (r[13] >> 26) & 7;
1722 // pr->frame_type_m = (r[13] >> 24) & 3;
1723 // pr->otag_fmt_m = r[13] & BIT(23);
1724 // pr->itag_fmt_m = r[13] & BIT(22);
1725 // pr->otag_exist_m = r[13] & BIT(21);
1726 // pr->itag_exist_m = r[13] & BIT (20);
1727 // pr->frame_type_l2_m = (r[13] >> 18) & 3;
1728 // pr->igr_normal_port_m = r[13] & BIT(17);
1729 // pr->tid_m = (r[13] >> 16) & 1;
1730
1731 // pr->valid = r[13] & BIT(15);
1732 // pr->cond_not = r[13] & BIT(14);
1733 // pr->cond_and1 = r[13] & BIT(13);
1734 // pr->cond_and2 = r[13] & BIT(12);
1735 // }
1736
1737 static void rtl930x_write_pie_fixed_fields(u32 r[], struct pie_rule *pr)
1738 {
1739 r[6] = pr->stacking_port ? BIT(31) : 0;
1740 r[6] |= ((u32) (pr->spn & 0x7f)) << 24;
1741 r[6] |= pr->mgnt_vlan ? BIT(23) : 0;
1742 if (pr->phase == PHASE_IACL)
1743 r[6] |= pr->dmac_hit_sw ? BIT(22) : 0;
1744 else
1745 r[6] |= pr->content_too_deep ? BIT(22) : 0;
1746 r[6] |= pr->not_first_frag ? BIT(21) : 0;
1747 r[6] |= ((u32) (pr->frame_type_l4 & 0x7)) << 18;
1748 r[6] |= ((u32) (pr->frame_type & 0x3)) << 16;
1749 r[6] |= pr->otag_fmt ? BIT(15) : 0;
1750 r[6] |= pr->itag_fmt ? BIT(14) : 0;
1751 r[6] |= pr->otag_exist ? BIT(13) : 0;
1752 r[6] |= pr->itag_exist ? BIT(12) : 0;
1753 r[6] |= ((u32) (pr->frame_type_l2 & 0x3)) << 10;
1754 r[6] |= pr->igr_normal_port ? BIT(9) : 0;
1755 r[6] |= ((u32) (pr->tid & 0x1)) << 8;
1756
1757 r[12] |= pr->stacking_port_m ? BIT(7) : 0;
1758 r[12] |= (u32) (pr->spn_m & 0x7f);
1759 r[13] |= pr->mgnt_vlan_m ? BIT(31) : 0;
1760 if (pr->phase == PHASE_IACL)
1761 r[13] |= pr->dmac_hit_sw_m ? BIT(30) : 0;
1762 else
1763 r[13] |= pr->content_too_deep_m ? BIT(30) : 0;
1764 r[13] |= pr->not_first_frag_m ? BIT(29) : 0;
1765 r[13] |= ((u32) (pr->frame_type_l4_m & 0x7)) << 26;
1766 r[13] |= ((u32) (pr->frame_type_m & 0x3)) << 24;
1767 r[13] |= pr->otag_fmt_m ? BIT(23) : 0;
1768 r[13] |= pr->itag_fmt_m ? BIT(22) : 0;
1769 r[13] |= pr->otag_exist_m ? BIT(21) : 0;
1770 r[13] |= pr->itag_exist_m ? BIT(20) : 0;
1771 r[13] |= ((u32) (pr->frame_type_l2_m & 0x3)) << 18;
1772 r[13] |= pr->igr_normal_port_m ? BIT(17) : 0;
1773 r[13] |= ((u32) (pr->tid_m & 0x1)) << 16;
1774
1775 r[13] |= pr->valid ? BIT(15) : 0;
1776 r[13] |= pr->cond_not ? BIT(14) : 0;
1777 r[13] |= pr->cond_and1 ? BIT(13) : 0;
1778 r[13] |= pr->cond_and2 ? BIT(12) : 0;
1779 }
1780
1781 static void rtl930x_write_pie_action(u32 r[], struct pie_rule *pr)
1782 {
1783 /* Either drop or forward */
1784 if (pr->drop) {
1785 r[14] |= BIT(24) | BIT(25) | BIT(26); /* Do Green, Yellow and Red drops */
1786 /* Actually DROP, not PERMIT in Green / Yellow / Red */
1787 r[14] |= BIT(23) | BIT(22) | BIT(20);
1788 } else {
1789 r[14] |= pr->fwd_sel ? BIT(27) : 0;
1790 r[14] |= pr->fwd_act << 18;
1791 r[14] |= BIT(14); /* We overwrite any drop */
1792 }
1793 if (pr->phase == PHASE_VACL)
1794 r[14] |= pr->fwd_sa_lrn ? BIT(15) : 0;
1795 r[13] |= pr->bypass_sel ? BIT(5) : 0;
1796 r[13] |= pr->nopri_sel ? BIT(4) : 0;
1797 r[13] |= pr->tagst_sel ? BIT(3) : 0;
1798 r[13] |= pr->ovid_sel ? BIT(1) : 0;
1799 r[14] |= pr->ivid_sel ? BIT(31) : 0;
1800 r[14] |= pr->meter_sel ? BIT(30) : 0;
1801 r[14] |= pr->mir_sel ? BIT(29) : 0;
1802 r[14] |= pr->log_sel ? BIT(28) : 0;
1803
1804 r[14] |= ((u32)(pr->fwd_data & 0x3fff)) << 3;
1805 r[15] |= pr->log_octets ? BIT(31) : 0;
1806 r[15] |= (u32)(pr->meter_data) << 23;
1807
1808 r[15] |= ((u32)(pr->ivid_act) << 21) & 0x3;
1809 r[15] |= ((u32)(pr->ivid_data) << 9) & 0xfff;
1810 r[16] |= ((u32)(pr->ovid_act) << 30) & 0x3;
1811 r[16] |= ((u32)(pr->ovid_data) & 0xfff) << 16;
1812 r[16] |= (pr->mir_data & 0x3) << 6;
1813 r[17] |= ((u32)(pr->tagst_data) & 0xf) << 28;
1814 r[17] |= ((u32)(pr->nopri_data) & 0x7) << 25;
1815 r[17] |= pr->bypass_ibc_sc ? BIT(16) : 0;
1816 }
1817
1818 void rtl930x_pie_rule_dump_raw(u32 r[])
1819 {
1820 pr_info("Raw IACL table entry:\n");
1821 pr_info("r 0 - 7: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1822 r[0], r[1], r[2], r[3], r[4], r[5], r[6], r[7]);
1823 pr_info("r 8 - 15: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1824 r[8], r[9], r[10], r[11], r[12], r[13], r[14], r[15]);
1825 pr_info("r 16 - 18: %08x %08x %08x\n", r[16], r[17], r[18]);
1826 pr_info("Match : %08x %08x %08x %08x %08x %08x\n", r[0], r[1], r[2], r[3], r[4], r[5]);
1827 pr_info("Fixed : %06x\n", r[6] >> 8);
1828 pr_info("Match M: %08x %08x %08x %08x %08x %08x\n",
1829 (r[6] << 24) | (r[7] >> 8), (r[7] << 24) | (r[8] >> 8), (r[8] << 24) | (r[9] >> 8),
1830 (r[9] << 24) | (r[10] >> 8), (r[10] << 24) | (r[11] >> 8),
1831 (r[11] << 24) | (r[12] >> 8));
1832 pr_info("R[13]: %08x\n", r[13]);
1833 pr_info("Fixed M: %06x\n", ((r[12] << 16) | (r[13] >> 16)) & 0xffffff);
1834 pr_info("Valid / not / and1 / and2 : %1x\n", (r[13] >> 12) & 0xf);
1835 pr_info("r 13-16: %08x %08x %08x %08x\n", r[13], r[14], r[15], r[16]);
1836 }
1837
1838 static int rtl930x_pie_rule_write(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr)
1839 {
1840 /* Access IACL table (2) via register 0 */
1841 struct table_reg *q = rtl_table_get(RTL9300_TBL_0, 2);
1842 u32 r[19];
1843 int block = idx / PIE_BLOCK_SIZE;
1844 u32 t_select = sw_r32(RTL930X_PIE_BLK_TMPLTE_CTRL(block));
1845
1846 pr_debug("%s: %d, t_select: %08x\n", __func__, idx, t_select);
1847
1848 for (int i = 0; i < 19; i++)
1849 r[i] = 0;
1850
1851 if (!pr->valid) {
1852 rtl_table_write(q, idx);
1853 rtl_table_release(q);
1854 return 0;
1855 }
1856 rtl930x_write_pie_fixed_fields(r, pr);
1857
1858 pr_debug("%s: template %d\n", __func__, (t_select >> (pr->tid * 4)) & 0xf);
1859 rtl930x_write_pie_templated(r, pr, fixed_templates[(t_select >> (pr->tid * 4)) & 0xf]);
1860
1861 rtl930x_write_pie_action(r, pr);
1862
1863 /* rtl930x_pie_rule_dump_raw(r); */
1864
1865 for (int i = 0; i < 19; i++)
1866 sw_w32(r[i], rtl_table_data(q, i));
1867
1868 rtl_table_write(q, idx);
1869 rtl_table_release(q);
1870
1871 return 0;
1872 }
1873
1874 static bool rtl930x_pie_templ_has(int t, enum template_field_id field_type)
1875 {
1876 for (int i = 0; i < N_FIXED_FIELDS; i++) {
1877 enum template_field_id ft = fixed_templates[t][i];
1878 if (field_type == ft)
1879 return true;
1880 }
1881
1882 return false;
1883 }
1884
1885 /* Verify that the rule pr is compatible with a given template t in block block
1886 * Note that this function is SoC specific since the values of e.g. TEMPLATE_FIELD_SIP0
1887 * depend on the SoC
1888 */
1889 static int rtl930x_pie_verify_template(struct rtl838x_switch_priv *priv,
1890 struct pie_rule *pr, int t, int block)
1891 {
1892 int i;
1893
1894 if (!pr->is_ipv6 && pr->sip_m && !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_SIP0))
1895 return -1;
1896
1897 if (!pr->is_ipv6 && pr->dip_m && !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_DIP0))
1898 return -1;
1899
1900 if (pr->is_ipv6) {
1901 if ((pr->sip6_m.s6_addr32[0] ||
1902 pr->sip6_m.s6_addr32[1] ||
1903 pr->sip6_m.s6_addr32[2] ||
1904 pr->sip6_m.s6_addr32[3]) &&
1905 !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_SIP2))
1906 return -1;
1907 if ((pr->dip6_m.s6_addr32[0] ||
1908 pr->dip6_m.s6_addr32[1] ||
1909 pr->dip6_m.s6_addr32[2] ||
1910 pr->dip6_m.s6_addr32[3]) &&
1911 !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_DIP2))
1912 return -1;
1913 }
1914
1915 if (ether_addr_to_u64(pr->smac) && !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_SMAC0))
1916 return -1;
1917
1918 if (ether_addr_to_u64(pr->dmac) && !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_DMAC0))
1919 return -1;
1920
1921 /* TODO: Check more */
1922
1923 i = find_first_zero_bit(&priv->pie_use_bm[block * 4], PIE_BLOCK_SIZE);
1924
1925 if (i >= PIE_BLOCK_SIZE)
1926 return -1;
1927
1928 return i + PIE_BLOCK_SIZE * block;
1929 }
1930
1931 static int rtl930x_pie_rule_add(struct rtl838x_switch_priv *priv, struct pie_rule *pr)
1932 {
1933 int idx, block, j, t;
1934 int min_block = 0;
1935 int max_block = priv->n_pie_blocks / 2;
1936
1937 if (pr->is_egress) {
1938 min_block = max_block;
1939 max_block = priv->n_pie_blocks;
1940 }
1941 pr_debug("In %s\n", __func__);
1942
1943 mutex_lock(&priv->pie_mutex);
1944
1945 for (block = min_block; block < max_block; block++) {
1946 for (j = 0; j < 2; j++) {
1947 t = (sw_r32(RTL930X_PIE_BLK_TMPLTE_CTRL(block)) >> (j * 4)) & 0xf;
1948 pr_debug("Testing block %d, template %d, template id %d\n", block, j, t);
1949 pr_debug("%s: %08x\n",
1950 __func__, sw_r32(RTL930X_PIE_BLK_TMPLTE_CTRL(block)));
1951 idx = rtl930x_pie_verify_template(priv, pr, t, block);
1952 if (idx >= 0)
1953 break;
1954 }
1955 if (j < 2)
1956 break;
1957 }
1958
1959 if (block >= priv->n_pie_blocks) {
1960 mutex_unlock(&priv->pie_mutex);
1961 return -EOPNOTSUPP;
1962 }
1963
1964 pr_debug("Using block: %d, index %d, template-id %d\n", block, idx, j);
1965 set_bit(idx, priv->pie_use_bm);
1966
1967 pr->valid = true;
1968 pr->tid = j; /* Mapped to template number */
1969 pr->tid_m = 0x1;
1970 pr->id = idx;
1971
1972 rtl930x_pie_lookup_enable(priv, idx);
1973 rtl930x_pie_rule_write(priv, idx, pr);
1974
1975 mutex_unlock(&priv->pie_mutex);
1976 return 0;
1977 }
1978
1979 /* Delete a range of Packet Inspection Engine rules */
1980 static int rtl930x_pie_rule_del(struct rtl838x_switch_priv *priv, int index_from, int index_to)
1981 {
1982 u32 v = (index_from << 1)| (index_to << 12 ) | BIT(0);
1983
1984 pr_debug("%s: from %d to %d\n", __func__, index_from, index_to);
1985 mutex_lock(&priv->reg_mutex);
1986
1987 /* Write from-to and execute bit into control register */
1988 sw_w32(v, RTL930X_PIE_CLR_CTRL);
1989
1990 /* Wait until command has completed */
1991 do {
1992 } while (sw_r32(RTL930X_PIE_CLR_CTRL) & BIT(0));
1993
1994 mutex_unlock(&priv->reg_mutex);
1995 return 0;
1996 }
1997
1998 static void rtl930x_pie_rule_rm(struct rtl838x_switch_priv *priv, struct pie_rule *pr)
1999 {
2000 int idx = pr->id;
2001
2002 rtl930x_pie_rule_del(priv, idx, idx);
2003 clear_bit(idx, priv->pie_use_bm);
2004 }
2005
2006 static void rtl930x_pie_init(struct rtl838x_switch_priv *priv)
2007 {
2008 u32 template_selectors;
2009
2010 mutex_init(&priv->pie_mutex);
2011
2012 pr_info("%s\n", __func__);
2013 /* Enable ACL lookup on all ports, including CPU_PORT */
2014 for (int i = 0; i <= priv->cpu_port; i++)
2015 sw_w32(1, RTL930X_ACL_PORT_LOOKUP_CTRL(i));
2016
2017 /* Include IPG in metering */
2018 sw_w32_mask(0, 1, RTL930X_METER_GLB_CTRL);
2019
2020 /* Delete all present rules, block size is 128 on all SoC families */
2021 rtl930x_pie_rule_del(priv, 0, priv->n_pie_blocks * 128 - 1);
2022
2023 /* Assign blocks 0-7 to VACL phase (bit = 0), blocks 8-15 to IACL (bit = 1) */
2024 sw_w32(0xff00, RTL930X_PIE_BLK_PHASE_CTRL);
2025
2026 /* Enable predefined templates 0, 1 for first quarter of all blocks */
2027 template_selectors = 0 | (1 << 4);
2028 for (int i = 0; i < priv->n_pie_blocks / 4; i++)
2029 sw_w32(template_selectors, RTL930X_PIE_BLK_TMPLTE_CTRL(i));
2030
2031 /* Enable predefined templates 2, 3 for second quarter of all blocks */
2032 template_selectors = 2 | (3 << 4);
2033 for (int i = priv->n_pie_blocks / 4; i < priv->n_pie_blocks / 2; i++)
2034 sw_w32(template_selectors, RTL930X_PIE_BLK_TMPLTE_CTRL(i));
2035
2036 /* Enable predefined templates 0, 1 for third half of all blocks */
2037 template_selectors = 0 | (1 << 4);
2038 for (int i = priv->n_pie_blocks / 2; i < priv->n_pie_blocks * 3 / 4; i++)
2039 sw_w32(template_selectors, RTL930X_PIE_BLK_TMPLTE_CTRL(i));
2040
2041 /* Enable predefined templates 2, 3 for fourth quater of all blocks */
2042 template_selectors = 2 | (3 << 4);
2043 for (int i = priv->n_pie_blocks * 3 / 4; i < priv->n_pie_blocks; i++)
2044 sw_w32(template_selectors, RTL930X_PIE_BLK_TMPLTE_CTRL(i));
2045
2046 }
2047
2048 /* Sets up an egress interface for L3 actions
2049 * Actions for ip4/6_icmp_redirect, ip4/6_pbr_icmp_redirect are:
2050 * 0: FORWARD, 1: DROP, 2: TRAP2CPU, 3: COPY2CPU, 4: TRAP2MASTERCPU 5: COPY2MASTERCPU
2051 * 6: HARDDROP
2052 * idx is the index in the HW interface table: idx < 0x80
2053 */
2054 static void rtl930x_set_l3_egress_intf(int idx, struct rtl838x_l3_intf *intf)
2055 {
2056 u32 u, v;
2057 /* Read L3_EGR_INTF table (4) via register RTL9300_TBL_1 */
2058 struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 4);
2059
2060 /* The table has 2 registers */
2061 u = (intf->vid & 0xfff) << 9;
2062 u |= (intf->smac_idx & 0x3f) << 3;
2063 u |= (intf->ip4_mtu_id & 0x7);
2064
2065 v = (intf->ip6_mtu_id & 0x7) << 28;
2066 v |= (intf->ttl_scope & 0xff) << 20;
2067 v |= (intf->hl_scope & 0xff) << 12;
2068 v |= (intf->ip4_icmp_redirect & 0x7) << 9;
2069 v |= (intf->ip6_icmp_redirect & 0x7)<< 6;
2070 v |= (intf->ip4_pbr_icmp_redirect & 0x7) << 3;
2071 v |= (intf->ip6_pbr_icmp_redirect & 0x7);
2072
2073 sw_w32(u, rtl_table_data(r, 0));
2074 sw_w32(v, rtl_table_data(r, 1));
2075
2076 pr_info("%s writing to index %d: %08x %08x\n", __func__, idx, u, v);
2077 rtl_table_write(r, idx & 0x7f);
2078 rtl_table_release(r);
2079 }
2080
2081 /* Reads a MAC entry for L3 termination as entry point for routing
2082 * from the hardware table
2083 * idx is the index into the L3_ROUTER_MAC table
2084 */
2085 static void rtl930x_get_l3_router_mac(u32 idx, struct rtl93xx_rt_mac *m)
2086 {
2087 u32 v, w;
2088 /* Read L3_ROUTER_MAC table (0) via register RTL9300_TBL_1 */
2089 struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 0);
2090
2091 rtl_table_read(r, idx);
2092 /* The table has a size of 7 registers, 64 entries */
2093 v = sw_r32(rtl_table_data(r, 0));
2094 w = sw_r32(rtl_table_data(r, 3));
2095 m->valid = !!(v & BIT(20));
2096 if (!m->valid)
2097 goto out;
2098
2099 m->p_type = !!(v & BIT(19));
2100 m->p_id = (v >> 13) & 0x3f; /* trunk id of port */
2101 m->vid = v & 0xfff;
2102 m->vid_mask = w & 0xfff;
2103 m->action = sw_r32(rtl_table_data(r, 6)) & 0x7;
2104 m->mac_mask = ((((u64)sw_r32(rtl_table_data(r, 5))) << 32) & 0xffffffffffffULL) |
2105 (sw_r32(rtl_table_data(r, 4)));
2106 m->mac = ((((u64)sw_r32(rtl_table_data(r, 1))) << 32) & 0xffffffffffffULL) |
2107 (sw_r32(rtl_table_data(r, 2)));
2108 /* Bits L3_INTF and BMSK_L3_INTF are 0 */
2109
2110 out:
2111 rtl_table_release(r);
2112 }
2113
2114 /* Writes a MAC entry for L3 termination as entry point for routing
2115 * into the hardware table
2116 * idx is the index into the L3_ROUTER_MAC table
2117 */
2118 static void rtl930x_set_l3_router_mac(u32 idx, struct rtl93xx_rt_mac *m)
2119 {
2120 u32 v, w;
2121 /* Read L3_ROUTER_MAC table (0) via register RTL9300_TBL_1 */
2122 struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 0);
2123
2124 /* The table has a size of 7 registers, 64 entries */
2125 v = BIT(20); /* mac entry valid, port type is 0: individual */
2126 v |= (m->p_id & 0x3f) << 13;
2127 v |= (m->vid & 0xfff); /* Set the interface_id to the vlan id */
2128
2129 w = m->vid_mask;
2130 w |= (m->p_id_mask & 0x3f) << 13;
2131
2132 sw_w32(v, rtl_table_data(r, 0));
2133 sw_w32(w, rtl_table_data(r, 3));
2134
2135 /* Set MAC address, L3_INTF (bit 12 in register 1) needs to be 0 */
2136 sw_w32((u32)(m->mac), rtl_table_data(r, 2));
2137 sw_w32(m->mac >> 32, rtl_table_data(r, 1));
2138
2139 /* Set MAC address mask, BMSK_L3_INTF (bit 12 in register 5) needs to be 0 */
2140 sw_w32((u32)(m->mac_mask >> 32), rtl_table_data(r, 4));
2141 sw_w32((u32)m->mac_mask, rtl_table_data(r, 5));
2142
2143 sw_w32(m->action & 0x7, rtl_table_data(r, 6));
2144
2145 pr_debug("%s writing index %d: %08x %08x %08x %08x %08x %08x %08x\n", __func__, idx,
2146 sw_r32(rtl_table_data(r, 0)), sw_r32(rtl_table_data(r, 1)), sw_r32(rtl_table_data(r, 2)),
2147 sw_r32(rtl_table_data(r, 3)), sw_r32(rtl_table_data(r, 4)), sw_r32(rtl_table_data(r, 5)),
2148 sw_r32(rtl_table_data(r, 6))
2149 );
2150 rtl_table_write(r, idx);
2151 rtl_table_release(r);
2152 }
2153
2154 /* Get the Destination-MAC of an L3 egress interface or the Source MAC for routed packets
2155 * from the SoC's L3_EGR_INTF_MAC table
2156 * Indexes 0-2047 are DMACs, 2048+ are SMACs
2157 */
2158 static u64 rtl930x_get_l3_egress_mac(u32 idx)
2159 {
2160 u64 mac;
2161 /* Read L3_EGR_INTF_MAC table (2) via register RTL9300_TBL_2 */
2162 struct table_reg *r = rtl_table_get(RTL9300_TBL_2, 2);
2163
2164 rtl_table_read(r, idx);
2165 /* The table has a size of 2 registers */
2166 mac = sw_r32(rtl_table_data(r, 0));
2167 mac <<= 32;
2168 mac |= sw_r32(rtl_table_data(r, 1));
2169 rtl_table_release(r);
2170
2171 return mac;
2172 }
2173
2174 /* Set the Destination-MAC of a route or the Source MAC of an L3 egress interface
2175 * in the SoC's L3_EGR_INTF_MAC table
2176 * Indexes 0-2047 are DMACs, 2048+ are SMACs
2177 */
2178 static void rtl930x_set_l3_egress_mac(u32 idx, u64 mac)
2179 {
2180 /* Access L3_EGR_INTF_MAC table (2) via register RTL9300_TBL_2 */
2181 struct table_reg *r = rtl_table_get(RTL9300_TBL_2, 2);
2182
2183 /* The table has a size of 2 registers */
2184 sw_w32(mac >> 32, rtl_table_data(r, 0));
2185 sw_w32(mac, rtl_table_data(r, 1));
2186
2187 pr_debug("%s: setting index %d to %016llx\n", __func__, idx, mac);
2188 rtl_table_write(r, idx);
2189 rtl_table_release(r);
2190 }
2191
2192 /* Configure L3 routing settings of the device:
2193 * - MTUs
2194 * - Egress interface
2195 * - The router's MAC address on which routed packets are expected
2196 * - MAC addresses used as source macs of routed packets
2197 */
2198 int rtl930x_l3_setup(struct rtl838x_switch_priv *priv)
2199 {
2200 /* Setup MTU with id 0 for default interface */
2201 for (int i = 0; i < MAX_INTF_MTUS; i++)
2202 priv->intf_mtu_count[i] = priv->intf_mtus[i] = 0;
2203
2204 priv->intf_mtu_count[0] = 0; /* Needs to stay forever */
2205 priv->intf_mtus[0] = DEFAULT_MTU;
2206 sw_w32_mask(0xffff, DEFAULT_MTU, RTL930X_L3_IP_MTU_CTRL(0));
2207 sw_w32_mask(0xffff, DEFAULT_MTU, RTL930X_L3_IP6_MTU_CTRL(0));
2208 priv->intf_mtus[1] = DEFAULT_MTU;
2209 sw_w32_mask(0xffff0000, DEFAULT_MTU << 16, RTL930X_L3_IP_MTU_CTRL(0));
2210 sw_w32_mask(0xffff0000, DEFAULT_MTU << 16, RTL930X_L3_IP6_MTU_CTRL(0));
2211
2212 sw_w32_mask(0xffff, DEFAULT_MTU, RTL930X_L3_IP_MTU_CTRL(1));
2213 sw_w32_mask(0xffff, DEFAULT_MTU, RTL930X_L3_IP6_MTU_CTRL(1));
2214 sw_w32_mask(0xffff0000, DEFAULT_MTU << 16, RTL930X_L3_IP_MTU_CTRL(1));
2215 sw_w32_mask(0xffff0000, DEFAULT_MTU << 16, RTL930X_L3_IP6_MTU_CTRL(1));
2216
2217 /* Clear all source port MACs */
2218 for (int i = 0; i < MAX_SMACS; i++)
2219 rtl930x_set_l3_egress_mac(L3_EGRESS_DMACS + i, 0ULL);
2220
2221 /* Configure the default L3 hash algorithm */
2222 sw_w32_mask(BIT(2), 0, RTL930X_L3_HOST_TBL_CTRL); /* Algorithm selection 0 = 0 */
2223 sw_w32_mask(0, BIT(3), RTL930X_L3_HOST_TBL_CTRL); /* Algorithm selection 1 = 1 */
2224
2225 pr_info("L3_IPUC_ROUTE_CTRL %08x, IPMC_ROUTE %08x, IP6UC_ROUTE %08x, IP6MC_ROUTE %08x\n",
2226 sw_r32(RTL930X_L3_IPUC_ROUTE_CTRL), sw_r32(RTL930X_L3_IPMC_ROUTE_CTRL),
2227 sw_r32(RTL930X_L3_IP6UC_ROUTE_CTRL), sw_r32(RTL930X_L3_IP6MC_ROUTE_CTRL));
2228 sw_w32_mask(0, 1, RTL930X_L3_IPUC_ROUTE_CTRL);
2229 sw_w32_mask(0, 1, RTL930X_L3_IP6UC_ROUTE_CTRL);
2230 sw_w32_mask(0, 1, RTL930X_L3_IPMC_ROUTE_CTRL);
2231 sw_w32_mask(0, 1, RTL930X_L3_IP6MC_ROUTE_CTRL);
2232
2233 sw_w32(0x00002001, RTL930X_L3_IPUC_ROUTE_CTRL);
2234 sw_w32(0x00014581, RTL930X_L3_IP6UC_ROUTE_CTRL);
2235 sw_w32(0x00000501, RTL930X_L3_IPMC_ROUTE_CTRL);
2236 sw_w32(0x00012881, RTL930X_L3_IP6MC_ROUTE_CTRL);
2237
2238 pr_info("L3_IPUC_ROUTE_CTRL %08x, IPMC_ROUTE %08x, IP6UC_ROUTE %08x, IP6MC_ROUTE %08x\n",
2239 sw_r32(RTL930X_L3_IPUC_ROUTE_CTRL), sw_r32(RTL930X_L3_IPMC_ROUTE_CTRL),
2240 sw_r32(RTL930X_L3_IP6UC_ROUTE_CTRL), sw_r32(RTL930X_L3_IP6MC_ROUTE_CTRL));
2241
2242 /* Trap non-ip traffic to the CPU-port (e.g. ARP so we stay reachable) */
2243 sw_w32_mask(0x3 << 8, 0x1 << 8, RTL930X_L3_IP_ROUTE_CTRL);
2244 pr_info("L3_IP_ROUTE_CTRL %08x\n", sw_r32(RTL930X_L3_IP_ROUTE_CTRL));
2245
2246 /* PORT_ISO_RESTRICT_ROUTE_CTRL? */
2247
2248 /* Do not use prefix route 0 because of HW limitations */
2249 set_bit(0, priv->route_use_bm);
2250
2251 return 0;
2252 }
2253
2254 static u32 rtl930x_packet_cntr_read(int counter)
2255 {
2256 u32 v;
2257
2258 /* Read LOG table (3) via register RTL9300_TBL_0 */
2259 struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 3);
2260
2261 pr_debug("In %s, id %d\n", __func__, counter);
2262 rtl_table_read(r, counter / 2);
2263
2264 pr_debug("Registers: %08x %08x\n",
2265 sw_r32(rtl_table_data(r, 0)), sw_r32(rtl_table_data(r, 1)));
2266 /* The table has a size of 2 registers */
2267 if (counter % 2)
2268 v = sw_r32(rtl_table_data(r, 0));
2269 else
2270 v = sw_r32(rtl_table_data(r, 1));
2271
2272 rtl_table_release(r);
2273
2274 return v;
2275 }
2276
2277 static void rtl930x_packet_cntr_clear(int counter)
2278 {
2279 /* Access LOG table (3) via register RTL9300_TBL_0 */
2280 struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 3);
2281
2282 pr_info("In %s, id %d\n", __func__, counter);
2283 /* The table has a size of 2 registers */
2284 if (counter % 2)
2285 sw_w32(0, rtl_table_data(r, 0));
2286 else
2287 sw_w32(0, rtl_table_data(r, 1));
2288
2289 rtl_table_write(r, counter / 2);
2290
2291 rtl_table_release(r);
2292 }
2293
2294 void rtl930x_vlan_port_keep_tag_set(int port, bool keep_outer, bool keep_inner)
2295 {
2296 sw_w32(FIELD_PREP(RTL930X_VLAN_PORT_TAG_STS_CTRL_EGR_OTAG_STS_MASK,
2297 keep_outer ? RTL930X_VLAN_PORT_TAG_STS_TAGGED : RTL930X_VLAN_PORT_TAG_STS_UNTAG) |
2298 FIELD_PREP(RTL930X_VLAN_PORT_TAG_STS_CTRL_EGR_ITAG_STS_MASK,
2299 keep_inner ? RTL930X_VLAN_PORT_TAG_STS_TAGGED : RTL930X_VLAN_PORT_TAG_STS_UNTAG),
2300 RTL930X_VLAN_PORT_TAG_STS_CTRL(port));
2301 }
2302
2303 void rtl930x_vlan_port_pvidmode_set(int port, enum pbvlan_type type, enum pbvlan_mode mode)
2304 {
2305 if (type == PBVLAN_TYPE_INNER)
2306 sw_w32_mask(0x3, mode, RTL930X_VLAN_PORT_PB_VLAN + (port << 2));
2307 else
2308 sw_w32_mask(0x3 << 14, mode << 14 ,RTL930X_VLAN_PORT_PB_VLAN + (port << 2));
2309 }
2310
2311 void rtl930x_vlan_port_pvid_set(int port, enum pbvlan_type type, int pvid)
2312 {
2313 if (type == PBVLAN_TYPE_INNER)
2314 sw_w32_mask(0xfff << 2, pvid << 2, RTL930X_VLAN_PORT_PB_VLAN + (port << 2));
2315 else
2316 sw_w32_mask(0xfff << 16, pvid << 16, RTL930X_VLAN_PORT_PB_VLAN + (port << 2));
2317 }
2318
2319 static int rtl930x_set_ageing_time(unsigned long msec)
2320 {
2321 int t = sw_r32(RTL930X_L2_AGE_CTRL);
2322
2323 t &= 0x1FFFFF;
2324 t = (t * 7) / 10;
2325 pr_debug("L2 AGING time: %d sec\n", t);
2326
2327 t = (msec / 100 + 6) / 7;
2328 t = t > 0x1FFFFF ? 0x1FFFFF : t;
2329 sw_w32_mask(0x1FFFFF, t, RTL930X_L2_AGE_CTRL);
2330 pr_debug("Dynamic aging for ports: %x\n", sw_r32(RTL930X_L2_PORT_AGE_CTRL));
2331
2332 return 0;
2333 }
2334
2335 static void rtl930x_set_igr_filter(int port, enum igr_filter state)
2336 {
2337 sw_w32_mask(0x3 << ((port & 0xf)<<1), state << ((port & 0xf)<<1),
2338 RTL930X_VLAN_PORT_IGR_FLTR + (((port >> 4) << 2)));
2339 }
2340
2341 static void rtl930x_set_egr_filter(int port, enum egr_filter state)
2342 {
2343 sw_w32_mask(0x1 << (port % 0x1D), state << (port % 0x1D),
2344 RTL930X_VLAN_PORT_EGR_FLTR + (((port / 29) << 2)));
2345 }
2346
2347 void rtl930x_set_distribution_algorithm(int group, int algoidx, u32 algomsk)
2348 {
2349 u32 l3shift = 0;
2350 u32 newmask = 0;
2351
2352 /* TODO: for now we set algoidx to 0 */
2353 algoidx = 0;
2354 if (algomsk & TRUNK_DISTRIBUTION_ALGO_SIP_BIT) {
2355 l3shift = 4;
2356 newmask |= TRUNK_DISTRIBUTION_ALGO_L3_SIP_BIT;
2357 }
2358 if (algomsk & TRUNK_DISTRIBUTION_ALGO_DIP_BIT) {
2359 l3shift = 4;
2360 newmask |= TRUNK_DISTRIBUTION_ALGO_L3_DIP_BIT;
2361 }
2362 if (algomsk & TRUNK_DISTRIBUTION_ALGO_SRC_L4PORT_BIT) {
2363 l3shift = 4;
2364 newmask |= TRUNK_DISTRIBUTION_ALGO_L3_SRC_L4PORT_BIT;
2365 }
2366 if (algomsk & TRUNK_DISTRIBUTION_ALGO_SRC_L4PORT_BIT) {
2367 l3shift = 4;
2368 newmask |= TRUNK_DISTRIBUTION_ALGO_L3_SRC_L4PORT_BIT;
2369 }
2370
2371 if (l3shift == 4) {
2372 if (algomsk & TRUNK_DISTRIBUTION_ALGO_SMAC_BIT)
2373 newmask |= TRUNK_DISTRIBUTION_ALGO_L3_SMAC_BIT;
2374
2375 if (algomsk & TRUNK_DISTRIBUTION_ALGO_DMAC_BIT)
2376 newmask |= TRUNK_DISTRIBUTION_ALGO_L3_DMAC_BIT;
2377 } else {
2378 if (algomsk & TRUNK_DISTRIBUTION_ALGO_SMAC_BIT)
2379 newmask |= TRUNK_DISTRIBUTION_ALGO_L2_SMAC_BIT;
2380 if (algomsk & TRUNK_DISTRIBUTION_ALGO_DMAC_BIT)
2381 newmask |= TRUNK_DISTRIBUTION_ALGO_L2_DMAC_BIT;
2382 }
2383
2384 sw_w32(newmask << l3shift, RTL930X_TRK_HASH_CTRL + (algoidx << 2));
2385 }
2386
2387 static void rtl930x_led_init(struct rtl838x_switch_priv *priv)
2388 {
2389 struct device_node *node;
2390 u32 pm = 0;
2391
2392 pr_info("%s called\n", __func__);
2393 node = of_find_compatible_node(NULL, NULL, "realtek,rtl9300-leds");
2394 if (!node) {
2395 pr_info("%s No compatible LED node found\n", __func__);
2396 return;
2397 }
2398
2399 for (int i = 0; i < priv->cpu_port; i++) {
2400 int pos = (i << 1) % 32;
2401 u32 set;
2402 u32 v;
2403
2404 sw_w32_mask(0x3 << pos, 0, RTL930X_LED_PORT_FIB_SET_SEL_CTRL(i));
2405 sw_w32_mask(0x3 << pos, 0, RTL930X_LED_PORT_COPR_SET_SEL_CTRL(i));
2406
2407 if (!priv->ports[i].phy)
2408 continue;
2409
2410 v = 0x1;
2411 if (priv->ports[i].is10G)
2412 v = 0x3;
2413 if (priv->ports[i].phy_is_integrated)
2414 v = 0x1;
2415 sw_w32_mask(0x3 << pos, v << pos, RTL930X_LED_PORT_NUM_CTRL(i));
2416
2417 pm |= BIT(i);
2418
2419 set = priv->ports[i].led_set;
2420 sw_w32_mask(0, set << pos, RTL930X_LED_PORT_COPR_SET_SEL_CTRL(i));
2421 sw_w32_mask(0, set << pos, RTL930X_LED_PORT_FIB_SET_SEL_CTRL(i));
2422 }
2423
2424 for (int i = 0; i < 4; i++) {
2425 const __be32 *led_set;
2426 char set_name[9];
2427 u32 setlen;
2428 u32 v;
2429
2430 sprintf(set_name, "led_set%d", i);
2431 led_set = of_get_property(node, set_name, &setlen);
2432 if (!led_set || setlen != 16)
2433 break;
2434 v = be32_to_cpup(led_set) << 16 | be32_to_cpup(led_set + 1);
2435 sw_w32(v, RTL930X_LED_SET0_0_CTRL - 4 - i * 8);
2436 v = be32_to_cpup(led_set + 2) << 16 | be32_to_cpup(led_set + 3);
2437 sw_w32(v, RTL930X_LED_SET0_0_CTRL - i * 8);
2438 }
2439
2440 /* Set LED mode to serial (0x1) */
2441 sw_w32_mask(0x3, 0x1, RTL930X_LED_GLB_CTRL);
2442
2443 /* Set LED active state */
2444 if (of_property_read_bool(node, "active-low"))
2445 sw_w32_mask(RTL930X_LED_GLB_ACTIVE_LOW, 0, RTL930X_LED_GLB_CTRL);
2446 else
2447 sw_w32_mask(0, RTL930X_LED_GLB_ACTIVE_LOW, RTL930X_LED_GLB_CTRL);
2448
2449 /* Set port type masks */
2450 sw_w32(pm, RTL930X_LED_PORT_COPR_MASK_CTRL);
2451 sw_w32(pm, RTL930X_LED_PORT_FIB_MASK_CTRL);
2452 sw_w32(pm, RTL930X_LED_PORT_COMBO_MASK_CTRL);
2453
2454 for (int i = 0; i < 24; i++)
2455 pr_info("%s %08x: %08x\n",__func__, 0xbb00cc00 + i * 4, sw_r32(0xcc00 + i * 4));
2456 }
2457
2458 const struct rtl838x_reg rtl930x_reg = {
2459 .mask_port_reg_be = rtl838x_mask_port_reg,
2460 .set_port_reg_be = rtl838x_set_port_reg,
2461 .get_port_reg_be = rtl838x_get_port_reg,
2462 .mask_port_reg_le = rtl838x_mask_port_reg,
2463 .set_port_reg_le = rtl838x_set_port_reg,
2464 .get_port_reg_le = rtl838x_get_port_reg,
2465 .stat_port_rst = RTL930X_STAT_PORT_RST,
2466 .stat_rst = RTL930X_STAT_RST,
2467 .stat_port_std_mib = RTL930X_STAT_PORT_MIB_CNTR,
2468 .traffic_enable = rtl930x_traffic_enable,
2469 .traffic_disable = rtl930x_traffic_disable,
2470 .traffic_get = rtl930x_traffic_get,
2471 .traffic_set = rtl930x_traffic_set,
2472 .l2_ctrl_0 = RTL930X_L2_CTRL,
2473 .l2_ctrl_1 = RTL930X_L2_AGE_CTRL,
2474 .l2_port_aging_out = RTL930X_L2_PORT_AGE_CTRL,
2475 .set_ageing_time = rtl930x_set_ageing_time,
2476 .smi_poll_ctrl = RTL930X_SMI_POLL_CTRL, /* TODO: Difference to RTL9300_SMI_PRVTE_POLLING_CTRL */
2477 .l2_tbl_flush_ctrl = RTL930X_L2_TBL_FLUSH_CTRL,
2478 .exec_tbl0_cmd = rtl930x_exec_tbl0_cmd,
2479 .exec_tbl1_cmd = rtl930x_exec_tbl1_cmd,
2480 .tbl_access_data_0 = rtl930x_tbl_access_data_0,
2481 .isr_glb_src = RTL930X_ISR_GLB,
2482 .isr_port_link_sts_chg = RTL930X_ISR_PORT_LINK_STS_CHG,
2483 .imr_port_link_sts_chg = RTL930X_IMR_PORT_LINK_STS_CHG,
2484 .imr_glb = RTL930X_IMR_GLB,
2485 .vlan_tables_read = rtl930x_vlan_tables_read,
2486 .vlan_set_tagged = rtl930x_vlan_set_tagged,
2487 .vlan_set_untagged = rtl930x_vlan_set_untagged,
2488 .vlan_profile_dump = rtl930x_vlan_profile_dump,
2489 .vlan_profile_setup = rtl930x_vlan_profile_setup,
2490 .vlan_fwd_on_inner = rtl930x_vlan_fwd_on_inner,
2491 .set_vlan_igr_filter = rtl930x_set_igr_filter,
2492 .set_vlan_egr_filter = rtl930x_set_egr_filter,
2493 .stp_get = rtl930x_stp_get,
2494 .stp_set = rtl930x_stp_set,
2495 .mac_force_mode_ctrl = rtl930x_mac_force_mode_ctrl,
2496 .mac_port_ctrl = rtl930x_mac_port_ctrl,
2497 .l2_port_new_salrn = rtl930x_l2_port_new_salrn,
2498 .l2_port_new_sa_fwd = rtl930x_l2_port_new_sa_fwd,
2499 .mir_ctrl = RTL930X_MIR_CTRL,
2500 .mir_dpm = RTL930X_MIR_DPM_CTRL,
2501 .mir_spm = RTL930X_MIR_SPM_CTRL,
2502 .mac_link_sts = RTL930X_MAC_LINK_STS,
2503 .mac_link_dup_sts = RTL930X_MAC_LINK_DUP_STS,
2504 .mac_link_spd_sts = rtl930x_mac_link_spd_sts,
2505 .mac_rx_pause_sts = RTL930X_MAC_RX_PAUSE_STS,
2506 .mac_tx_pause_sts = RTL930X_MAC_TX_PAUSE_STS,
2507 .read_l2_entry_using_hash = rtl930x_read_l2_entry_using_hash,
2508 .write_l2_entry_using_hash = rtl930x_write_l2_entry_using_hash,
2509 .read_cam = rtl930x_read_cam,
2510 .write_cam = rtl930x_write_cam,
2511 .vlan_port_keep_tag_set = rtl930x_vlan_port_keep_tag_set,
2512 .vlan_port_pvidmode_set = rtl930x_vlan_port_pvidmode_set,
2513 .vlan_port_pvid_set = rtl930x_vlan_port_pvid_set,
2514 .trk_mbr_ctr = rtl930x_trk_mbr_ctr,
2515 .rma_bpdu_fld_pmask = RTL930X_RMA_BPDU_FLD_PMSK,
2516 .init_eee = rtl930x_init_eee,
2517 .port_eee_set = rtl930x_port_eee_set,
2518 .eee_port_ability = rtl930x_eee_port_ability,
2519 .l2_hash_seed = rtl930x_l2_hash_seed,
2520 .l2_hash_key = rtl930x_l2_hash_key,
2521 .read_mcast_pmask = rtl930x_read_mcast_pmask,
2522 .write_mcast_pmask = rtl930x_write_mcast_pmask,
2523 .pie_init = rtl930x_pie_init,
2524 .pie_rule_write = rtl930x_pie_rule_write,
2525 .pie_rule_add = rtl930x_pie_rule_add,
2526 .pie_rule_rm = rtl930x_pie_rule_rm,
2527 .l2_learning_setup = rtl930x_l2_learning_setup,
2528 .packet_cntr_read = rtl930x_packet_cntr_read,
2529 .packet_cntr_clear = rtl930x_packet_cntr_clear,
2530 .route_read = rtl930x_route_read,
2531 .route_write = rtl930x_route_write,
2532 .host_route_write = rtl930x_host_route_write,
2533 .l3_setup = rtl930x_l3_setup,
2534 .set_l3_nexthop = rtl930x_set_l3_nexthop,
2535 .get_l3_nexthop = rtl930x_get_l3_nexthop,
2536 .get_l3_egress_mac = rtl930x_get_l3_egress_mac,
2537 .set_l3_egress_mac = rtl930x_set_l3_egress_mac,
2538 .find_l3_slot = rtl930x_find_l3_slot,
2539 .route_lookup_hw = rtl930x_route_lookup_hw,
2540 .get_l3_router_mac = rtl930x_get_l3_router_mac,
2541 .set_l3_router_mac = rtl930x_set_l3_router_mac,
2542 .set_l3_egress_intf = rtl930x_set_l3_egress_intf,
2543 .set_distribution_algorithm = rtl930x_set_distribution_algorithm,
2544 .led_init = rtl930x_led_init,
2545 };
Staging tree of Jo-Philipp Wich