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rtl93xx: dsa: Fix 802.1QinQ for trunk ports
[openwrt/staging/stintel.git] / target / linux / realtek / files-5.15 / drivers / net / dsa / rtl83xx / rtl930x.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <asm/mach-rtl838x/mach-rtl83xx.h>
4 #include <linux/etherdevice.h>
5 #include <linux/inetdevice.h>
6
7 #include "rtl83xx.h"
8
9 #define RTL930X_VLAN_PORT_TAG_STS_INTERNAL 0x0
10 #define RTL930X_VLAN_PORT_TAG_STS_UNTAG 0x1
11 #define RTL930X_VLAN_PORT_TAG_STS_TAGGED 0x2
12 #define RTL930X_VLAN_PORT_TAG_STS_PRIORITY_TAGGED 0x3
13
14 #define RTL930X_VLAN_PORT_TAG_STS_CTRL_BASE 0xCE24
15 /* port 0-28 */
16 #define RTL930X_VLAN_PORT_TAG_STS_CTRL(port) \
17 RTL930X_VLAN_PORT_TAG_STS_CTRL_BASE + (port << 2)
18 #define RTL930X_VLAN_PORT_TAG_STS_CTRL_EGR_OTAG_STS_MASK GENMASK(7,6)
19 #define RTL930X_VLAN_PORT_TAG_STS_CTRL_EGR_ITAG_STS_MASK GENMASK(5,4)
20 #define RTL930X_VLAN_PORT_TAG_STS_CTRL_EGR_P_OTAG_KEEP_MASK GENMASK(3,3)
21 #define RTL930X_VLAN_PORT_TAG_STS_CTRL_EGR_P_ITAG_KEEP_MASK GENMASK(2,2)
22 #define RTL930X_VLAN_PORT_TAG_STS_CTRL_IGR_P_OTAG_KEEP_MASK GENMASK(1,1)
23 #define RTL930X_VLAN_PORT_TAG_STS_CTRL_IGR_P_ITAG_KEEP_MASK GENMASK(0,0)
24
25 #define RTL930X_LED_GLB_ACTIVE_LOW BIT(22)
26
27 #define RTL930X_LED_SETX_0_CTRL(x) (RTL930X_LED_SET0_0_CTRL - (x * 8))
28 #define RTL930X_LED_SETX_1_CTRL(x) (RTL930X_LED_SETX_0_CTRL(x) - 4)
29
30 /* get register for given set and led in the set */
31 #define RTL930X_LED_SETX_LEDY(x,y) (RTL930X_LED_SETX_0_CTRL(x) - 4 * (y / 2))
32
33 /* get shift for given led in any set */
34 #define RTL930X_LED_SET_LEDX_SHIFT(x) (16 * (x % 2))
35
36 extern struct mutex smi_lock;
37 extern struct rtl83xx_soc_info soc_info;
38
39 /* Definition of the RTL930X-specific template field IDs as used in the PIE */
40 enum template_field_id {
41 TEMPLATE_FIELD_SPM0 = 0, /* Source portmask ports 0-15 */
42 TEMPLATE_FIELD_SPM1 = 1, /* Source portmask ports 16-31 */
43 TEMPLATE_FIELD_DMAC0 = 2, /* Destination MAC [15:0] */
44 TEMPLATE_FIELD_DMAC1 = 3, /* Destination MAC [31:16] */
45 TEMPLATE_FIELD_DMAC2 = 4, /* Destination MAC [47:32] */
46 TEMPLATE_FIELD_SMAC0 = 5, /* Source MAC [15:0] */
47 TEMPLATE_FIELD_SMAC1 = 6, /* Source MAC [31:16] */
48 TEMPLATE_FIELD_SMAC2 = 7, /* Source MAC [47:32] */
49 TEMPLATE_FIELD_ETHERTYPE = 8, /* Ethernet frame type field */
50 TEMPLATE_FIELD_OTAG = 9,
51 TEMPLATE_FIELD_ITAG = 10,
52 TEMPLATE_FIELD_SIP0 = 11,
53 TEMPLATE_FIELD_SIP1 = 12,
54 TEMPLATE_FIELD_DIP0 = 13,
55 TEMPLATE_FIELD_DIP1 = 14,
56 TEMPLATE_FIELD_IP_TOS_PROTO = 15,
57 TEMPLATE_FIELD_L4_SPORT = 16,
58 TEMPLATE_FIELD_L4_DPORT = 17,
59 TEMPLATE_FIELD_L34_HEADER = 18,
60 TEMPLATE_FIELD_TCP_INFO = 19,
61 TEMPLATE_FIELD_FIELD_SELECTOR_VALID = 20,
62 TEMPLATE_FIELD_FIELD_SELECTOR_0 = 21,
63 TEMPLATE_FIELD_FIELD_SELECTOR_1 = 22,
64 TEMPLATE_FIELD_FIELD_SELECTOR_2 = 23,
65 TEMPLATE_FIELD_FIELD_SELECTOR_3 = 24,
66 TEMPLATE_FIELD_FIELD_SELECTOR_4 = 25,
67 TEMPLATE_FIELD_FIELD_SELECTOR_5 = 26,
68 TEMPLATE_FIELD_SIP2 = 27,
69 TEMPLATE_FIELD_SIP3 = 28,
70 TEMPLATE_FIELD_SIP4 = 29,
71 TEMPLATE_FIELD_SIP5 = 30,
72 TEMPLATE_FIELD_SIP6 = 31,
73 TEMPLATE_FIELD_SIP7 = 32,
74 TEMPLATE_FIELD_DIP2 = 33,
75 TEMPLATE_FIELD_DIP3 = 34,
76 TEMPLATE_FIELD_DIP4 = 35,
77 TEMPLATE_FIELD_DIP5 = 36,
78 TEMPLATE_FIELD_DIP6 = 37,
79 TEMPLATE_FIELD_DIP7 = 38,
80 TEMPLATE_FIELD_PKT_INFO = 39,
81 TEMPLATE_FIELD_FLOW_LABEL = 40,
82 TEMPLATE_FIELD_DSAP_SSAP = 41,
83 TEMPLATE_FIELD_SNAP_OUI = 42,
84 TEMPLATE_FIELD_FWD_VID = 43,
85 TEMPLATE_FIELD_RANGE_CHK = 44,
86 TEMPLATE_FIELD_VLAN_GMSK = 45, /* VLAN Group Mask/IP range check */
87 TEMPLATE_FIELD_DLP = 46,
88 TEMPLATE_FIELD_META_DATA = 47,
89 TEMPLATE_FIELD_SRC_FWD_VID = 48,
90 TEMPLATE_FIELD_SLP = 49,
91 };
92
93 /* The meaning of TEMPLATE_FIELD_VLAN depends on phase and the configuration in
94 * RTL930X_PIE_CTRL. We use always the same definition and map to the inner VLAN tag:
95 */
96 #define TEMPLATE_FIELD_VLAN TEMPLATE_FIELD_ITAG
97
98 /* Number of fixed templates predefined in the RTL9300 SoC */
99 #define N_FIXED_TEMPLATES 5
100 /* RTL9300 specific predefined templates */
101 static enum template_field_id fixed_templates[N_FIXED_TEMPLATES][N_FIXED_FIELDS] =
102 {
103 {
104 TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2,
105 TEMPLATE_FIELD_SMAC0, TEMPLATE_FIELD_SMAC1, TEMPLATE_FIELD_SMAC2,
106 TEMPLATE_FIELD_VLAN, TEMPLATE_FIELD_IP_TOS_PROTO, TEMPLATE_FIELD_DSAP_SSAP,
107 TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1
108 }, {
109 TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0,
110 TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_IP_TOS_PROTO, TEMPLATE_FIELD_TCP_INFO,
111 TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_L4_DPORT, TEMPLATE_FIELD_VLAN,
112 TEMPLATE_FIELD_RANGE_CHK, TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1
113 }, {
114 TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2,
115 TEMPLATE_FIELD_VLAN, TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_IP_TOS_PROTO,
116 TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0,
117 TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_L4_DPORT
118 }, {
119 TEMPLATE_FIELD_DIP0, TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_DIP2,
120 TEMPLATE_FIELD_DIP3, TEMPLATE_FIELD_DIP4, TEMPLATE_FIELD_DIP5,
121 TEMPLATE_FIELD_DIP6, TEMPLATE_FIELD_DIP7, TEMPLATE_FIELD_IP_TOS_PROTO,
122 TEMPLATE_FIELD_TCP_INFO, TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_L4_DPORT
123 }, {
124 TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_SIP2,
125 TEMPLATE_FIELD_SIP3, TEMPLATE_FIELD_SIP4, TEMPLATE_FIELD_SIP5,
126 TEMPLATE_FIELD_SIP6, TEMPLATE_FIELD_SIP7, TEMPLATE_FIELD_VLAN,
127 TEMPLATE_FIELD_RANGE_CHK, TEMPLATE_FIELD_SPM1, TEMPLATE_FIELD_SPM1
128 },
129 };
130
131 void rtl930x_print_matrix(void)
132 {
133 struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6);
134
135 for (int i = 0; i < 29; i++) {
136 rtl_table_read(r, i);
137 pr_debug("> %08x\n", sw_r32(rtl_table_data(r, 0)));
138 }
139 rtl_table_release(r);
140 }
141
142 inline void rtl930x_exec_tbl0_cmd(u32 cmd)
143 {
144 sw_w32(cmd, RTL930X_TBL_ACCESS_CTRL_0);
145 do { } while (sw_r32(RTL930X_TBL_ACCESS_CTRL_0) & (1 << 17));
146 }
147
148 inline void rtl930x_exec_tbl1_cmd(u32 cmd)
149 {
150 sw_w32(cmd, RTL930X_TBL_ACCESS_CTRL_1);
151 do { } while (sw_r32(RTL930X_TBL_ACCESS_CTRL_1) & (1 << 17));
152 }
153
154 inline int rtl930x_tbl_access_data_0(int i)
155 {
156 return RTL930X_TBL_ACCESS_DATA_0(i);
157 }
158
159 static inline int rtl930x_l2_port_new_salrn(int p)
160 {
161 return RTL930X_L2_PORT_SALRN(p);
162 }
163
164 static inline int rtl930x_l2_port_new_sa_fwd(int p)
165 {
166 /* TODO: The definition of the fields changed, because of the master-cpu in a stack */
167 return RTL930X_L2_PORT_NEW_SA_FWD(p);
168 }
169
170 inline static int rtl930x_trk_mbr_ctr(int group)
171 {
172 return RTL930X_TRK_MBR_CTRL + (group << 2);
173 }
174
175 static void rtl930x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info)
176 {
177 u32 v, w;
178 /* Read VLAN table (1) via register 0 */
179 struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 1);
180
181 rtl_table_read(r, vlan);
182 v = sw_r32(rtl_table_data(r, 0));
183 w = sw_r32(rtl_table_data(r, 1));
184 pr_debug("VLAN_READ %d: %08x %08x\n", vlan, v, w);
185 rtl_table_release(r);
186
187 info->tagged_ports = v >> 3;
188 info->profile_id = (w >> 24) & 7;
189 info->hash_mc_fid = !!(w & BIT(27));
190 info->hash_uc_fid = !!(w & BIT(28));
191 info->fid = ((v & 0x7) << 3) | ((w >> 29) & 0x7);
192
193 /* Read UNTAG table via table register 2 */
194 r = rtl_table_get(RTL9300_TBL_2, 0);
195 rtl_table_read(r, vlan);
196 v = sw_r32(rtl_table_data(r, 0));
197 rtl_table_release(r);
198
199 info->untagged_ports = v >> 3;
200 }
201
202 static void rtl930x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info)
203 {
204 u32 v, w;
205 /* Access VLAN table (1) via register 0 */
206 struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 1);
207
208 v = info->tagged_ports << 3;
209 v |= ((u32)info->fid) >> 3;
210
211 w = ((u32)info->fid) << 29;
212 w |= info->hash_mc_fid ? BIT(27) : 0;
213 w |= info->hash_uc_fid ? BIT(28) : 0;
214 w |= info->profile_id << 24;
215
216 sw_w32(v, rtl_table_data(r, 0));
217 sw_w32(w, rtl_table_data(r, 1));
218
219 rtl_table_write(r, vlan);
220 rtl_table_release(r);
221 }
222
223 void rtl930x_vlan_profile_dump(int profile)
224 {
225 u32 p[5];
226
227 if (profile < 0 || profile > 7)
228 return;
229
230 p[0] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile));
231 p[1] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 4);
232 p[2] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 8) & 0x1FFFFFFF;
233 p[3] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 12) & 0x1FFFFFFF;
234 p[4] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 16) & 0x1FFFFFFF;
235
236 pr_info("VLAN %d: L2 learn: %d; Unknown MC PMasks: L2 %0x, IPv4 %0x, IPv6: %0x",
237 profile, p[0] & (3 << 21), p[2], p[3], p[4]);
238 pr_info(" Routing enabled: IPv4 UC %c, IPv6 UC %c, IPv4 MC %c, IPv6 MC %c\n",
239 p[0] & BIT(17) ? 'y' : 'n', p[0] & BIT(16) ? 'y' : 'n',
240 p[0] & BIT(13) ? 'y' : 'n', p[0] & BIT(12) ? 'y' : 'n');
241 pr_info(" Bridge enabled: IPv4 MC %c, IPv6 MC %c,\n",
242 p[0] & BIT(15) ? 'y' : 'n', p[0] & BIT(14) ? 'y' : 'n');
243 pr_info("VLAN profile %d: raw %08x %08x %08x %08x %08x\n",
244 profile, p[0], p[1], p[2], p[3], p[4]);
245 }
246
247 static void rtl930x_vlan_set_untagged(u32 vlan, u64 portmask)
248 {
249 struct table_reg *r = rtl_table_get(RTL9300_TBL_2, 0);
250
251 sw_w32(portmask << 3, rtl_table_data(r, 0));
252 rtl_table_write(r, vlan);
253 rtl_table_release(r);
254 }
255
256 /* Sets the L2 forwarding to be based on either the inner VLAN tag or the outer */
257 static void rtl930x_vlan_fwd_on_inner(int port, bool is_set)
258 {
259 /* Always set all tag modes to fwd based on either inner or outer tag */
260 if (is_set)
261 sw_w32_mask(0xf, 0, RTL930X_VLAN_PORT_FWD + (port << 2));
262 else
263 sw_w32_mask(0, 0xf, RTL930X_VLAN_PORT_FWD + (port << 2));
264 }
265
266 static void rtl930x_vlan_profile_setup(int profile)
267 {
268 u32 p[5];
269
270 pr_info("In %s\n", __func__);
271 p[0] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile));
272 p[1] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 4);
273
274 /* Enable routing of Ipv4/6 Unicast and IPv4/6 Multicast traffic */
275 p[0] |= BIT(17) | BIT(16) | BIT(13) | BIT(12);
276 p[2] = 0x1fffffff; /* L2 unknown MC flooding portmask all ports, including the CPU-port */
277 p[3] = 0x1fffffff; /* IPv4 unknown MC flooding portmask */
278 p[4] = 0x1fffffff; /* IPv6 unknown MC flooding portmask */
279
280 sw_w32(p[0], RTL930X_VLAN_PROFILE_SET(profile));
281 sw_w32(p[1], RTL930X_VLAN_PROFILE_SET(profile) + 4);
282 sw_w32(p[2], RTL930X_VLAN_PROFILE_SET(profile) + 8);
283 sw_w32(p[3], RTL930X_VLAN_PROFILE_SET(profile) + 12);
284 sw_w32(p[4], RTL930X_VLAN_PROFILE_SET(profile) + 16);
285 }
286
287 static void rtl930x_l2_learning_setup(void)
288 {
289 /* Portmask for flooding broadcast traffic */
290 sw_w32(0x1fffffff, RTL930X_L2_BC_FLD_PMSK);
291
292 /* Portmask for flooding unicast traffic with unknown destination */
293 sw_w32(0x1fffffff, RTL930X_L2_UNKN_UC_FLD_PMSK);
294
295 /* Limit learning to maximum: 32k entries, after that just flood (bits 0-1) */
296 sw_w32((0x7fff << 2) | 0, RTL930X_L2_LRN_CONSTRT_CTRL);
297 }
298
299 static void rtl930x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
300 {
301 u32 cmd = 1 << 17 | /* Execute cmd */
302 0 << 16 | /* Read */
303 4 << 12 | /* Table type 0b10 */
304 (msti & 0xfff);
305 priv->r->exec_tbl0_cmd(cmd);
306
307 for (int i = 0; i < 2; i++)
308 port_state[i] = sw_r32(RTL930X_TBL_ACCESS_DATA_0(i));
309 pr_debug("MSTI: %d STATE: %08x, %08x\n", msti, port_state[0], port_state[1]);
310 }
311
312 static void rtl930x_stp_set(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
313 {
314 u32 cmd = 1 << 17 | /* Execute cmd */
315 1 << 16 | /* Write */
316 4 << 12 | /* Table type 4 */
317 (msti & 0xfff);
318
319 for (int i = 0; i < 2; i++)
320 sw_w32(port_state[i], RTL930X_TBL_ACCESS_DATA_0(i));
321 priv->r->exec_tbl0_cmd(cmd);
322 }
323
324 static inline int rtl930x_mac_force_mode_ctrl(int p)
325 {
326 return RTL930X_MAC_FORCE_MODE_CTRL + (p << 2);
327 }
328
329 static inline int rtl930x_mac_port_ctrl(int p)
330 {
331 return RTL930X_MAC_L2_PORT_CTRL(p);
332 }
333
334 static inline int rtl930x_mac_link_spd_sts(int p)
335 {
336 return RTL930X_MAC_LINK_SPD_STS(p);
337 }
338
339 static u64 rtl930x_l2_hash_seed(u64 mac, u32 vid)
340 {
341 u64 v = vid;
342
343 v <<= 48;
344 v |= mac;
345
346 return v;
347 }
348
349 /* Calculate both the block 0 and the block 1 hash by applyingthe same hash
350 * algorithm as the one used currently by the ASIC to the seed, and return
351 * both hashes in the lower and higher word of the return value since only 12 bit of
352 * the hash are significant
353 */
354 static u32 rtl930x_l2_hash_key(struct rtl838x_switch_priv *priv, u64 seed)
355 {
356 u32 k0, k1, h1, h2, h;
357
358 k0 = (u32) (((seed >> 55) & 0x1f) ^
359 ((seed >> 44) & 0x7ff) ^
360 ((seed >> 33) & 0x7ff) ^
361 ((seed >> 22) & 0x7ff) ^
362 ((seed >> 11) & 0x7ff) ^
363 (seed & 0x7ff));
364
365 h1 = (seed >> 11) & 0x7ff;
366 h1 = ((h1 & 0x1f) << 6) | ((h1 >> 5) & 0x3f);
367
368 h2 = (seed >> 33) & 0x7ff;
369 h2 = ((h2 & 0x3f) << 5)| ((h2 >> 6) & 0x3f);
370
371 k1 = (u32) (((seed << 55) & 0x1f) ^
372 ((seed >> 44) & 0x7ff) ^
373 h2 ^
374 ((seed >> 22) & 0x7ff) ^
375 h1 ^
376 (seed & 0x7ff));
377
378 /* Algorithm choice for block 0 */
379 if (sw_r32(RTL930X_L2_CTRL) & BIT(0))
380 h = k1;
381 else
382 h = k0;
383
384 /* Algorithm choice for block 1
385 * Since k0 and k1 are < 2048, adding 2048 will offset the hash into the second
386 * half of hash-space
387 * 2048 is in fact the hash-table size 16384 divided by 4 hashes per bucket
388 * divided by 2 to divide the hash space in 2
389 */
390 if (sw_r32(RTL930X_L2_CTRL) & BIT(1))
391 h |= (k1 + 2048) << 16;
392 else
393 h |= (k0 + 2048) << 16;
394
395 return h;
396 }
397
398 /* Fills an L2 entry structure from the SoC registers */
399 static void rtl930x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e)
400 {
401 pr_debug("In %s valid?\n", __func__);
402 e->valid = !!(r[2] & BIT(31));
403 if (!e->valid)
404 return;
405
406 pr_debug("In %s is valid\n", __func__);
407 e->is_ip_mc = false;
408 e->is_ipv6_mc = false;
409
410 /* TODO: Is there not a function to copy directly MAC memory? */
411 e->mac[0] = (r[0] >> 24);
412 e->mac[1] = (r[0] >> 16);
413 e->mac[2] = (r[0] >> 8);
414 e->mac[3] = r[0];
415 e->mac[4] = (r[1] >> 24);
416 e->mac[5] = (r[1] >> 16);
417
418 e->next_hop = !!(r[2] & BIT(12));
419 e->rvid = r[1] & 0xfff;
420
421 /* Is it a unicast entry? check multicast bit */
422 if (!(e->mac[0] & 1)) {
423 e->type = L2_UNICAST;
424 e->is_static = !!(r[2] & BIT(14));
425 e->port = (r[2] >> 20) & 0x3ff;
426 /* Check for trunk port */
427 if (r[2] & BIT(30)) {
428 e->is_trunk = true;
429 e->stack_dev = (e->port >> 9) & 1;
430 e->trunk = e->port & 0x3f;
431 } else {
432 e->is_trunk = false;
433 e->stack_dev = (e->port >> 6) & 0xf;
434 e->port = e->port & 0x3f;
435 }
436
437 e->block_da = !!(r[2] & BIT(15));
438 e->block_sa = !!(r[2] & BIT(16));
439 e->suspended = !!(r[2] & BIT(13));
440 e->age = (r[2] >> 17) & 3;
441 e->valid = true;
442 /* the UC_VID field in hardware is used for the VID or for the route id */
443 if (e->next_hop) {
444 e->nh_route_id = r[2] & 0x7ff;
445 e->vid = 0;
446 } else {
447 e->vid = r[2] & 0xfff;
448 e->nh_route_id = 0;
449 }
450 } else {
451 e->valid = true;
452 e->type = L2_MULTICAST;
453 e->mc_portmask_index = (r[2] >> 16) & 0x3ff;
454 }
455 }
456
457 /* Fills the 3 SoC table registers r[] with the information of in the rtl838x_l2_entry */
458 static void rtl930x_fill_l2_row(u32 r[], struct rtl838x_l2_entry *e)
459 {
460 u32 port;
461
462 if (!e->valid) {
463 r[0] = r[1] = r[2] = 0;
464 return;
465 }
466
467 r[2] = BIT(31); /* Set valid bit */
468
469 r[0] = ((u32)e->mac[0]) << 24 |
470 ((u32)e->mac[1]) << 16 |
471 ((u32)e->mac[2]) << 8 |
472 ((u32)e->mac[3]);
473 r[1] = ((u32)e->mac[4]) << 24 |
474 ((u32)e->mac[5]) << 16;
475
476 r[2] |= e->next_hop ? BIT(12) : 0;
477
478 if (e->type == L2_UNICAST) {
479 r[2] |= e->is_static ? BIT(14) : 0;
480 r[1] |= e->rvid & 0xfff;
481 r[2] |= (e->port & 0x3ff) << 20;
482 if (e->is_trunk) {
483 r[2] |= BIT(30);
484 port = e->stack_dev << 9 | (e->port & 0x3f);
485 } else {
486 port = (e->stack_dev & 0xf) << 6;
487 port |= e->port & 0x3f;
488 }
489 r[2] |= port << 20;
490 r[2] |= e->block_da ? BIT(15) : 0;
491 r[2] |= e->block_sa ? BIT(17) : 0;
492 r[2] |= e->suspended ? BIT(13) : 0;
493 r[2] |= (e->age & 0x3) << 17;
494 /* the UC_VID field in hardware is used for the VID or for the route id */
495 if (e->next_hop)
496 r[2] |= e->nh_route_id & 0x7ff;
497 else
498 r[2] |= e->vid & 0xfff;
499 } else { /* L2_MULTICAST */
500 r[2] |= (e->mc_portmask_index & 0x3ff) << 16;
501 r[2] |= e->mc_mac_index & 0x7ff;
502 }
503 }
504
505 /* Read an L2 UC or MC entry out of a hash bucket of the L2 forwarding table
506 * hash is the id of the bucket and pos is the position of the entry in that bucket
507 * The data read from the SoC is filled into rtl838x_l2_entry
508 */
509 static u64 rtl930x_read_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e)
510 {
511 u32 r[3];
512 struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 0);
513 u32 idx;
514 u64 mac;
515 u64 seed;
516
517 pr_debug("%s: hash %08x, pos: %d\n", __func__, hash, pos);
518
519 /* On the RTL93xx, 2 different hash algorithms are used making it a
520 * total of 8 buckets that need to be searched, 4 for each hash-half
521 * Use second hash space when bucket is between 4 and 8
522 */
523 if (pos >= 4) {
524 pos -= 4;
525 hash >>= 16;
526 } else {
527 hash &= 0xffff;
528 }
529
530 idx = (0 << 14) | (hash << 2) | pos; /* Search SRAM, with hash and at pos in bucket */
531 pr_debug("%s: NOW hash %08x, pos: %d\n", __func__, hash, pos);
532
533 rtl_table_read(q, idx);
534 for (int i = 0; i < 3; i++)
535 r[i] = sw_r32(rtl_table_data(q, i));
536
537 rtl_table_release(q);
538
539 rtl930x_fill_l2_entry(r, e);
540
541 pr_debug("%s: valid: %d, nh: %d\n", __func__, e->valid, e->next_hop);
542 if (!e->valid)
543 return 0;
544
545 mac = ((u64)e->mac[0]) << 40 |
546 ((u64)e->mac[1]) << 32 |
547 ((u64)e->mac[2]) << 24 |
548 ((u64)e->mac[3]) << 16 |
549 ((u64)e->mac[4]) << 8 |
550 ((u64)e->mac[5]);
551
552 seed = rtl930x_l2_hash_seed(mac, e->rvid);
553 pr_debug("%s: mac %016llx, seed %016llx\n", __func__, mac, seed);
554
555 /* return vid with concatenated mac as unique id */
556 return seed;
557 }
558
559 static void rtl930x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e)
560 {
561 u32 r[3];
562 struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 0);
563 u32 idx = (0 << 14) | (hash << 2) | pos; /* Access SRAM, with hash and at pos in bucket */
564
565 pr_debug("%s: hash %d, pos %d\n", __func__, hash, pos);
566 pr_debug("%s: index %d -> mac %02x:%02x:%02x:%02x:%02x:%02x\n", __func__, idx,
567 e->mac[0], e->mac[1], e->mac[2], e->mac[3],e->mac[4],e->mac[5]);
568
569 rtl930x_fill_l2_row(r, e);
570
571 for (int i = 0; i < 3; i++)
572 sw_w32(r[i], rtl_table_data(q, i));
573
574 rtl_table_write(q, idx);
575 rtl_table_release(q);
576 }
577
578 static u64 rtl930x_read_cam(int idx, struct rtl838x_l2_entry *e)
579 {
580 u32 r[3];
581 struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 1);
582
583 rtl_table_read(q, idx);
584 for (int i = 0; i < 3; i++)
585 r[i] = sw_r32(rtl_table_data(q, i));
586
587 rtl_table_release(q);
588
589 rtl930x_fill_l2_entry(r, e);
590 if (!e->valid)
591 return 0;
592
593 /* return mac with concatenated vid as unique id */
594 return ((u64)r[0] << 28) | ((r[1] & 0xffff0000) >> 4) | e->vid;
595 }
596
597 static void rtl930x_write_cam(int idx, struct rtl838x_l2_entry *e)
598 {
599 u32 r[3];
600 struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 1); /* Access L2 Table 1 */
601
602 rtl930x_fill_l2_row(r, e);
603
604 for (int i = 0; i < 3; i++)
605 sw_w32(r[i], rtl_table_data(q, i));
606
607 rtl_table_write(q, idx);
608 rtl_table_release(q);
609 }
610
611 static u64 rtl930x_read_mcast_pmask(int idx)
612 {
613 u32 portmask;
614 /* Read MC_PORTMASK (2) via register RTL9300_TBL_L2 */
615 struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 2);
616
617 rtl_table_read(q, idx);
618 portmask = sw_r32(rtl_table_data(q, 0));
619 portmask >>= 3;
620 rtl_table_release(q);
621
622 pr_debug("%s: Index idx %d has portmask %08x\n", __func__, idx, portmask);
623
624 return portmask;
625 }
626
627 static void rtl930x_write_mcast_pmask(int idx, u64 portmask)
628 {
629 u32 pm = portmask;
630
631 /* Access MC_PORTMASK (2) via register RTL9300_TBL_L2 */
632 struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 2);
633
634 pr_debug("%s: Index idx %d has portmask %08x\n", __func__, idx, pm);
635 pm <<= 3;
636 sw_w32(pm, rtl_table_data(q, 0));
637 rtl_table_write(q, idx);
638 rtl_table_release(q);
639 }
640
641 u64 rtl930x_traffic_get(int source)
642 {
643 u32 v;
644 struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6);
645
646 rtl_table_read(r, source);
647 v = sw_r32(rtl_table_data(r, 0));
648 rtl_table_release(r);
649 v = v >> 3;
650
651 return v;
652 }
653
654 /* Enable traffic between a source port and a destination port matrix */
655 void rtl930x_traffic_set(int source, u64 dest_matrix)
656 {
657 struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6);
658
659 sw_w32((dest_matrix << 3), rtl_table_data(r, 0));
660 rtl_table_write(r, source);
661 rtl_table_release(r);
662 }
663
664 void rtl930x_traffic_enable(int source, int dest)
665 {
666 struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6);
667 rtl_table_read(r, source);
668 sw_w32_mask(0, BIT(dest + 3), rtl_table_data(r, 0));
669 rtl_table_write(r, source);
670 rtl_table_release(r);
671 }
672
673 void rtl930x_traffic_disable(int source, int dest)
674 {
675 struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6);
676 rtl_table_read(r, source);
677 sw_w32_mask(BIT(dest + 3), 0, rtl_table_data(r, 0));
678 rtl_table_write(r, source);
679 rtl_table_release(r);
680 }
681
682 void rtl9300_dump_debug(void)
683 {
684 u16 r = RTL930X_STAT_PRVTE_DROP_COUNTER0;
685
686 for (int i = 0; i < 10; i ++) {
687 pr_info("# %d %08x %08x %08x %08x %08x %08x %08x %08x\n", i * 8,
688 sw_r32(r), sw_r32(r + 4), sw_r32(r + 8), sw_r32(r + 12),
689 sw_r32(r + 16), sw_r32(r + 20), sw_r32(r + 24), sw_r32(r + 28));
690 r += 32;
691 }
692 pr_info("# %08x %08x %08x %08x %08x\n",
693 sw_r32(r), sw_r32(r + 4), sw_r32(r + 8), sw_r32(r + 12), sw_r32(r + 16));
694 rtl930x_print_matrix();
695 pr_info("RTL930X_L2_PORT_SABLK_CTRL: %08x, RTL930X_L2_PORT_DABLK_CTRL %08x\n",
696 sw_r32(RTL930X_L2_PORT_SABLK_CTRL), sw_r32(RTL930X_L2_PORT_DABLK_CTRL)
697
698 );
699 }
700
701 irqreturn_t rtl930x_switch_irq(int irq, void *dev_id)
702 {
703 struct dsa_switch *ds = dev_id;
704 u32 ports = sw_r32(RTL930X_ISR_PORT_LINK_STS_CHG);
705 u32 link;
706
707 /* Clear status */
708 sw_w32(ports, RTL930X_ISR_PORT_LINK_STS_CHG);
709
710 for (int i = 0; i < 28; i++) {
711 if (ports & BIT(i)) {
712 /* Read the register twice because of issues with latency at least
713 * with the external RTL8226 PHY on the XGS1210
714 */
715 link = sw_r32(RTL930X_MAC_LINK_STS);
716 link = sw_r32(RTL930X_MAC_LINK_STS);
717 if (link & BIT(i))
718 dsa_port_phylink_mac_change(ds, i, true);
719 else
720 dsa_port_phylink_mac_change(ds, i, false);
721 }
722 }
723
724 return IRQ_HANDLED;
725 }
726
727 int rtl930x_write_phy(u32 port, u32 page, u32 reg, u32 val)
728 {
729 u32 v;
730 int err = 0;
731
732 pr_debug("%s: port %d, page: %d, reg: %x, val: %x\n", __func__, port, page, reg, val);
733
734 if (port > 63 || page > 4095 || reg > 31)
735 return -ENOTSUPP;
736
737 val &= 0xffff;
738 mutex_lock(&smi_lock);
739
740 sw_w32(BIT(port), RTL930X_SMI_ACCESS_PHY_CTRL_0);
741 sw_w32_mask(0xffff << 16, val << 16, RTL930X_SMI_ACCESS_PHY_CTRL_2);
742 v = reg << 20 | page << 3 | 0x1f << 15 | BIT(2) | BIT(0);
743 sw_w32(v, RTL930X_SMI_ACCESS_PHY_CTRL_1);
744
745 do {
746 v = sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_1);
747 } while (v & 0x1);
748
749 if (v & 0x2)
750 err = -EIO;
751
752 mutex_unlock(&smi_lock);
753
754 return err;
755 }
756
757 int rtl930x_read_phy(u32 port, u32 page, u32 reg, u32 *val)
758 {
759 u32 v;
760 int err = 0;
761
762 if (port > 63 || page > 4095 || reg > 31)
763 return -ENOTSUPP;
764
765 mutex_lock(&smi_lock);
766
767 sw_w32_mask(0xffff << 16, port << 16, RTL930X_SMI_ACCESS_PHY_CTRL_2);
768 v = reg << 20 | page << 3 | 0x1f << 15 | 1;
769 sw_w32(v, RTL930X_SMI_ACCESS_PHY_CTRL_1);
770
771 do {
772 v = sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_1);
773 } while ( v & 0x1);
774
775 if (v & BIT(25)) {
776 pr_debug("Error reading phy %d, register %d\n", port, reg);
777 err = -EIO;
778 }
779 *val = (sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_2) & 0xffff);
780
781 pr_debug("%s: port %d, page: %d, reg: %x, val: %x\n", __func__, port, page, reg, *val);
782
783 mutex_unlock(&smi_lock);
784
785 return err;
786 }
787
788 /* Write to an mmd register of the PHY */
789 int rtl930x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val)
790 {
791 int err = 0;
792 u32 v;
793
794 mutex_lock(&smi_lock);
795
796 /* Set PHY to access */
797 sw_w32(BIT(port), RTL930X_SMI_ACCESS_PHY_CTRL_0);
798
799 /* Set data to write */
800 sw_w32_mask(0xffff << 16, val << 16, RTL930X_SMI_ACCESS_PHY_CTRL_2);
801
802 /* Set MMD device number and register to write to */
803 sw_w32(devnum << 16 | (regnum & 0xffff), RTL930X_SMI_ACCESS_PHY_CTRL_3);
804
805 v = BIT(2) | BIT(1) | BIT(0); /* WRITE | MMD-access | EXEC */
806 sw_w32(v, RTL930X_SMI_ACCESS_PHY_CTRL_1);
807
808 do {
809 v = sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_1);
810 } while (v & BIT(0));
811
812 pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__, port, regnum, val, err);
813 mutex_unlock(&smi_lock);
814 return err;
815 }
816
817 /* Read an mmd register of the PHY */
818 int rtl930x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val)
819 {
820 int err = 0;
821 u32 v;
822
823 mutex_lock(&smi_lock);
824
825 /* Set PHY to access */
826 sw_w32_mask(0xffff << 16, port << 16, RTL930X_SMI_ACCESS_PHY_CTRL_2);
827
828 /* Set MMD device number and register to write to */
829 sw_w32(devnum << 16 | (regnum & 0xffff), RTL930X_SMI_ACCESS_PHY_CTRL_3);
830
831 v = BIT(1) | BIT(0); /* MMD-access | EXEC */
832 sw_w32(v, RTL930X_SMI_ACCESS_PHY_CTRL_1);
833
834 do {
835 v = sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_1);
836 } while (v & BIT(0));
837 /* There is no error-checking via BIT 25 of v, as it does not seem to be set correctly */
838 *val = (sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_2) & 0xffff);
839 pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__, port, regnum, *val, err);
840
841 mutex_unlock(&smi_lock);
842
843 return err;
844 }
845
846 /* Calculate both the block 0 and the block 1 hash, and return in
847 * lower and higher word of the return value since only 12 bit of
848 * the hash are significant
849 */
850 u32 rtl930x_hash(struct rtl838x_switch_priv *priv, u64 seed)
851 {
852 u32 k0, k1, h1, h2, h;
853
854 k0 = (u32) (((seed >> 55) & 0x1f) ^
855 ((seed >> 44) & 0x7ff) ^
856 ((seed >> 33) & 0x7ff) ^
857 ((seed >> 22) & 0x7ff) ^
858 ((seed >> 11) & 0x7ff) ^
859 (seed & 0x7ff));
860
861 h1 = (seed >> 11) & 0x7ff;
862 h1 = ((h1 & 0x1f) << 6) | ((h1 >> 5) & 0x3f);
863
864 h2 = (seed >> 33) & 0x7ff;
865 h2 = ((h2 & 0x3f) << 5) | ((h2 >> 6) & 0x3f);
866
867 k1 = (u32) (((seed << 55) & 0x1f) ^
868 ((seed >> 44) & 0x7ff) ^
869 h2 ^
870 ((seed >> 22) & 0x7ff) ^
871 h1 ^
872 (seed & 0x7ff));
873
874 /* Algorithm choice for block 0 */
875 if (sw_r32(RTL930X_L2_CTRL) & BIT(0))
876 h = k1;
877 else
878 h = k0;
879
880 /* Algorithm choice for block 1
881 * Since k0 and k1 are < 2048, adding 2048 will offset the hash into the second
882 * half of hash-space
883 * 2048 is in fact the hash-table size 16384 divided by 4 hashes per bucket
884 * divided by 2 to divide the hash space in 2
885 */
886 if (sw_r32(RTL930X_L2_CTRL) & BIT(1))
887 h |= (k1 + 2048) << 16;
888 else
889 h |= (k0 + 2048) << 16;
890
891 return h;
892 }
893
894 /* Enables or disables the EEE/EEEP capability of a port */
895 void rtl930x_port_eee_set(struct rtl838x_switch_priv *priv, int port, bool enable)
896 {
897 u32 v;
898
899 /* This works only for Ethernet ports, and on the RTL930X, ports from 26 are SFP */
900 if (port >= 26)
901 return;
902
903 pr_debug("In %s: setting port %d to %d\n", __func__, port, enable);
904 v = enable ? 0x3f : 0x0;
905
906 /* Set EEE/EEEP state for 100, 500, 1000MBit and 2.5, 5 and 10GBit */
907 sw_w32_mask(0, v << 10, rtl930x_mac_force_mode_ctrl(port));
908
909 /* Set TX/RX EEE state */
910 v = enable ? 0x3 : 0x0;
911 sw_w32(v, RTL930X_EEE_CTRL(port));
912
913 priv->ports[port].eee_enabled = enable;
914 }
915
916 /* Get EEE own capabilities and negotiation result */
917 int rtl930x_eee_port_ability(struct rtl838x_switch_priv *priv, struct ethtool_eee *e, int port)
918 {
919 u32 link, a;
920
921 if (port >= 26)
922 return -ENOTSUPP;
923
924 pr_info("In %s, port %d\n", __func__, port);
925 link = sw_r32(RTL930X_MAC_LINK_STS);
926 link = sw_r32(RTL930X_MAC_LINK_STS);
927 if (!(link & BIT(port)))
928 return 0;
929
930 pr_info("Setting advertised\n");
931 if (sw_r32(rtl930x_mac_force_mode_ctrl(port)) & BIT(10))
932 e->advertised |= ADVERTISED_100baseT_Full;
933
934 if (sw_r32(rtl930x_mac_force_mode_ctrl(port)) & BIT(12))
935 e->advertised |= ADVERTISED_1000baseT_Full;
936
937 if (priv->ports[port].is2G5 && sw_r32(rtl930x_mac_force_mode_ctrl(port)) & BIT(13)) {
938 pr_info("ADVERTISING 2.5G EEE\n");
939 e->advertised |= ADVERTISED_2500baseX_Full;
940 }
941
942 if (priv->ports[port].is10G && sw_r32(rtl930x_mac_force_mode_ctrl(port)) & BIT(15))
943 e->advertised |= ADVERTISED_10000baseT_Full;
944
945 a = sw_r32(RTL930X_MAC_EEE_ABLTY);
946 a = sw_r32(RTL930X_MAC_EEE_ABLTY);
947 pr_info("Link partner: %08x\n", a);
948 if (a & BIT(port)) {
949 e->lp_advertised = ADVERTISED_100baseT_Full;
950 e->lp_advertised |= ADVERTISED_1000baseT_Full;
951 if (priv->ports[port].is2G5)
952 e->lp_advertised |= ADVERTISED_2500baseX_Full;
953 if (priv->ports[port].is10G)
954 e->lp_advertised |= ADVERTISED_10000baseT_Full;
955 }
956
957 /* Read 2x to clear latched state */
958 a = sw_r32(RTL930X_EEEP_PORT_CTRL(port));
959 a = sw_r32(RTL930X_EEEP_PORT_CTRL(port));
960 pr_info("%s RTL930X_EEEP_PORT_CTRL: %08x\n", __func__, a);
961
962 return 0;
963 }
964
965 static void rtl930x_init_eee(struct rtl838x_switch_priv *priv, bool enable)
966 {
967 pr_info("Setting up EEE, state: %d\n", enable);
968
969 /* Setup EEE on all ports */
970 for (int i = 0; i < priv->cpu_port; i++) {
971 if (priv->ports[i].phy)
972 rtl930x_port_eee_set(priv, i, enable);
973 }
974
975 priv->eee_enabled = enable;
976 }
977 #define HASH_PICK(val, lsb, len) ((val & (((1 << len) - 1) << lsb)) >> lsb)
978
979 static u32 rtl930x_l3_hash4(u32 ip, int algorithm, bool move_dip)
980 {
981 u32 rows[4];
982 u32 hash;
983 u32 s0, s1, pH;
984
985 memset(rows, 0, sizeof(rows));
986
987 rows[0] = HASH_PICK(ip, 27, 5);
988 rows[1] = HASH_PICK(ip, 18, 9);
989 rows[2] = HASH_PICK(ip, 9, 9);
990
991 if (!move_dip)
992 rows[3] = HASH_PICK(ip, 0, 9);
993
994 if (!algorithm) {
995 hash = rows[0] ^ rows[1] ^ rows[2] ^ rows[3];
996 } else {
997 s0 = rows[0] + rows[1] + rows[2];
998 s1 = (s0 & 0x1ff) + ((s0 & (0x1ff << 9)) >> 9);
999 pH = (s1 & 0x1ff) + ((s1 & (0x1ff << 9)) >> 9);
1000 hash = pH ^ rows[3];
1001 }
1002 return hash;
1003 }
1004
1005 // Currently not used
1006 // static u32 rtl930x_l3_hash6(struct in6_addr *ip6, int algorithm, bool move_dip)
1007 // {
1008 // u32 rows[16];
1009 // u32 hash;
1010 // u32 s0, s1, pH;
1011
1012 // rows[0] = (HASH_PICK(ip6->s6_addr[0], 6, 2) << 0);
1013 // rows[1] = (HASH_PICK(ip6->s6_addr[0], 0, 6) << 3) | HASH_PICK(ip6->s6_addr[1], 5, 3);
1014 // rows[2] = (HASH_PICK(ip6->s6_addr[1], 0, 5) << 4) | HASH_PICK(ip6->s6_addr[2], 4, 4);
1015 // rows[3] = (HASH_PICK(ip6->s6_addr[2], 0, 4) << 5) | HASH_PICK(ip6->s6_addr[3], 3, 5);
1016 // rows[4] = (HASH_PICK(ip6->s6_addr[3], 0, 3) << 6) | HASH_PICK(ip6->s6_addr[4], 2, 6);
1017 // rows[5] = (HASH_PICK(ip6->s6_addr[4], 0, 2) << 7) | HASH_PICK(ip6->s6_addr[5], 1, 7);
1018 // rows[6] = (HASH_PICK(ip6->s6_addr[5], 0, 1) << 8) | HASH_PICK(ip6->s6_addr[6], 0, 8);
1019 // rows[7] = (HASH_PICK(ip6->s6_addr[7], 0, 8) << 1) | HASH_PICK(ip6->s6_addr[8], 7, 1);
1020 // rows[8] = (HASH_PICK(ip6->s6_addr[8], 0, 7) << 2) | HASH_PICK(ip6->s6_addr[9], 6, 2);
1021 // rows[9] = (HASH_PICK(ip6->s6_addr[9], 0, 6) << 3) | HASH_PICK(ip6->s6_addr[10], 5, 3);
1022 // rows[10] = (HASH_PICK(ip6->s6_addr[10], 0, 5) << 4) | HASH_PICK(ip6->s6_addr[11], 4, 4);
1023 // if (!algorithm) {
1024 // rows[11] = (HASH_PICK(ip6->s6_addr[11], 0, 4) << 5) |
1025 // (HASH_PICK(ip6->s6_addr[12], 3, 5) << 0);
1026 // rows[12] = (HASH_PICK(ip6->s6_addr[12], 0, 3) << 6) |
1027 // (HASH_PICK(ip6->s6_addr[13], 2, 6) << 0);
1028 // rows[13] = (HASH_PICK(ip6->s6_addr[13], 0, 2) << 7) |
1029 // (HASH_PICK(ip6->s6_addr[14], 1, 7) << 0);
1030 // if (!move_dip) {
1031 // rows[14] = (HASH_PICK(ip6->s6_addr[14], 0, 1) << 8) |
1032 // (HASH_PICK(ip6->s6_addr[15], 0, 8) << 0);
1033 // }
1034 // hash = rows[0] ^ rows[1] ^ rows[2] ^ rows[3] ^ rows[4] ^
1035 // rows[5] ^ rows[6] ^ rows[7] ^ rows[8] ^ rows[9] ^
1036 // rows[10] ^ rows[11] ^ rows[12] ^ rows[13] ^ rows[14];
1037 // } else {
1038 // rows[11] = (HASH_PICK(ip6->s6_addr[11], 0, 4) << 5);
1039 // rows[12] = (HASH_PICK(ip6->s6_addr[12], 3, 5) << 0);
1040 // rows[13] = (HASH_PICK(ip6->s6_addr[12], 0, 3) << 6) |
1041 // HASH_PICK(ip6->s6_addr[13], 2, 6);
1042 // rows[14] = (HASH_PICK(ip6->s6_addr[13], 0, 2) << 7) |
1043 // HASH_PICK(ip6->s6_addr[14], 1, 7);
1044 // if (!move_dip) {
1045 // rows[15] = (HASH_PICK(ip6->s6_addr[14], 0, 1) << 8) |
1046 // (HASH_PICK(ip6->s6_addr[15], 0, 8) << 0);
1047 // }
1048 // s0 = rows[12] + rows[13] + rows[14];
1049 // s1 = (s0 & 0x1ff) + ((s0 & (0x1ff << 9)) >> 9);
1050 // pH = (s1 & 0x1ff) + ((s1 & (0x1ff << 9)) >> 9);
1051 // hash = rows[0] ^ rows[1] ^ rows[2] ^ rows[3] ^ rows[4] ^
1052 // rows[5] ^ rows[6] ^ rows[7] ^ rows[8] ^ rows[9] ^
1053 // rows[10] ^ rows[11] ^ pH ^ rows[15];
1054 // }
1055 // return hash;
1056 // }
1057
1058 /* Read a prefix route entry from the L3_PREFIX_ROUTE_IPUC table
1059 * We currently only support IPv4 and IPv6 unicast route
1060 */
1061 static void rtl930x_route_read(int idx, struct rtl83xx_route *rt)
1062 {
1063 u32 v, ip4_m;
1064 bool host_route, default_route;
1065 struct in6_addr ip6_m;
1066
1067 /* Read L3_PREFIX_ROUTE_IPUC table (2) via register RTL9300_TBL_1 */
1068 struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 2);
1069
1070 rtl_table_read(r, idx);
1071 /* The table has a size of 11 registers */
1072 rt->attr.valid = !!(sw_r32(rtl_table_data(r, 0)) & BIT(31));
1073 if (!rt->attr.valid)
1074 goto out;
1075
1076 rt->attr.type = (sw_r32(rtl_table_data(r, 0)) >> 29) & 0x3;
1077
1078 v = sw_r32(rtl_table_data(r, 10));
1079 host_route = !!(v & BIT(21));
1080 default_route = !!(v & BIT(20));
1081 rt->prefix_len = -1;
1082 pr_info("%s: host route %d, default_route %d\n", __func__, host_route, default_route);
1083
1084 switch (rt->attr.type) {
1085 case 0: /* IPv4 Unicast route */
1086 rt->dst_ip = sw_r32(rtl_table_data(r, 4));
1087 ip4_m = sw_r32(rtl_table_data(r, 9));
1088 pr_info("%s: Read ip4 mask: %08x\n", __func__, ip4_m);
1089 rt->prefix_len = host_route ? 32 : -1;
1090 rt->prefix_len = (rt->prefix_len < 0 && default_route) ? 0 : -1;
1091 if (rt->prefix_len < 0)
1092 rt->prefix_len = inet_mask_len(ip4_m);
1093 break;
1094 case 2: /* IPv6 Unicast route */
1095 ipv6_addr_set(&rt->dst_ip6,
1096 sw_r32(rtl_table_data(r, 1)), sw_r32(rtl_table_data(r, 2)),
1097 sw_r32(rtl_table_data(r, 3)), sw_r32(rtl_table_data(r, 4)));
1098 ipv6_addr_set(&ip6_m,
1099 sw_r32(rtl_table_data(r, 6)), sw_r32(rtl_table_data(r, 7)),
1100 sw_r32(rtl_table_data(r, 8)), sw_r32(rtl_table_data(r, 9)));
1101 rt->prefix_len = host_route ? 128 : 0;
1102 rt->prefix_len = (rt->prefix_len < 0 && default_route) ? 0 : -1;
1103 if (rt->prefix_len < 0)
1104 rt->prefix_len = find_last_bit((unsigned long int *)&ip6_m.s6_addr32,
1105 128);
1106 break;
1107 case 1: /* IPv4 Multicast route */
1108 case 3: /* IPv6 Multicast route */
1109 pr_warn("%s: route type not supported\n", __func__);
1110 goto out;
1111 }
1112
1113 rt->attr.hit = !!(v & BIT(22));
1114 rt->attr.action = (v >> 18) & 3;
1115 rt->nh.id = (v >> 7) & 0x7ff;
1116 rt->attr.ttl_dec = !!(v & BIT(6));
1117 rt->attr.ttl_check = !!(v & BIT(5));
1118 rt->attr.dst_null = !!(v & BIT(4));
1119 rt->attr.qos_as = !!(v & BIT(3));
1120 rt->attr.qos_prio = v & 0x7;
1121 pr_info("%s: index %d is valid: %d\n", __func__, idx, rt->attr.valid);
1122 pr_info("%s: next_hop: %d, hit: %d, action :%d, ttl_dec %d, ttl_check %d, dst_null %d\n",
1123 __func__, rt->nh.id, rt->attr.hit, rt->attr.action,
1124 rt->attr.ttl_dec, rt->attr.ttl_check, rt->attr.dst_null);
1125 pr_info("%s: GW: %pI4, prefix_len: %d\n", __func__, &rt->dst_ip, rt->prefix_len);
1126 out:
1127 rtl_table_release(r);
1128 }
1129
1130 static void rtl930x_net6_mask(int prefix_len, struct in6_addr *ip6_m)
1131 {
1132 int o, b;
1133 /* Define network mask */
1134 o = prefix_len >> 3;
1135 b = prefix_len & 0x7;
1136 memset(ip6_m->s6_addr, 0xff, o);
1137 ip6_m->s6_addr[o] |= b ? 0xff00 >> b : 0x00;
1138 }
1139
1140 /* Read a host route entry from the table using its index
1141 * We currently only support IPv4 and IPv6 unicast route
1142 */
1143 static void rtl930x_host_route_read(int idx, struct rtl83xx_route *rt)
1144 {
1145 u32 v;
1146 /* Read L3_HOST_ROUTE_IPUC table (1) via register RTL9300_TBL_1 */
1147 struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 1);
1148
1149 idx = ((idx / 6) * 8) + (idx % 6);
1150
1151 pr_debug("In %s, physical index %d\n", __func__, idx);
1152 rtl_table_read(r, idx);
1153 /* The table has a size of 5 (for UC, 11 for MC) registers */
1154 v = sw_r32(rtl_table_data(r, 0));
1155 rt->attr.valid = !!(v & BIT(31));
1156 if (!rt->attr.valid)
1157 goto out;
1158 rt->attr.type = (v >> 29) & 0x3;
1159 switch (rt->attr.type) {
1160 case 0: /* IPv4 Unicast route */
1161 rt->dst_ip = sw_r32(rtl_table_data(r, 4));
1162 break;
1163 case 2: /* IPv6 Unicast route */
1164 ipv6_addr_set(&rt->dst_ip6,
1165 sw_r32(rtl_table_data(r, 3)), sw_r32(rtl_table_data(r, 2)),
1166 sw_r32(rtl_table_data(r, 1)), sw_r32(rtl_table_data(r, 0)));
1167 break;
1168 case 1: /* IPv4 Multicast route */
1169 case 3: /* IPv6 Multicast route */
1170 pr_warn("%s: route type not supported\n", __func__);
1171 goto out;
1172 }
1173
1174 rt->attr.hit = !!(v & BIT(20));
1175 rt->attr.dst_null = !!(v & BIT(19));
1176 rt->attr.action = (v >> 17) & 3;
1177 rt->nh.id = (v >> 6) & 0x7ff;
1178 rt->attr.ttl_dec = !!(v & BIT(5));
1179 rt->attr.ttl_check = !!(v & BIT(4));
1180 rt->attr.qos_as = !!(v & BIT(3));
1181 rt->attr.qos_prio = v & 0x7;
1182 pr_debug("%s: index %d is valid: %d\n", __func__, idx, rt->attr.valid);
1183 pr_debug("%s: next_hop: %d, hit: %d, action :%d, ttl_dec %d, ttl_check %d, dst_null %d\n",
1184 __func__, rt->nh.id, rt->attr.hit, rt->attr.action, rt->attr.ttl_dec, rt->attr.ttl_check,
1185 rt->attr.dst_null);
1186 pr_debug("%s: Destination: %pI4\n", __func__, &rt->dst_ip);
1187
1188 out:
1189 rtl_table_release(r);
1190 }
1191
1192 /* Write a host route entry from the table using its index
1193 * We currently only support IPv4 and IPv6 unicast route
1194 */
1195 static void rtl930x_host_route_write(int idx, struct rtl83xx_route *rt)
1196 {
1197 u32 v;
1198 /* Access L3_HOST_ROUTE_IPUC table (1) via register RTL9300_TBL_1 */
1199 struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 1);
1200 /* The table has a size of 5 (for UC, 11 for MC) registers */
1201
1202 idx = ((idx / 6) * 8) + (idx % 6);
1203
1204 pr_debug("%s: index %d is valid: %d\n", __func__, idx, rt->attr.valid);
1205 pr_debug("%s: next_hop: %d, hit: %d, action :%d, ttl_dec %d, ttl_check %d, dst_null %d\n",
1206 __func__, rt->nh.id, rt->attr.hit, rt->attr.action, rt->attr.ttl_dec, rt->attr.ttl_check,
1207 rt->attr.dst_null);
1208 pr_debug("%s: GW: %pI4, prefix_len: %d\n", __func__, &rt->dst_ip, rt->prefix_len);
1209
1210 v = BIT(31); /* Entry is valid */
1211 v |= (rt->attr.type & 0x3) << 29;
1212 v |= rt->attr.hit ? BIT(20) : 0;
1213 v |= rt->attr.dst_null ? BIT(19) : 0;
1214 v |= (rt->attr.action & 0x3) << 17;
1215 v |= (rt->nh.id & 0x7ff) << 6;
1216 v |= rt->attr.ttl_dec ? BIT(5) : 0;
1217 v |= rt->attr.ttl_check ? BIT(4) : 0;
1218 v |= rt->attr.qos_as ? BIT(3) : 0;
1219 v |= rt->attr.qos_prio & 0x7;
1220
1221 sw_w32(v, rtl_table_data(r, 0));
1222 switch (rt->attr.type) {
1223 case 0: /* IPv4 Unicast route */
1224 sw_w32(0, rtl_table_data(r, 1));
1225 sw_w32(0, rtl_table_data(r, 2));
1226 sw_w32(0, rtl_table_data(r, 3));
1227 sw_w32(rt->dst_ip, rtl_table_data(r, 4));
1228 break;
1229 case 2: /* IPv6 Unicast route */
1230 sw_w32(rt->dst_ip6.s6_addr32[0], rtl_table_data(r, 1));
1231 sw_w32(rt->dst_ip6.s6_addr32[1], rtl_table_data(r, 2));
1232 sw_w32(rt->dst_ip6.s6_addr32[2], rtl_table_data(r, 3));
1233 sw_w32(rt->dst_ip6.s6_addr32[3], rtl_table_data(r, 4));
1234 break;
1235 case 1: /* IPv4 Multicast route */
1236 case 3: /* IPv6 Multicast route */
1237 pr_warn("%s: route type not supported\n", __func__);
1238 goto out;
1239 }
1240
1241 rtl_table_write(r, idx);
1242
1243 out:
1244 rtl_table_release(r);
1245 }
1246
1247 /* Look up the index of a prefix route in the routing table CAM for unicast IPv4/6 routes
1248 * using hardware offload.
1249 */
1250 static int rtl930x_route_lookup_hw(struct rtl83xx_route *rt)
1251 {
1252 u32 ip4_m, v;
1253 struct in6_addr ip6_m;
1254
1255 if (rt->attr.type == 1 || rt->attr.type == 3) /* Hardware only supports UC routes */
1256 return -1;
1257
1258 sw_w32_mask(0x3 << 19, rt->attr.type, RTL930X_L3_HW_LU_KEY_CTRL);
1259 if (rt->attr.type) { /* IPv6 */
1260 rtl930x_net6_mask(rt->prefix_len, &ip6_m);
1261 for (int i = 0; i < 4; i++)
1262 sw_w32(rt->dst_ip6.s6_addr32[0] & ip6_m.s6_addr32[0],
1263 RTL930X_L3_HW_LU_KEY_IP_CTRL + (i << 2));
1264 } else { /* IPv4 */
1265 ip4_m = inet_make_mask(rt->prefix_len);
1266 sw_w32(0, RTL930X_L3_HW_LU_KEY_IP_CTRL);
1267 sw_w32(0, RTL930X_L3_HW_LU_KEY_IP_CTRL + 4);
1268 sw_w32(0, RTL930X_L3_HW_LU_KEY_IP_CTRL + 8);
1269 v = rt->dst_ip & ip4_m;
1270 pr_info("%s: searching for %pI4\n", __func__, &v);
1271 sw_w32(v, RTL930X_L3_HW_LU_KEY_IP_CTRL + 12);
1272 }
1273
1274 /* Execute CAM lookup in SoC */
1275 sw_w32(BIT(15), RTL930X_L3_HW_LU_CTRL);
1276
1277 /* Wait until execute bit clears and result is ready */
1278 do {
1279 v = sw_r32(RTL930X_L3_HW_LU_CTRL);
1280 } while (v & BIT(15));
1281
1282 pr_info("%s: found: %d, index: %d\n", __func__, !!(v & BIT(14)), v & 0x1ff);
1283
1284 /* Test if search successful (BIT 14 set) */
1285 if (v & BIT(14))
1286 return v & 0x1ff;
1287
1288 return -1;
1289 }
1290
1291 static int rtl930x_find_l3_slot(struct rtl83xx_route *rt, bool must_exist)
1292 {
1293 int slot_width, algorithm, addr, idx;
1294 u32 hash;
1295 struct rtl83xx_route route_entry;
1296
1297 /* IPv6 entries take up 3 slots */
1298 slot_width = (rt->attr.type == 0) || (rt->attr.type == 2) ? 1 : 3;
1299
1300 for (int t = 0; t < 2; t++) {
1301 algorithm = (sw_r32(RTL930X_L3_HOST_TBL_CTRL) >> (2 + t)) & 0x1;
1302 hash = rtl930x_l3_hash4(rt->dst_ip, algorithm, false);
1303
1304 pr_debug("%s: table %d, algorithm %d, hash %04x\n", __func__, t, algorithm, hash);
1305
1306 for (int s = 0; s < 6; s += slot_width) {
1307 addr = (t << 12) | ((hash & 0x1ff) << 3) | s;
1308 pr_debug("%s physical address %d\n", __func__, addr);
1309 idx = ((addr / 8) * 6) + (addr % 8);
1310 pr_debug("%s logical address %d\n", __func__, idx);
1311
1312 rtl930x_host_route_read(idx, &route_entry);
1313 pr_debug("%s route valid %d, route dest: %pI4, hit %d\n", __func__,
1314 rt->attr.valid, &rt->dst_ip, rt->attr.hit);
1315 if (!must_exist && rt->attr.valid)
1316 return idx;
1317 if (must_exist && route_entry.dst_ip == rt->dst_ip)
1318 return idx;
1319 }
1320 }
1321
1322 return -1;
1323 }
1324
1325 /* Write a prefix route into the routing table CAM at position idx
1326 * Currently only IPv4 and IPv6 unicast routes are supported
1327 */
1328 static void rtl930x_route_write(int idx, struct rtl83xx_route *rt)
1329 {
1330 u32 v, ip4_m;
1331 struct in6_addr ip6_m;
1332 /* Access L3_PREFIX_ROUTE_IPUC table (2) via register RTL9300_TBL_1 */
1333 /* The table has a size of 11 registers (20 for MC) */
1334 struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 2);
1335
1336 pr_debug("%s: index %d is valid: %d\n", __func__, idx, rt->attr.valid);
1337 pr_debug("%s: nexthop: %d, hit: %d, action :%d, ttl_dec %d, ttl_check %d, dst_null %d\n",
1338 __func__, rt->nh.id, rt->attr.hit, rt->attr.action,
1339 rt->attr.ttl_dec, rt->attr.ttl_check, rt->attr.dst_null);
1340 pr_debug("%s: GW: %pI4, prefix_len: %d\n", __func__, &rt->dst_ip, rt->prefix_len);
1341
1342 v = rt->attr.valid ? BIT(31) : 0;
1343 v |= (rt->attr.type & 0x3) << 29;
1344 sw_w32(v, rtl_table_data(r, 0));
1345
1346 v = rt->attr.hit ? BIT(22) : 0;
1347 v |= (rt->attr.action & 0x3) << 18;
1348 v |= (rt->nh.id & 0x7ff) << 7;
1349 v |= rt->attr.ttl_dec ? BIT(6) : 0;
1350 v |= rt->attr.ttl_check ? BIT(5) : 0;
1351 v |= rt->attr.dst_null ? BIT(6) : 0;
1352 v |= rt->attr.qos_as ? BIT(6) : 0;
1353 v |= rt->attr.qos_prio & 0x7;
1354 v |= rt->prefix_len == 0 ? BIT(20) : 0; /* set default route bit */
1355
1356 /* set bit mask for entry type always to 0x3 */
1357 sw_w32(0x3 << 29, rtl_table_data(r, 5));
1358
1359 switch (rt->attr.type) {
1360 case 0: /* IPv4 Unicast route */
1361 sw_w32(0, rtl_table_data(r, 1));
1362 sw_w32(0, rtl_table_data(r, 2));
1363 sw_w32(0, rtl_table_data(r, 3));
1364 sw_w32(rt->dst_ip, rtl_table_data(r, 4));
1365
1366 v |= rt->prefix_len == 32 ? BIT(21) : 0; /* set host-route bit */
1367 ip4_m = inet_make_mask(rt->prefix_len);
1368 sw_w32(0, rtl_table_data(r, 6));
1369 sw_w32(0, rtl_table_data(r, 7));
1370 sw_w32(0, rtl_table_data(r, 8));
1371 sw_w32(ip4_m, rtl_table_data(r, 9));
1372 break;
1373 case 2: /* IPv6 Unicast route */
1374 sw_w32(rt->dst_ip6.s6_addr32[0], rtl_table_data(r, 1));
1375 sw_w32(rt->dst_ip6.s6_addr32[1], rtl_table_data(r, 2));
1376 sw_w32(rt->dst_ip6.s6_addr32[2], rtl_table_data(r, 3));
1377 sw_w32(rt->dst_ip6.s6_addr32[3], rtl_table_data(r, 4));
1378
1379 v |= rt->prefix_len == 128 ? BIT(21) : 0; /* set host-route bit */
1380
1381 rtl930x_net6_mask(rt->prefix_len, &ip6_m);
1382
1383 sw_w32(ip6_m.s6_addr32[0], rtl_table_data(r, 6));
1384 sw_w32(ip6_m.s6_addr32[1], rtl_table_data(r, 7));
1385 sw_w32(ip6_m.s6_addr32[2], rtl_table_data(r, 8));
1386 sw_w32(ip6_m.s6_addr32[3], rtl_table_data(r, 9));
1387 break;
1388 case 1: /* IPv4 Multicast route */
1389 case 3: /* IPv6 Multicast route */
1390 pr_warn("%s: route type not supported\n", __func__);
1391 rtl_table_release(r);
1392 return;
1393 }
1394 sw_w32(v, rtl_table_data(r, 10));
1395
1396 pr_debug("%s: %08x %08x %08x %08x %08x %08x %08x %08x %08x %08x %08x\n", __func__,
1397 sw_r32(rtl_table_data(r, 0)), sw_r32(rtl_table_data(r, 1)), sw_r32(rtl_table_data(r, 2)),
1398 sw_r32(rtl_table_data(r, 3)), sw_r32(rtl_table_data(r, 4)), sw_r32(rtl_table_data(r, 5)),
1399 sw_r32(rtl_table_data(r, 6)), sw_r32(rtl_table_data(r, 7)), sw_r32(rtl_table_data(r, 8)),
1400 sw_r32(rtl_table_data(r, 9)), sw_r32(rtl_table_data(r, 10)));
1401
1402 rtl_table_write(r, idx);
1403 rtl_table_release(r);
1404 }
1405
1406
1407 /* Get the destination MAC and L3 egress interface ID of a nexthop entry from
1408 * the SoC's L3_NEXTHOP table
1409 */
1410 static void rtl930x_get_l3_nexthop(int idx, u16 *dmac_id, u16 *interface)
1411 {
1412 u32 v;
1413 /* Read L3_NEXTHOP table (3) via register RTL9300_TBL_1 */
1414 struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 3);
1415
1416 rtl_table_read(r, idx);
1417 /* The table has a size of 1 register */
1418 v = sw_r32(rtl_table_data(r, 0));
1419 rtl_table_release(r);
1420
1421 *dmac_id = (v >> 7) & 0x7fff;
1422 *interface = v & 0x7f;
1423 }
1424
1425 // Currently not used
1426 // static int rtl930x_l3_mtu_del(struct rtl838x_switch_priv *priv, int mtu)
1427 // {
1428 // int i;
1429
1430 // for (i = 0; i < MAX_INTF_MTUS; i++) {
1431 // if (mtu == priv->intf_mtus[i])
1432 // break;
1433 // }
1434 // if (i >= MAX_INTF_MTUS || !priv->intf_mtu_count[i]) {
1435 // pr_err("%s: No MTU slot found for MTU: %d\n", __func__, mtu);
1436 // return -EINVAL;
1437 // }
1438
1439 // priv->intf_mtu_count[i]--;
1440 // }
1441
1442 // Currently not used
1443 // static int rtl930x_l3_mtu_add(struct rtl838x_switch_priv *priv, int mtu)
1444 // {
1445 // int i, free_mtu;
1446 // int mtu_id;
1447
1448 // /* Try to find an existing mtu-value or a free slot */
1449 // free_mtu = MAX_INTF_MTUS;
1450 // for (i = 0; i < MAX_INTF_MTUS && priv->intf_mtus[i] != mtu; i++) {
1451 // if ((!priv->intf_mtu_count[i]) && (free_mtu == MAX_INTF_MTUS))
1452 // free_mtu = i;
1453 // }
1454 // i = (i < MAX_INTF_MTUS) ? i : free_mtu;
1455 // if (i < MAX_INTF_MTUS) {
1456 // mtu_id = i;
1457 // } else {
1458 // pr_err("%s: No free MTU slot available!\n", __func__);
1459 // return -EINVAL;
1460 // }
1461
1462 // priv->intf_mtus[i] = mtu;
1463 // pr_info("Writing MTU %d to slot %d\n", priv->intf_mtus[i], i);
1464 // /* Set MTU-value of the slot TODO: distinguish between IPv4/IPv6 routes / slots */
1465 // sw_w32_mask(0xffff << ((i % 2) * 16), priv->intf_mtus[i] << ((i % 2) * 16),
1466 // RTL930X_L3_IP_MTU_CTRL(i));
1467 // sw_w32_mask(0xffff << ((i % 2) * 16), priv->intf_mtus[i] << ((i % 2) * 16),
1468 // RTL930X_L3_IP6_MTU_CTRL(i));
1469
1470 // priv->intf_mtu_count[i]++;
1471
1472 // return mtu_id;
1473 // }
1474
1475
1476 // Currently not used
1477 // /* Creates an interface for a route by setting up the HW tables in the SoC
1478 // static int rtl930x_l3_intf_add(struct rtl838x_switch_priv *priv, struct rtl838x_l3_intf *intf)
1479 // {
1480 // int i, intf_id, mtu_id;
1481 // /* number of MTU-values < 16384 *\/
1482
1483 // /* Use the same IPv6 mtu as the ip4 mtu for this route if unset */
1484 // intf->ip6_mtu = intf->ip6_mtu ? intf->ip6_mtu : intf->ip4_mtu;
1485
1486 // mtu_id = rtl930x_l3_mtu_add(priv, intf->ip4_mtu);
1487 // pr_info("%s: added mtu %d with mtu-id %d\n", __func__, intf->ip4_mtu, mtu_id);
1488 // if (mtu_id < 0)
1489 // return -ENOSPC;
1490 // intf->ip4_mtu_id = mtu_id;
1491 // intf->ip6_mtu_id = mtu_id;
1492
1493 // for (i = 0; i < MAX_INTERFACES; i++) {
1494 // if (!priv->interfaces[i])
1495 // break;
1496 // }
1497 // if (i >= MAX_INTERFACES) {
1498 // pr_err("%s: cannot find free interface entry\n", __func__);
1499 // return -EINVAL;
1500 // }
1501 // intf_id = i;
1502 // priv->interfaces[i] = kzalloc(sizeof(struct rtl838x_l3_intf), GFP_KERNEL);
1503 // if (!priv->interfaces[i]) {
1504 // pr_err("%s: no memory to allocate new interface\n", __func__);
1505 // return -ENOMEM;
1506 // }
1507 // }
1508
1509 /* Set the destination MAC and L3 egress interface ID for a nexthop entry in the SoC's
1510 * L3_NEXTHOP table. The nexthop entry is identified by idx.
1511 * dmac_id is the reference to the L2 entry in the L2 forwarding table, special values are
1512 * 0x7ffe: TRAP2CPU
1513 * 0x7ffd: TRAP2MASTERCPU
1514 * 0x7fff: DMAC_ID_DROP
1515 */
1516 static void rtl930x_set_l3_nexthop(int idx, u16 dmac_id, u16 interface)
1517 {
1518 /* Access L3_NEXTHOP table (3) via register RTL9300_TBL_1 */
1519 struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 3);
1520
1521 pr_info("%s: Writing to L3_NEXTHOP table, index %d, dmac_id %d, interface %d\n",
1522 __func__, idx, dmac_id, interface);
1523 sw_w32(((dmac_id & 0x7fff) << 7) | (interface & 0x7f), rtl_table_data(r, 0));
1524
1525 pr_info("%s: %08x\n", __func__, sw_r32(rtl_table_data(r,0)));
1526 rtl_table_write(r, idx);
1527 rtl_table_release(r);
1528 }
1529
1530 static void rtl930x_pie_lookup_enable(struct rtl838x_switch_priv *priv, int index)
1531 {
1532 int block = index / PIE_BLOCK_SIZE;
1533
1534 sw_w32_mask(0, BIT(block), RTL930X_PIE_BLK_LOOKUP_CTRL);
1535 }
1536
1537 /* Reads the intermediate representation of the templated match-fields of the
1538 * PIE rule in the pie_rule structure and fills in the raw data fields in the
1539 * raw register space r[].
1540 * The register space configuration size is identical for the RTL8380/90 and RTL9300,
1541 * however the RTL9310 has 2 more registers / fields and the physical field-ids are different
1542 * on all SoCs
1543 * On the RTL9300 the mask fields are not word-aligend!
1544 */
1545 static void rtl930x_write_pie_templated(u32 r[], struct pie_rule *pr, enum template_field_id t[])
1546 {
1547 for (int i = 0; i < N_FIXED_FIELDS; i++) {
1548 enum template_field_id field_type = t[i];
1549 u16 data = 0, data_m = 0;
1550
1551 switch (field_type) {
1552 case TEMPLATE_FIELD_SPM0:
1553 data = pr->spm;
1554 data_m = pr->spm_m;
1555 break;
1556 case TEMPLATE_FIELD_SPM1:
1557 data = pr->spm >> 16;
1558 data_m = pr->spm_m >> 16;
1559 break;
1560 case TEMPLATE_FIELD_OTAG:
1561 data = pr->otag;
1562 data_m = pr->otag_m;
1563 break;
1564 case TEMPLATE_FIELD_SMAC0:
1565 data = pr->smac[4];
1566 data = (data << 8) | pr->smac[5];
1567 data_m = pr->smac_m[4];
1568 data_m = (data_m << 8) | pr->smac_m[5];
1569 break;
1570 case TEMPLATE_FIELD_SMAC1:
1571 data = pr->smac[2];
1572 data = (data << 8) | pr->smac[3];
1573 data_m = pr->smac_m[2];
1574 data_m = (data_m << 8) | pr->smac_m[3];
1575 break;
1576 case TEMPLATE_FIELD_SMAC2:
1577 data = pr->smac[0];
1578 data = (data << 8) | pr->smac[1];
1579 data_m = pr->smac_m[0];
1580 data_m = (data_m << 8) | pr->smac_m[1];
1581 break;
1582 case TEMPLATE_FIELD_DMAC0:
1583 data = pr->dmac[4];
1584 data = (data << 8) | pr->dmac[5];
1585 data_m = pr->dmac_m[4];
1586 data_m = (data_m << 8) | pr->dmac_m[5];
1587 break;
1588 case TEMPLATE_FIELD_DMAC1:
1589 data = pr->dmac[2];
1590 data = (data << 8) | pr->dmac[3];
1591 data_m = pr->dmac_m[2];
1592 data_m = (data_m << 8) | pr->dmac_m[3];
1593 break;
1594 case TEMPLATE_FIELD_DMAC2:
1595 data = pr->dmac[0];
1596 data = (data << 8) | pr->dmac[1];
1597 data_m = pr->dmac_m[0];
1598 data_m = (data_m << 8) | pr->dmac_m[1];
1599 break;
1600 case TEMPLATE_FIELD_ETHERTYPE:
1601 data = pr->ethertype;
1602 data_m = pr->ethertype_m;
1603 break;
1604 case TEMPLATE_FIELD_ITAG:
1605 data = pr->itag;
1606 data_m = pr->itag_m;
1607 break;
1608 case TEMPLATE_FIELD_SIP0:
1609 if (pr->is_ipv6) {
1610 data = pr->sip6.s6_addr16[7];
1611 data_m = pr->sip6_m.s6_addr16[7];
1612 } else {
1613 data = pr->sip;
1614 data_m = pr->sip_m;
1615 }
1616 break;
1617 case TEMPLATE_FIELD_SIP1:
1618 if (pr->is_ipv6) {
1619 data = pr->sip6.s6_addr16[6];
1620 data_m = pr->sip6_m.s6_addr16[6];
1621 } else {
1622 data = pr->sip >> 16;
1623 data_m = pr->sip_m >> 16;
1624 }
1625 break;
1626 case TEMPLATE_FIELD_SIP2:
1627 case TEMPLATE_FIELD_SIP3:
1628 case TEMPLATE_FIELD_SIP4:
1629 case TEMPLATE_FIELD_SIP5:
1630 case TEMPLATE_FIELD_SIP6:
1631 case TEMPLATE_FIELD_SIP7:
1632 data = pr->sip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)];
1633 data_m = pr->sip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)];
1634 break;
1635 case TEMPLATE_FIELD_DIP0:
1636 if (pr->is_ipv6) {
1637 data = pr->dip6.s6_addr16[7];
1638 data_m = pr->dip6_m.s6_addr16[7];
1639 } else {
1640 data = pr->dip;
1641 data_m = pr->dip_m;
1642 }
1643 break;
1644 case TEMPLATE_FIELD_DIP1:
1645 if (pr->is_ipv6) {
1646 data = pr->dip6.s6_addr16[6];
1647 data_m = pr->dip6_m.s6_addr16[6];
1648 } else {
1649 data = pr->dip >> 16;
1650 data_m = pr->dip_m >> 16;
1651 }
1652 break;
1653 case TEMPLATE_FIELD_DIP2:
1654 case TEMPLATE_FIELD_DIP3:
1655 case TEMPLATE_FIELD_DIP4:
1656 case TEMPLATE_FIELD_DIP5:
1657 case TEMPLATE_FIELD_DIP6:
1658 case TEMPLATE_FIELD_DIP7:
1659 data = pr->dip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)];
1660 data_m = pr->dip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)];
1661 break;
1662 case TEMPLATE_FIELD_IP_TOS_PROTO:
1663 data = pr->tos_proto;
1664 data_m = pr->tos_proto_m;
1665 break;
1666 case TEMPLATE_FIELD_L4_SPORT:
1667 data = pr->sport;
1668 data_m = pr->sport_m;
1669 break;
1670 case TEMPLATE_FIELD_L4_DPORT:
1671 data = pr->dport;
1672 data_m = pr->dport_m;
1673 break;
1674 case TEMPLATE_FIELD_DSAP_SSAP:
1675 data = pr->dsap_ssap;
1676 data_m = pr->dsap_ssap_m;
1677 break;
1678 case TEMPLATE_FIELD_TCP_INFO:
1679 data = pr->tcp_info;
1680 data_m = pr->tcp_info_m;
1681 break;
1682 case TEMPLATE_FIELD_RANGE_CHK:
1683 pr_warn("Warning: TEMPLATE_FIELD_RANGE_CHK: not configured\n");
1684 break;
1685 default:
1686 pr_info("%s: unknown field %d\n", __func__, field_type);
1687 }
1688
1689 /* On the RTL9300, the mask fields are not word aligned! */
1690 if (!(i % 2)) {
1691 r[5 - i / 2] = data;
1692 r[12 - i / 2] |= ((u32)data_m << 8);
1693 } else {
1694 r[5 - i / 2] |= ((u32)data) << 16;
1695 r[12 - i / 2] |= ((u32)data_m) << 24;
1696 r[11 - i / 2] |= ((u32)data_m) >> 8;
1697 }
1698 }
1699 }
1700
1701 // Currently not used
1702 // static void rtl930x_read_pie_fixed_fields(u32 r[], struct pie_rule *pr)
1703 // {
1704 // pr->stacking_port = r[6] & BIT(31);
1705 // pr->spn = (r[6] >> 24) & 0x7f;
1706 // pr->mgnt_vlan = r[6] & BIT(23);
1707 // if (pr->phase == PHASE_IACL)
1708 // pr->dmac_hit_sw = r[6] & BIT(22);
1709 // else
1710 // pr->content_too_deep = r[6] & BIT(22);
1711 // pr->not_first_frag = r[6] & BIT(21);
1712 // pr->frame_type_l4 = (r[6] >> 18) & 7;
1713 // pr->frame_type = (r[6] >> 16) & 3;
1714 // pr->otag_fmt = (r[6] >> 15) & 1;
1715 // pr->itag_fmt = (r[6] >> 14) & 1;
1716 // pr->otag_exist = (r[6] >> 13) & 1;
1717 // pr->itag_exist = (r[6] >> 12) & 1;
1718 // pr->frame_type_l2 = (r[6] >> 10) & 3;
1719 // pr->igr_normal_port = (r[6] >> 9) & 1;
1720 // pr->tid = (r[6] >> 8) & 1;
1721
1722 // pr->stacking_port_m = r[12] & BIT(7);
1723 // pr->spn_m = r[12] & 0x7f;
1724 // pr->mgnt_vlan_m = r[13] & BIT(31);
1725 // if (pr->phase == PHASE_IACL)
1726 // pr->dmac_hit_sw_m = r[13] & BIT(30);
1727 // else
1728 // pr->content_too_deep_m = r[13] & BIT(30);
1729 // pr->not_first_frag_m = r[13] & BIT(29);
1730 // pr->frame_type_l4_m = (r[13] >> 26) & 7;
1731 // pr->frame_type_m = (r[13] >> 24) & 3;
1732 // pr->otag_fmt_m = r[13] & BIT(23);
1733 // pr->itag_fmt_m = r[13] & BIT(22);
1734 // pr->otag_exist_m = r[13] & BIT(21);
1735 // pr->itag_exist_m = r[13] & BIT (20);
1736 // pr->frame_type_l2_m = (r[13] >> 18) & 3;
1737 // pr->igr_normal_port_m = r[13] & BIT(17);
1738 // pr->tid_m = (r[13] >> 16) & 1;
1739
1740 // pr->valid = r[13] & BIT(15);
1741 // pr->cond_not = r[13] & BIT(14);
1742 // pr->cond_and1 = r[13] & BIT(13);
1743 // pr->cond_and2 = r[13] & BIT(12);
1744 // }
1745
1746 static void rtl930x_write_pie_fixed_fields(u32 r[], struct pie_rule *pr)
1747 {
1748 r[6] = pr->stacking_port ? BIT(31) : 0;
1749 r[6] |= ((u32) (pr->spn & 0x7f)) << 24;
1750 r[6] |= pr->mgnt_vlan ? BIT(23) : 0;
1751 if (pr->phase == PHASE_IACL)
1752 r[6] |= pr->dmac_hit_sw ? BIT(22) : 0;
1753 else
1754 r[6] |= pr->content_too_deep ? BIT(22) : 0;
1755 r[6] |= pr->not_first_frag ? BIT(21) : 0;
1756 r[6] |= ((u32) (pr->frame_type_l4 & 0x7)) << 18;
1757 r[6] |= ((u32) (pr->frame_type & 0x3)) << 16;
1758 r[6] |= pr->otag_fmt ? BIT(15) : 0;
1759 r[6] |= pr->itag_fmt ? BIT(14) : 0;
1760 r[6] |= pr->otag_exist ? BIT(13) : 0;
1761 r[6] |= pr->itag_exist ? BIT(12) : 0;
1762 r[6] |= ((u32) (pr->frame_type_l2 & 0x3)) << 10;
1763 r[6] |= pr->igr_normal_port ? BIT(9) : 0;
1764 r[6] |= ((u32) (pr->tid & 0x1)) << 8;
1765
1766 r[12] |= pr->stacking_port_m ? BIT(7) : 0;
1767 r[12] |= (u32) (pr->spn_m & 0x7f);
1768 r[13] |= pr->mgnt_vlan_m ? BIT(31) : 0;
1769 if (pr->phase == PHASE_IACL)
1770 r[13] |= pr->dmac_hit_sw_m ? BIT(30) : 0;
1771 else
1772 r[13] |= pr->content_too_deep_m ? BIT(30) : 0;
1773 r[13] |= pr->not_first_frag_m ? BIT(29) : 0;
1774 r[13] |= ((u32) (pr->frame_type_l4_m & 0x7)) << 26;
1775 r[13] |= ((u32) (pr->frame_type_m & 0x3)) << 24;
1776 r[13] |= pr->otag_fmt_m ? BIT(23) : 0;
1777 r[13] |= pr->itag_fmt_m ? BIT(22) : 0;
1778 r[13] |= pr->otag_exist_m ? BIT(21) : 0;
1779 r[13] |= pr->itag_exist_m ? BIT(20) : 0;
1780 r[13] |= ((u32) (pr->frame_type_l2_m & 0x3)) << 18;
1781 r[13] |= pr->igr_normal_port_m ? BIT(17) : 0;
1782 r[13] |= ((u32) (pr->tid_m & 0x1)) << 16;
1783
1784 r[13] |= pr->valid ? BIT(15) : 0;
1785 r[13] |= pr->cond_not ? BIT(14) : 0;
1786 r[13] |= pr->cond_and1 ? BIT(13) : 0;
1787 r[13] |= pr->cond_and2 ? BIT(12) : 0;
1788 }
1789
1790 static void rtl930x_write_pie_action(u32 r[], struct pie_rule *pr)
1791 {
1792 /* Either drop or forward */
1793 if (pr->drop) {
1794 r[14] |= BIT(24) | BIT(25) | BIT(26); /* Do Green, Yellow and Red drops */
1795 /* Actually DROP, not PERMIT in Green / Yellow / Red */
1796 r[14] |= BIT(23) | BIT(22) | BIT(20);
1797 } else {
1798 r[14] |= pr->fwd_sel ? BIT(27) : 0;
1799 r[14] |= pr->fwd_act << 18;
1800 r[14] |= BIT(14); /* We overwrite any drop */
1801 }
1802 if (pr->phase == PHASE_VACL)
1803 r[14] |= pr->fwd_sa_lrn ? BIT(15) : 0;
1804 r[13] |= pr->bypass_sel ? BIT(5) : 0;
1805 r[13] |= pr->nopri_sel ? BIT(4) : 0;
1806 r[13] |= pr->tagst_sel ? BIT(3) : 0;
1807 r[13] |= pr->ovid_sel ? BIT(1) : 0;
1808 r[14] |= pr->ivid_sel ? BIT(31) : 0;
1809 r[14] |= pr->meter_sel ? BIT(30) : 0;
1810 r[14] |= pr->mir_sel ? BIT(29) : 0;
1811 r[14] |= pr->log_sel ? BIT(28) : 0;
1812
1813 r[14] |= ((u32)(pr->fwd_data & 0x3fff)) << 3;
1814 r[15] |= pr->log_octets ? BIT(31) : 0;
1815 r[15] |= (u32)(pr->meter_data) << 23;
1816
1817 r[15] |= ((u32)(pr->ivid_act) << 21) & 0x3;
1818 r[15] |= ((u32)(pr->ivid_data) << 9) & 0xfff;
1819 r[16] |= ((u32)(pr->ovid_act) << 30) & 0x3;
1820 r[16] |= ((u32)(pr->ovid_data) & 0xfff) << 16;
1821 r[16] |= (pr->mir_data & 0x3) << 6;
1822 r[17] |= ((u32)(pr->tagst_data) & 0xf) << 28;
1823 r[17] |= ((u32)(pr->nopri_data) & 0x7) << 25;
1824 r[17] |= pr->bypass_ibc_sc ? BIT(16) : 0;
1825 }
1826
1827 void rtl930x_pie_rule_dump_raw(u32 r[])
1828 {
1829 pr_info("Raw IACL table entry:\n");
1830 pr_info("r 0 - 7: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1831 r[0], r[1], r[2], r[3], r[4], r[5], r[6], r[7]);
1832 pr_info("r 8 - 15: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1833 r[8], r[9], r[10], r[11], r[12], r[13], r[14], r[15]);
1834 pr_info("r 16 - 18: %08x %08x %08x\n", r[16], r[17], r[18]);
1835 pr_info("Match : %08x %08x %08x %08x %08x %08x\n", r[0], r[1], r[2], r[3], r[4], r[5]);
1836 pr_info("Fixed : %06x\n", r[6] >> 8);
1837 pr_info("Match M: %08x %08x %08x %08x %08x %08x\n",
1838 (r[6] << 24) | (r[7] >> 8), (r[7] << 24) | (r[8] >> 8), (r[8] << 24) | (r[9] >> 8),
1839 (r[9] << 24) | (r[10] >> 8), (r[10] << 24) | (r[11] >> 8),
1840 (r[11] << 24) | (r[12] >> 8));
1841 pr_info("R[13]: %08x\n", r[13]);
1842 pr_info("Fixed M: %06x\n", ((r[12] << 16) | (r[13] >> 16)) & 0xffffff);
1843 pr_info("Valid / not / and1 / and2 : %1x\n", (r[13] >> 12) & 0xf);
1844 pr_info("r 13-16: %08x %08x %08x %08x\n", r[13], r[14], r[15], r[16]);
1845 }
1846
1847 static int rtl930x_pie_rule_write(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr)
1848 {
1849 /* Access IACL table (2) via register 0 */
1850 struct table_reg *q = rtl_table_get(RTL9300_TBL_0, 2);
1851 u32 r[19];
1852 int block = idx / PIE_BLOCK_SIZE;
1853 u32 t_select = sw_r32(RTL930X_PIE_BLK_TMPLTE_CTRL(block));
1854
1855 pr_debug("%s: %d, t_select: %08x\n", __func__, idx, t_select);
1856
1857 for (int i = 0; i < 19; i++)
1858 r[i] = 0;
1859
1860 if (!pr->valid) {
1861 rtl_table_write(q, idx);
1862 rtl_table_release(q);
1863 return 0;
1864 }
1865 rtl930x_write_pie_fixed_fields(r, pr);
1866
1867 pr_debug("%s: template %d\n", __func__, (t_select >> (pr->tid * 4)) & 0xf);
1868 rtl930x_write_pie_templated(r, pr, fixed_templates[(t_select >> (pr->tid * 4)) & 0xf]);
1869
1870 rtl930x_write_pie_action(r, pr);
1871
1872 /* rtl930x_pie_rule_dump_raw(r); */
1873
1874 for (int i = 0; i < 19; i++)
1875 sw_w32(r[i], rtl_table_data(q, i));
1876
1877 rtl_table_write(q, idx);
1878 rtl_table_release(q);
1879
1880 return 0;
1881 }
1882
1883 static bool rtl930x_pie_templ_has(int t, enum template_field_id field_type)
1884 {
1885 for (int i = 0; i < N_FIXED_FIELDS; i++) {
1886 enum template_field_id ft = fixed_templates[t][i];
1887 if (field_type == ft)
1888 return true;
1889 }
1890
1891 return false;
1892 }
1893
1894 /* Verify that the rule pr is compatible with a given template t in block block
1895 * Note that this function is SoC specific since the values of e.g. TEMPLATE_FIELD_SIP0
1896 * depend on the SoC
1897 */
1898 static int rtl930x_pie_verify_template(struct rtl838x_switch_priv *priv,
1899 struct pie_rule *pr, int t, int block)
1900 {
1901 int i;
1902
1903 if (!pr->is_ipv6 && pr->sip_m && !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_SIP0))
1904 return -1;
1905
1906 if (!pr->is_ipv6 && pr->dip_m && !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_DIP0))
1907 return -1;
1908
1909 if (pr->is_ipv6) {
1910 if ((pr->sip6_m.s6_addr32[0] ||
1911 pr->sip6_m.s6_addr32[1] ||
1912 pr->sip6_m.s6_addr32[2] ||
1913 pr->sip6_m.s6_addr32[3]) &&
1914 !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_SIP2))
1915 return -1;
1916 if ((pr->dip6_m.s6_addr32[0] ||
1917 pr->dip6_m.s6_addr32[1] ||
1918 pr->dip6_m.s6_addr32[2] ||
1919 pr->dip6_m.s6_addr32[3]) &&
1920 !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_DIP2))
1921 return -1;
1922 }
1923
1924 if (ether_addr_to_u64(pr->smac) && !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_SMAC0))
1925 return -1;
1926
1927 if (ether_addr_to_u64(pr->dmac) && !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_DMAC0))
1928 return -1;
1929
1930 /* TODO: Check more */
1931
1932 i = find_first_zero_bit(&priv->pie_use_bm[block * 4], PIE_BLOCK_SIZE);
1933
1934 if (i >= PIE_BLOCK_SIZE)
1935 return -1;
1936
1937 return i + PIE_BLOCK_SIZE * block;
1938 }
1939
1940 static int rtl930x_pie_rule_add(struct rtl838x_switch_priv *priv, struct pie_rule *pr)
1941 {
1942 int idx, block, j, t;
1943 int min_block = 0;
1944 int max_block = priv->n_pie_blocks / 2;
1945
1946 if (pr->is_egress) {
1947 min_block = max_block;
1948 max_block = priv->n_pie_blocks;
1949 }
1950 pr_debug("In %s\n", __func__);
1951
1952 mutex_lock(&priv->pie_mutex);
1953
1954 for (block = min_block; block < max_block; block++) {
1955 for (j = 0; j < 2; j++) {
1956 t = (sw_r32(RTL930X_PIE_BLK_TMPLTE_CTRL(block)) >> (j * 4)) & 0xf;
1957 pr_debug("Testing block %d, template %d, template id %d\n", block, j, t);
1958 pr_debug("%s: %08x\n",
1959 __func__, sw_r32(RTL930X_PIE_BLK_TMPLTE_CTRL(block)));
1960 idx = rtl930x_pie_verify_template(priv, pr, t, block);
1961 if (idx >= 0)
1962 break;
1963 }
1964 if (j < 2)
1965 break;
1966 }
1967
1968 if (block >= priv->n_pie_blocks) {
1969 mutex_unlock(&priv->pie_mutex);
1970 return -EOPNOTSUPP;
1971 }
1972
1973 pr_debug("Using block: %d, index %d, template-id %d\n", block, idx, j);
1974 set_bit(idx, priv->pie_use_bm);
1975
1976 pr->valid = true;
1977 pr->tid = j; /* Mapped to template number */
1978 pr->tid_m = 0x1;
1979 pr->id = idx;
1980
1981 rtl930x_pie_lookup_enable(priv, idx);
1982 rtl930x_pie_rule_write(priv, idx, pr);
1983
1984 mutex_unlock(&priv->pie_mutex);
1985 return 0;
1986 }
1987
1988 /* Delete a range of Packet Inspection Engine rules */
1989 static int rtl930x_pie_rule_del(struct rtl838x_switch_priv *priv, int index_from, int index_to)
1990 {
1991 u32 v = (index_from << 1)| (index_to << 12 ) | BIT(0);
1992
1993 pr_debug("%s: from %d to %d\n", __func__, index_from, index_to);
1994 mutex_lock(&priv->reg_mutex);
1995
1996 /* Write from-to and execute bit into control register */
1997 sw_w32(v, RTL930X_PIE_CLR_CTRL);
1998
1999 /* Wait until command has completed */
2000 do {
2001 } while (sw_r32(RTL930X_PIE_CLR_CTRL) & BIT(0));
2002
2003 mutex_unlock(&priv->reg_mutex);
2004 return 0;
2005 }
2006
2007 static void rtl930x_pie_rule_rm(struct rtl838x_switch_priv *priv, struct pie_rule *pr)
2008 {
2009 int idx = pr->id;
2010
2011 rtl930x_pie_rule_del(priv, idx, idx);
2012 clear_bit(idx, priv->pie_use_bm);
2013 }
2014
2015 static void rtl930x_pie_init(struct rtl838x_switch_priv *priv)
2016 {
2017 u32 template_selectors;
2018
2019 mutex_init(&priv->pie_mutex);
2020
2021 pr_info("%s\n", __func__);
2022 /* Enable ACL lookup on all ports, including CPU_PORT */
2023 for (int i = 0; i <= priv->cpu_port; i++)
2024 sw_w32(1, RTL930X_ACL_PORT_LOOKUP_CTRL(i));
2025
2026 /* Include IPG in metering */
2027 sw_w32_mask(0, 1, RTL930X_METER_GLB_CTRL);
2028
2029 /* Delete all present rules, block size is 128 on all SoC families */
2030 rtl930x_pie_rule_del(priv, 0, priv->n_pie_blocks * 128 - 1);
2031
2032 /* Assign blocks 0-7 to VACL phase (bit = 0), blocks 8-15 to IACL (bit = 1) */
2033 sw_w32(0xff00, RTL930X_PIE_BLK_PHASE_CTRL);
2034
2035 /* Enable predefined templates 0, 1 for first quarter of all blocks */
2036 template_selectors = 0 | (1 << 4);
2037 for (int i = 0; i < priv->n_pie_blocks / 4; i++)
2038 sw_w32(template_selectors, RTL930X_PIE_BLK_TMPLTE_CTRL(i));
2039
2040 /* Enable predefined templates 2, 3 for second quarter of all blocks */
2041 template_selectors = 2 | (3 << 4);
2042 for (int i = priv->n_pie_blocks / 4; i < priv->n_pie_blocks / 2; i++)
2043 sw_w32(template_selectors, RTL930X_PIE_BLK_TMPLTE_CTRL(i));
2044
2045 /* Enable predefined templates 0, 1 for third half of all blocks */
2046 template_selectors = 0 | (1 << 4);
2047 for (int i = priv->n_pie_blocks / 2; i < priv->n_pie_blocks * 3 / 4; i++)
2048 sw_w32(template_selectors, RTL930X_PIE_BLK_TMPLTE_CTRL(i));
2049
2050 /* Enable predefined templates 2, 3 for fourth quater of all blocks */
2051 template_selectors = 2 | (3 << 4);
2052 for (int i = priv->n_pie_blocks * 3 / 4; i < priv->n_pie_blocks; i++)
2053 sw_w32(template_selectors, RTL930X_PIE_BLK_TMPLTE_CTRL(i));
2054
2055 }
2056
2057 /* Sets up an egress interface for L3 actions
2058 * Actions for ip4/6_icmp_redirect, ip4/6_pbr_icmp_redirect are:
2059 * 0: FORWARD, 1: DROP, 2: TRAP2CPU, 3: COPY2CPU, 4: TRAP2MASTERCPU 5: COPY2MASTERCPU
2060 * 6: HARDDROP
2061 * idx is the index in the HW interface table: idx < 0x80
2062 */
2063 static void rtl930x_set_l3_egress_intf(int idx, struct rtl838x_l3_intf *intf)
2064 {
2065 u32 u, v;
2066 /* Read L3_EGR_INTF table (4) via register RTL9300_TBL_1 */
2067 struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 4);
2068
2069 /* The table has 2 registers */
2070 u = (intf->vid & 0xfff) << 9;
2071 u |= (intf->smac_idx & 0x3f) << 3;
2072 u |= (intf->ip4_mtu_id & 0x7);
2073
2074 v = (intf->ip6_mtu_id & 0x7) << 28;
2075 v |= (intf->ttl_scope & 0xff) << 20;
2076 v |= (intf->hl_scope & 0xff) << 12;
2077 v |= (intf->ip4_icmp_redirect & 0x7) << 9;
2078 v |= (intf->ip6_icmp_redirect & 0x7)<< 6;
2079 v |= (intf->ip4_pbr_icmp_redirect & 0x7) << 3;
2080 v |= (intf->ip6_pbr_icmp_redirect & 0x7);
2081
2082 sw_w32(u, rtl_table_data(r, 0));
2083 sw_w32(v, rtl_table_data(r, 1));
2084
2085 pr_info("%s writing to index %d: %08x %08x\n", __func__, idx, u, v);
2086 rtl_table_write(r, idx & 0x7f);
2087 rtl_table_release(r);
2088 }
2089
2090 /* Reads a MAC entry for L3 termination as entry point for routing
2091 * from the hardware table
2092 * idx is the index into the L3_ROUTER_MAC table
2093 */
2094 static void rtl930x_get_l3_router_mac(u32 idx, struct rtl93xx_rt_mac *m)
2095 {
2096 u32 v, w;
2097 /* Read L3_ROUTER_MAC table (0) via register RTL9300_TBL_1 */
2098 struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 0);
2099
2100 rtl_table_read(r, idx);
2101 /* The table has a size of 7 registers, 64 entries */
2102 v = sw_r32(rtl_table_data(r, 0));
2103 w = sw_r32(rtl_table_data(r, 3));
2104 m->valid = !!(v & BIT(20));
2105 if (!m->valid)
2106 goto out;
2107
2108 m->p_type = !!(v & BIT(19));
2109 m->p_id = (v >> 13) & 0x3f; /* trunk id of port */
2110 m->vid = v & 0xfff;
2111 m->vid_mask = w & 0xfff;
2112 m->action = sw_r32(rtl_table_data(r, 6)) & 0x7;
2113 m->mac_mask = ((((u64)sw_r32(rtl_table_data(r, 5))) << 32) & 0xffffffffffffULL) |
2114 (sw_r32(rtl_table_data(r, 4)));
2115 m->mac = ((((u64)sw_r32(rtl_table_data(r, 1))) << 32) & 0xffffffffffffULL) |
2116 (sw_r32(rtl_table_data(r, 2)));
2117 /* Bits L3_INTF and BMSK_L3_INTF are 0 */
2118
2119 out:
2120 rtl_table_release(r);
2121 }
2122
2123 /* Writes a MAC entry for L3 termination as entry point for routing
2124 * into the hardware table
2125 * idx is the index into the L3_ROUTER_MAC table
2126 */
2127 static void rtl930x_set_l3_router_mac(u32 idx, struct rtl93xx_rt_mac *m)
2128 {
2129 u32 v, w;
2130 /* Read L3_ROUTER_MAC table (0) via register RTL9300_TBL_1 */
2131 struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 0);
2132
2133 /* The table has a size of 7 registers, 64 entries */
2134 v = BIT(20); /* mac entry valid, port type is 0: individual */
2135 v |= (m->p_id & 0x3f) << 13;
2136 v |= (m->vid & 0xfff); /* Set the interface_id to the vlan id */
2137
2138 w = m->vid_mask;
2139 w |= (m->p_id_mask & 0x3f) << 13;
2140
2141 sw_w32(v, rtl_table_data(r, 0));
2142 sw_w32(w, rtl_table_data(r, 3));
2143
2144 /* Set MAC address, L3_INTF (bit 12 in register 1) needs to be 0 */
2145 sw_w32((u32)(m->mac), rtl_table_data(r, 2));
2146 sw_w32(m->mac >> 32, rtl_table_data(r, 1));
2147
2148 /* Set MAC address mask, BMSK_L3_INTF (bit 12 in register 5) needs to be 0 */
2149 sw_w32((u32)(m->mac_mask >> 32), rtl_table_data(r, 4));
2150 sw_w32((u32)m->mac_mask, rtl_table_data(r, 5));
2151
2152 sw_w32(m->action & 0x7, rtl_table_data(r, 6));
2153
2154 pr_debug("%s writing index %d: %08x %08x %08x %08x %08x %08x %08x\n", __func__, idx,
2155 sw_r32(rtl_table_data(r, 0)), sw_r32(rtl_table_data(r, 1)), sw_r32(rtl_table_data(r, 2)),
2156 sw_r32(rtl_table_data(r, 3)), sw_r32(rtl_table_data(r, 4)), sw_r32(rtl_table_data(r, 5)),
2157 sw_r32(rtl_table_data(r, 6))
2158 );
2159 rtl_table_write(r, idx);
2160 rtl_table_release(r);
2161 }
2162
2163 /* Get the Destination-MAC of an L3 egress interface or the Source MAC for routed packets
2164 * from the SoC's L3_EGR_INTF_MAC table
2165 * Indexes 0-2047 are DMACs, 2048+ are SMACs
2166 */
2167 static u64 rtl930x_get_l3_egress_mac(u32 idx)
2168 {
2169 u64 mac;
2170 /* Read L3_EGR_INTF_MAC table (2) via register RTL9300_TBL_2 */
2171 struct table_reg *r = rtl_table_get(RTL9300_TBL_2, 2);
2172
2173 rtl_table_read(r, idx);
2174 /* The table has a size of 2 registers */
2175 mac = sw_r32(rtl_table_data(r, 0));
2176 mac <<= 32;
2177 mac |= sw_r32(rtl_table_data(r, 1));
2178 rtl_table_release(r);
2179
2180 return mac;
2181 }
2182
2183 /* Set the Destination-MAC of a route or the Source MAC of an L3 egress interface
2184 * in the SoC's L3_EGR_INTF_MAC table
2185 * Indexes 0-2047 are DMACs, 2048+ are SMACs
2186 */
2187 static void rtl930x_set_l3_egress_mac(u32 idx, u64 mac)
2188 {
2189 /* Access L3_EGR_INTF_MAC table (2) via register RTL9300_TBL_2 */
2190 struct table_reg *r = rtl_table_get(RTL9300_TBL_2, 2);
2191
2192 /* The table has a size of 2 registers */
2193 sw_w32(mac >> 32, rtl_table_data(r, 0));
2194 sw_w32(mac, rtl_table_data(r, 1));
2195
2196 pr_debug("%s: setting index %d to %016llx\n", __func__, idx, mac);
2197 rtl_table_write(r, idx);
2198 rtl_table_release(r);
2199 }
2200
2201 /* Configure L3 routing settings of the device:
2202 * - MTUs
2203 * - Egress interface
2204 * - The router's MAC address on which routed packets are expected
2205 * - MAC addresses used as source macs of routed packets
2206 */
2207 int rtl930x_l3_setup(struct rtl838x_switch_priv *priv)
2208 {
2209 /* Setup MTU with id 0 for default interface */
2210 for (int i = 0; i < MAX_INTF_MTUS; i++)
2211 priv->intf_mtu_count[i] = priv->intf_mtus[i] = 0;
2212
2213 priv->intf_mtu_count[0] = 0; /* Needs to stay forever */
2214 priv->intf_mtus[0] = DEFAULT_MTU;
2215 sw_w32_mask(0xffff, DEFAULT_MTU, RTL930X_L3_IP_MTU_CTRL(0));
2216 sw_w32_mask(0xffff, DEFAULT_MTU, RTL930X_L3_IP6_MTU_CTRL(0));
2217 priv->intf_mtus[1] = DEFAULT_MTU;
2218 sw_w32_mask(0xffff0000, DEFAULT_MTU << 16, RTL930X_L3_IP_MTU_CTRL(0));
2219 sw_w32_mask(0xffff0000, DEFAULT_MTU << 16, RTL930X_L3_IP6_MTU_CTRL(0));
2220
2221 sw_w32_mask(0xffff, DEFAULT_MTU, RTL930X_L3_IP_MTU_CTRL(1));
2222 sw_w32_mask(0xffff, DEFAULT_MTU, RTL930X_L3_IP6_MTU_CTRL(1));
2223 sw_w32_mask(0xffff0000, DEFAULT_MTU << 16, RTL930X_L3_IP_MTU_CTRL(1));
2224 sw_w32_mask(0xffff0000, DEFAULT_MTU << 16, RTL930X_L3_IP6_MTU_CTRL(1));
2225
2226 /* Clear all source port MACs */
2227 for (int i = 0; i < MAX_SMACS; i++)
2228 rtl930x_set_l3_egress_mac(L3_EGRESS_DMACS + i, 0ULL);
2229
2230 /* Configure the default L3 hash algorithm */
2231 sw_w32_mask(BIT(2), 0, RTL930X_L3_HOST_TBL_CTRL); /* Algorithm selection 0 = 0 */
2232 sw_w32_mask(0, BIT(3), RTL930X_L3_HOST_TBL_CTRL); /* Algorithm selection 1 = 1 */
2233
2234 pr_info("L3_IPUC_ROUTE_CTRL %08x, IPMC_ROUTE %08x, IP6UC_ROUTE %08x, IP6MC_ROUTE %08x\n",
2235 sw_r32(RTL930X_L3_IPUC_ROUTE_CTRL), sw_r32(RTL930X_L3_IPMC_ROUTE_CTRL),
2236 sw_r32(RTL930X_L3_IP6UC_ROUTE_CTRL), sw_r32(RTL930X_L3_IP6MC_ROUTE_CTRL));
2237 sw_w32_mask(0, 1, RTL930X_L3_IPUC_ROUTE_CTRL);
2238 sw_w32_mask(0, 1, RTL930X_L3_IP6UC_ROUTE_CTRL);
2239 sw_w32_mask(0, 1, RTL930X_L3_IPMC_ROUTE_CTRL);
2240 sw_w32_mask(0, 1, RTL930X_L3_IP6MC_ROUTE_CTRL);
2241
2242 sw_w32(0x00002001, RTL930X_L3_IPUC_ROUTE_CTRL);
2243 sw_w32(0x00014581, RTL930X_L3_IP6UC_ROUTE_CTRL);
2244 sw_w32(0x00000501, RTL930X_L3_IPMC_ROUTE_CTRL);
2245 sw_w32(0x00012881, RTL930X_L3_IP6MC_ROUTE_CTRL);
2246
2247 pr_info("L3_IPUC_ROUTE_CTRL %08x, IPMC_ROUTE %08x, IP6UC_ROUTE %08x, IP6MC_ROUTE %08x\n",
2248 sw_r32(RTL930X_L3_IPUC_ROUTE_CTRL), sw_r32(RTL930X_L3_IPMC_ROUTE_CTRL),
2249 sw_r32(RTL930X_L3_IP6UC_ROUTE_CTRL), sw_r32(RTL930X_L3_IP6MC_ROUTE_CTRL));
2250
2251 /* Trap non-ip traffic to the CPU-port (e.g. ARP so we stay reachable) */
2252 sw_w32_mask(0x3 << 8, 0x1 << 8, RTL930X_L3_IP_ROUTE_CTRL);
2253 pr_info("L3_IP_ROUTE_CTRL %08x\n", sw_r32(RTL930X_L3_IP_ROUTE_CTRL));
2254
2255 /* PORT_ISO_RESTRICT_ROUTE_CTRL? */
2256
2257 /* Do not use prefix route 0 because of HW limitations */
2258 set_bit(0, priv->route_use_bm);
2259
2260 return 0;
2261 }
2262
2263 static u32 rtl930x_packet_cntr_read(int counter)
2264 {
2265 u32 v;
2266
2267 /* Read LOG table (3) via register RTL9300_TBL_0 */
2268 struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 3);
2269
2270 pr_debug("In %s, id %d\n", __func__, counter);
2271 rtl_table_read(r, counter / 2);
2272
2273 pr_debug("Registers: %08x %08x\n",
2274 sw_r32(rtl_table_data(r, 0)), sw_r32(rtl_table_data(r, 1)));
2275 /* The table has a size of 2 registers */
2276 if (counter % 2)
2277 v = sw_r32(rtl_table_data(r, 0));
2278 else
2279 v = sw_r32(rtl_table_data(r, 1));
2280
2281 rtl_table_release(r);
2282
2283 return v;
2284 }
2285
2286 static void rtl930x_packet_cntr_clear(int counter)
2287 {
2288 /* Access LOG table (3) via register RTL9300_TBL_0 */
2289 struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 3);
2290
2291 pr_info("In %s, id %d\n", __func__, counter);
2292 /* The table has a size of 2 registers */
2293 if (counter % 2)
2294 sw_w32(0, rtl_table_data(r, 0));
2295 else
2296 sw_w32(0, rtl_table_data(r, 1));
2297
2298 rtl_table_write(r, counter / 2);
2299
2300 rtl_table_release(r);
2301 }
2302
2303 void rtl930x_vlan_port_keep_tag_set(int port, bool keep_outer, bool keep_inner)
2304 {
2305 sw_w32(FIELD_PREP(RTL930X_VLAN_PORT_TAG_STS_CTRL_EGR_OTAG_STS_MASK,
2306 keep_outer ? RTL930X_VLAN_PORT_TAG_STS_TAGGED : RTL930X_VLAN_PORT_TAG_STS_UNTAG) |
2307 FIELD_PREP(RTL930X_VLAN_PORT_TAG_STS_CTRL_EGR_ITAG_STS_MASK,
2308 keep_inner ? RTL930X_VLAN_PORT_TAG_STS_TAGGED : RTL930X_VLAN_PORT_TAG_STS_UNTAG),
2309 RTL930X_VLAN_PORT_TAG_STS_CTRL(port));
2310 }
2311
2312 void rtl930x_vlan_port_pvidmode_set(int port, enum pbvlan_type type, enum pbvlan_mode mode)
2313 {
2314 if (type == PBVLAN_TYPE_INNER)
2315 sw_w32_mask(0x3, mode, RTL930X_VLAN_PORT_PB_VLAN + (port << 2));
2316 else
2317 sw_w32_mask(0x3 << 14, mode << 14 ,RTL930X_VLAN_PORT_PB_VLAN + (port << 2));
2318 }
2319
2320 void rtl930x_vlan_port_pvid_set(int port, enum pbvlan_type type, int pvid)
2321 {
2322 if (type == PBVLAN_TYPE_INNER)
2323 sw_w32_mask(0xfff << 2, pvid << 2, RTL930X_VLAN_PORT_PB_VLAN + (port << 2));
2324 else
2325 sw_w32_mask(0xfff << 16, pvid << 16, RTL930X_VLAN_PORT_PB_VLAN + (port << 2));
2326 }
2327
2328 static int rtl930x_set_ageing_time(unsigned long msec)
2329 {
2330 int t = sw_r32(RTL930X_L2_AGE_CTRL);
2331
2332 t &= 0x1FFFFF;
2333 t = (t * 7) / 10;
2334 pr_debug("L2 AGING time: %d sec\n", t);
2335
2336 t = (msec / 100 + 6) / 7;
2337 t = t > 0x1FFFFF ? 0x1FFFFF : t;
2338 sw_w32_mask(0x1FFFFF, t, RTL930X_L2_AGE_CTRL);
2339 pr_debug("Dynamic aging for ports: %x\n", sw_r32(RTL930X_L2_PORT_AGE_CTRL));
2340
2341 return 0;
2342 }
2343
2344 static void rtl930x_set_igr_filter(int port, enum igr_filter state)
2345 {
2346 sw_w32_mask(0x3 << ((port & 0xf)<<1), state << ((port & 0xf)<<1),
2347 RTL930X_VLAN_PORT_IGR_FLTR + (((port >> 4) << 2)));
2348 }
2349
2350 static void rtl930x_set_egr_filter(int port, enum egr_filter state)
2351 {
2352 sw_w32_mask(0x1 << (port % 0x1D), state << (port % 0x1D),
2353 RTL930X_VLAN_PORT_EGR_FLTR + (((port / 29) << 2)));
2354 }
2355
2356 void rtl930x_set_distribution_algorithm(int group, int algoidx, u32 algomsk)
2357 {
2358 u32 l3shift = 0;
2359 u32 newmask = 0;
2360
2361 /* TODO: for now we set algoidx to 0 */
2362 algoidx = 0;
2363 if (algomsk & TRUNK_DISTRIBUTION_ALGO_SIP_BIT) {
2364 l3shift = 4;
2365 newmask |= TRUNK_DISTRIBUTION_ALGO_L3_SIP_BIT;
2366 }
2367 if (algomsk & TRUNK_DISTRIBUTION_ALGO_DIP_BIT) {
2368 l3shift = 4;
2369 newmask |= TRUNK_DISTRIBUTION_ALGO_L3_DIP_BIT;
2370 }
2371 if (algomsk & TRUNK_DISTRIBUTION_ALGO_SRC_L4PORT_BIT) {
2372 l3shift = 4;
2373 newmask |= TRUNK_DISTRIBUTION_ALGO_L3_SRC_L4PORT_BIT;
2374 }
2375 if (algomsk & TRUNK_DISTRIBUTION_ALGO_SRC_L4PORT_BIT) {
2376 l3shift = 4;
2377 newmask |= TRUNK_DISTRIBUTION_ALGO_L3_SRC_L4PORT_BIT;
2378 }
2379
2380 if (l3shift == 4) {
2381 if (algomsk & TRUNK_DISTRIBUTION_ALGO_SMAC_BIT)
2382 newmask |= TRUNK_DISTRIBUTION_ALGO_L3_SMAC_BIT;
2383
2384 if (algomsk & TRUNK_DISTRIBUTION_ALGO_DMAC_BIT)
2385 newmask |= TRUNK_DISTRIBUTION_ALGO_L3_DMAC_BIT;
2386 } else {
2387 if (algomsk & TRUNK_DISTRIBUTION_ALGO_SMAC_BIT)
2388 newmask |= TRUNK_DISTRIBUTION_ALGO_L2_SMAC_BIT;
2389 if (algomsk & TRUNK_DISTRIBUTION_ALGO_DMAC_BIT)
2390 newmask |= TRUNK_DISTRIBUTION_ALGO_L2_DMAC_BIT;
2391 }
2392
2393 sw_w32(newmask << l3shift, RTL930X_TRK_HASH_CTRL + (algoidx << 2));
2394 }
2395
2396 static void rtl930x_led_init(struct rtl838x_switch_priv *priv)
2397 {
2398 struct device_node *node;
2399 u32 pm = 0;
2400
2401 pr_info("%s called\n", __func__);
2402 node = of_find_compatible_node(NULL, NULL, "realtek,rtl9300-leds");
2403 if (!node) {
2404 pr_info("%s No compatible LED node found\n", __func__);
2405 return;
2406 }
2407
2408 for (int set = 0; set < 4; set++) {
2409 char set_name[16] = {0};
2410 u32 set_config[4];
2411 int leds_in_this_set = 0;
2412
2413 /* Reset LED set configuration */
2414 sw_w32(0, RTL930X_LED_SETX_0_CTRL(set));
2415 sw_w32(0, RTL930X_LED_SETX_1_CTRL(set));
2416
2417 /**
2418 * Each led set has 4 number of leds, and each LED is configured with 16 bits
2419 * So each 32bit register holds configuration for 2 leds
2420 * And therefore each set requires 2 registers for configuring 4 LEDs
2421 *
2422 */
2423 sprintf(set_name, "led_set%d", set);
2424 leds_in_this_set = of_property_count_u32_elems(node, set_name);
2425
2426 if (leds_in_this_set == 0 || leds_in_this_set > sizeof(set_config)) {
2427 pr_err("%s led_set configuration invalid skipping over this set\n", __func__);
2428 continue;
2429 }
2430
2431 if (of_property_read_u32_array(node, set_name, set_config, leds_in_this_set)) {
2432 break;
2433 }
2434
2435 /* Write configuration as per number of LEDs */
2436 for (int i=0, led = leds_in_this_set-1; led >= 0; led--,i++) {
2437 sw_w32_mask(0xffff << RTL930X_LED_SET_LEDX_SHIFT(led),
2438 (0xffff & set_config[i]) << RTL930X_LED_SET_LEDX_SHIFT(led),
2439 RTL930X_LED_SETX_LEDY(set, led));
2440 }
2441 }
2442
2443 for (int i = 0; i < priv->cpu_port; i++) {
2444 int pos = (i << 1) % 32;
2445 u32 set;
2446
2447 sw_w32_mask(0x3 << pos, 0, RTL930X_LED_PORT_FIB_SET_SEL_CTRL(i));
2448 sw_w32_mask(0x3 << pos, 0, RTL930X_LED_PORT_COPR_SET_SEL_CTRL(i));
2449
2450 if (!priv->ports[i].phy)
2451 continue;
2452
2453 /* 0x0 = 1 led, 0x1 = 2 leds, 0x2 = 3 leds, 0x3 = 4 leds per port */
2454 sw_w32_mask(0x3 << pos, (priv->ports[i].leds_on_this_port -1) << pos, RTL930X_LED_PORT_NUM_CTRL(i));
2455
2456 pm |= BIT(i);
2457
2458 set = priv->ports[i].led_set;
2459 sw_w32_mask(0, set << pos, RTL930X_LED_PORT_COPR_SET_SEL_CTRL(i));
2460 sw_w32_mask(0, set << pos, RTL930X_LED_PORT_FIB_SET_SEL_CTRL(i));
2461 }
2462
2463 /* Set LED mode to serial (0x1) */
2464 sw_w32_mask(0x3, 0x1, RTL930X_LED_GLB_CTRL);
2465
2466 /* Set LED active state */
2467 if (of_property_read_bool(node, "active-low"))
2468 sw_w32_mask(RTL930X_LED_GLB_ACTIVE_LOW, 0, RTL930X_LED_GLB_CTRL);
2469 else
2470 sw_w32_mask(0, RTL930X_LED_GLB_ACTIVE_LOW, RTL930X_LED_GLB_CTRL);
2471
2472 /* Set port type masks */
2473 sw_w32(pm, RTL930X_LED_PORT_COPR_MASK_CTRL);
2474 sw_w32(pm, RTL930X_LED_PORT_FIB_MASK_CTRL);
2475 sw_w32(pm, RTL930X_LED_PORT_COMBO_MASK_CTRL);
2476
2477 for (int i = 0; i < 24; i++)
2478 pr_info("%s %08x: %08x\n",__func__, 0xbb00cc00 + i * 4, sw_r32(0xcc00 + i * 4));
2479 }
2480
2481 const struct rtl838x_reg rtl930x_reg = {
2482 .mask_port_reg_be = rtl838x_mask_port_reg,
2483 .set_port_reg_be = rtl838x_set_port_reg,
2484 .get_port_reg_be = rtl838x_get_port_reg,
2485 .mask_port_reg_le = rtl838x_mask_port_reg,
2486 .set_port_reg_le = rtl838x_set_port_reg,
2487 .get_port_reg_le = rtl838x_get_port_reg,
2488 .stat_port_rst = RTL930X_STAT_PORT_RST,
2489 .stat_rst = RTL930X_STAT_RST,
2490 .stat_port_std_mib = RTL930X_STAT_PORT_MIB_CNTR,
2491 .traffic_enable = rtl930x_traffic_enable,
2492 .traffic_disable = rtl930x_traffic_disable,
2493 .traffic_get = rtl930x_traffic_get,
2494 .traffic_set = rtl930x_traffic_set,
2495 .l2_ctrl_0 = RTL930X_L2_CTRL,
2496 .l2_ctrl_1 = RTL930X_L2_AGE_CTRL,
2497 .l2_port_aging_out = RTL930X_L2_PORT_AGE_CTRL,
2498 .set_ageing_time = rtl930x_set_ageing_time,
2499 .smi_poll_ctrl = RTL930X_SMI_POLL_CTRL, /* TODO: Difference to RTL9300_SMI_PRVTE_POLLING_CTRL */
2500 .l2_tbl_flush_ctrl = RTL930X_L2_TBL_FLUSH_CTRL,
2501 .exec_tbl0_cmd = rtl930x_exec_tbl0_cmd,
2502 .exec_tbl1_cmd = rtl930x_exec_tbl1_cmd,
2503 .tbl_access_data_0 = rtl930x_tbl_access_data_0,
2504 .isr_glb_src = RTL930X_ISR_GLB,
2505 .isr_port_link_sts_chg = RTL930X_ISR_PORT_LINK_STS_CHG,
2506 .imr_port_link_sts_chg = RTL930X_IMR_PORT_LINK_STS_CHG,
2507 .imr_glb = RTL930X_IMR_GLB,
2508 .vlan_tables_read = rtl930x_vlan_tables_read,
2509 .vlan_set_tagged = rtl930x_vlan_set_tagged,
2510 .vlan_set_untagged = rtl930x_vlan_set_untagged,
2511 .vlan_profile_dump = rtl930x_vlan_profile_dump,
2512 .vlan_profile_setup = rtl930x_vlan_profile_setup,
2513 .vlan_fwd_on_inner = rtl930x_vlan_fwd_on_inner,
2514 .set_vlan_igr_filter = rtl930x_set_igr_filter,
2515 .set_vlan_egr_filter = rtl930x_set_egr_filter,
2516 .stp_get = rtl930x_stp_get,
2517 .stp_set = rtl930x_stp_set,
2518 .mac_force_mode_ctrl = rtl930x_mac_force_mode_ctrl,
2519 .mac_port_ctrl = rtl930x_mac_port_ctrl,
2520 .l2_port_new_salrn = rtl930x_l2_port_new_salrn,
2521 .l2_port_new_sa_fwd = rtl930x_l2_port_new_sa_fwd,
2522 .mir_ctrl = RTL930X_MIR_CTRL,
2523 .mir_dpm = RTL930X_MIR_DPM_CTRL,
2524 .mir_spm = RTL930X_MIR_SPM_CTRL,
2525 .mac_link_sts = RTL930X_MAC_LINK_STS,
2526 .mac_link_dup_sts = RTL930X_MAC_LINK_DUP_STS,
2527 .mac_link_spd_sts = rtl930x_mac_link_spd_sts,
2528 .mac_rx_pause_sts = RTL930X_MAC_RX_PAUSE_STS,
2529 .mac_tx_pause_sts = RTL930X_MAC_TX_PAUSE_STS,
2530 .read_l2_entry_using_hash = rtl930x_read_l2_entry_using_hash,
2531 .write_l2_entry_using_hash = rtl930x_write_l2_entry_using_hash,
2532 .read_cam = rtl930x_read_cam,
2533 .write_cam = rtl930x_write_cam,
2534 .vlan_port_keep_tag_set = rtl930x_vlan_port_keep_tag_set,
2535 .vlan_port_pvidmode_set = rtl930x_vlan_port_pvidmode_set,
2536 .vlan_port_pvid_set = rtl930x_vlan_port_pvid_set,
2537 .trk_mbr_ctr = rtl930x_trk_mbr_ctr,
2538 .rma_bpdu_fld_pmask = RTL930X_RMA_BPDU_FLD_PMSK,
2539 .init_eee = rtl930x_init_eee,
2540 .port_eee_set = rtl930x_port_eee_set,
2541 .eee_port_ability = rtl930x_eee_port_ability,
2542 .l2_hash_seed = rtl930x_l2_hash_seed,
2543 .l2_hash_key = rtl930x_l2_hash_key,
2544 .read_mcast_pmask = rtl930x_read_mcast_pmask,
2545 .write_mcast_pmask = rtl930x_write_mcast_pmask,
2546 .pie_init = rtl930x_pie_init,
2547 .pie_rule_write = rtl930x_pie_rule_write,
2548 .pie_rule_add = rtl930x_pie_rule_add,
2549 .pie_rule_rm = rtl930x_pie_rule_rm,
2550 .l2_learning_setup = rtl930x_l2_learning_setup,
2551 .packet_cntr_read = rtl930x_packet_cntr_read,
2552 .packet_cntr_clear = rtl930x_packet_cntr_clear,
2553 .route_read = rtl930x_route_read,
2554 .route_write = rtl930x_route_write,
2555 .host_route_write = rtl930x_host_route_write,
2556 .l3_setup = rtl930x_l3_setup,
2557 .set_l3_nexthop = rtl930x_set_l3_nexthop,
2558 .get_l3_nexthop = rtl930x_get_l3_nexthop,
2559 .get_l3_egress_mac = rtl930x_get_l3_egress_mac,
2560 .set_l3_egress_mac = rtl930x_set_l3_egress_mac,
2561 .find_l3_slot = rtl930x_find_l3_slot,
2562 .route_lookup_hw = rtl930x_route_lookup_hw,
2563 .get_l3_router_mac = rtl930x_get_l3_router_mac,
2564 .set_l3_router_mac = rtl930x_set_l3_router_mac,
2565 .set_l3_egress_intf = rtl930x_set_l3_egress_intf,
2566 .set_distribution_algorithm = rtl930x_set_distribution_algorithm,
2567 .led_init = rtl930x_led_init,
2568 };
Staging tree of Stijn Tintel