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realtek: Whitespace and codestyle cleanup
[openwrt/staging/jow.git] / target / linux / realtek / files-5.15 / drivers / net / dsa / rtl83xx / rtl930x.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <asm/mach-rtl838x/mach-rtl83xx.h>
4 #include <linux/inetdevice.h>
5
6 #include "rtl83xx.h"
7
8 #define RTL930X_VLAN_PORT_TAG_STS_INTERNAL 0x0
9 #define RTL930X_VLAN_PORT_TAG_STS_UNTAG 0x1
10 #define RTL930X_VLAN_PORT_TAG_STS_TAGGED 0x2
11 #define RTL930X_VLAN_PORT_TAG_STS_PRIORITY_TAGGED 0x3
12
13 #define RTL930X_VLAN_PORT_TAG_STS_CTRL_BASE 0xCE24
14 /* port 0-28 */
15 #define RTL930X_VLAN_PORT_TAG_STS_CTRL(port) \
16 RTL930X_VLAN_PORT_TAG_STS_CTRL_BASE + (port << 2)
17 #define RTL930X_VLAN_PORT_TAG_STS_CTRL_EGR_OTAG_STS_MASK GENMASK(7,6)
18 #define RTL930X_VLAN_PORT_TAG_STS_CTRL_EGR_ITAG_STS_MASK GENMASK(5,4)
19 #define RTL930X_VLAN_PORT_TAG_STS_CTRL_EGR_P_OTAG_KEEP_MASK GENMASK(3,3)
20 #define RTL930X_VLAN_PORT_TAG_STS_CTRL_EGR_P_ITAG_KEEP_MASK GENMASK(2,2)
21 #define RTL930X_VLAN_PORT_TAG_STS_CTRL_IGR_P_OTAG_KEEP_MASK GENMASK(1,1)
22 #define RTL930X_VLAN_PORT_TAG_STS_CTRL_IGR_P_ITAG_KEEP_MASK GENMASK(0,0)
23
24 extern struct mutex smi_lock;
25 extern struct rtl83xx_soc_info soc_info;
26
27 /* Definition of the RTL930X-specific template field IDs as used in the PIE */
28 enum template_field_id {
29 TEMPLATE_FIELD_SPM0 = 0, // Source portmask ports 0-15
30 TEMPLATE_FIELD_SPM1 = 1, // Source portmask ports 16-31
31 TEMPLATE_FIELD_DMAC0 = 2, // Destination MAC [15:0]
32 TEMPLATE_FIELD_DMAC1 = 3, // Destination MAC [31:16]
33 TEMPLATE_FIELD_DMAC2 = 4, // Destination MAC [47:32]
34 TEMPLATE_FIELD_SMAC0 = 5, // Source MAC [15:0]
35 TEMPLATE_FIELD_SMAC1 = 6, // Source MAC [31:16]
36 TEMPLATE_FIELD_SMAC2 = 7, // Source MAC [47:32]
37 TEMPLATE_FIELD_ETHERTYPE = 8, // Ethernet frame type field
38 TEMPLATE_FIELD_OTAG = 9,
39 TEMPLATE_FIELD_ITAG = 10,
40 TEMPLATE_FIELD_SIP0 = 11,
41 TEMPLATE_FIELD_SIP1 = 12,
42 TEMPLATE_FIELD_DIP0 = 13,
43 TEMPLATE_FIELD_DIP1 = 14,
44 TEMPLATE_FIELD_IP_TOS_PROTO = 15,
45 TEMPLATE_FIELD_L4_SPORT = 16,
46 TEMPLATE_FIELD_L4_DPORT = 17,
47 TEMPLATE_FIELD_L34_HEADER = 18,
48 TEMPLATE_FIELD_TCP_INFO = 19,
49 TEMPLATE_FIELD_FIELD_SELECTOR_VALID = 20,
50 TEMPLATE_FIELD_FIELD_SELECTOR_0 = 21,
51 TEMPLATE_FIELD_FIELD_SELECTOR_1 = 22,
52 TEMPLATE_FIELD_FIELD_SELECTOR_2 = 23,
53 TEMPLATE_FIELD_FIELD_SELECTOR_3 = 24,
54 TEMPLATE_FIELD_FIELD_SELECTOR_4 = 25,
55 TEMPLATE_FIELD_FIELD_SELECTOR_5 = 26,
56 TEMPLATE_FIELD_SIP2 = 27,
57 TEMPLATE_FIELD_SIP3 = 28,
58 TEMPLATE_FIELD_SIP4 = 29,
59 TEMPLATE_FIELD_SIP5 = 30,
60 TEMPLATE_FIELD_SIP6 = 31,
61 TEMPLATE_FIELD_SIP7 = 32,
62 TEMPLATE_FIELD_DIP2 = 33,
63 TEMPLATE_FIELD_DIP3 = 34,
64 TEMPLATE_FIELD_DIP4 = 35,
65 TEMPLATE_FIELD_DIP5 = 36,
66 TEMPLATE_FIELD_DIP6 = 37,
67 TEMPLATE_FIELD_DIP7 = 38,
68 TEMPLATE_FIELD_PKT_INFO = 39,
69 TEMPLATE_FIELD_FLOW_LABEL = 40,
70 TEMPLATE_FIELD_DSAP_SSAP = 41,
71 TEMPLATE_FIELD_SNAP_OUI = 42,
72 TEMPLATE_FIELD_FWD_VID = 43,
73 TEMPLATE_FIELD_RANGE_CHK = 44,
74 TEMPLATE_FIELD_VLAN_GMSK = 45, // VLAN Group Mask/IP range check
75 TEMPLATE_FIELD_DLP = 46,
76 TEMPLATE_FIELD_META_DATA = 47,
77 TEMPLATE_FIELD_SRC_FWD_VID = 48,
78 TEMPLATE_FIELD_SLP = 49,
79 };
80
81 /* The meaning of TEMPLATE_FIELD_VLAN depends on phase and the configuration in
82 * RTL930X_PIE_CTRL. We use always the same definition and map to the inner VLAN tag:
83 */
84 #define TEMPLATE_FIELD_VLAN TEMPLATE_FIELD_ITAG
85
86 // Number of fixed templates predefined in the RTL9300 SoC
87 #define N_FIXED_TEMPLATES 5
88 // RTL9300 specific predefined templates
89 static enum template_field_id fixed_templates[N_FIXED_TEMPLATES][N_FIXED_FIELDS] =
90 {
91 {
92 TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2,
93 TEMPLATE_FIELD_SMAC0, TEMPLATE_FIELD_SMAC1, TEMPLATE_FIELD_SMAC2,
94 TEMPLATE_FIELD_VLAN, TEMPLATE_FIELD_IP_TOS_PROTO, TEMPLATE_FIELD_DSAP_SSAP,
95 TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1
96 }, {
97 TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0,
98 TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_IP_TOS_PROTO, TEMPLATE_FIELD_TCP_INFO,
99 TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_L4_DPORT, TEMPLATE_FIELD_VLAN,
100 TEMPLATE_FIELD_RANGE_CHK, TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1
101 }, {
102 TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2,
103 TEMPLATE_FIELD_VLAN, TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_IP_TOS_PROTO,
104 TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0,
105 TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_L4_DPORT
106 }, {
107 TEMPLATE_FIELD_DIP0, TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_DIP2,
108 TEMPLATE_FIELD_DIP3, TEMPLATE_FIELD_DIP4, TEMPLATE_FIELD_DIP5,
109 TEMPLATE_FIELD_DIP6, TEMPLATE_FIELD_DIP7, TEMPLATE_FIELD_IP_TOS_PROTO,
110 TEMPLATE_FIELD_TCP_INFO, TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_L4_DPORT
111 }, {
112 TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_SIP2,
113 TEMPLATE_FIELD_SIP3, TEMPLATE_FIELD_SIP4, TEMPLATE_FIELD_SIP5,
114 TEMPLATE_FIELD_SIP6, TEMPLATE_FIELD_SIP7, TEMPLATE_FIELD_VLAN,
115 TEMPLATE_FIELD_RANGE_CHK, TEMPLATE_FIELD_SPM1, TEMPLATE_FIELD_SPM1
116 },
117 };
118
119 void rtl930x_print_matrix(void)
120 {
121 int i;
122 struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6);
123
124 for (i = 0; i < 29; i++) {
125 rtl_table_read(r, i);
126 pr_debug("> %08x\n", sw_r32(rtl_table_data(r, 0)));
127 }
128 rtl_table_release(r);
129 }
130
131 inline void rtl930x_exec_tbl0_cmd(u32 cmd)
132 {
133 sw_w32(cmd, RTL930X_TBL_ACCESS_CTRL_0);
134 do { } while (sw_r32(RTL930X_TBL_ACCESS_CTRL_0) & (1 << 17));
135 }
136
137 inline void rtl930x_exec_tbl1_cmd(u32 cmd)
138 {
139 sw_w32(cmd, RTL930X_TBL_ACCESS_CTRL_1);
140 do { } while (sw_r32(RTL930X_TBL_ACCESS_CTRL_1) & (1 << 17));
141 }
142
143 inline int rtl930x_tbl_access_data_0(int i)
144 {
145 return RTL930X_TBL_ACCESS_DATA_0(i);
146 }
147
148 static inline int rtl930x_l2_port_new_salrn(int p)
149 {
150 return RTL930X_L2_PORT_SALRN(p);
151 }
152
153 static inline int rtl930x_l2_port_new_sa_fwd(int p)
154 {
155 // TODO: The definition of the fields changed, because of the master-cpu in a stack
156 return RTL930X_L2_PORT_NEW_SA_FWD(p);
157 }
158
159 inline static int rtl930x_trk_mbr_ctr(int group)
160 {
161 return RTL930X_TRK_MBR_CTRL + (group << 2);
162 }
163
164 static void rtl930x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info)
165 {
166 u32 v, w;
167 // Read VLAN table (1) via register 0
168 struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 1);
169
170 rtl_table_read(r, vlan);
171 v = sw_r32(rtl_table_data(r, 0));
172 w = sw_r32(rtl_table_data(r, 1));
173 pr_debug("VLAN_READ %d: %08x %08x\n", vlan, v, w);
174 rtl_table_release(r);
175
176 info->tagged_ports = v >> 3;
177 info->profile_id = (w >> 24) & 7;
178 info->hash_mc_fid = !!(w & BIT(27));
179 info->hash_uc_fid = !!(w & BIT(28));
180 info->fid = ((v & 0x7) << 3) | ((w >> 29) & 0x7);
181
182 // Read UNTAG table via table register 2
183 r = rtl_table_get(RTL9300_TBL_2, 0);
184 rtl_table_read(r, vlan);
185 v = sw_r32(rtl_table_data(r, 0));
186 rtl_table_release(r);
187
188 info->untagged_ports = v >> 3;
189 }
190
191 static void rtl930x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info)
192 {
193 u32 v, w;
194 // Access VLAN table (1) via register 0
195 struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 1);
196
197 v = info->tagged_ports << 3;
198 v |= ((u32)info->fid) >> 3;
199
200 w = ((u32)info->fid) << 29;
201 w |= info->hash_mc_fid ? BIT(27) : 0;
202 w |= info->hash_uc_fid ? BIT(28) : 0;
203 w |= info->profile_id << 24;
204
205 sw_w32(v, rtl_table_data(r, 0));
206 sw_w32(w, rtl_table_data(r, 1));
207
208 rtl_table_write(r, vlan);
209 rtl_table_release(r);
210 }
211
212 void rtl930x_vlan_profile_dump(int profile)
213 {
214 u32 p[5];
215
216 if (profile < 0 || profile > 7)
217 return;
218
219 p[0] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile));
220 p[1] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 4);
221 p[2] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 8) & 0x1FFFFFFF;
222 p[3] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 12) & 0x1FFFFFFF;
223 p[4] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 16) & 0x1FFFFFFF;
224
225 pr_info("VLAN %d: L2 learn: %d; Unknown MC PMasks: L2 %0x, IPv4 %0x, IPv6: %0x",
226 profile, p[0] & (3 << 21), p[2], p[3], p[4]);
227 pr_info(" Routing enabled: IPv4 UC %c, IPv6 UC %c, IPv4 MC %c, IPv6 MC %c\n",
228 p[0] & BIT(17) ? 'y' : 'n', p[0] & BIT(16) ? 'y' : 'n',
229 p[0] & BIT(13) ? 'y' : 'n', p[0] & BIT(12) ? 'y' : 'n');
230 pr_info(" Bridge enabled: IPv4 MC %c, IPv6 MC %c,\n",
231 p[0] & BIT(15) ? 'y' : 'n', p[0] & BIT(14) ? 'y' : 'n');
232 pr_info("VLAN profile %d: raw %08x %08x %08x %08x %08x\n",
233 profile, p[0], p[1], p[2], p[3], p[4]);
234 }
235
236 static void rtl930x_vlan_set_untagged(u32 vlan, u64 portmask)
237 {
238 struct table_reg *r = rtl_table_get(RTL9300_TBL_2, 0);
239
240 sw_w32(portmask << 3, rtl_table_data(r, 0));
241 rtl_table_write(r, vlan);
242 rtl_table_release(r);
243 }
244
245 /* Sets the L2 forwarding to be based on either the inner VLAN tag or the outer */
246 static void rtl930x_vlan_fwd_on_inner(int port, bool is_set)
247 {
248 // Always set all tag modes to fwd based on either inner or outer tag
249 if (is_set)
250 sw_w32_mask(0, 0xf, RTL930X_VLAN_PORT_FWD + (port << 2));
251 else
252 sw_w32_mask(0xf, 0, RTL930X_VLAN_PORT_FWD + (port << 2));
253 }
254
255 static void rtl930x_vlan_profile_setup(int profile)
256 {
257 u32 p[5];
258
259 pr_info("In %s\n", __func__);
260 p[0] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile));
261 p[1] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 4);
262
263 // Enable routing of Ipv4/6 Unicast and IPv4/6 Multicast traffic
264 p[0] |= BIT(17) | BIT(16) | BIT(13) | BIT(12);
265 p[2] = 0x1fffffff; // L2 unknown MC flooding portmask all ports, including the CPU-port
266 p[3] = 0x1fffffff; // IPv4 unknown MC flooding portmask
267 p[4] = 0x1fffffff; // IPv6 unknown MC flooding portmask
268
269 sw_w32(p[0], RTL930X_VLAN_PROFILE_SET(profile));
270 sw_w32(p[1], RTL930X_VLAN_PROFILE_SET(profile) + 4);
271 sw_w32(p[2], RTL930X_VLAN_PROFILE_SET(profile) + 8);
272 sw_w32(p[3], RTL930X_VLAN_PROFILE_SET(profile) + 12);
273 sw_w32(p[4], RTL930X_VLAN_PROFILE_SET(profile) + 16);
274 }
275
276 static void rtl930x_l2_learning_setup(void)
277 {
278 // Portmask for flooding broadcast traffic
279 sw_w32(0x1fffffff, RTL930X_L2_BC_FLD_PMSK);
280
281 // Portmask for flooding unicast traffic with unknown destination
282 sw_w32(0x1fffffff, RTL930X_L2_UNKN_UC_FLD_PMSK);
283
284 // Limit learning to maximum: 32k entries, after that just flood (bits 0-1)
285 sw_w32((0x7fff << 2) | 0, RTL930X_L2_LRN_CONSTRT_CTRL);
286 }
287
288 static void rtl930x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
289 {
290 int i;
291 u32 cmd = 1 << 17 | /* Execute cmd */
292 0 << 16 | /* Read */
293 4 << 12 | /* Table type 0b10 */
294 (msti & 0xfff);
295 priv->r->exec_tbl0_cmd(cmd);
296
297 for (i = 0; i < 2; i++)
298 port_state[i] = sw_r32(RTL930X_TBL_ACCESS_DATA_0(i));
299 pr_debug("MSTI: %d STATE: %08x, %08x\n", msti, port_state[0], port_state[1]);
300 }
301
302 static void rtl930x_stp_set(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
303 {
304 int i;
305 u32 cmd = 1 << 17 | /* Execute cmd */
306 1 << 16 | /* Write */
307 4 << 12 | /* Table type 4 */
308 (msti & 0xfff);
309
310 for (i = 0; i < 2; i++)
311 sw_w32(port_state[i], RTL930X_TBL_ACCESS_DATA_0(i));
312 priv->r->exec_tbl0_cmd(cmd);
313 }
314
315 static inline int rtl930x_mac_force_mode_ctrl(int p)
316 {
317 return RTL930X_MAC_FORCE_MODE_CTRL + (p << 2);
318 }
319
320 static inline int rtl930x_mac_port_ctrl(int p)
321 {
322 return RTL930X_MAC_L2_PORT_CTRL(p);
323 }
324
325 static inline int rtl930x_mac_link_spd_sts(int p)
326 {
327 return RTL930X_MAC_LINK_SPD_STS(p);
328 }
329
330 static u64 rtl930x_l2_hash_seed(u64 mac, u32 vid)
331 {
332 u64 v = vid;
333
334 v <<= 48;
335 v |= mac;
336
337 return v;
338 }
339
340 /* Calculate both the block 0 and the block 1 hash by applyingthe same hash
341 * algorithm as the one used currently by the ASIC to the seed, and return
342 * both hashes in the lower and higher word of the return value since only 12 bit of
343 * the hash are significant
344 */
345 static u32 rtl930x_l2_hash_key(struct rtl838x_switch_priv *priv, u64 seed)
346 {
347 u32 k0, k1, h1, h2, h;
348
349 k0 = (u32) (((seed >> 55) & 0x1f) ^
350 ((seed >> 44) & 0x7ff) ^
351 ((seed >> 33) & 0x7ff) ^
352 ((seed >> 22) & 0x7ff) ^
353 ((seed >> 11) & 0x7ff) ^
354 (seed & 0x7ff));
355
356 h1 = (seed >> 11) & 0x7ff;
357 h1 = ((h1 & 0x1f) << 6) | ((h1 >> 5) & 0x3f);
358
359 h2 = (seed >> 33) & 0x7ff;
360 h2 = ((h2 & 0x3f) << 5)| ((h2 >> 6) & 0x3f);
361
362 k1 = (u32) (((seed << 55) & 0x1f) ^
363 ((seed >> 44) & 0x7ff) ^
364 h2 ^
365 ((seed >> 22) & 0x7ff) ^
366 h1 ^
367 (seed & 0x7ff));
368
369 // Algorithm choice for block 0
370 if (sw_r32(RTL930X_L2_CTRL) & BIT(0))
371 h = k1;
372 else
373 h = k0;
374
375 /* Algorithm choice for block 1
376 * Since k0 and k1 are < 2048, adding 2048 will offset the hash into the second
377 * half of hash-space
378 * 2048 is in fact the hash-table size 16384 divided by 4 hashes per bucket
379 * divided by 2 to divide the hash space in 2
380 */
381 if (sw_r32(RTL930X_L2_CTRL) & BIT(1))
382 h |= (k1 + 2048) << 16;
383 else
384 h |= (k0 + 2048) << 16;
385
386 return h;
387 }
388
389 /* Fills an L2 entry structure from the SoC registers */
390 static void rtl930x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e)
391 {
392 pr_debug("In %s valid?\n", __func__);
393 e->valid = !!(r[2] & BIT(31));
394 if (!e->valid)
395 return;
396
397 pr_debug("In %s is valid\n", __func__);
398 e->is_ip_mc = false;
399 e->is_ipv6_mc = false;
400
401 // TODO: Is there not a function to copy directly MAC memory?
402 e->mac[0] = (r[0] >> 24);
403 e->mac[1] = (r[0] >> 16);
404 e->mac[2] = (r[0] >> 8);
405 e->mac[3] = r[0];
406 e->mac[4] = (r[1] >> 24);
407 e->mac[5] = (r[1] >> 16);
408
409 e->next_hop = !!(r[2] & BIT(12));
410 e->rvid = r[1] & 0xfff;
411
412 /* Is it a unicast entry? check multicast bit */
413 if (!(e->mac[0] & 1)) {
414 e->type = L2_UNICAST;
415 e->is_static = !!(r[2] & BIT(14));
416 e->port = (r[2] >> 20) & 0x3ff;
417 // Check for trunk port
418 if (r[2] & BIT(30)) {
419 e->is_trunk = true;
420 e->stack_dev = (e->port >> 9) & 1;
421 e->trunk = e->port & 0x3f;
422 } else {
423 e->is_trunk = false;
424 e->stack_dev = (e->port >> 6) & 0xf;
425 e->port = e->port & 0x3f;
426 }
427
428 e->block_da = !!(r[2] & BIT(15));
429 e->block_sa = !!(r[2] & BIT(16));
430 e->suspended = !!(r[2] & BIT(13));
431 e->age = (r[2] >> 17) & 3;
432 e->valid = true;
433 // the UC_VID field in hardware is used for the VID or for the route id
434 if (e->next_hop) {
435 e->nh_route_id = r[2] & 0x7ff;
436 e->vid = 0;
437 } else {
438 e->vid = r[2] & 0xfff;
439 e->nh_route_id = 0;
440 }
441 } else {
442 e->valid = true;
443 e->type = L2_MULTICAST;
444 e->mc_portmask_index = (r[2] >> 16) & 0x3ff;
445 }
446 }
447
448 /* Fills the 3 SoC table registers r[] with the information of in the rtl838x_l2_entry */
449 static void rtl930x_fill_l2_row(u32 r[], struct rtl838x_l2_entry *e)
450 {
451 u32 port;
452
453 if (!e->valid) {
454 r[0] = r[1] = r[2] = 0;
455 return;
456 }
457
458 r[2] = BIT(31); // Set valid bit
459
460 r[0] = ((u32)e->mac[0]) << 24 |
461 ((u32)e->mac[1]) << 16 |
462 ((u32)e->mac[2]) << 8 |
463 ((u32)e->mac[3]);
464 r[1] = ((u32)e->mac[4]) << 24 |
465 ((u32)e->mac[5]) << 16;
466
467 r[2] |= e->next_hop ? BIT(12) : 0;
468
469 if (e->type == L2_UNICAST) {
470 r[2] |= e->is_static ? BIT(14) : 0;
471 r[1] |= e->rvid & 0xfff;
472 r[2] |= (e->port & 0x3ff) << 20;
473 if (e->is_trunk) {
474 r[2] |= BIT(30);
475 port = e->stack_dev << 9 | (e->port & 0x3f);
476 } else {
477 port = (e->stack_dev & 0xf) << 6;
478 port |= e->port & 0x3f;
479 }
480 r[2] |= port << 20;
481 r[2] |= e->block_da ? BIT(15) : 0;
482 r[2] |= e->block_sa ? BIT(17) : 0;
483 r[2] |= e->suspended ? BIT(13) : 0;
484 r[2] |= (e->age & 0x3) << 17;
485 // the UC_VID field in hardware is used for the VID or for the route id
486 if (e->next_hop)
487 r[2] |= e->nh_route_id & 0x7ff;
488 else
489 r[2] |= e->vid & 0xfff;
490 } else { // L2_MULTICAST
491 r[2] |= (e->mc_portmask_index & 0x3ff) << 16;
492 r[2] |= e->mc_mac_index & 0x7ff;
493 }
494 }
495
496 /* Read an L2 UC or MC entry out of a hash bucket of the L2 forwarding table
497 * hash is the id of the bucket and pos is the position of the entry in that bucket
498 * The data read from the SoC is filled into rtl838x_l2_entry
499 */
500 static u64 rtl930x_read_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e)
501 {
502 u32 r[3];
503 struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 0);
504 u32 idx;
505 int i;
506 u64 mac;
507 u64 seed;
508
509 pr_debug("%s: hash %08x, pos: %d\n", __func__, hash, pos);
510
511 /* On the RTL93xx, 2 different hash algorithms are used making it a
512 * total of 8 buckets that need to be searched, 4 for each hash-half
513 * Use second hash space when bucket is between 4 and 8
514 */
515 if (pos >= 4) {
516 pos -= 4;
517 hash >>= 16;
518 } else {
519 hash &= 0xffff;
520 }
521
522 idx = (0 << 14) | (hash << 2) | pos; // Search SRAM, with hash and at pos in bucket
523 pr_debug("%s: NOW hash %08x, pos: %d\n", __func__, hash, pos);
524
525 rtl_table_read(q, idx);
526 for (i = 0; i < 3; i++)
527 r[i] = sw_r32(rtl_table_data(q, i));
528
529 rtl_table_release(q);
530
531 rtl930x_fill_l2_entry(r, e);
532
533 pr_debug("%s: valid: %d, nh: %d\n", __func__, e->valid, e->next_hop);
534 if (!e->valid)
535 return 0;
536
537 mac = ((u64)e->mac[0]) << 40 |
538 ((u64)e->mac[1]) << 32 |
539 ((u64)e->mac[2]) << 24 |
540 ((u64)e->mac[3]) << 16 |
541 ((u64)e->mac[4]) << 8 |
542 ((u64)e->mac[5]);
543
544 seed = rtl930x_l2_hash_seed(mac, e->rvid);
545 pr_debug("%s: mac %016llx, seed %016llx\n", __func__, mac, seed);
546
547 // return vid with concatenated mac as unique id
548 return seed;
549 }
550
551 static void rtl930x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e)
552 {
553 u32 r[3];
554 struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 0);
555 u32 idx = (0 << 14) | (hash << 2) | pos; // Access SRAM, with hash and at pos in bucket
556 int i;
557
558 pr_debug("%s: hash %d, pos %d\n", __func__, hash, pos);
559 pr_debug("%s: index %d -> mac %02x:%02x:%02x:%02x:%02x:%02x\n", __func__, idx,
560 e->mac[0], e->mac[1], e->mac[2], e->mac[3],e->mac[4],e->mac[5]);
561
562 rtl930x_fill_l2_row(r, e);
563
564 for (i = 0; i < 3; i++)
565 sw_w32(r[i], rtl_table_data(q, i));
566
567 rtl_table_write(q, idx);
568 rtl_table_release(q);
569 }
570
571 static u64 rtl930x_read_cam(int idx, struct rtl838x_l2_entry *e)
572 {
573 u32 r[3];
574 struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 1);
575 int i;
576
577 rtl_table_read(q, idx);
578 for (i = 0; i < 3; i++)
579 r[i] = sw_r32(rtl_table_data(q, i));
580
581 rtl_table_release(q);
582
583 rtl930x_fill_l2_entry(r, e);
584 if (!e->valid)
585 return 0;
586
587 // return mac with concatenated vid as unique id
588 return ((u64)r[0] << 28) | ((r[1] & 0xffff0000) >> 4) | e->vid;
589 }
590
591 static void rtl930x_write_cam(int idx, struct rtl838x_l2_entry *e)
592 {
593 u32 r[3];
594 struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 1); // Access L2 Table 1
595 int i;
596
597 rtl930x_fill_l2_row(r, e);
598
599 for (i = 0; i < 3; i++)
600 sw_w32(r[i], rtl_table_data(q, i));
601
602 rtl_table_write(q, idx);
603 rtl_table_release(q);
604 }
605
606 static u64 rtl930x_read_mcast_pmask(int idx)
607 {
608 u32 portmask;
609 // Read MC_PORTMASK (2) via register RTL9300_TBL_L2
610 struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 2);
611
612 rtl_table_read(q, idx);
613 portmask = sw_r32(rtl_table_data(q, 0));
614 portmask >>= 3;
615 rtl_table_release(q);
616
617 pr_debug("%s: Index idx %d has portmask %08x\n", __func__, idx, portmask);
618
619 return portmask;
620 }
621
622 static void rtl930x_write_mcast_pmask(int idx, u64 portmask)
623 {
624 u32 pm = portmask;
625
626 // Access MC_PORTMASK (2) via register RTL9300_TBL_L2
627 struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 2);
628
629 pr_debug("%s: Index idx %d has portmask %08x\n", __func__, idx, pm);
630 pm <<= 3;
631 sw_w32(pm, rtl_table_data(q, 0));
632 rtl_table_write(q, idx);
633 rtl_table_release(q);
634 }
635
636 u64 rtl930x_traffic_get(int source)
637 {
638 u32 v;
639 struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6);
640
641 rtl_table_read(r, source);
642 v = sw_r32(rtl_table_data(r, 0));
643 rtl_table_release(r);
644 v = v >> 3;
645
646 return v;
647 }
648
649 /* Enable traffic between a source port and a destination port matrix */
650 void rtl930x_traffic_set(int source, u64 dest_matrix)
651 {
652 struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6);
653
654 sw_w32((dest_matrix << 3), rtl_table_data(r, 0));
655 rtl_table_write(r, source);
656 rtl_table_release(r);
657 }
658
659 void rtl930x_traffic_enable(int source, int dest)
660 {
661 struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6);
662 rtl_table_read(r, source);
663 sw_w32_mask(0, BIT(dest + 3), rtl_table_data(r, 0));
664 rtl_table_write(r, source);
665 rtl_table_release(r);
666 }
667
668 void rtl930x_traffic_disable(int source, int dest)
669 {
670 struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6);
671 rtl_table_read(r, source);
672 sw_w32_mask(BIT(dest + 3), 0, rtl_table_data(r, 0));
673 rtl_table_write(r, source);
674 rtl_table_release(r);
675 }
676
677 void rtl9300_dump_debug(void)
678 {
679 int i;
680 u16 r = RTL930X_STAT_PRVTE_DROP_COUNTER0;
681
682 for (i = 0; i < 10; i ++) {
683 pr_info("# %d %08x %08x %08x %08x %08x %08x %08x %08x\n", i * 8,
684 sw_r32(r), sw_r32(r + 4), sw_r32(r + 8), sw_r32(r + 12),
685 sw_r32(r + 16), sw_r32(r + 20), sw_r32(r + 24), sw_r32(r + 28));
686 r += 32;
687 }
688 pr_info("# %08x %08x %08x %08x %08x\n",
689 sw_r32(r), sw_r32(r + 4), sw_r32(r + 8), sw_r32(r + 12), sw_r32(r + 16));
690 rtl930x_print_matrix();
691 pr_info("RTL930X_L2_PORT_SABLK_CTRL: %08x, RTL930X_L2_PORT_DABLK_CTRL %08x\n",
692 sw_r32(RTL930X_L2_PORT_SABLK_CTRL), sw_r32(RTL930X_L2_PORT_DABLK_CTRL)
693
694 );
695 }
696
697 irqreturn_t rtl930x_switch_irq(int irq, void *dev_id)
698 {
699 struct dsa_switch *ds = dev_id;
700 u32 ports = sw_r32(RTL930X_ISR_PORT_LINK_STS_CHG);
701 u32 link;
702 int i;
703
704 /* Clear status */
705 sw_w32(ports, RTL930X_ISR_PORT_LINK_STS_CHG);
706
707 for (i = 0; i < 28; i++) {
708 if (ports & BIT(i)) {
709 /* Read the register twice because of issues with latency at least
710 * with the external RTL8226 PHY on the XGS1210
711 */
712 link = sw_r32(RTL930X_MAC_LINK_STS);
713 link = sw_r32(RTL930X_MAC_LINK_STS);
714 if (link & BIT(i))
715 dsa_port_phylink_mac_change(ds, i, true);
716 else
717 dsa_port_phylink_mac_change(ds, i, false);
718 }
719 }
720
721 return IRQ_HANDLED;
722 }
723
724 int rtl930x_write_phy(u32 port, u32 page, u32 reg, u32 val)
725 {
726 u32 v;
727 int err = 0;
728
729 pr_debug("%s: port %d, page: %d, reg: %x, val: %x\n", __func__, port, page, reg, val);
730
731 if (port > 63 || page > 4095 || reg > 31)
732 return -ENOTSUPP;
733
734 val &= 0xffff;
735 mutex_lock(&smi_lock);
736
737 sw_w32(BIT(port), RTL930X_SMI_ACCESS_PHY_CTRL_0);
738 sw_w32_mask(0xffff << 16, val << 16, RTL930X_SMI_ACCESS_PHY_CTRL_2);
739 v = reg << 20 | page << 3 | 0x1f << 15 | BIT(2) | BIT(0);
740 sw_w32(v, RTL930X_SMI_ACCESS_PHY_CTRL_1);
741
742 do {
743 v = sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_1);
744 } while (v & 0x1);
745
746 if (v & 0x2)
747 err = -EIO;
748
749 mutex_unlock(&smi_lock);
750
751 return err;
752 }
753
754 int rtl930x_read_phy(u32 port, u32 page, u32 reg, u32 *val)
755 {
756 u32 v;
757 int err = 0;
758
759 if (port > 63 || page > 4095 || reg > 31)
760 return -ENOTSUPP;
761
762 mutex_lock(&smi_lock);
763
764 sw_w32_mask(0xffff << 16, port << 16, RTL930X_SMI_ACCESS_PHY_CTRL_2);
765 v = reg << 20 | page << 3 | 0x1f << 15 | 1;
766 sw_w32(v, RTL930X_SMI_ACCESS_PHY_CTRL_1);
767
768 do {
769 v = sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_1);
770 } while ( v & 0x1);
771
772 if (v & BIT(25)) {
773 pr_debug("Error reading phy %d, register %d\n", port, reg);
774 err = -EIO;
775 }
776 *val = (sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_2) & 0xffff);
777
778 pr_debug("%s: port %d, page: %d, reg: %x, val: %x\n", __func__, port, page, reg, *val);
779
780 mutex_unlock(&smi_lock);
781
782 return err;
783 }
784
785 /* Write to an mmd register of the PHY */
786 int rtl930x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val)
787 {
788 int err = 0;
789 u32 v;
790
791 mutex_lock(&smi_lock);
792
793 // Set PHY to access
794 sw_w32(BIT(port), RTL930X_SMI_ACCESS_PHY_CTRL_0);
795
796 // Set data to write
797 sw_w32_mask(0xffff << 16, val << 16, RTL930X_SMI_ACCESS_PHY_CTRL_2);
798
799 // Set MMD device number and register to write to
800 sw_w32(devnum << 16 | (regnum & 0xffff), RTL930X_SMI_ACCESS_PHY_CTRL_3);
801
802 v = BIT(2) | BIT(1) | BIT(0); // WRITE | MMD-access | EXEC
803 sw_w32(v, RTL930X_SMI_ACCESS_PHY_CTRL_1);
804
805 do {
806 v = sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_1);
807 } while (v & BIT(0));
808
809 pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__, port, regnum, val, err);
810 mutex_unlock(&smi_lock);
811 return err;
812 }
813
814 /* Read an mmd register of the PHY */
815 int rtl930x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val)
816 {
817 int err = 0;
818 u32 v;
819
820 mutex_lock(&smi_lock);
821
822 // Set PHY to access
823 sw_w32_mask(0xffff << 16, port << 16, RTL930X_SMI_ACCESS_PHY_CTRL_2);
824
825 // Set MMD device number and register to write to
826 sw_w32(devnum << 16 | (regnum & 0xffff), RTL930X_SMI_ACCESS_PHY_CTRL_3);
827
828 v = BIT(1) | BIT(0); // MMD-access | EXEC
829 sw_w32(v, RTL930X_SMI_ACCESS_PHY_CTRL_1);
830
831 do {
832 v = sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_1);
833 } while (v & BIT(0));
834 // There is no error-checking via BIT 25 of v, as it does not seem to be set correctly
835 *val = (sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_2) & 0xffff);
836 pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__, port, regnum, *val, err);
837
838 mutex_unlock(&smi_lock);
839
840 return err;
841 }
842
843 /* Calculate both the block 0 and the block 1 hash, and return in
844 * lower and higher word of the return value since only 12 bit of
845 * the hash are significant
846 */
847 u32 rtl930x_hash(struct rtl838x_switch_priv *priv, u64 seed)
848 {
849 u32 k0, k1, h1, h2, h;
850
851 k0 = (u32) (((seed >> 55) & 0x1f) ^
852 ((seed >> 44) & 0x7ff) ^
853 ((seed >> 33) & 0x7ff) ^
854 ((seed >> 22) & 0x7ff) ^
855 ((seed >> 11) & 0x7ff) ^
856 (seed & 0x7ff));
857
858 h1 = (seed >> 11) & 0x7ff;
859 h1 = ((h1 & 0x1f) << 6) | ((h1 >> 5) & 0x3f);
860
861 h2 = (seed >> 33) & 0x7ff;
862 h2 = ((h2 & 0x3f) << 5) | ((h2 >> 6) & 0x3f);
863
864 k1 = (u32) (((seed << 55) & 0x1f) ^
865 ((seed >> 44) & 0x7ff) ^
866 h2 ^
867 ((seed >> 22) & 0x7ff) ^
868 h1 ^
869 (seed & 0x7ff));
870
871 // Algorithm choice for block 0
872 if (sw_r32(RTL930X_L2_CTRL) & BIT(0))
873 h = k1;
874 else
875 h = k0;
876
877 /* Algorithm choice for block 1
878 * Since k0 and k1 are < 2048, adding 2048 will offset the hash into the second
879 * half of hash-space
880 * 2048 is in fact the hash-table size 16384 divided by 4 hashes per bucket
881 * divided by 2 to divide the hash space in 2
882 */
883 if (sw_r32(RTL930X_L2_CTRL) & BIT(1))
884 h |= (k1 + 2048) << 16;
885 else
886 h |= (k0 + 2048) << 16;
887
888 return h;
889 }
890
891 /* Enables or disables the EEE/EEEP capability of a port */
892 void rtl930x_port_eee_set(struct rtl838x_switch_priv *priv, int port, bool enable)
893 {
894 u32 v;
895
896 // This works only for Ethernet ports, and on the RTL930X, ports from 26 are SFP
897 if (port >= 26)
898 return;
899
900 pr_debug("In %s: setting port %d to %d\n", __func__, port, enable);
901 v = enable ? 0x3f : 0x0;
902
903 // Set EEE/EEEP state for 100, 500, 1000MBit and 2.5, 5 and 10GBit
904 sw_w32_mask(0, v << 10, rtl930x_mac_force_mode_ctrl(port));
905
906 // Set TX/RX EEE state
907 v = enable ? 0x3 : 0x0;
908 sw_w32(v, RTL930X_EEE_CTRL(port));
909
910 priv->ports[port].eee_enabled = enable;
911 }
912
913 /* Get EEE own capabilities and negotiation result */
914 int rtl930x_eee_port_ability(struct rtl838x_switch_priv *priv, struct ethtool_eee *e, int port)
915 {
916 u32 link, a;
917
918 if (port >= 26)
919 return -ENOTSUPP;
920
921 pr_info("In %s, port %d\n", __func__, port);
922 link = sw_r32(RTL930X_MAC_LINK_STS);
923 link = sw_r32(RTL930X_MAC_LINK_STS);
924 if (!(link & BIT(port)))
925 return 0;
926
927 pr_info("Setting advertised\n");
928 if (sw_r32(rtl930x_mac_force_mode_ctrl(port)) & BIT(10))
929 e->advertised |= ADVERTISED_100baseT_Full;
930
931 if (sw_r32(rtl930x_mac_force_mode_ctrl(port)) & BIT(12))
932 e->advertised |= ADVERTISED_1000baseT_Full;
933
934 if (priv->ports[port].is2G5 && sw_r32(rtl930x_mac_force_mode_ctrl(port)) & BIT(13)) {
935 pr_info("ADVERTISING 2.5G EEE\n");
936 e->advertised |= ADVERTISED_2500baseX_Full;
937 }
938
939 if (priv->ports[port].is10G && sw_r32(rtl930x_mac_force_mode_ctrl(port)) & BIT(15))
940 e->advertised |= ADVERTISED_10000baseT_Full;
941
942 a = sw_r32(RTL930X_MAC_EEE_ABLTY);
943 a = sw_r32(RTL930X_MAC_EEE_ABLTY);
944 pr_info("Link partner: %08x\n", a);
945 if (a & BIT(port)) {
946 e->lp_advertised = ADVERTISED_100baseT_Full;
947 e->lp_advertised |= ADVERTISED_1000baseT_Full;
948 if (priv->ports[port].is2G5)
949 e->lp_advertised |= ADVERTISED_2500baseX_Full;
950 if (priv->ports[port].is10G)
951 e->lp_advertised |= ADVERTISED_10000baseT_Full;
952 }
953
954 // Read 2x to clear latched state
955 a = sw_r32(RTL930X_EEEP_PORT_CTRL(port));
956 a = sw_r32(RTL930X_EEEP_PORT_CTRL(port));
957 pr_info("%s RTL930X_EEEP_PORT_CTRL: %08x\n", __func__, a);
958
959 return 0;
960 }
961
962 static void rtl930x_init_eee(struct rtl838x_switch_priv *priv, bool enable)
963 {
964 int i;
965
966 pr_info("Setting up EEE, state: %d\n", enable);
967
968 // Setup EEE on all ports
969 for (i = 0; i < priv->cpu_port; i++) {
970 if (priv->ports[i].phy)
971 rtl930x_port_eee_set(priv, i, enable);
972 }
973
974 priv->eee_enabled = enable;
975 }
976 #define HASH_PICK(val, lsb, len) ((val & (((1 << len) - 1) << lsb)) >> lsb)
977
978 static u32 rtl930x_l3_hash4(u32 ip, int algorithm, bool move_dip)
979 {
980 u32 rows[4];
981 u32 hash;
982 u32 s0, s1, pH;
983
984 memset(rows, 0, sizeof(rows));
985
986 rows[0] = HASH_PICK(ip, 27, 5);
987 rows[1] = HASH_PICK(ip, 18, 9);
988 rows[2] = HASH_PICK(ip, 9, 9);
989
990 if (!move_dip)
991 rows[3] = HASH_PICK(ip, 0, 9);
992
993 if (!algorithm) {
994 hash = rows[0] ^ rows[1] ^ rows[2] ^ rows[3];
995 } else {
996 s0 = rows[0] + rows[1] + rows[2];
997 s1 = (s0 & 0x1ff) + ((s0 & (0x1ff << 9)) >> 9);
998 pH = (s1 & 0x1ff) + ((s1 & (0x1ff << 9)) >> 9);
999 hash = pH ^ rows[3];
1000 }
1001 return hash;
1002 }
1003
1004 static u32 rtl930x_l3_hash6(struct in6_addr *ip6, int algorithm, bool move_dip)
1005 {
1006 u32 rows[16];
1007 u32 hash;
1008 u32 s0, s1, pH;
1009
1010 rows[0] = (HASH_PICK(ip6->s6_addr[0], 6, 2) << 0);
1011 rows[1] = (HASH_PICK(ip6->s6_addr[0], 0, 6) << 3) | HASH_PICK(ip6->s6_addr[1], 5, 3);
1012 rows[2] = (HASH_PICK(ip6->s6_addr[1], 0, 5) << 4) | HASH_PICK(ip6->s6_addr[2], 4, 4);
1013 rows[3] = (HASH_PICK(ip6->s6_addr[2], 0, 4) << 5) | HASH_PICK(ip6->s6_addr[3], 3, 5);
1014 rows[4] = (HASH_PICK(ip6->s6_addr[3], 0, 3) << 6) | HASH_PICK(ip6->s6_addr[4], 2, 6);
1015 rows[5] = (HASH_PICK(ip6->s6_addr[4], 0, 2) << 7) | HASH_PICK(ip6->s6_addr[5], 1, 7);
1016 rows[6] = (HASH_PICK(ip6->s6_addr[5], 0, 1) << 8) | HASH_PICK(ip6->s6_addr[6], 0, 8);
1017 rows[7] = (HASH_PICK(ip6->s6_addr[7], 0, 8) << 1) | HASH_PICK(ip6->s6_addr[8], 7, 1);
1018 rows[8] = (HASH_PICK(ip6->s6_addr[8], 0, 7) << 2) | HASH_PICK(ip6->s6_addr[9], 6, 2);
1019 rows[9] = (HASH_PICK(ip6->s6_addr[9], 0, 6) << 3) | HASH_PICK(ip6->s6_addr[10], 5, 3);
1020 rows[10] = (HASH_PICK(ip6->s6_addr[10], 0, 5) << 4) | HASH_PICK(ip6->s6_addr[11], 4, 4);
1021 if (!algorithm) {
1022 rows[11] = (HASH_PICK(ip6->s6_addr[11], 0, 4) << 5) |
1023 (HASH_PICK(ip6->s6_addr[12], 3, 5) << 0);
1024 rows[12] = (HASH_PICK(ip6->s6_addr[12], 0, 3) << 6) |
1025 (HASH_PICK(ip6->s6_addr[13], 2, 6) << 0);
1026 rows[13] = (HASH_PICK(ip6->s6_addr[13], 0, 2) << 7) |
1027 (HASH_PICK(ip6->s6_addr[14], 1, 7) << 0);
1028 if (!move_dip) {
1029 rows[14] = (HASH_PICK(ip6->s6_addr[14], 0, 1) << 8) |
1030 (HASH_PICK(ip6->s6_addr[15], 0, 8) << 0);
1031 }
1032 hash = rows[0] ^ rows[1] ^ rows[2] ^ rows[3] ^ rows[4] ^
1033 rows[5] ^ rows[6] ^ rows[7] ^ rows[8] ^ rows[9] ^
1034 rows[10] ^ rows[11] ^ rows[12] ^ rows[13] ^ rows[14];
1035 } else {
1036 rows[11] = (HASH_PICK(ip6->s6_addr[11], 0, 4) << 5);
1037 rows[12] = (HASH_PICK(ip6->s6_addr[12], 3, 5) << 0);
1038 rows[13] = (HASH_PICK(ip6->s6_addr[12], 0, 3) << 6) |
1039 HASH_PICK(ip6->s6_addr[13], 2, 6);
1040 rows[14] = (HASH_PICK(ip6->s6_addr[13], 0, 2) << 7) |
1041 HASH_PICK(ip6->s6_addr[14], 1, 7);
1042 if (!move_dip) {
1043 rows[15] = (HASH_PICK(ip6->s6_addr[14], 0, 1) << 8) |
1044 (HASH_PICK(ip6->s6_addr[15], 0, 8) << 0);
1045 }
1046 s0 = rows[12] + rows[13] + rows[14];
1047 s1 = (s0 & 0x1ff) + ((s0 & (0x1ff << 9)) >> 9);
1048 pH = (s1 & 0x1ff) + ((s1 & (0x1ff << 9)) >> 9);
1049 hash = rows[0] ^ rows[1] ^ rows[2] ^ rows[3] ^ rows[4] ^
1050 rows[5] ^ rows[6] ^ rows[7] ^ rows[8] ^ rows[9] ^
1051 rows[10] ^ rows[11] ^ pH ^ rows[15];
1052 }
1053 return hash;
1054 }
1055
1056 /* Read a prefix route entry from the L3_PREFIX_ROUTE_IPUC table
1057 * We currently only support IPv4 and IPv6 unicast route
1058 */
1059 static void rtl930x_route_read(int idx, struct rtl83xx_route *rt)
1060 {
1061 u32 v, ip4_m;
1062 bool host_route, default_route;
1063 struct in6_addr ip6_m;
1064
1065 // Read L3_PREFIX_ROUTE_IPUC table (2) via register RTL9300_TBL_1
1066 struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 2);
1067
1068 rtl_table_read(r, idx);
1069 // The table has a size of 11 registers
1070 rt->attr.valid = !!(sw_r32(rtl_table_data(r, 0)) & BIT(31));
1071 if (!rt->attr.valid)
1072 goto out;
1073
1074 rt->attr.type = (sw_r32(rtl_table_data(r, 0)) >> 29) & 0x3;
1075
1076 v = sw_r32(rtl_table_data(r, 10));
1077 host_route = !!(v & BIT(21));
1078 default_route = !!(v & BIT(20));
1079 rt->prefix_len = -1;
1080 pr_info("%s: host route %d, default_route %d\n", __func__, host_route, default_route);
1081
1082 switch (rt->attr.type) {
1083 case 0: // IPv4 Unicast route
1084 rt->dst_ip = sw_r32(rtl_table_data(r, 4));
1085 ip4_m = sw_r32(rtl_table_data(r, 9));
1086 pr_info("%s: Read ip4 mask: %08x\n", __func__, ip4_m);
1087 rt->prefix_len = host_route ? 32 : -1;
1088 rt->prefix_len = (rt->prefix_len < 0 && default_route) ? 0 : -1;
1089 if (rt->prefix_len < 0)
1090 rt->prefix_len = inet_mask_len(ip4_m);
1091 break;
1092 case 2: // IPv6 Unicast route
1093 ipv6_addr_set(&rt->dst_ip6,
1094 sw_r32(rtl_table_data(r, 1)), sw_r32(rtl_table_data(r, 2)),
1095 sw_r32(rtl_table_data(r, 3)), sw_r32(rtl_table_data(r, 4)));
1096 ipv6_addr_set(&ip6_m,
1097 sw_r32(rtl_table_data(r, 6)), sw_r32(rtl_table_data(r, 7)),
1098 sw_r32(rtl_table_data(r, 8)), sw_r32(rtl_table_data(r, 9)));
1099 rt->prefix_len = host_route ? 128 : 0;
1100 rt->prefix_len = (rt->prefix_len < 0 && default_route) ? 0 : -1;
1101 if (rt->prefix_len < 0)
1102 rt->prefix_len = find_last_bit((unsigned long int *)&ip6_m.s6_addr32,
1103 128);
1104 break;
1105 case 1: // IPv4 Multicast route
1106 case 3: // IPv6 Multicast route
1107 pr_warn("%s: route type not supported\n", __func__);
1108 goto out;
1109 }
1110
1111 rt->attr.hit = !!(v & BIT(22));
1112 rt->attr.action = (v >> 18) & 3;
1113 rt->nh.id = (v >> 7) & 0x7ff;
1114 rt->attr.ttl_dec = !!(v & BIT(6));
1115 rt->attr.ttl_check = !!(v & BIT(5));
1116 rt->attr.dst_null = !!(v & BIT(4));
1117 rt->attr.qos_as = !!(v & BIT(3));
1118 rt->attr.qos_prio = v & 0x7;
1119 pr_info("%s: index %d is valid: %d\n", __func__, idx, rt->attr.valid);
1120 pr_info("%s: next_hop: %d, hit: %d, action :%d, ttl_dec %d, ttl_check %d, dst_null %d\n",
1121 __func__, rt->nh.id, rt->attr.hit, rt->attr.action,
1122 rt->attr.ttl_dec, rt->attr.ttl_check, rt->attr.dst_null);
1123 pr_info("%s: GW: %pI4, prefix_len: %d\n", __func__, &rt->dst_ip, rt->prefix_len);
1124 out:
1125 rtl_table_release(r);
1126 }
1127
1128 static void rtl930x_net6_mask(int prefix_len, struct in6_addr *ip6_m)
1129 {
1130 int o, b;
1131 // Define network mask
1132 o = prefix_len >> 3;
1133 b = prefix_len & 0x7;
1134 memset(ip6_m->s6_addr, 0xff, o);
1135 ip6_m->s6_addr[o] |= b ? 0xff00 >> b : 0x00;
1136 }
1137
1138 /* Read a host route entry from the table using its index
1139 * We currently only support IPv4 and IPv6 unicast route
1140 */
1141 static void rtl930x_host_route_read(int idx, struct rtl83xx_route *rt)
1142 {
1143 u32 v;
1144 // Read L3_HOST_ROUTE_IPUC table (1) via register RTL9300_TBL_1
1145 struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 1);
1146
1147 idx = ((idx / 6) * 8) + (idx % 6);
1148
1149 pr_debug("In %s, physical index %d\n", __func__, idx);
1150 rtl_table_read(r, idx);
1151 // The table has a size of 5 (for UC, 11 for MC) registers
1152 v = sw_r32(rtl_table_data(r, 0));
1153 rt->attr.valid = !!(v & BIT(31));
1154 if (!rt->attr.valid)
1155 goto out;
1156 rt->attr.type = (v >> 29) & 0x3;
1157 switch (rt->attr.type) {
1158 case 0: // IPv4 Unicast route
1159 rt->dst_ip = sw_r32(rtl_table_data(r, 4));
1160 break;
1161 case 2: // IPv6 Unicast route
1162 ipv6_addr_set(&rt->dst_ip6,
1163 sw_r32(rtl_table_data(r, 3)), sw_r32(rtl_table_data(r, 2)),
1164 sw_r32(rtl_table_data(r, 1)), sw_r32(rtl_table_data(r, 0)));
1165 break;
1166 case 1: // IPv4 Multicast route
1167 case 3: // IPv6 Multicast route
1168 pr_warn("%s: route type not supported\n", __func__);
1169 goto out;
1170 }
1171
1172 rt->attr.hit = !!(v & BIT(20));
1173 rt->attr.dst_null = !!(v & BIT(19));
1174 rt->attr.action = (v >> 17) & 3;
1175 rt->nh.id = (v >> 6) & 0x7ff;
1176 rt->attr.ttl_dec = !!(v & BIT(5));
1177 rt->attr.ttl_check = !!(v & BIT(4));
1178 rt->attr.qos_as = !!(v & BIT(3));
1179 rt->attr.qos_prio = v & 0x7;
1180 pr_debug("%s: index %d is valid: %d\n", __func__, idx, rt->attr.valid);
1181 pr_debug("%s: next_hop: %d, hit: %d, action :%d, ttl_dec %d, ttl_check %d, dst_null %d\n",
1182 __func__, rt->nh.id, rt->attr.hit, rt->attr.action, rt->attr.ttl_dec, rt->attr.ttl_check,
1183 rt->attr.dst_null);
1184 pr_debug("%s: Destination: %pI4\n", __func__, &rt->dst_ip);
1185
1186 out:
1187 rtl_table_release(r);
1188 }
1189
1190 /* Write a host route entry from the table using its index
1191 * We currently only support IPv4 and IPv6 unicast route
1192 */
1193 static void rtl930x_host_route_write(int idx, struct rtl83xx_route *rt)
1194 {
1195 u32 v;
1196 // Access L3_HOST_ROUTE_IPUC table (1) via register RTL9300_TBL_1
1197 struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 1);
1198 // The table has a size of 5 (for UC, 11 for MC) registers
1199
1200 idx = ((idx / 6) * 8) + (idx % 6);
1201
1202 pr_debug("%s: index %d is valid: %d\n", __func__, idx, rt->attr.valid);
1203 pr_debug("%s: next_hop: %d, hit: %d, action :%d, ttl_dec %d, ttl_check %d, dst_null %d\n",
1204 __func__, rt->nh.id, rt->attr.hit, rt->attr.action, rt->attr.ttl_dec, rt->attr.ttl_check,
1205 rt->attr.dst_null);
1206 pr_debug("%s: GW: %pI4, prefix_len: %d\n", __func__, &rt->dst_ip, rt->prefix_len);
1207
1208 v = BIT(31); // Entry is valid
1209 v |= (rt->attr.type & 0x3) << 29;
1210 v |= rt->attr.hit ? BIT(20) : 0;
1211 v |= rt->attr.dst_null ? BIT(19) : 0;
1212 v |= (rt->attr.action & 0x3) << 17;
1213 v |= (rt->nh.id & 0x7ff) << 6;
1214 v |= rt->attr.ttl_dec ? BIT(5) : 0;
1215 v |= rt->attr.ttl_check ? BIT(4) : 0;
1216 v |= rt->attr.qos_as ? BIT(3) : 0;
1217 v |= rt->attr.qos_prio & 0x7;
1218
1219 sw_w32(v, rtl_table_data(r, 0));
1220 switch (rt->attr.type) {
1221 case 0: // IPv4 Unicast route
1222 sw_w32(0, rtl_table_data(r, 1));
1223 sw_w32(0, rtl_table_data(r, 2));
1224 sw_w32(0, rtl_table_data(r, 3));
1225 sw_w32(rt->dst_ip, rtl_table_data(r, 4));
1226 break;
1227 case 2: // IPv6 Unicast route
1228 sw_w32(rt->dst_ip6.s6_addr32[0], rtl_table_data(r, 1));
1229 sw_w32(rt->dst_ip6.s6_addr32[1], rtl_table_data(r, 2));
1230 sw_w32(rt->dst_ip6.s6_addr32[2], rtl_table_data(r, 3));
1231 sw_w32(rt->dst_ip6.s6_addr32[3], rtl_table_data(r, 4));
1232 break;
1233 case 1: // IPv4 Multicast route
1234 case 3: // IPv6 Multicast route
1235 pr_warn("%s: route type not supported\n", __func__);
1236 goto out;
1237 }
1238
1239 rtl_table_write(r, idx);
1240
1241 out:
1242 rtl_table_release(r);
1243 }
1244
1245 /* Look up the index of a prefix route in the routing table CAM for unicast IPv4/6 routes
1246 * using hardware offload.
1247 */
1248 static int rtl930x_route_lookup_hw(struct rtl83xx_route *rt)
1249 {
1250 u32 ip4_m, v;
1251 struct in6_addr ip6_m;
1252 int i;
1253
1254 if (rt->attr.type == 1 || rt->attr.type == 3) // Hardware only supports UC routes
1255 return -1;
1256
1257 sw_w32_mask(0x3 << 19, rt->attr.type, RTL930X_L3_HW_LU_KEY_CTRL);
1258 if (rt->attr.type) { // IPv6
1259 rtl930x_net6_mask(rt->prefix_len, &ip6_m);
1260 for (i = 0; i < 4; i++)
1261 sw_w32(rt->dst_ip6.s6_addr32[0] & ip6_m.s6_addr32[0],
1262 RTL930X_L3_HW_LU_KEY_IP_CTRL + (i << 2));
1263 } else { // IPv4
1264 ip4_m = inet_make_mask(rt->prefix_len);
1265 sw_w32(0, RTL930X_L3_HW_LU_KEY_IP_CTRL);
1266 sw_w32(0, RTL930X_L3_HW_LU_KEY_IP_CTRL + 4);
1267 sw_w32(0, RTL930X_L3_HW_LU_KEY_IP_CTRL + 8);
1268 v = rt->dst_ip & ip4_m;
1269 pr_info("%s: searching for %pI4\n", __func__, &v);
1270 sw_w32(v, RTL930X_L3_HW_LU_KEY_IP_CTRL + 12);
1271 }
1272
1273 // Execute CAM lookup in SoC
1274 sw_w32(BIT(15), RTL930X_L3_HW_LU_CTRL);
1275
1276 // Wait until execute bit clears and result is ready
1277 do {
1278 v = sw_r32(RTL930X_L3_HW_LU_CTRL);
1279 } while (v & BIT(15));
1280
1281 pr_info("%s: found: %d, index: %d\n", __func__, !!(v & BIT(14)), v & 0x1ff);
1282
1283 // Test if search successful (BIT 14 set)
1284 if (v & BIT(14))
1285 return v & 0x1ff;
1286
1287 return -1;
1288 }
1289
1290 static int rtl930x_find_l3_slot(struct rtl83xx_route *rt, bool must_exist)
1291 {
1292 int t, s, slot_width, algorithm, addr, idx;
1293 u32 hash;
1294 struct rtl83xx_route route_entry;
1295
1296 // IPv6 entries take up 3 slots
1297 slot_width = (rt->attr.type == 0) || (rt->attr.type == 2) ? 1 : 3;
1298
1299 for (t = 0; t < 2; t++) {
1300 algorithm = (sw_r32(RTL930X_L3_HOST_TBL_CTRL) >> (2 + t)) & 0x1;
1301 hash = rtl930x_l3_hash4(rt->dst_ip, algorithm, false);
1302
1303 pr_debug("%s: table %d, algorithm %d, hash %04x\n", __func__, t, algorithm, hash);
1304
1305 for (s = 0; s < 6; s += slot_width) {
1306 addr = (t << 12) | ((hash & 0x1ff) << 3) | s;
1307 pr_debug("%s physical address %d\n", __func__, addr);
1308 idx = ((addr / 8) * 6) + (addr % 8);
1309 pr_debug("%s logical address %d\n", __func__, idx);
1310
1311 rtl930x_host_route_read(idx, &route_entry);
1312 pr_debug("%s route valid %d, route dest: %pI4, hit %d\n", __func__,
1313 rt->attr.valid, &rt->dst_ip, rt->attr.hit);
1314 if (!must_exist && rt->attr.valid)
1315 return idx;
1316 if (must_exist && route_entry.dst_ip == rt->dst_ip)
1317 return idx;
1318 }
1319 }
1320
1321 return -1;
1322 }
1323
1324 /* Write a prefix route into the routing table CAM at position idx
1325 * Currently only IPv4 and IPv6 unicast routes are supported
1326 */
1327 static void rtl930x_route_write(int idx, struct rtl83xx_route *rt)
1328 {
1329 u32 v, ip4_m;
1330 struct in6_addr ip6_m;
1331 // Access L3_PREFIX_ROUTE_IPUC table (2) via register RTL9300_TBL_1
1332 // The table has a size of 11 registers (20 for MC)
1333 struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 2);
1334
1335 pr_debug("%s: index %d is valid: %d\n", __func__, idx, rt->attr.valid);
1336 pr_debug("%s: nexthop: %d, hit: %d, action :%d, ttl_dec %d, ttl_check %d, dst_null %d\n",
1337 __func__, rt->nh.id, rt->attr.hit, rt->attr.action,
1338 rt->attr.ttl_dec, rt->attr.ttl_check, rt->attr.dst_null);
1339 pr_debug("%s: GW: %pI4, prefix_len: %d\n", __func__, &rt->dst_ip, rt->prefix_len);
1340
1341 v = rt->attr.valid ? BIT(31) : 0;
1342 v |= (rt->attr.type & 0x3) << 29;
1343 sw_w32(v, rtl_table_data(r, 0));
1344
1345 v = rt->attr.hit ? BIT(22) : 0;
1346 v |= (rt->attr.action & 0x3) << 18;
1347 v |= (rt->nh.id & 0x7ff) << 7;
1348 v |= rt->attr.ttl_dec ? BIT(6) : 0;
1349 v |= rt->attr.ttl_check ? BIT(5) : 0;
1350 v |= rt->attr.dst_null ? BIT(6) : 0;
1351 v |= rt->attr.qos_as ? BIT(6) : 0;
1352 v |= rt->attr.qos_prio & 0x7;
1353 v |= rt->prefix_len == 0 ? BIT(20) : 0; // set default route bit
1354
1355 // set bit mask for entry type always to 0x3
1356 sw_w32(0x3 << 29, rtl_table_data(r, 5));
1357
1358 switch (rt->attr.type) {
1359 case 0: // IPv4 Unicast route
1360 sw_w32(0, rtl_table_data(r, 1));
1361 sw_w32(0, rtl_table_data(r, 2));
1362 sw_w32(0, rtl_table_data(r, 3));
1363 sw_w32(rt->dst_ip, rtl_table_data(r, 4));
1364
1365 v |= rt->prefix_len == 32 ? BIT(21) : 0; // set host-route bit
1366 ip4_m = inet_make_mask(rt->prefix_len);
1367 sw_w32(0, rtl_table_data(r, 6));
1368 sw_w32(0, rtl_table_data(r, 7));
1369 sw_w32(0, rtl_table_data(r, 8));
1370 sw_w32(ip4_m, rtl_table_data(r, 9));
1371 break;
1372 case 2: // IPv6 Unicast route
1373 sw_w32(rt->dst_ip6.s6_addr32[0], rtl_table_data(r, 1));
1374 sw_w32(rt->dst_ip6.s6_addr32[1], rtl_table_data(r, 2));
1375 sw_w32(rt->dst_ip6.s6_addr32[2], rtl_table_data(r, 3));
1376 sw_w32(rt->dst_ip6.s6_addr32[3], rtl_table_data(r, 4));
1377
1378 v |= rt->prefix_len == 128 ? BIT(21) : 0; // set host-route bit
1379
1380 rtl930x_net6_mask(rt->prefix_len, &ip6_m);
1381
1382 sw_w32(ip6_m.s6_addr32[0], rtl_table_data(r, 6));
1383 sw_w32(ip6_m.s6_addr32[1], rtl_table_data(r, 7));
1384 sw_w32(ip6_m.s6_addr32[2], rtl_table_data(r, 8));
1385 sw_w32(ip6_m.s6_addr32[3], rtl_table_data(r, 9));
1386 break;
1387 case 1: // IPv4 Multicast route
1388 case 3: // IPv6 Multicast route
1389 pr_warn("%s: route type not supported\n", __func__);
1390 rtl_table_release(r);
1391 return;
1392 }
1393 sw_w32(v, rtl_table_data(r, 10));
1394
1395 pr_debug("%s: %08x %08x %08x %08x %08x %08x %08x %08x %08x %08x %08x\n", __func__,
1396 sw_r32(rtl_table_data(r, 0)), sw_r32(rtl_table_data(r, 1)), sw_r32(rtl_table_data(r, 2)),
1397 sw_r32(rtl_table_data(r, 3)), sw_r32(rtl_table_data(r, 4)), sw_r32(rtl_table_data(r, 5)),
1398 sw_r32(rtl_table_data(r, 6)), sw_r32(rtl_table_data(r, 7)), sw_r32(rtl_table_data(r, 8)),
1399 sw_r32(rtl_table_data(r, 9)), sw_r32(rtl_table_data(r, 10)));
1400
1401 rtl_table_write(r, idx);
1402 rtl_table_release(r);
1403 }
1404
1405
1406 /* Get the destination MAC and L3 egress interface ID of a nexthop entry from
1407 * the SoC's L3_NEXTHOP table
1408 */
1409 static void rtl930x_get_l3_nexthop(int idx, u16 *dmac_id, u16 *interface)
1410 {
1411 u32 v;
1412 // Read L3_NEXTHOP table (3) via register RTL9300_TBL_1
1413 struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 3);
1414
1415 rtl_table_read(r, idx);
1416 // The table has a size of 1 register
1417 v = sw_r32(rtl_table_data(r, 0));
1418 rtl_table_release(r);
1419
1420 *dmac_id = (v >> 7) & 0x7fff;
1421 *interface = v & 0x7f;
1422 }
1423
1424 static int rtl930x_l3_mtu_del(struct rtl838x_switch_priv *priv, int mtu)
1425 {
1426 int i;
1427
1428 for (i = 0; i < MAX_INTF_MTUS; i++) {
1429 if (mtu == priv->intf_mtus[i])
1430 break;
1431 }
1432 if (i >= MAX_INTF_MTUS || !priv->intf_mtu_count[i]) {
1433 pr_err("%s: No MTU slot found for MTU: %d\n", __func__, mtu);
1434 return -EINVAL;
1435 }
1436
1437 priv->intf_mtu_count[i]--;
1438 }
1439
1440 static int rtl930x_l3_mtu_add(struct rtl838x_switch_priv *priv, int mtu)
1441 {
1442 int i, free_mtu;
1443 int mtu_id;
1444
1445 // Try to find an existing mtu-value or a free slot
1446 free_mtu = MAX_INTF_MTUS;
1447 for (i = 0; i < MAX_INTF_MTUS && priv->intf_mtus[i] != mtu; i++) {
1448 if ((!priv->intf_mtu_count[i]) && (free_mtu == MAX_INTF_MTUS))
1449 free_mtu = i;
1450 }
1451 i = (i < MAX_INTF_MTUS) ? i : free_mtu;
1452 if (i < MAX_INTF_MTUS) {
1453 mtu_id = i;
1454 } else {
1455 pr_err("%s: No free MTU slot available!\n", __func__);
1456 return -EINVAL;
1457 }
1458
1459 priv->intf_mtus[i] = mtu;
1460 pr_info("Writing MTU %d to slot %d\n", priv->intf_mtus[i], i);
1461 // Set MTU-value of the slot TODO: distinguish between IPv4/IPv6 routes / slots
1462 sw_w32_mask(0xffff << ((i % 2) * 16), priv->intf_mtus[i] << ((i % 2) * 16),
1463 RTL930X_L3_IP_MTU_CTRL(i));
1464 sw_w32_mask(0xffff << ((i % 2) * 16), priv->intf_mtus[i] << ((i % 2) * 16),
1465 RTL930X_L3_IP6_MTU_CTRL(i));
1466
1467 priv->intf_mtu_count[i]++;
1468
1469 return mtu_id;
1470 }
1471
1472 /* Creates an interface for a route by setting up the HW tables in the SoC */
1473 static int rtl930x_l3_intf_add(struct rtl838x_switch_priv *priv, struct rtl838x_l3_intf *intf)
1474 {
1475 int i, intf_id, mtu_id;
1476 // number of MTU-values < 16384
1477
1478 // Use the same IPv6 mtu as the ip4 mtu for this route if unset
1479 intf->ip6_mtu = intf->ip6_mtu ? intf->ip6_mtu : intf->ip4_mtu;
1480
1481 mtu_id = rtl930x_l3_mtu_add(priv, intf->ip4_mtu);
1482 pr_info("%s: added mtu %d with mtu-id %d\n", __func__, intf->ip4_mtu, mtu_id);
1483 if (mtu_id < 0)
1484 return -ENOSPC;
1485 intf->ip4_mtu_id = mtu_id;
1486 intf->ip6_mtu_id = mtu_id;
1487
1488 for (i = 0; i < MAX_INTERFACES; i++) {
1489 if (!priv->interfaces[i])
1490 break;
1491 }
1492 if (i >= MAX_INTERFACES) {
1493 pr_err("%s: cannot find free interface entry\n", __func__);
1494 return -EINVAL;
1495 }
1496 intf_id = i;
1497 priv->interfaces[i] = kzalloc(sizeof(struct rtl838x_l3_intf), GFP_KERNEL);
1498 if (!priv->interfaces[i]) {
1499 pr_err("%s: no memory to allocate new interface\n", __func__);
1500 return -ENOMEM;
1501 }
1502 }
1503
1504 /* Set the destination MAC and L3 egress interface ID for a nexthop entry in the SoC's
1505 * L3_NEXTHOP table. The nexthop entry is identified by idx.
1506 * dmac_id is the reference to the L2 entry in the L2 forwarding table, special values are
1507 * 0x7ffe: TRAP2CPU
1508 * 0x7ffd: TRAP2MASTERCPU
1509 * 0x7fff: DMAC_ID_DROP
1510 */
1511 static void rtl930x_set_l3_nexthop(int idx, u16 dmac_id, u16 interface)
1512 {
1513 // Access L3_NEXTHOP table (3) via register RTL9300_TBL_1
1514 struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 3);
1515
1516 pr_info("%s: Writing to L3_NEXTHOP table, index %d, dmac_id %d, interface %d\n",
1517 __func__, idx, dmac_id, interface);
1518 sw_w32(((dmac_id & 0x7fff) << 7) | (interface & 0x7f), rtl_table_data(r, 0));
1519
1520 pr_info("%s: %08x\n", __func__, sw_r32(rtl_table_data(r,0)));
1521 rtl_table_write(r, idx);
1522 rtl_table_release(r);
1523 }
1524
1525 static void rtl930x_pie_lookup_enable(struct rtl838x_switch_priv *priv, int index)
1526 {
1527 int block = index / PIE_BLOCK_SIZE;
1528
1529 sw_w32_mask(0, BIT(block), RTL930X_PIE_BLK_LOOKUP_CTRL);
1530 }
1531
1532 /* Reads the intermediate representation of the templated match-fields of the
1533 * PIE rule in the pie_rule structure and fills in the raw data fields in the
1534 * raw register space r[].
1535 * The register space configuration size is identical for the RTL8380/90 and RTL9300,
1536 * however the RTL9310 has 2 more registers / fields and the physical field-ids are different
1537 * on all SoCs
1538 * On the RTL9300 the mask fields are not word-aligend!
1539 */
1540 static void rtl930x_write_pie_templated(u32 r[], struct pie_rule *pr, enum template_field_id t[])
1541 {
1542 int i;
1543 enum template_field_id field_type;
1544 u16 data, data_m;
1545
1546 for (i = 0; i < N_FIXED_FIELDS; i++) {
1547 field_type = t[i];
1548 data = data_m = 0;
1549
1550 switch (field_type) {
1551 case TEMPLATE_FIELD_SPM0:
1552 data = pr->spm;
1553 data_m = pr->spm_m;
1554 break;
1555 case TEMPLATE_FIELD_SPM1:
1556 data = pr->spm >> 16;
1557 data_m = pr->spm_m >> 16;
1558 break;
1559 case TEMPLATE_FIELD_OTAG:
1560 data = pr->otag;
1561 data_m = pr->otag_m;
1562 break;
1563 case TEMPLATE_FIELD_SMAC0:
1564 data = pr->smac[4];
1565 data = (data << 8) | pr->smac[5];
1566 data_m = pr->smac_m[4];
1567 data_m = (data_m << 8) | pr->smac_m[5];
1568 break;
1569 case TEMPLATE_FIELD_SMAC1:
1570 data = pr->smac[2];
1571 data = (data << 8) | pr->smac[3];
1572 data_m = pr->smac_m[2];
1573 data_m = (data_m << 8) | pr->smac_m[3];
1574 break;
1575 case TEMPLATE_FIELD_SMAC2:
1576 data = pr->smac[0];
1577 data = (data << 8) | pr->smac[1];
1578 data_m = pr->smac_m[0];
1579 data_m = (data_m << 8) | pr->smac_m[1];
1580 break;
1581 case TEMPLATE_FIELD_DMAC0:
1582 data = pr->dmac[4];
1583 data = (data << 8) | pr->dmac[5];
1584 data_m = pr->dmac_m[4];
1585 data_m = (data_m << 8) | pr->dmac_m[5];
1586 break;
1587 case TEMPLATE_FIELD_DMAC1:
1588 data = pr->dmac[2];
1589 data = (data << 8) | pr->dmac[3];
1590 data_m = pr->dmac_m[2];
1591 data_m = (data_m << 8) | pr->dmac_m[3];
1592 break;
1593 case TEMPLATE_FIELD_DMAC2:
1594 data = pr->dmac[0];
1595 data = (data << 8) | pr->dmac[1];
1596 data_m = pr->dmac_m[0];
1597 data_m = (data_m << 8) | pr->dmac_m[1];
1598 break;
1599 case TEMPLATE_FIELD_ETHERTYPE:
1600 data = pr->ethertype;
1601 data_m = pr->ethertype_m;
1602 break;
1603 case TEMPLATE_FIELD_ITAG:
1604 data = pr->itag;
1605 data_m = pr->itag_m;
1606 break;
1607 case TEMPLATE_FIELD_SIP0:
1608 if (pr->is_ipv6) {
1609 data = pr->sip6.s6_addr16[7];
1610 data_m = pr->sip6_m.s6_addr16[7];
1611 } else {
1612 data = pr->sip;
1613 data_m = pr->sip_m;
1614 }
1615 break;
1616 case TEMPLATE_FIELD_SIP1:
1617 if (pr->is_ipv6) {
1618 data = pr->sip6.s6_addr16[6];
1619 data_m = pr->sip6_m.s6_addr16[6];
1620 } else {
1621 data = pr->sip >> 16;
1622 data_m = pr->sip_m >> 16;
1623 }
1624 break;
1625 case TEMPLATE_FIELD_SIP2:
1626 case TEMPLATE_FIELD_SIP3:
1627 case TEMPLATE_FIELD_SIP4:
1628 case TEMPLATE_FIELD_SIP5:
1629 case TEMPLATE_FIELD_SIP6:
1630 case TEMPLATE_FIELD_SIP7:
1631 data = pr->sip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)];
1632 data_m = pr->sip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)];
1633 break;
1634 case TEMPLATE_FIELD_DIP0:
1635 if (pr->is_ipv6) {
1636 data = pr->dip6.s6_addr16[7];
1637 data_m = pr->dip6_m.s6_addr16[7];
1638 } else {
1639 data = pr->dip;
1640 data_m = pr->dip_m;
1641 }
1642 break;
1643 case TEMPLATE_FIELD_DIP1:
1644 if (pr->is_ipv6) {
1645 data = pr->dip6.s6_addr16[6];
1646 data_m = pr->dip6_m.s6_addr16[6];
1647 } else {
1648 data = pr->dip >> 16;
1649 data_m = pr->dip_m >> 16;
1650 }
1651 break;
1652 case TEMPLATE_FIELD_DIP2:
1653 case TEMPLATE_FIELD_DIP3:
1654 case TEMPLATE_FIELD_DIP4:
1655 case TEMPLATE_FIELD_DIP5:
1656 case TEMPLATE_FIELD_DIP6:
1657 case TEMPLATE_FIELD_DIP7:
1658 data = pr->dip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)];
1659 data_m = pr->dip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)];
1660 break;
1661 case TEMPLATE_FIELD_IP_TOS_PROTO:
1662 data = pr->tos_proto;
1663 data_m = pr->tos_proto_m;
1664 break;
1665 case TEMPLATE_FIELD_L4_SPORT:
1666 data = pr->sport;
1667 data_m = pr->sport_m;
1668 break;
1669 case TEMPLATE_FIELD_L4_DPORT:
1670 data = pr->dport;
1671 data_m = pr->dport_m;
1672 break;
1673 case TEMPLATE_FIELD_DSAP_SSAP:
1674 data = pr->dsap_ssap;
1675 data_m = pr->dsap_ssap_m;
1676 break;
1677 case TEMPLATE_FIELD_TCP_INFO:
1678 data = pr->tcp_info;
1679 data_m = pr->tcp_info_m;
1680 break;
1681 case TEMPLATE_FIELD_RANGE_CHK:
1682 pr_warn("Warning: TEMPLATE_FIELD_RANGE_CHK: not configured\n");
1683 break;
1684 default:
1685 pr_info("%s: unknown field %d\n", __func__, field_type);
1686 }
1687
1688 // On the RTL9300, the mask fields are not word aligned!
1689 if (!(i % 2)) {
1690 r[5 - i / 2] = data;
1691 r[12 - i / 2] |= ((u32)data_m << 8);
1692 } else {
1693 r[5 - i / 2] |= ((u32)data) << 16;
1694 r[12 - i / 2] |= ((u32)data_m) << 24;
1695 r[11 - i / 2] |= ((u32)data_m) >> 8;
1696 }
1697 }
1698 }
1699
1700 static void rtl930x_read_pie_fixed_fields(u32 r[], struct pie_rule *pr)
1701 {
1702 pr->stacking_port = r[6] & BIT(31);
1703 pr->spn = (r[6] >> 24) & 0x7f;
1704 pr->mgnt_vlan = r[6] & BIT(23);
1705 if (pr->phase == PHASE_IACL)
1706 pr->dmac_hit_sw = r[6] & BIT(22);
1707 else
1708 pr->content_too_deep = r[6] & BIT(22);
1709 pr->not_first_frag = r[6] & BIT(21);
1710 pr->frame_type_l4 = (r[6] >> 18) & 7;
1711 pr->frame_type = (r[6] >> 16) & 3;
1712 pr->otag_fmt = (r[6] >> 15) & 1;
1713 pr->itag_fmt = (r[6] >> 14) & 1;
1714 pr->otag_exist = (r[6] >> 13) & 1;
1715 pr->itag_exist = (r[6] >> 12) & 1;
1716 pr->frame_type_l2 = (r[6] >> 10) & 3;
1717 pr->igr_normal_port = (r[6] >> 9) & 1;
1718 pr->tid = (r[6] >> 8) & 1;
1719
1720 pr->stacking_port_m = r[12] & BIT(7);
1721 pr->spn_m = r[12] & 0x7f;
1722 pr->mgnt_vlan_m = r[13] & BIT(31);
1723 if (pr->phase == PHASE_IACL)
1724 pr->dmac_hit_sw_m = r[13] & BIT(30);
1725 else
1726 pr->content_too_deep_m = r[13] & BIT(30);
1727 pr->not_first_frag_m = r[13] & BIT(29);
1728 pr->frame_type_l4_m = (r[13] >> 26) & 7;
1729 pr->frame_type_m = (r[13] >> 24) & 3;
1730 pr->otag_fmt_m = r[13] & BIT(23);
1731 pr->itag_fmt_m = r[13] & BIT(22);
1732 pr->otag_exist_m = r[13] & BIT(21);
1733 pr->itag_exist_m = r[13] & BIT (20);
1734 pr->frame_type_l2_m = (r[13] >> 18) & 3;
1735 pr->igr_normal_port_m = r[13] & BIT(17);
1736 pr->tid_m = (r[13] >> 16) & 1;
1737
1738 pr->valid = r[13] & BIT(15);
1739 pr->cond_not = r[13] & BIT(14);
1740 pr->cond_and1 = r[13] & BIT(13);
1741 pr->cond_and2 = r[13] & BIT(12);
1742 }
1743
1744 static void rtl930x_write_pie_fixed_fields(u32 r[], struct pie_rule *pr)
1745 {
1746 r[6] = pr->stacking_port ? BIT(31) : 0;
1747 r[6] |= ((u32) (pr->spn & 0x7f)) << 24;
1748 r[6] |= pr->mgnt_vlan ? BIT(23) : 0;
1749 if (pr->phase == PHASE_IACL)
1750 r[6] |= pr->dmac_hit_sw ? BIT(22) : 0;
1751 else
1752 r[6] |= pr->content_too_deep ? BIT(22) : 0;
1753 r[6] |= pr->not_first_frag ? BIT(21) : 0;
1754 r[6] |= ((u32) (pr->frame_type_l4 & 0x7)) << 18;
1755 r[6] |= ((u32) (pr->frame_type & 0x3)) << 16;
1756 r[6] |= pr->otag_fmt ? BIT(15) : 0;
1757 r[6] |= pr->itag_fmt ? BIT(14) : 0;
1758 r[6] |= pr->otag_exist ? BIT(13) : 0;
1759 r[6] |= pr->itag_exist ? BIT(12) : 0;
1760 r[6] |= ((u32) (pr->frame_type_l2 & 0x3)) << 10;
1761 r[6] |= pr->igr_normal_port ? BIT(9) : 0;
1762 r[6] |= ((u32) (pr->tid & 0x1)) << 8;
1763
1764 r[12] |= pr->stacking_port_m ? BIT(7) : 0;
1765 r[12] |= (u32) (pr->spn_m & 0x7f);
1766 r[13] |= pr->mgnt_vlan_m ? BIT(31) : 0;
1767 if (pr->phase == PHASE_IACL)
1768 r[13] |= pr->dmac_hit_sw_m ? BIT(30) : 0;
1769 else
1770 r[13] |= pr->content_too_deep_m ? BIT(30) : 0;
1771 r[13] |= pr->not_first_frag_m ? BIT(29) : 0;
1772 r[13] |= ((u32) (pr->frame_type_l4_m & 0x7)) << 26;
1773 r[13] |= ((u32) (pr->frame_type_m & 0x3)) << 24;
1774 r[13] |= pr->otag_fmt_m ? BIT(23) : 0;
1775 r[13] |= pr->itag_fmt_m ? BIT(22) : 0;
1776 r[13] |= pr->otag_exist_m ? BIT(21) : 0;
1777 r[13] |= pr->itag_exist_m ? BIT(20) : 0;
1778 r[13] |= ((u32) (pr->frame_type_l2_m & 0x3)) << 18;
1779 r[13] |= pr->igr_normal_port_m ? BIT(17) : 0;
1780 r[13] |= ((u32) (pr->tid_m & 0x1)) << 16;
1781
1782 r[13] |= pr->valid ? BIT(15) : 0;
1783 r[13] |= pr->cond_not ? BIT(14) : 0;
1784 r[13] |= pr->cond_and1 ? BIT(13) : 0;
1785 r[13] |= pr->cond_and2 ? BIT(12) : 0;
1786 }
1787
1788 static void rtl930x_write_pie_action(u32 r[], struct pie_rule *pr)
1789 {
1790 // Either drop or forward
1791 if (pr->drop) {
1792 r[14] |= BIT(24) | BIT(25) | BIT(26); // Do Green, Yellow and Red drops
1793 // Actually DROP, not PERMIT in Green / Yellow / Red
1794 r[14] |= BIT(23) | BIT(22) | BIT(20);
1795 } else {
1796 r[14] |= pr->fwd_sel ? BIT(27) : 0;
1797 r[14] |= pr->fwd_act << 18;
1798 r[14] |= BIT(14); // We overwrite any drop
1799 }
1800 if (pr->phase == PHASE_VACL)
1801 r[14] |= pr->fwd_sa_lrn ? BIT(15) : 0;
1802 r[13] |= pr->bypass_sel ? BIT(5) : 0;
1803 r[13] |= pr->nopri_sel ? BIT(4) : 0;
1804 r[13] |= pr->tagst_sel ? BIT(3) : 0;
1805 r[13] |= pr->ovid_sel ? BIT(1) : 0;
1806 r[14] |= pr->ivid_sel ? BIT(31) : 0;
1807 r[14] |= pr->meter_sel ? BIT(30) : 0;
1808 r[14] |= pr->mir_sel ? BIT(29) : 0;
1809 r[14] |= pr->log_sel ? BIT(28) : 0;
1810
1811 r[14] |= ((u32)(pr->fwd_data & 0x3fff)) << 3;
1812 r[15] |= pr->log_octets ? BIT(31) : 0;
1813 r[15] |= (u32)(pr->meter_data) << 23;
1814
1815 r[15] |= ((u32)(pr->ivid_act) << 21) & 0x3;
1816 r[15] |= ((u32)(pr->ivid_data) << 9) & 0xfff;
1817 r[16] |= ((u32)(pr->ovid_act) << 30) & 0x3;
1818 r[16] |= ((u32)(pr->ovid_data) & 0xfff) << 16;
1819 r[16] |= (pr->mir_data & 0x3) << 6;
1820 r[17] |= ((u32)(pr->tagst_data) & 0xf) << 28;
1821 r[17] |= ((u32)(pr->nopri_data) & 0x7) << 25;
1822 r[17] |= pr->bypass_ibc_sc ? BIT(16) : 0;
1823 }
1824
1825 void rtl930x_pie_rule_dump_raw(u32 r[])
1826 {
1827 pr_info("Raw IACL table entry:\n");
1828 pr_info("r 0 - 7: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1829 r[0], r[1], r[2], r[3], r[4], r[5], r[6], r[7]);
1830 pr_info("r 8 - 15: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1831 r[8], r[9], r[10], r[11], r[12], r[13], r[14], r[15]);
1832 pr_info("r 16 - 18: %08x %08x %08x\n", r[16], r[17], r[18]);
1833 pr_info("Match : %08x %08x %08x %08x %08x %08x\n", r[0], r[1], r[2], r[3], r[4], r[5]);
1834 pr_info("Fixed : %06x\n", r[6] >> 8);
1835 pr_info("Match M: %08x %08x %08x %08x %08x %08x\n",
1836 (r[6] << 24) | (r[7] >> 8), (r[7] << 24) | (r[8] >> 8), (r[8] << 24) | (r[9] >> 8),
1837 (r[9] << 24) | (r[10] >> 8), (r[10] << 24) | (r[11] >> 8),
1838 (r[11] << 24) | (r[12] >> 8));
1839 pr_info("R[13]: %08x\n", r[13]);
1840 pr_info("Fixed M: %06x\n", ((r[12] << 16) | (r[13] >> 16)) & 0xffffff);
1841 pr_info("Valid / not / and1 / and2 : %1x\n", (r[13] >> 12) & 0xf);
1842 pr_info("r 13-16: %08x %08x %08x %08x\n", r[13], r[14], r[15], r[16]);
1843 }
1844
1845 static int rtl930x_pie_rule_write(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr)
1846 {
1847 // Access IACL table (2) via register 0
1848 struct table_reg *q = rtl_table_get(RTL9300_TBL_0, 2);
1849 u32 r[19];
1850 int i;
1851 int block = idx / PIE_BLOCK_SIZE;
1852 u32 t_select = sw_r32(RTL930X_PIE_BLK_TMPLTE_CTRL(block));
1853
1854 pr_debug("%s: %d, t_select: %08x\n", __func__, idx, t_select);
1855
1856 for (i = 0; i < 19; i++)
1857 r[i] = 0;
1858
1859 if (!pr->valid) {
1860 rtl_table_write(q, idx);
1861 rtl_table_release(q);
1862 return 0;
1863 }
1864 rtl930x_write_pie_fixed_fields(r, pr);
1865
1866 pr_debug("%s: template %d\n", __func__, (t_select >> (pr->tid * 4)) & 0xf);
1867 rtl930x_write_pie_templated(r, pr, fixed_templates[(t_select >> (pr->tid * 4)) & 0xf]);
1868
1869 rtl930x_write_pie_action(r, pr);
1870
1871 // rtl930x_pie_rule_dump_raw(r);
1872
1873 for (i = 0; i < 19; i++)
1874 sw_w32(r[i], rtl_table_data(q, i));
1875
1876 rtl_table_write(q, idx);
1877 rtl_table_release(q);
1878
1879 return 0;
1880 }
1881
1882 static bool rtl930x_pie_templ_has(int t, enum template_field_id field_type)
1883 {
1884 int i;
1885 enum template_field_id ft;
1886
1887 for (i = 0; i < N_FIXED_FIELDS; i++) {
1888 ft = fixed_templates[t][i];
1889 if (field_type == ft)
1890 return true;
1891 }
1892
1893 return false;
1894 }
1895
1896 /* Verify that the rule pr is compatible with a given template t in block block
1897 * Note that this function is SoC specific since the values of e.g. TEMPLATE_FIELD_SIP0
1898 * depend on the SoC
1899 */
1900 static int rtl930x_pie_verify_template(struct rtl838x_switch_priv *priv,
1901 struct pie_rule *pr, int t, int block)
1902 {
1903 int i;
1904
1905 if (!pr->is_ipv6 && pr->sip_m && !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_SIP0))
1906 return -1;
1907
1908 if (!pr->is_ipv6 && pr->dip_m && !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_DIP0))
1909 return -1;
1910
1911 if (pr->is_ipv6) {
1912 if ((pr->sip6_m.s6_addr32[0] ||
1913 pr->sip6_m.s6_addr32[1] ||
1914 pr->sip6_m.s6_addr32[2] ||
1915 pr->sip6_m.s6_addr32[3]) &&
1916 !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_SIP2))
1917 return -1;
1918 if ((pr->dip6_m.s6_addr32[0] ||
1919 pr->dip6_m.s6_addr32[1] ||
1920 pr->dip6_m.s6_addr32[2] ||
1921 pr->dip6_m.s6_addr32[3]) &&
1922 !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_DIP2))
1923 return -1;
1924 }
1925
1926 if (ether_addr_to_u64(pr->smac) && !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_SMAC0))
1927 return -1;
1928
1929 if (ether_addr_to_u64(pr->dmac) && !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_DMAC0))
1930 return -1;
1931
1932 // TODO: Check more
1933
1934 i = find_first_zero_bit(&priv->pie_use_bm[block * 4], PIE_BLOCK_SIZE);
1935
1936 if (i >= PIE_BLOCK_SIZE)
1937 return -1;
1938
1939 return i + PIE_BLOCK_SIZE * block;
1940 }
1941
1942 static int rtl930x_pie_rule_add(struct rtl838x_switch_priv *priv, struct pie_rule *pr)
1943 {
1944 int idx, block, j, t;
1945 int min_block = 0;
1946 int max_block = priv->n_pie_blocks / 2;
1947
1948 if (pr->is_egress) {
1949 min_block = max_block;
1950 max_block = priv->n_pie_blocks;
1951 }
1952 pr_debug("In %s\n", __func__);
1953
1954 mutex_lock(&priv->pie_mutex);
1955
1956 for (block = min_block; block < max_block; block++) {
1957 for (j = 0; j < 2; j++) {
1958 t = (sw_r32(RTL930X_PIE_BLK_TMPLTE_CTRL(block)) >> (j * 4)) & 0xf;
1959 pr_debug("Testing block %d, template %d, template id %d\n", block, j, t);
1960 pr_debug("%s: %08x\n",
1961 __func__, sw_r32(RTL930X_PIE_BLK_TMPLTE_CTRL(block)));
1962 idx = rtl930x_pie_verify_template(priv, pr, t, block);
1963 if (idx >= 0)
1964 break;
1965 }
1966 if (j < 2)
1967 break;
1968 }
1969
1970 if (block >= priv->n_pie_blocks) {
1971 mutex_unlock(&priv->pie_mutex);
1972 return -EOPNOTSUPP;
1973 }
1974
1975 pr_debug("Using block: %d, index %d, template-id %d\n", block, idx, j);
1976 set_bit(idx, priv->pie_use_bm);
1977
1978 pr->valid = true;
1979 pr->tid = j; // Mapped to template number
1980 pr->tid_m = 0x1;
1981 pr->id = idx;
1982
1983 rtl930x_pie_lookup_enable(priv, idx);
1984 rtl930x_pie_rule_write(priv, idx, pr);
1985
1986 mutex_unlock(&priv->pie_mutex);
1987 return 0;
1988 }
1989
1990 /* Delete a range of Packet Inspection Engine rules */
1991 static int rtl930x_pie_rule_del(struct rtl838x_switch_priv *priv, int index_from, int index_to)
1992 {
1993 u32 v = (index_from << 1)| (index_to << 12 ) | BIT(0);
1994
1995 pr_debug("%s: from %d to %d\n", __func__, index_from, index_to);
1996 mutex_lock(&priv->reg_mutex);
1997
1998 // Write from-to and execute bit into control register
1999 sw_w32(v, RTL930X_PIE_CLR_CTRL);
2000
2001 // Wait until command has completed
2002 do {
2003 } while (sw_r32(RTL930X_PIE_CLR_CTRL) & BIT(0));
2004
2005 mutex_unlock(&priv->reg_mutex);
2006 return 0;
2007 }
2008
2009 static void rtl930x_pie_rule_rm(struct rtl838x_switch_priv *priv, struct pie_rule *pr)
2010 {
2011 int idx = pr->id;
2012
2013 rtl930x_pie_rule_del(priv, idx, idx);
2014 clear_bit(idx, priv->pie_use_bm);
2015 }
2016
2017 static void rtl930x_pie_init(struct rtl838x_switch_priv *priv)
2018 {
2019 int i;
2020 u32 template_selectors;
2021
2022 mutex_init(&priv->pie_mutex);
2023
2024 pr_info("%s\n", __func__);
2025 // Enable ACL lookup on all ports, including CPU_PORT
2026 for (i = 0; i <= priv->cpu_port; i++)
2027 sw_w32(1, RTL930X_ACL_PORT_LOOKUP_CTRL(i));
2028
2029 // Include IPG in metering
2030 sw_w32_mask(0, 1, RTL930X_METER_GLB_CTRL);
2031
2032 // Delete all present rules, block size is 128 on all SoC families
2033 rtl930x_pie_rule_del(priv, 0, priv->n_pie_blocks * 128 - 1);
2034
2035 // Assign blocks 0-7 to VACL phase (bit = 0), blocks 8-15 to IACL (bit = 1)
2036 sw_w32(0xff00, RTL930X_PIE_BLK_PHASE_CTRL);
2037
2038 // Enable predefined templates 0, 1 for first quarter of all blocks
2039 template_selectors = 0 | (1 << 4);
2040 for (i = 0; i < priv->n_pie_blocks / 4; i++)
2041 sw_w32(template_selectors, RTL930X_PIE_BLK_TMPLTE_CTRL(i));
2042
2043 // Enable predefined templates 2, 3 for second quarter of all blocks
2044 template_selectors = 2 | (3 << 4);
2045 for (i = priv->n_pie_blocks / 4; i < priv->n_pie_blocks / 2; i++)
2046 sw_w32(template_selectors, RTL930X_PIE_BLK_TMPLTE_CTRL(i));
2047
2048 // Enable predefined templates 0, 1 for third half of all blocks
2049 template_selectors = 0 | (1 << 4);
2050 for (i = priv->n_pie_blocks / 2; i < priv->n_pie_blocks * 3 / 4; i++)
2051 sw_w32(template_selectors, RTL930X_PIE_BLK_TMPLTE_CTRL(i));
2052
2053 // Enable predefined templates 2, 3 for fourth quater of all blocks
2054 template_selectors = 2 | (3 << 4);
2055 for (i = priv->n_pie_blocks * 3 / 4; i < priv->n_pie_blocks; i++)
2056 sw_w32(template_selectors, RTL930X_PIE_BLK_TMPLTE_CTRL(i));
2057
2058 }
2059
2060 /* Sets up an egress interface for L3 actions
2061 * Actions for ip4/6_icmp_redirect, ip4/6_pbr_icmp_redirect are:
2062 * 0: FORWARD, 1: DROP, 2: TRAP2CPU, 3: COPY2CPU, 4: TRAP2MASTERCPU 5: COPY2MASTERCPU
2063 * 6: HARDDROP
2064 * idx is the index in the HW interface table: idx < 0x80
2065 */
2066 static void rtl930x_set_l3_egress_intf(int idx, struct rtl838x_l3_intf *intf)
2067 {
2068 u32 u, v;
2069 // Read L3_EGR_INTF table (4) via register RTL9300_TBL_1
2070 struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 4);
2071
2072 // The table has 2 registers
2073 u = (intf->vid & 0xfff) << 9;
2074 u |= (intf->smac_idx & 0x3f) << 3;
2075 u |= (intf->ip4_mtu_id & 0x7);
2076
2077 v = (intf->ip6_mtu_id & 0x7) << 28;
2078 v |= (intf->ttl_scope & 0xff) << 20;
2079 v |= (intf->hl_scope & 0xff) << 12;
2080 v |= (intf->ip4_icmp_redirect & 0x7) << 9;
2081 v |= (intf->ip6_icmp_redirect & 0x7)<< 6;
2082 v |= (intf->ip4_pbr_icmp_redirect & 0x7) << 3;
2083 v |= (intf->ip6_pbr_icmp_redirect & 0x7);
2084
2085 sw_w32(u, rtl_table_data(r, 0));
2086 sw_w32(v, rtl_table_data(r, 1));
2087
2088 pr_info("%s writing to index %d: %08x %08x\n", __func__, idx, u, v);
2089 rtl_table_write(r, idx & 0x7f);
2090 rtl_table_release(r);
2091 }
2092
2093 /* Reads a MAC entry for L3 termination as entry point for routing
2094 * from the hardware table
2095 * idx is the index into the L3_ROUTER_MAC table
2096 */
2097 static void rtl930x_get_l3_router_mac(u32 idx, struct rtl93xx_rt_mac *m)
2098 {
2099 u32 v, w;
2100 // Read L3_ROUTER_MAC table (0) via register RTL9300_TBL_1
2101 struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 0);
2102
2103 rtl_table_read(r, idx);
2104 // The table has a size of 7 registers, 64 entries
2105 v = sw_r32(rtl_table_data(r, 0));
2106 w = sw_r32(rtl_table_data(r, 3));
2107 m->valid = !!(v & BIT(20));
2108 if (!m->valid)
2109 goto out;
2110
2111 m->p_type = !!(v & BIT(19));
2112 m->p_id = (v >> 13) & 0x3f; // trunk id of port
2113 m->vid = v & 0xfff;
2114 m->vid_mask = w & 0xfff;
2115 m->action = sw_r32(rtl_table_data(r, 6)) & 0x7;
2116 m->mac_mask = ((((u64)sw_r32(rtl_table_data(r, 5))) << 32) & 0xffffffffffffULL) |
2117 (sw_r32(rtl_table_data(r, 4)));
2118 m->mac = ((((u64)sw_r32(rtl_table_data(r, 1))) << 32) & 0xffffffffffffULL) |
2119 (sw_r32(rtl_table_data(r, 2)));
2120 // Bits L3_INTF and BMSK_L3_INTF are 0
2121
2122 out:
2123 rtl_table_release(r);
2124 }
2125
2126 /* Writes a MAC entry for L3 termination as entry point for routing
2127 * into the hardware table
2128 * idx is the index into the L3_ROUTER_MAC table
2129 */
2130 static void rtl930x_set_l3_router_mac(u32 idx, struct rtl93xx_rt_mac *m)
2131 {
2132 u32 v, w;
2133 // Read L3_ROUTER_MAC table (0) via register RTL9300_TBL_1
2134 struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 0);
2135
2136 // The table has a size of 7 registers, 64 entries
2137 v = BIT(20); // mac entry valid, port type is 0: individual
2138 v |= (m->p_id & 0x3f) << 13;
2139 v |= (m->vid & 0xfff); // Set the interface_id to the vlan id
2140
2141 w = m->vid_mask;
2142 w |= (m->p_id_mask & 0x3f) << 13;
2143
2144 sw_w32(v, rtl_table_data(r, 0));
2145 sw_w32(w, rtl_table_data(r, 3));
2146
2147 // Set MAC address, L3_INTF (bit 12 in register 1) needs to be 0
2148 sw_w32((u32)(m->mac), rtl_table_data(r, 2));
2149 sw_w32(m->mac >> 32, rtl_table_data(r, 1));
2150
2151 // Set MAC address mask, BMSK_L3_INTF (bit 12 in register 5) needs to be 0
2152 sw_w32((u32)(m->mac_mask >> 32), rtl_table_data(r, 4));
2153 sw_w32((u32)m->mac_mask, rtl_table_data(r, 5));
2154
2155 sw_w32(m->action & 0x7, rtl_table_data(r, 6));
2156
2157 pr_debug("%s writing index %d: %08x %08x %08x %08x %08x %08x %08x\n", __func__, idx,
2158 sw_r32(rtl_table_data(r, 0)), sw_r32(rtl_table_data(r, 1)), sw_r32(rtl_table_data(r, 2)),
2159 sw_r32(rtl_table_data(r, 3)), sw_r32(rtl_table_data(r, 4)), sw_r32(rtl_table_data(r, 5)),
2160 sw_r32(rtl_table_data(r, 6))
2161 );
2162 rtl_table_write(r, idx);
2163 rtl_table_release(r);
2164 }
2165
2166 /* Get the Destination-MAC of an L3 egress interface or the Source MAC for routed packets
2167 * from the SoC's L3_EGR_INTF_MAC table
2168 * Indexes 0-2047 are DMACs, 2048+ are SMACs
2169 */
2170 static u64 rtl930x_get_l3_egress_mac(u32 idx)
2171 {
2172 u64 mac;
2173 // Read L3_EGR_INTF_MAC table (2) via register RTL9300_TBL_2
2174 struct table_reg *r = rtl_table_get(RTL9300_TBL_2, 2);
2175
2176 rtl_table_read(r, idx);
2177 // The table has a size of 2 registers
2178 mac = sw_r32(rtl_table_data(r, 0));
2179 mac <<= 32;
2180 mac |= sw_r32(rtl_table_data(r, 1));
2181 rtl_table_release(r);
2182
2183 return mac;
2184 }
2185
2186 /* Set the Destination-MAC of a route or the Source MAC of an L3 egress interface
2187 * in the SoC's L3_EGR_INTF_MAC table
2188 * Indexes 0-2047 are DMACs, 2048+ are SMACs
2189 */
2190 static void rtl930x_set_l3_egress_mac(u32 idx, u64 mac)
2191 {
2192 // Access L3_EGR_INTF_MAC table (2) via register RTL9300_TBL_2
2193 struct table_reg *r = rtl_table_get(RTL9300_TBL_2, 2);
2194
2195 // The table has a size of 2 registers
2196 sw_w32(mac >> 32, rtl_table_data(r, 0));
2197 sw_w32(mac, rtl_table_data(r, 1));
2198
2199 pr_debug("%s: setting index %d to %016llx\n", __func__, idx, mac);
2200 rtl_table_write(r, idx);
2201 rtl_table_release(r);
2202 }
2203
2204 /* Configure L3 routing settings of the device:
2205 * - MTUs
2206 * - Egress interface
2207 * - The router's MAC address on which routed packets are expected
2208 * - MAC addresses used as source macs of routed packets
2209 */
2210 int rtl930x_l3_setup(struct rtl838x_switch_priv *priv)
2211 {
2212 int i;
2213
2214 // Setup MTU with id 0 for default interface
2215 for (i = 0; i < MAX_INTF_MTUS; i++)
2216 priv->intf_mtu_count[i] = priv->intf_mtus[i] = 0;
2217
2218 priv->intf_mtu_count[0] = 0; // Needs to stay forever
2219 priv->intf_mtus[0] = DEFAULT_MTU;
2220 sw_w32_mask(0xffff, DEFAULT_MTU, RTL930X_L3_IP_MTU_CTRL(0));
2221 sw_w32_mask(0xffff, DEFAULT_MTU, RTL930X_L3_IP6_MTU_CTRL(0));
2222 priv->intf_mtus[1] = DEFAULT_MTU;
2223 sw_w32_mask(0xffff0000, DEFAULT_MTU << 16, RTL930X_L3_IP_MTU_CTRL(0));
2224 sw_w32_mask(0xffff0000, DEFAULT_MTU << 16, RTL930X_L3_IP6_MTU_CTRL(0));
2225
2226 sw_w32_mask(0xffff, DEFAULT_MTU, RTL930X_L3_IP_MTU_CTRL(1));
2227 sw_w32_mask(0xffff, DEFAULT_MTU, RTL930X_L3_IP6_MTU_CTRL(1));
2228 sw_w32_mask(0xffff0000, DEFAULT_MTU << 16, RTL930X_L3_IP_MTU_CTRL(1));
2229 sw_w32_mask(0xffff0000, DEFAULT_MTU << 16, RTL930X_L3_IP6_MTU_CTRL(1));
2230
2231 // Clear all source port MACs
2232 for (i = 0; i < MAX_SMACS; i++)
2233 rtl930x_set_l3_egress_mac(L3_EGRESS_DMACS + i, 0ULL);
2234
2235 // Configure the default L3 hash algorithm
2236 sw_w32_mask(BIT(2), 0, RTL930X_L3_HOST_TBL_CTRL); // Algorithm selection 0 = 0
2237 sw_w32_mask(0, BIT(3), RTL930X_L3_HOST_TBL_CTRL); // Algorithm selection 1 = 1
2238
2239 pr_info("L3_IPUC_ROUTE_CTRL %08x, IPMC_ROUTE %08x, IP6UC_ROUTE %08x, IP6MC_ROUTE %08x\n",
2240 sw_r32(RTL930X_L3_IPUC_ROUTE_CTRL), sw_r32(RTL930X_L3_IPMC_ROUTE_CTRL),
2241 sw_r32(RTL930X_L3_IP6UC_ROUTE_CTRL), sw_r32(RTL930X_L3_IP6MC_ROUTE_CTRL));
2242 sw_w32_mask(0, 1, RTL930X_L3_IPUC_ROUTE_CTRL);
2243 sw_w32_mask(0, 1, RTL930X_L3_IP6UC_ROUTE_CTRL);
2244 sw_w32_mask(0, 1, RTL930X_L3_IPMC_ROUTE_CTRL);
2245 sw_w32_mask(0, 1, RTL930X_L3_IP6MC_ROUTE_CTRL);
2246
2247 sw_w32(0x00002001, RTL930X_L3_IPUC_ROUTE_CTRL);
2248 sw_w32(0x00014581, RTL930X_L3_IP6UC_ROUTE_CTRL);
2249 sw_w32(0x00000501, RTL930X_L3_IPMC_ROUTE_CTRL);
2250 sw_w32(0x00012881, RTL930X_L3_IP6MC_ROUTE_CTRL);
2251
2252 pr_info("L3_IPUC_ROUTE_CTRL %08x, IPMC_ROUTE %08x, IP6UC_ROUTE %08x, IP6MC_ROUTE %08x\n",
2253 sw_r32(RTL930X_L3_IPUC_ROUTE_CTRL), sw_r32(RTL930X_L3_IPMC_ROUTE_CTRL),
2254 sw_r32(RTL930X_L3_IP6UC_ROUTE_CTRL), sw_r32(RTL930X_L3_IP6MC_ROUTE_CTRL));
2255
2256 // Trap non-ip traffic to the CPU-port (e.g. ARP so we stay reachable)
2257 sw_w32_mask(0x3 << 8, 0x1 << 8, RTL930X_L3_IP_ROUTE_CTRL);
2258 pr_info("L3_IP_ROUTE_CTRL %08x\n", sw_r32(RTL930X_L3_IP_ROUTE_CTRL));
2259
2260 // PORT_ISO_RESTRICT_ROUTE_CTRL ?
2261
2262 // Do not use prefix route 0 because of HW limitations
2263 set_bit(0, priv->route_use_bm);
2264
2265 return 0;
2266 }
2267
2268 static u32 rtl930x_packet_cntr_read(int counter)
2269 {
2270 u32 v;
2271
2272 // Read LOG table (3) via register RTL9300_TBL_0
2273 struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 3);
2274
2275 pr_debug("In %s, id %d\n", __func__, counter);
2276 rtl_table_read(r, counter / 2);
2277
2278 pr_debug("Registers: %08x %08x\n",
2279 sw_r32(rtl_table_data(r, 0)), sw_r32(rtl_table_data(r, 1)));
2280 // The table has a size of 2 registers
2281 if (counter % 2)
2282 v = sw_r32(rtl_table_data(r, 0));
2283 else
2284 v = sw_r32(rtl_table_data(r, 1));
2285
2286 rtl_table_release(r);
2287
2288 return v;
2289 }
2290
2291 static void rtl930x_packet_cntr_clear(int counter)
2292 {
2293 // Access LOG table (3) via register RTL9300_TBL_0
2294 struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 3);
2295
2296 pr_info("In %s, id %d\n", __func__, counter);
2297 // The table has a size of 2 registers
2298 if (counter % 2)
2299 sw_w32(0, rtl_table_data(r, 0));
2300 else
2301 sw_w32(0, rtl_table_data(r, 1));
2302
2303 rtl_table_write(r, counter / 2);
2304
2305 rtl_table_release(r);
2306 }
2307
2308 void rtl930x_vlan_port_keep_tag_set(int port, bool keep_outer, bool keep_inner)
2309 {
2310 sw_w32(FIELD_PREP(RTL930X_VLAN_PORT_TAG_STS_CTRL_EGR_OTAG_STS_MASK,
2311 keep_outer ? RTL930X_VLAN_PORT_TAG_STS_TAGGED : RTL930X_VLAN_PORT_TAG_STS_UNTAG) |
2312 FIELD_PREP(RTL930X_VLAN_PORT_TAG_STS_CTRL_EGR_ITAG_STS_MASK,
2313 keep_inner ? RTL930X_VLAN_PORT_TAG_STS_TAGGED : RTL930X_VLAN_PORT_TAG_STS_UNTAG),
2314 RTL930X_VLAN_PORT_TAG_STS_CTRL(port));
2315 }
2316
2317 void rtl930x_vlan_port_pvidmode_set(int port, enum pbvlan_type type, enum pbvlan_mode mode)
2318 {
2319 if (type == PBVLAN_TYPE_INNER)
2320 sw_w32_mask(0x3, mode, RTL930X_VLAN_PORT_PB_VLAN + (port << 2));
2321 else
2322 sw_w32_mask(0x3 << 14, mode << 14 ,RTL930X_VLAN_PORT_PB_VLAN + (port << 2));
2323 }
2324
2325 void rtl930x_vlan_port_pvid_set(int port, enum pbvlan_type type, int pvid)
2326 {
2327 if (type == PBVLAN_TYPE_INNER)
2328 sw_w32_mask(0xfff << 2, pvid << 2, RTL930X_VLAN_PORT_PB_VLAN + (port << 2));
2329 else
2330 sw_w32_mask(0xfff << 16, pvid << 16, RTL930X_VLAN_PORT_PB_VLAN + (port << 2));
2331 }
2332
2333 static int rtl930x_set_ageing_time(unsigned long msec)
2334 {
2335 int t = sw_r32(RTL930X_L2_AGE_CTRL);
2336
2337 t &= 0x1FFFFF;
2338 t = (t * 7) / 10;
2339 pr_debug("L2 AGING time: %d sec\n", t);
2340
2341 t = (msec / 100 + 6) / 7;
2342 t = t > 0x1FFFFF ? 0x1FFFFF : t;
2343 sw_w32_mask(0x1FFFFF, t, RTL930X_L2_AGE_CTRL);
2344 pr_debug("Dynamic aging for ports: %x\n", sw_r32(RTL930X_L2_PORT_AGE_CTRL));
2345
2346 return 0;
2347 }
2348
2349 static void rtl930x_set_igr_filter(int port, enum igr_filter state)
2350 {
2351 sw_w32_mask(0x3 << ((port & 0xf)<<1), state << ((port & 0xf)<<1),
2352 RTL930X_VLAN_PORT_IGR_FLTR + (((port >> 4) << 2)));
2353 }
2354
2355 static void rtl930x_set_egr_filter(int port, enum egr_filter state)
2356 {
2357 sw_w32_mask(0x1 << (port % 0x1D), state << (port % 0x1D),
2358 RTL930X_VLAN_PORT_EGR_FLTR + (((port / 29) << 2)));
2359 }
2360
2361 void rtl930x_set_distribution_algorithm(int group, int algoidx, u32 algomsk)
2362 {
2363 u32 l3shift = 0;
2364 u32 newmask = 0;
2365
2366 /* TODO: for now we set algoidx to 0 */
2367 algoidx = 0;
2368 if (algomsk & TRUNK_DISTRIBUTION_ALGO_SIP_BIT) {
2369 l3shift = 4;
2370 newmask |= TRUNK_DISTRIBUTION_ALGO_L3_SIP_BIT;
2371 }
2372 if (algomsk & TRUNK_DISTRIBUTION_ALGO_DIP_BIT) {
2373 l3shift = 4;
2374 newmask |= TRUNK_DISTRIBUTION_ALGO_L3_DIP_BIT;
2375 }
2376 if (algomsk & TRUNK_DISTRIBUTION_ALGO_SRC_L4PORT_BIT) {
2377 l3shift = 4;
2378 newmask |= TRUNK_DISTRIBUTION_ALGO_L3_SRC_L4PORT_BIT;
2379 }
2380 if (algomsk & TRUNK_DISTRIBUTION_ALGO_SRC_L4PORT_BIT) {
2381 l3shift = 4;
2382 newmask |= TRUNK_DISTRIBUTION_ALGO_L3_SRC_L4PORT_BIT;
2383 }
2384
2385 if (l3shift == 4) {
2386 if (algomsk & TRUNK_DISTRIBUTION_ALGO_SMAC_BIT)
2387 newmask |= TRUNK_DISTRIBUTION_ALGO_L3_SMAC_BIT;
2388
2389 if (algomsk & TRUNK_DISTRIBUTION_ALGO_DMAC_BIT)
2390 newmask |= TRUNK_DISTRIBUTION_ALGO_L3_DMAC_BIT;
2391 } else {
2392 if (algomsk & TRUNK_DISTRIBUTION_ALGO_SMAC_BIT)
2393 newmask |= TRUNK_DISTRIBUTION_ALGO_L2_SMAC_BIT;
2394 if (algomsk & TRUNK_DISTRIBUTION_ALGO_DMAC_BIT)
2395 newmask |= TRUNK_DISTRIBUTION_ALGO_L2_DMAC_BIT;
2396 }
2397
2398 sw_w32(newmask << l3shift, RTL930X_TRK_HASH_CTRL + (algoidx << 2));
2399 }
2400
2401 static void rtl930x_led_init(struct rtl838x_switch_priv *priv)
2402 {
2403 int i, pos;
2404 u32 v, pm = 0, set;
2405 u32 setlen;
2406 const __be32 *led_set;
2407 char set_name[9];
2408 struct device_node *node;
2409
2410 pr_info("%s called\n", __func__);
2411 node = of_find_compatible_node(NULL, NULL, "realtek,rtl9300-leds");
2412 if (!node) {
2413 pr_info("%s No compatible LED node found\n", __func__);
2414 return;
2415 }
2416
2417 for (i = 0; i < priv->cpu_port; i++) {
2418 pos = (i << 1) % 32;
2419 sw_w32_mask(0x3 << pos, 0, RTL930X_LED_PORT_FIB_SET_SEL_CTRL(i));
2420 sw_w32_mask(0x3 << pos, 0, RTL930X_LED_PORT_COPR_SET_SEL_CTRL(i));
2421
2422 if (!priv->ports[i].phy)
2423 continue;
2424
2425 v = 0x1;
2426 if (priv->ports[i].is10G)
2427 v = 0x3;
2428 if (priv->ports[i].phy_is_integrated)
2429 v = 0x1;
2430 sw_w32_mask(0x3 << pos, v << pos, RTL930X_LED_PORT_NUM_CTRL(i));
2431
2432 pm |= BIT(i);
2433
2434 set = priv->ports[i].led_set;
2435 sw_w32_mask(0, set << pos, RTL930X_LED_PORT_COPR_SET_SEL_CTRL(i));
2436 sw_w32_mask(0, set << pos, RTL930X_LED_PORT_FIB_SET_SEL_CTRL(i));
2437 }
2438
2439 for (i = 0; i < 4; i++) {
2440 sprintf(set_name, "led_set%d", i);
2441 led_set = of_get_property(node, set_name, &setlen);
2442 if (!led_set || setlen != 16)
2443 break;
2444 v = be32_to_cpup(led_set) << 16 | be32_to_cpup(led_set + 1);
2445 sw_w32(v, RTL930X_LED_SET0_0_CTRL - 4 - i * 8);
2446 v = be32_to_cpup(led_set + 2) << 16 | be32_to_cpup(led_set + 3);
2447 sw_w32(v, RTL930X_LED_SET0_0_CTRL - i * 8);
2448 }
2449
2450 // Set LED mode to serial (0x1)
2451 sw_w32_mask(0x3, 0x1, RTL930X_LED_GLB_CTRL);
2452
2453 // Set port type masks
2454 sw_w32(pm, RTL930X_LED_PORT_COPR_MASK_CTRL);
2455 sw_w32(pm, RTL930X_LED_PORT_FIB_MASK_CTRL);
2456 sw_w32(pm, RTL930X_LED_PORT_COMBO_MASK_CTRL);
2457
2458 for (i = 0; i < 24; i++)
2459 pr_info("%s %08x: %08x\n",__func__, 0xbb00cc00 + i * 4, sw_r32(0xcc00 + i * 4));
2460 }
2461
2462 const struct rtl838x_reg rtl930x_reg = {
2463 .mask_port_reg_be = rtl838x_mask_port_reg,
2464 .set_port_reg_be = rtl838x_set_port_reg,
2465 .get_port_reg_be = rtl838x_get_port_reg,
2466 .mask_port_reg_le = rtl838x_mask_port_reg,
2467 .set_port_reg_le = rtl838x_set_port_reg,
2468 .get_port_reg_le = rtl838x_get_port_reg,
2469 .stat_port_rst = RTL930X_STAT_PORT_RST,
2470 .stat_rst = RTL930X_STAT_RST,
2471 .stat_port_std_mib = RTL930X_STAT_PORT_MIB_CNTR,
2472 .traffic_enable = rtl930x_traffic_enable,
2473 .traffic_disable = rtl930x_traffic_disable,
2474 .traffic_get = rtl930x_traffic_get,
2475 .traffic_set = rtl930x_traffic_set,
2476 .l2_ctrl_0 = RTL930X_L2_CTRL,
2477 .l2_ctrl_1 = RTL930X_L2_AGE_CTRL,
2478 .l2_port_aging_out = RTL930X_L2_PORT_AGE_CTRL,
2479 .set_ageing_time = rtl930x_set_ageing_time,
2480 .smi_poll_ctrl = RTL930X_SMI_POLL_CTRL, // TODO: Difference to RTL9300_SMI_PRVTE_POLLING_CTRL
2481 .l2_tbl_flush_ctrl = RTL930X_L2_TBL_FLUSH_CTRL,
2482 .exec_tbl0_cmd = rtl930x_exec_tbl0_cmd,
2483 .exec_tbl1_cmd = rtl930x_exec_tbl1_cmd,
2484 .tbl_access_data_0 = rtl930x_tbl_access_data_0,
2485 .isr_glb_src = RTL930X_ISR_GLB,
2486 .isr_port_link_sts_chg = RTL930X_ISR_PORT_LINK_STS_CHG,
2487 .imr_port_link_sts_chg = RTL930X_IMR_PORT_LINK_STS_CHG,
2488 .imr_glb = RTL930X_IMR_GLB,
2489 .vlan_tables_read = rtl930x_vlan_tables_read,
2490 .vlan_set_tagged = rtl930x_vlan_set_tagged,
2491 .vlan_set_untagged = rtl930x_vlan_set_untagged,
2492 .vlan_profile_dump = rtl930x_vlan_profile_dump,
2493 .vlan_profile_setup = rtl930x_vlan_profile_setup,
2494 .vlan_fwd_on_inner = rtl930x_vlan_fwd_on_inner,
2495 .set_vlan_igr_filter = rtl930x_set_igr_filter,
2496 .set_vlan_egr_filter = rtl930x_set_egr_filter,
2497 .stp_get = rtl930x_stp_get,
2498 .stp_set = rtl930x_stp_set,
2499 .mac_force_mode_ctrl = rtl930x_mac_force_mode_ctrl,
2500 .mac_port_ctrl = rtl930x_mac_port_ctrl,
2501 .l2_port_new_salrn = rtl930x_l2_port_new_salrn,
2502 .l2_port_new_sa_fwd = rtl930x_l2_port_new_sa_fwd,
2503 .mir_ctrl = RTL930X_MIR_CTRL,
2504 .mir_dpm = RTL930X_MIR_DPM_CTRL,
2505 .mir_spm = RTL930X_MIR_SPM_CTRL,
2506 .mac_link_sts = RTL930X_MAC_LINK_STS,
2507 .mac_link_dup_sts = RTL930X_MAC_LINK_DUP_STS,
2508 .mac_link_spd_sts = rtl930x_mac_link_spd_sts,
2509 .mac_rx_pause_sts = RTL930X_MAC_RX_PAUSE_STS,
2510 .mac_tx_pause_sts = RTL930X_MAC_TX_PAUSE_STS,
2511 .read_l2_entry_using_hash = rtl930x_read_l2_entry_using_hash,
2512 .write_l2_entry_using_hash = rtl930x_write_l2_entry_using_hash,
2513 .read_cam = rtl930x_read_cam,
2514 .write_cam = rtl930x_write_cam,
2515 .vlan_port_keep_tag_set = rtl930x_vlan_port_keep_tag_set,
2516 .vlan_port_pvidmode_set = rtl930x_vlan_port_pvidmode_set,
2517 .vlan_port_pvid_set = rtl930x_vlan_port_pvid_set,
2518 .trk_mbr_ctr = rtl930x_trk_mbr_ctr,
2519 .rma_bpdu_fld_pmask = RTL930X_RMA_BPDU_FLD_PMSK,
2520 .init_eee = rtl930x_init_eee,
2521 .port_eee_set = rtl930x_port_eee_set,
2522 .eee_port_ability = rtl930x_eee_port_ability,
2523 .l2_hash_seed = rtl930x_l2_hash_seed,
2524 .l2_hash_key = rtl930x_l2_hash_key,
2525 .read_mcast_pmask = rtl930x_read_mcast_pmask,
2526 .write_mcast_pmask = rtl930x_write_mcast_pmask,
2527 .pie_init = rtl930x_pie_init,
2528 .pie_rule_write = rtl930x_pie_rule_write,
2529 .pie_rule_add = rtl930x_pie_rule_add,
2530 .pie_rule_rm = rtl930x_pie_rule_rm,
2531 .l2_learning_setup = rtl930x_l2_learning_setup,
2532 .packet_cntr_read = rtl930x_packet_cntr_read,
2533 .packet_cntr_clear = rtl930x_packet_cntr_clear,
2534 .route_read = rtl930x_route_read,
2535 .route_write = rtl930x_route_write,
2536 .host_route_write = rtl930x_host_route_write,
2537 .l3_setup = rtl930x_l3_setup,
2538 .set_l3_nexthop = rtl930x_set_l3_nexthop,
2539 .get_l3_nexthop = rtl930x_get_l3_nexthop,
2540 .get_l3_egress_mac = rtl930x_get_l3_egress_mac,
2541 .set_l3_egress_mac = rtl930x_set_l3_egress_mac,
2542 .find_l3_slot = rtl930x_find_l3_slot,
2543 .route_lookup_hw = rtl930x_route_lookup_hw,
2544 .get_l3_router_mac = rtl930x_get_l3_router_mac,
2545 .set_l3_router_mac = rtl930x_set_l3_router_mac,
2546 .set_l3_egress_intf = rtl930x_set_l3_egress_intf,
2547 .set_distribution_algorithm = rtl930x_set_distribution_algorithm,
2548 .led_init = rtl930x_led_init,
2549 };
Staging tree of Jo-Philipp Wich