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realtek: Add missing headers
[openwrt/staging/nbd.git] / target / linux / realtek / files-5.15 / drivers / net / dsa / rtl83xx / rtl839x.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <asm/mach-rtl838x/mach-rtl83xx.h>
4 #include <linux/etherdevice.h>
5
6 #include "rtl83xx.h"
7
8 #define RTL839X_VLAN_PORT_TAG_STS_UNTAG 0x0
9 #define RTL839X_VLAN_PORT_TAG_STS_TAGGED 0x1
10 #define RTL839X_VLAN_PORT_TAG_STS_PRIORITY_TAGGED 0x2
11
12 #define RTL839X_VLAN_PORT_TAG_STS_CTRL_BASE 0x6828
13 /* port 0-52 */
14 #define RTL839X_VLAN_PORT_TAG_STS_CTRL(port) \
15 RTL839X_VLAN_PORT_TAG_STS_CTRL_BASE + (port << 2)
16 #define RTL839X_VLAN_PORT_TAG_STS_CTRL_OTAG_STS_MASK GENMASK(7,6)
17 #define RTL839X_VLAN_PORT_TAG_STS_CTRL_ITAG_STS_MASK GENMASK(5,4)
18 #define RTL839X_VLAN_PORT_TAG_STS_CTRL_EGR_P_OTAG_KEEP_MASK GENMASK(3,3)
19 #define RTL839X_VLAN_PORT_TAG_STS_CTRL_EGR_P_ITAG_KEEP_MASK GENMASK(2,2)
20 #define RTL839X_VLAN_PORT_TAG_STS_CTRL_IGR_P_OTAG_KEEP_MASK GENMASK(1,1)
21 #define RTL839X_VLAN_PORT_TAG_STS_CTRL_IGR_P_ITAG_KEEP_MASK GENMASK(0,0)
22
23 extern struct mutex smi_lock;
24 extern struct rtl83xx_soc_info soc_info;
25
26 /* Definition of the RTL839X-specific template field IDs as used in the PIE */
27 enum template_field_id {
28 TEMPLATE_FIELD_SPMMASK = 0,
29 TEMPLATE_FIELD_SPM0 = 1, /* Source portmask ports 0-15 */
30 TEMPLATE_FIELD_SPM1 = 2, /* Source portmask ports 16-31 */
31 TEMPLATE_FIELD_SPM2 = 3, /* Source portmask ports 32-47 */
32 TEMPLATE_FIELD_SPM3 = 4, /* Source portmask ports 48-56 */
33 TEMPLATE_FIELD_DMAC0 = 5, /* Destination MAC [15:0] */
34 TEMPLATE_FIELD_DMAC1 = 6, /* Destination MAC [31:16] */
35 TEMPLATE_FIELD_DMAC2 = 7, /* Destination MAC [47:32] */
36 TEMPLATE_FIELD_SMAC0 = 8, /* Source MAC [15:0] */
37 TEMPLATE_FIELD_SMAC1 = 9, /* Source MAC [31:16] */
38 TEMPLATE_FIELD_SMAC2 = 10, /* Source MAC [47:32] */
39 TEMPLATE_FIELD_ETHERTYPE = 11, /* Ethernet frame type field */
40 /* Field-ID 12 is not used */
41 TEMPLATE_FIELD_OTAG = 13,
42 TEMPLATE_FIELD_ITAG = 14,
43 TEMPLATE_FIELD_SIP0 = 15,
44 TEMPLATE_FIELD_SIP1 = 16,
45 TEMPLATE_FIELD_DIP0 = 17,
46 TEMPLATE_FIELD_DIP1 = 18,
47 TEMPLATE_FIELD_IP_TOS_PROTO = 19,
48 TEMPLATE_FIELD_IP_FLAG = 20,
49 TEMPLATE_FIELD_L4_SPORT = 21,
50 TEMPLATE_FIELD_L4_DPORT = 22,
51 TEMPLATE_FIELD_L34_HEADER = 23,
52 TEMPLATE_FIELD_ICMP_IGMP = 24,
53 TEMPLATE_FIELD_VID_RANG0 = 25,
54 TEMPLATE_FIELD_VID_RANG1 = 26,
55 TEMPLATE_FIELD_L4_PORT_RANG = 27,
56 TEMPLATE_FIELD_FIELD_SELECTOR_VALID = 28,
57 TEMPLATE_FIELD_FIELD_SELECTOR_0 = 29,
58 TEMPLATE_FIELD_FIELD_SELECTOR_1 = 30,
59 TEMPLATE_FIELD_FIELD_SELECTOR_2 = 31,
60 TEMPLATE_FIELD_FIELD_SELECTOR_3 = 32,
61 TEMPLATE_FIELD_FIELD_SELECTOR_4 = 33,
62 TEMPLATE_FIELD_FIELD_SELECTOR_5 = 34,
63 TEMPLATE_FIELD_SIP2 = 35,
64 TEMPLATE_FIELD_SIP3 = 36,
65 TEMPLATE_FIELD_SIP4 = 37,
66 TEMPLATE_FIELD_SIP5 = 38,
67 TEMPLATE_FIELD_SIP6 = 39,
68 TEMPLATE_FIELD_SIP7 = 40,
69 TEMPLATE_FIELD_OLABEL = 41,
70 TEMPLATE_FIELD_ILABEL = 42,
71 TEMPLATE_FIELD_OILABEL = 43,
72 TEMPLATE_FIELD_DPMMASK = 44,
73 TEMPLATE_FIELD_DPM0 = 45,
74 TEMPLATE_FIELD_DPM1 = 46,
75 TEMPLATE_FIELD_DPM2 = 47,
76 TEMPLATE_FIELD_DPM3 = 48,
77 TEMPLATE_FIELD_L2DPM0 = 49,
78 TEMPLATE_FIELD_L2DPM1 = 50,
79 TEMPLATE_FIELD_L2DPM2 = 51,
80 TEMPLATE_FIELD_L2DPM3 = 52,
81 TEMPLATE_FIELD_IVLAN = 53,
82 TEMPLATE_FIELD_OVLAN = 54,
83 TEMPLATE_FIELD_FWD_VID = 55,
84 TEMPLATE_FIELD_DIP2 = 56,
85 TEMPLATE_FIELD_DIP3 = 57,
86 TEMPLATE_FIELD_DIP4 = 58,
87 TEMPLATE_FIELD_DIP5 = 59,
88 TEMPLATE_FIELD_DIP6 = 60,
89 TEMPLATE_FIELD_DIP7 = 61,
90 };
91
92 /* Number of fixed templates predefined in the SoC */
93 #define N_FIXED_TEMPLATES 5
94 static enum template_field_id fixed_templates[N_FIXED_TEMPLATES][N_FIXED_FIELDS] =
95 {
96 {
97 TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1, TEMPLATE_FIELD_ITAG,
98 TEMPLATE_FIELD_SMAC0, TEMPLATE_FIELD_SMAC1, TEMPLATE_FIELD_SMAC2,
99 TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2,
100 TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_SPM2, TEMPLATE_FIELD_SPM3
101 }, {
102 TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0,
103 TEMPLATE_FIELD_DIP1,TEMPLATE_FIELD_IP_TOS_PROTO, TEMPLATE_FIELD_L4_SPORT,
104 TEMPLATE_FIELD_L4_DPORT, TEMPLATE_FIELD_ICMP_IGMP, TEMPLATE_FIELD_SPM0,
105 TEMPLATE_FIELD_SPM1, TEMPLATE_FIELD_SPM2, TEMPLATE_FIELD_SPM3
106 }, {
107 TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2,
108 TEMPLATE_FIELD_ITAG, TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_IP_TOS_PROTO,
109 TEMPLATE_FIELD_L4_DPORT, TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_SIP0,
110 TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0, TEMPLATE_FIELD_DIP1
111 }, {
112 TEMPLATE_FIELD_DIP0, TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_DIP2,
113 TEMPLATE_FIELD_DIP3, TEMPLATE_FIELD_DIP4, TEMPLATE_FIELD_DIP5,
114 TEMPLATE_FIELD_DIP6, TEMPLATE_FIELD_DIP7, TEMPLATE_FIELD_L4_DPORT,
115 TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_ICMP_IGMP, TEMPLATE_FIELD_IP_TOS_PROTO
116 }, {
117 TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_SIP2,
118 TEMPLATE_FIELD_SIP3, TEMPLATE_FIELD_SIP4, TEMPLATE_FIELD_SIP5,
119 TEMPLATE_FIELD_SIP6, TEMPLATE_FIELD_SIP7, TEMPLATE_FIELD_SPM0,
120 TEMPLATE_FIELD_SPM1, TEMPLATE_FIELD_SPM2, TEMPLATE_FIELD_SPM3
121 },
122 };
123
124 void rtl839x_print_matrix(void)
125 {
126 volatile u64 *ptr9;
127
128 ptr9 = RTL838X_SW_BASE + RTL839X_PORT_ISO_CTRL(0);
129 for (int i = 0; i < 52; i += 4)
130 pr_debug("> %16llx %16llx %16llx %16llx\n",
131 ptr9[i + 0], ptr9[i + 1], ptr9[i + 2], ptr9[i + 3]);
132 pr_debug("CPU_PORT> %16llx\n", ptr9[52]);
133 }
134
135 static inline int rtl839x_port_iso_ctrl(int p)
136 {
137 return RTL839X_PORT_ISO_CTRL(p);
138 }
139
140 static inline void rtl839x_exec_tbl0_cmd(u32 cmd)
141 {
142 sw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_0);
143 do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_0) & BIT(16));
144 }
145
146 static inline void rtl839x_exec_tbl1_cmd(u32 cmd)
147 {
148 sw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_1);
149 do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_1) & BIT(16));
150 }
151
152 inline void rtl839x_exec_tbl2_cmd(u32 cmd)
153 {
154 sw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_2);
155 do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_2) & (1 << 9));
156 }
157
158 static inline int rtl839x_tbl_access_data_0(int i)
159 {
160 return RTL839X_TBL_ACCESS_DATA_0(i);
161 }
162
163 static void rtl839x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info)
164 {
165 u32 u, v, w;
166 /* Read VLAN table (0) via register 0 */
167 struct table_reg *r = rtl_table_get(RTL8390_TBL_0, 0);
168
169 rtl_table_read(r, vlan);
170 u = sw_r32(rtl_table_data(r, 0));
171 v = sw_r32(rtl_table_data(r, 1));
172 w = sw_r32(rtl_table_data(r, 2));
173 rtl_table_release(r);
174
175 info->tagged_ports = u;
176 info->tagged_ports = (info->tagged_ports << 21) | ((v >> 11) & 0x1fffff);
177 info->profile_id = w >> 30 | ((v & 1) << 2);
178 info->hash_mc_fid = !!(w & BIT(2));
179 info->hash_uc_fid = !!(w & BIT(3));
180 info->fid = (v >> 3) & 0xff;
181
182 /* Read UNTAG table (0) via table register 1 */
183 r = rtl_table_get(RTL8390_TBL_1, 0);
184 rtl_table_read(r, vlan);
185 u = sw_r32(rtl_table_data(r, 0));
186 v = sw_r32(rtl_table_data(r, 1));
187 rtl_table_release(r);
188
189 info->untagged_ports = u;
190 info->untagged_ports = (info->untagged_ports << 21) | ((v >> 11) & 0x1fffff);
191 }
192
193 static void rtl839x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info)
194 {
195 u32 u, v, w;
196 /* Access VLAN table (0) via register 0 */
197 struct table_reg *r = rtl_table_get(RTL8390_TBL_0, 0);
198
199 u = info->tagged_ports >> 21;
200 v = info->tagged_ports << 11;
201 v |= ((u32)info->fid) << 3;
202 v |= info->hash_uc_fid ? BIT(2) : 0;
203 v |= info->hash_mc_fid ? BIT(1) : 0;
204 v |= (info->profile_id & 0x4) ? 1 : 0;
205 w = ((u32)(info->profile_id & 3)) << 30;
206
207 sw_w32(u, rtl_table_data(r, 0));
208 sw_w32(v, rtl_table_data(r, 1));
209 sw_w32(w, rtl_table_data(r, 2));
210
211 rtl_table_write(r, vlan);
212 rtl_table_release(r);
213 }
214
215 static void rtl839x_vlan_set_untagged(u32 vlan, u64 portmask)
216 {
217 u32 u, v;
218
219 /* Access UNTAG table (0) via table register 1 */
220 struct table_reg *r = rtl_table_get(RTL8390_TBL_1, 0);
221
222 u = portmask >> 21;
223 v = portmask << 11;
224
225 sw_w32(u, rtl_table_data(r, 0));
226 sw_w32(v, rtl_table_data(r, 1));
227 rtl_table_write(r, vlan);
228
229 rtl_table_release(r);
230 }
231
232 /* Sets the L2 forwarding to be based on either the inner VLAN tag or the outer */
233 static void rtl839x_vlan_fwd_on_inner(int port, bool is_set)
234 {
235 if (is_set)
236 rtl839x_mask_port_reg_be(BIT_ULL(port), 0ULL, RTL839X_VLAN_PORT_FWD);
237 else
238 rtl839x_mask_port_reg_be(0ULL, BIT_ULL(port), RTL839X_VLAN_PORT_FWD);
239 }
240
241 /* Hash seed is vid (actually rvid) concatenated with the MAC address */
242 static u64 rtl839x_l2_hash_seed(u64 mac, u32 vid)
243 {
244 u64 v = vid;
245
246 v <<= 48;
247 v |= mac;
248
249 return v;
250 }
251
252 /* Applies the same hash algorithm as the one used currently by the ASIC to the seed
253 * and returns a key into the L2 hash table
254 */
255 static u32 rtl839x_l2_hash_key(struct rtl838x_switch_priv *priv, u64 seed)
256 {
257 u32 h1, h2, h;
258
259 if (sw_r32(priv->r->l2_ctrl_0) & 1) {
260 h1 = (u32) (((seed >> 60) & 0x3f) ^ ((seed >> 54) & 0x3f) ^
261 ((seed >> 36) & 0x3f) ^ ((seed >> 30) & 0x3f) ^
262 ((seed >> 12) & 0x3f) ^ ((seed >> 6) & 0x3f));
263 h2 = (u32) (((seed >> 48) & 0x3f) ^ ((seed >> 42) & 0x3f) ^
264 ((seed >> 24) & 0x3f) ^ ((seed >> 18) & 0x3f) ^
265 (seed & 0x3f));
266 h = (h1 << 6) | h2;
267 } else {
268 h = (seed >> 60) ^
269 ((((seed >> 48) & 0x3f) << 6) | ((seed >> 54) & 0x3f)) ^
270 ((seed >> 36) & 0xfff) ^ ((seed >> 24) & 0xfff) ^
271 ((seed >> 12) & 0xfff) ^ (seed & 0xfff);
272 }
273
274 return h;
275 }
276
277 static inline int rtl839x_mac_force_mode_ctrl(int p)
278 {
279 return RTL839X_MAC_FORCE_MODE_CTRL + (p << 2);
280 }
281
282 static inline int rtl839x_mac_port_ctrl(int p)
283 {
284 return RTL839X_MAC_PORT_CTRL(p);
285 }
286
287 static inline int rtl839x_l2_port_new_salrn(int p)
288 {
289 return RTL839X_L2_PORT_NEW_SALRN(p);
290 }
291
292 static inline int rtl839x_l2_port_new_sa_fwd(int p)
293 {
294 return RTL839X_L2_PORT_NEW_SA_FWD(p);
295 }
296
297 static inline int rtl839x_mac_link_spd_sts(int p)
298 {
299 return RTL839X_MAC_LINK_SPD_STS(p);
300 }
301
302 static inline int rtl839x_trk_mbr_ctr(int group)
303 {
304 return RTL839X_TRK_MBR_CTR + (group << 3);
305 }
306
307 static void rtl839x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e)
308 {
309 /* Table contains different entry types, we need to identify the right one:
310 * Check for MC entries, first
311 */
312 e->is_ip_mc = !!(r[2] & BIT(31));
313 e->is_ipv6_mc = !!(r[2] & BIT(30));
314 e->type = L2_INVALID;
315 if (!e->is_ip_mc && !e->is_ipv6_mc) {
316 e->mac[0] = (r[0] >> 12);
317 e->mac[1] = (r[0] >> 4);
318 e->mac[2] = ((r[1] >> 28) | (r[0] << 4));
319 e->mac[3] = (r[1] >> 20);
320 e->mac[4] = (r[1] >> 12);
321 e->mac[5] = (r[1] >> 4);
322
323 e->vid = (r[2] >> 4) & 0xfff;
324 e->rvid = (r[0] >> 20) & 0xfff;
325
326 /* Is it a unicast entry? check multicast bit */
327 if (!(e->mac[0] & 1)) {
328 e->is_static = !!((r[2] >> 18) & 1);
329 e->port = (r[2] >> 24) & 0x3f;
330 e->block_da = !!(r[2] & (1 << 19));
331 e->block_sa = !!(r[2] & (1 << 20));
332 e->suspended = !!(r[2] & (1 << 17));
333 e->next_hop = !!(r[2] & (1 << 16));
334 if (e->next_hop) {
335 pr_debug("Found next hop entry, need to read data\n");
336 e->nh_vlan_target = !!(r[2] & BIT(15));
337 e->nh_route_id = (r[2] >> 4) & 0x1ff;
338 e->vid = e->rvid;
339 }
340 e->age = (r[2] >> 21) & 3;
341 e->valid = true;
342 if (!(r[2] & 0xc0fd0000)) /* Check for valid entry */
343 e->valid = false;
344 else
345 e->type = L2_UNICAST;
346 } else {
347 e->valid = true;
348 e->type = L2_MULTICAST;
349 e->mc_portmask_index = (r[2] >> 6) & 0xfff;
350 e->vid = e->rvid;
351 }
352 } else { /* IPv4 and IPv6 multicast */
353 e->vid = e->rvid = (r[0] << 20) & 0xfff;
354 e->mc_gip = r[1];
355 e->mc_portmask_index = (r[2] >> 6) & 0xfff;
356 }
357 if (e->is_ip_mc) {
358 e->valid = true;
359 e->type = IP4_MULTICAST;
360 }
361 if (e->is_ipv6_mc) {
362 e->valid = true;
363 e->type = IP6_MULTICAST;
364 }
365 /* pr_info("%s: vid %d, rvid: %d\n", __func__, e->vid, e->rvid); */
366 }
367
368 /* Fills the 3 SoC table registers r[] with the information in the rtl838x_l2_entry */
369 static void rtl839x_fill_l2_row(u32 r[], struct rtl838x_l2_entry *e)
370 {
371 if (!e->valid) {
372 r[0] = r[1] = r[2] = 0;
373 return;
374 }
375
376 r[2] = e->is_ip_mc ? BIT(31) : 0;
377 r[2] |= e->is_ipv6_mc ? BIT(30) : 0;
378
379 if (!e->is_ip_mc && !e->is_ipv6_mc) {
380 r[0] = ((u32)e->mac[0]) << 12;
381 r[0] |= ((u32)e->mac[1]) << 4;
382 r[0] |= ((u32)e->mac[2]) >> 4;
383 r[1] = ((u32)e->mac[2]) << 28;
384 r[1] |= ((u32)e->mac[3]) << 20;
385 r[1] |= ((u32)e->mac[4]) << 12;
386 r[1] |= ((u32)e->mac[5]) << 4;
387
388 if (!(e->mac[0] & 1)) { /* Not multicast */
389 r[2] |= e->is_static ? BIT(18) : 0;
390 r[0] |= ((u32)e->rvid) << 20;
391 r[2] |= e->port << 24;
392 r[2] |= e->block_da ? BIT(19) : 0;
393 r[2] |= e->block_sa ? BIT(20) : 0;
394 r[2] |= e->suspended ? BIT(17) : 0;
395 r[2] |= ((u32)e->age) << 21;
396 if (e->next_hop) {
397 r[2] |= BIT(16);
398 r[2] |= e->nh_vlan_target ? BIT(15) : 0;
399 r[2] |= (e->nh_route_id & 0x7ff) << 4;
400 } else {
401 r[2] |= e->vid << 4;
402 }
403 pr_debug("Write L2 NH: %08x %08x %08x\n", r[0], r[1], r[2]);
404 } else { /* L2 Multicast */
405 r[0] |= ((u32)e->rvid) << 20;
406 r[2] |= ((u32)e->mc_portmask_index) << 6;
407 }
408 } else { /* IPv4 or IPv6 MC entry */
409 r[0] = ((u32)e->rvid) << 20;
410 r[1] = e->mc_gip;
411 r[2] |= ((u32)e->mc_portmask_index) << 6;
412 }
413 }
414
415 /* Read an L2 UC or MC entry out of a hash bucket of the L2 forwarding table
416 * hash is the id of the bucket and pos is the position of the entry in that bucket
417 * The data read from the SoC is filled into rtl838x_l2_entry
418 */
419 static u64 rtl839x_read_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e)
420 {
421 u32 r[3];
422 struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 0);
423 u32 idx = (0 << 14) | (hash << 2) | pos; /* Search SRAM, with hash and at pos in bucket */
424
425 rtl_table_read(q, idx);
426 for (int i = 0; i < 3; i++)
427 r[i] = sw_r32(rtl_table_data(q, i));
428
429 rtl_table_release(q);
430
431 rtl839x_fill_l2_entry(r, e);
432 if (!e->valid)
433 return 0;
434
435 return rtl839x_l2_hash_seed(ether_addr_to_u64(&e->mac[0]), e->rvid);
436 }
437
438 static void rtl839x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e)
439 {
440 u32 r[3];
441 struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 0);
442
443 u32 idx = (0 << 14) | (hash << 2) | pos; /* Access SRAM, with hash and at pos in bucket */
444
445 rtl839x_fill_l2_row(r, e);
446
447 for (int i = 0; i < 3; i++)
448 sw_w32(r[i], rtl_table_data(q, i));
449
450 rtl_table_write(q, idx);
451 rtl_table_release(q);
452 }
453
454 static u64 rtl839x_read_cam(int idx, struct rtl838x_l2_entry *e)
455 {
456 u32 r[3];
457 struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 1); /* Access L2 Table 1 */
458
459 rtl_table_read(q, idx);
460 for (int i = 0; i < 3; i++)
461 r[i] = sw_r32(rtl_table_data(q, i));
462
463 rtl_table_release(q);
464
465 rtl839x_fill_l2_entry(r, e);
466 if (!e->valid)
467 return 0;
468
469 pr_debug("Found in CAM: R1 %x R2 %x R3 %x\n", r[0], r[1], r[2]);
470
471 /* Return MAC with concatenated VID ac concatenated ID */
472 return rtl839x_l2_hash_seed(ether_addr_to_u64(&e->mac[0]), e->rvid);
473 }
474
475 static void rtl839x_write_cam(int idx, struct rtl838x_l2_entry *e)
476 {
477 u32 r[3];
478 struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 1); /* Access L2 Table 1 */
479
480 rtl839x_fill_l2_row(r, e);
481
482 for (int i = 0; i < 3; i++)
483 sw_w32(r[i], rtl_table_data(q, i));
484
485 rtl_table_write(q, idx);
486 rtl_table_release(q);
487 }
488
489 static u64 rtl839x_read_mcast_pmask(int idx)
490 {
491 u64 portmask;
492 /* Read MC_PMSK (2) via register RTL8390_TBL_L2 */
493 struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 2);
494
495 rtl_table_read(q, idx);
496 portmask = sw_r32(rtl_table_data(q, 0));
497 portmask <<= 32;
498 portmask |= sw_r32(rtl_table_data(q, 1));
499 portmask >>= 11; /* LSB is bit 11 in data registers */
500 rtl_table_release(q);
501
502 return portmask;
503 }
504
505 static void rtl839x_write_mcast_pmask(int idx, u64 portmask)
506 {
507 /* Access MC_PMSK (2) via register RTL8380_TBL_L2 */
508 struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 2);
509
510 portmask <<= 11; /* LSB is bit 11 in data registers */
511 sw_w32((u32)(portmask >> 32), rtl_table_data(q, 0));
512 sw_w32((u32)((portmask & 0xfffff800)), rtl_table_data(q, 1));
513 rtl_table_write(q, idx);
514 rtl_table_release(q);
515 }
516
517 static void rtl839x_vlan_profile_setup(int profile)
518 {
519 u32 p[2];
520 u32 pmask_id = UNKNOWN_MC_PMASK;
521
522 p[0] = pmask_id; /* Use portmaks 0xfff for unknown IPv6 MC flooding */
523 /* Enable L2 Learning BIT 0, portmask UNKNOWN_MC_PMASK for IP/L2-MC traffic flooding */
524 p[1] = 1 | pmask_id << 1 | pmask_id << 13;
525
526 sw_w32(p[0], RTL839X_VLAN_PROFILE(profile));
527 sw_w32(p[1], RTL839X_VLAN_PROFILE(profile) + 4);
528
529 rtl839x_write_mcast_pmask(UNKNOWN_MC_PMASK, 0x001fffffffffffff);
530 }
531
532 u64 rtl839x_traffic_get(int source)
533 {
534 return rtl839x_get_port_reg_be(rtl839x_port_iso_ctrl(source));
535 }
536
537 void rtl839x_traffic_set(int source, u64 dest_matrix)
538 {
539 rtl839x_set_port_reg_be(dest_matrix, rtl839x_port_iso_ctrl(source));
540 }
541
542 void rtl839x_traffic_enable(int source, int dest)
543 {
544 rtl839x_mask_port_reg_be(0, BIT_ULL(dest), rtl839x_port_iso_ctrl(source));
545 }
546
547 void rtl839x_traffic_disable(int source, int dest)
548 {
549 rtl839x_mask_port_reg_be(BIT_ULL(dest), 0, rtl839x_port_iso_ctrl(source));
550 }
551
552 static void rtl839x_l2_learning_setup(void)
553 {
554 /* Set portmask for broadcast (offset bit 12) and unknown unicast (offset 0)
555 * address flooding to the reserved entry in the portmask table used
556 * also for multicast flooding */
557 sw_w32(UNKNOWN_MC_PMASK << 12 | UNKNOWN_MC_PMASK, RTL839X_L2_FLD_PMSK);
558
559 /* Limit learning to maximum: 32k entries, after that just flood (bits 0-1) */
560 sw_w32((0x7fff << 2) | 0, RTL839X_L2_LRN_CONSTRT);
561
562 /* Do not trap ARP packets to CPU_PORT */
563 sw_w32(0, RTL839X_SPCL_TRAP_ARP_CTRL);
564 }
565
566 static void rtl839x_enable_learning(int port, bool enable)
567 {
568 /* Limit learning to maximum: 32k entries */
569
570 sw_w32_mask(0x7fff << 2, enable ? (0x7fff << 2) : 0,
571 RTL839X_L2_PORT_LRN_CONSTRT + (port << 2));
572 }
573
574 static void rtl839x_enable_flood(int port, bool enable)
575 {
576 /* 0: Forward
577 * 1: Disable
578 * 2: to CPU
579 * 3: Copy to CPU
580 */
581 sw_w32_mask(0x3, enable ? 0 : 1,
582 RTL839X_L2_PORT_LRN_CONSTRT + (port << 2));
583 }
584
585 static void rtl839x_enable_mcast_flood(int port, bool enable)
586 {
587
588 }
589
590 static void rtl839x_enable_bcast_flood(int port, bool enable)
591 {
592
593 }
594
595 static void rtl839x_set_static_move_action(int port, bool forward)
596 {
597 int shift = MV_ACT_PORT_SHIFT(port);
598 u32 val = forward ? MV_ACT_FORWARD : MV_ACT_DROP;
599
600 sw_w32_mask(MV_ACT_MASK << shift, val << shift,
601 RTL839X_L2_PORT_STATIC_MV_ACT(port));
602 }
603
604 irqreturn_t rtl839x_switch_irq(int irq, void *dev_id)
605 {
606 struct dsa_switch *ds = dev_id;
607 u32 status = sw_r32(RTL839X_ISR_GLB_SRC);
608 u64 ports = rtl839x_get_port_reg_le(RTL839X_ISR_PORT_LINK_STS_CHG);
609 u64 link;
610
611 /* Clear status */
612 rtl839x_set_port_reg_le(ports, RTL839X_ISR_PORT_LINK_STS_CHG);
613 pr_debug("RTL8390 Link change: status: %x, ports %llx\n", status, ports);
614
615 for (int i = 0; i < RTL839X_CPU_PORT; i++) {
616 if (ports & BIT_ULL(i)) {
617 link = rtl839x_get_port_reg_le(RTL839X_MAC_LINK_STS);
618 if (link & BIT_ULL(i))
619 dsa_port_phylink_mac_change(ds, i, true);
620 else
621 dsa_port_phylink_mac_change(ds, i, false);
622 }
623 }
624
625 return IRQ_HANDLED;
626 }
627
628 /* TODO: unused */
629 int rtl8390_sds_power(int mac, int val)
630 {
631 u32 offset = (mac == 48) ? 0x0 : 0x100;
632 u32 mode = val ? 0 : 1;
633
634 pr_debug("In %s: mac %d, set %d\n", __func__, mac, val);
635
636 if ((mac != 48) && (mac != 49)) {
637 pr_err("%s: not an SFP port: %d\n", __func__, mac);
638 return -1;
639 }
640
641 /* Set bit 1003. 1000 starts at 7c */
642 sw_w32_mask(BIT(11), mode << 11, RTL839X_SDS12_13_PWR0 + offset);
643
644 return 0;
645 }
646
647 static int rtl839x_smi_wait_op(int timeout)
648 {
649 int ret = 0;
650 u32 val;
651
652 ret = readx_poll_timeout(sw_r32, RTL839X_PHYREG_ACCESS_CTRL,
653 val, !(val & 0x1), 20, timeout);
654 if (ret)
655 pr_err("%s: timeout\n", __func__);
656
657 return ret;
658 }
659
660 int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val)
661 {
662 u32 v;
663 int err = 0;
664
665 if (port > 63 || page > 4095 || reg > 31)
666 return -ENOTSUPP;
667
668 /* Take bug on RTL839x Rev <= C into account */
669 if (port >= RTL839X_CPU_PORT)
670 return -EIO;
671
672 mutex_lock(&smi_lock);
673
674 sw_w32_mask(0xffff0000, port << 16, RTL839X_PHYREG_DATA_CTRL);
675 v = reg << 5 | page << 10 | ((page == 0x1fff) ? 0x1f : 0) << 23;
676 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
677
678 sw_w32(0x1ff, RTL839X_PHYREG_CTRL);
679
680 v |= 1;
681 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
682
683 err = rtl839x_smi_wait_op(100000);
684 if (err)
685 goto errout;
686
687 *val = sw_r32(RTL839X_PHYREG_DATA_CTRL) & 0xffff;
688
689 errout:
690 mutex_unlock(&smi_lock);
691
692 return err;
693 }
694
695 int rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val)
696 {
697 u32 v;
698 int err = 0;
699
700 val &= 0xffff;
701 if (port > 63 || page > 4095 || reg > 31)
702 return -ENOTSUPP;
703
704 /* Take bug on RTL839x Rev <= C into account */
705 if (port >= RTL839X_CPU_PORT)
706 return -EIO;
707
708 mutex_lock(&smi_lock);
709
710 /* Set PHY to access */
711 rtl839x_set_port_reg_le(BIT_ULL(port), RTL839X_PHYREG_PORT_CTRL);
712
713 sw_w32_mask(0xffff0000, val << 16, RTL839X_PHYREG_DATA_CTRL);
714
715 v = reg << 5 | page << 10 | ((page == 0x1fff) ? 0x1f : 0) << 23;
716 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
717
718 sw_w32(0x1ff, RTL839X_PHYREG_CTRL);
719
720 v |= BIT(3) | 1; /* Write operation and execute */
721 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
722
723 err = rtl839x_smi_wait_op(100000);
724 if (err)
725 goto errout;
726
727 if (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x2)
728 err = -EIO;
729
730 errout:
731 mutex_unlock(&smi_lock);
732
733 return err;
734 }
735
736 /* Read an mmd register of the PHY */
737 int rtl839x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val)
738 {
739 int err = 0;
740 u32 v;
741
742 /* Take bug on RTL839x Rev <= C into account */
743 if (port >= RTL839X_CPU_PORT)
744 return -EIO;
745
746 mutex_lock(&smi_lock);
747
748 /* Set PHY to access */
749 sw_w32_mask(0xffff << 16, port << 16, RTL839X_PHYREG_DATA_CTRL);
750
751 /* Set MMD device number and register to write to */
752 sw_w32(devnum << 16 | (regnum & 0xffff), RTL839X_PHYREG_MMD_CTRL);
753
754 v = BIT(2) | BIT(0); /* MMD-access | EXEC */
755 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
756
757 err = rtl839x_smi_wait_op(100000);
758 if (err)
759 goto errout;
760
761 /* There is no error-checking via BIT 1 of v, as it does not seem to be set correctly */
762 *val = (sw_r32(RTL839X_PHYREG_DATA_CTRL) & 0xffff);
763 pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__, port, regnum, *val, err);
764
765 errout:
766 mutex_unlock(&smi_lock);
767
768 return err;
769 }
770
771 /* Write to an mmd register of the PHY */
772 int rtl839x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val)
773 {
774 int err = 0;
775 u32 v;
776
777 /* Take bug on RTL839x Rev <= C into account */
778 if (port >= RTL839X_CPU_PORT)
779 return -EIO;
780
781 mutex_lock(&smi_lock);
782
783 /* Set PHY to access */
784 rtl839x_set_port_reg_le(BIT_ULL(port), RTL839X_PHYREG_PORT_CTRL);
785
786 /* Set data to write */
787 sw_w32_mask(0xffff << 16, val << 16, RTL839X_PHYREG_DATA_CTRL);
788
789 /* Set MMD device number and register to write to */
790 sw_w32(devnum << 16 | (regnum & 0xffff), RTL839X_PHYREG_MMD_CTRL);
791
792 v = BIT(3) | BIT(2) | BIT(0); /* WRITE | MMD-access | EXEC */
793 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
794
795 err = rtl839x_smi_wait_op(100000);
796 if (err)
797 goto errout;
798
799 pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__, port, regnum, val, err);
800
801 errout:
802 mutex_unlock(&smi_lock);
803
804 return err;
805 }
806
807 void rtl8390_get_version(struct rtl838x_switch_priv *priv)
808 {
809 u32 info, model;
810
811 sw_w32_mask(0xf << 28, 0xa << 28, RTL839X_CHIP_INFO);
812 info = sw_r32(RTL839X_CHIP_INFO);
813
814 model = sw_r32(RTL839X_MODEL_NAME_INFO);
815 priv->version = RTL8390_VERSION_A + ((model & 0x3f) >> 1);
816
817 pr_info("RTL839X Chip-Info: %x, version %c\n", info, priv->version);
818 }
819
820 void rtl839x_vlan_profile_dump(int profile)
821 {
822 u32 p[2];
823
824 if (profile < 0 || profile > 7)
825 return;
826
827 p[0] = sw_r32(RTL839X_VLAN_PROFILE(profile));
828 p[1] = sw_r32(RTL839X_VLAN_PROFILE(profile) + 4);
829
830 pr_info("VLAN profile %d: L2 learning: %d, UNKN L2MC FLD PMSK %d, \
831 UNKN IPMC FLD PMSK %d, UNKN IPv6MC FLD PMSK: %d",
832 profile, p[1] & 1, (p[1] >> 1) & 0xfff, (p[1] >> 13) & 0xfff,
833 (p[0]) & 0xfff);
834 pr_info("VLAN profile %d: raw %08x, %08x\n", profile, p[0], p[1]);
835 }
836
837 static void rtl839x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
838 {
839 u32 cmd = 1 << 16 | /* Execute cmd */
840 0 << 15 | /* Read */
841 5 << 12 | /* Table type 0b101 */
842 (msti & 0xfff);
843 priv->r->exec_tbl0_cmd(cmd);
844
845 for (int i = 0; i < 4; i++)
846 port_state[i] = sw_r32(priv->r->tbl_access_data_0(i));
847 }
848
849 static void rtl839x_stp_set(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
850 {
851 u32 cmd = 1 << 16 | /* Execute cmd */
852 1 << 15 | /* Write */
853 5 << 12 | /* Table type 0b101 */
854 (msti & 0xfff);
855 for (int i = 0; i < 4; i++)
856 sw_w32(port_state[i], priv->r->tbl_access_data_0(i));
857 priv->r->exec_tbl0_cmd(cmd);
858 }
859
860 /* Enables or disables the EEE/EEEP capability of a port */
861 void rtl839x_port_eee_set(struct rtl838x_switch_priv *priv, int port, bool enable)
862 {
863 u32 v;
864
865 /* This works only for Ethernet ports, and on the RTL839X, ports above 47 are SFP */
866 if (port >= 48)
867 return;
868
869 enable = true;
870 pr_debug("In %s: setting port %d to %d\n", __func__, port, enable);
871 v = enable ? 0xf : 0x0;
872
873 /* Set EEE for 100, 500, 1000MBit and 10GBit */
874 sw_w32_mask(0xf << 8, v << 8, rtl839x_mac_force_mode_ctrl(port));
875
876 /* Set TX/RX EEE state */
877 v = enable ? 0x3 : 0x0;
878 sw_w32(v, RTL839X_EEE_CTRL(port));
879
880 priv->ports[port].eee_enabled = enable;
881 }
882
883 /* Get EEE own capabilities and negotiation result */
884 int rtl839x_eee_port_ability(struct rtl838x_switch_priv *priv, struct ethtool_eee *e, int port)
885 {
886 u64 link, a;
887
888 if (port >= 48)
889 return 0;
890
891 link = rtl839x_get_port_reg_le(RTL839X_MAC_LINK_STS);
892 if (!(link & BIT_ULL(port)))
893 return 0;
894
895 if (sw_r32(rtl839x_mac_force_mode_ctrl(port)) & BIT(8))
896 e->advertised |= ADVERTISED_100baseT_Full;
897
898 if (sw_r32(rtl839x_mac_force_mode_ctrl(port)) & BIT(10))
899 e->advertised |= ADVERTISED_1000baseT_Full;
900
901 a = rtl839x_get_port_reg_le(RTL839X_MAC_EEE_ABLTY);
902 pr_info("Link partner: %016llx\n", a);
903 if (rtl839x_get_port_reg_le(RTL839X_MAC_EEE_ABLTY) & BIT_ULL(port)) {
904 e->lp_advertised = ADVERTISED_100baseT_Full;
905 e->lp_advertised |= ADVERTISED_1000baseT_Full;
906 return 1;
907 }
908
909 return 0;
910 }
911
912 static void rtl839x_init_eee(struct rtl838x_switch_priv *priv, bool enable)
913 {
914 pr_info("Setting up EEE, state: %d\n", enable);
915
916 /* Set wake timer for TX and pause timer both to 0x21 */
917 sw_w32_mask(0xff << 20| 0xff, 0x21 << 20| 0x21, RTL839X_EEE_TX_TIMER_GELITE_CTRL);
918 /* Set pause wake timer for GIGA-EEE to 0x11 */
919 sw_w32_mask(0xff << 20, 0x11 << 20, RTL839X_EEE_TX_TIMER_GIGA_CTRL);
920 /* Set pause wake timer for 10GBit ports to 0x11 */
921 sw_w32_mask(0xff << 20, 0x11 << 20, RTL839X_EEE_TX_TIMER_10G_CTRL);
922
923 /* Setup EEE on all ports */
924 for (int i = 0; i < priv->cpu_port; i++) {
925 if (priv->ports[i].phy)
926 rtl839x_port_eee_set(priv, i, enable);
927 }
928 priv->eee_enabled = enable;
929 }
930
931 static void rtl839x_pie_lookup_enable(struct rtl838x_switch_priv *priv, int index)
932 {
933 int block = index / PIE_BLOCK_SIZE;
934
935 sw_w32_mask(0, BIT(block), RTL839X_ACL_BLK_LOOKUP_CTRL);
936 }
937
938 /* Delete a range of Packet Inspection Engine rules */
939 static int rtl839x_pie_rule_del(struct rtl838x_switch_priv *priv, int index_from, int index_to)
940 {
941 u32 v = (index_from << 1)| (index_to << 13 ) | BIT(0);
942
943 pr_debug("%s: from %d to %d\n", __func__, index_from, index_to);
944 mutex_lock(&priv->reg_mutex);
945
946 /* Write from-to and execute bit into control register */
947 sw_w32(v, RTL839X_ACL_CLR_CTRL);
948
949 /* Wait until command has completed */
950 do {
951 } while (sw_r32(RTL839X_ACL_CLR_CTRL) & BIT(0));
952
953 mutex_unlock(&priv->reg_mutex);
954
955 return 0;
956 }
957
958 /* Reads the intermediate representation of the templated match-fields of the
959 * PIE rule in the pie_rule structure and fills in the raw data fields in the
960 * raw register space r[].
961 * The register space configuration size is identical for the RTL8380/90 and RTL9300,
962 * however the RTL9310 has 2 more registers / fields and the physical field-ids are different
963 * on all SoCs
964 * On the RTL8390 the template mask registers are not word-aligned!
965 */
966 static void rtl839x_write_pie_templated(u32 r[], struct pie_rule *pr, enum template_field_id t[])
967 {
968 for (int i = 0; i < N_FIXED_FIELDS; i++) {
969 enum template_field_id field_type = t[i];
970 u16 data = 0, data_m = 0;
971
972 switch (field_type) {
973 case TEMPLATE_FIELD_SPM0:
974 data = pr->spm;
975 data_m = pr->spm_m;
976 break;
977 case TEMPLATE_FIELD_SPM1:
978 data = pr->spm >> 16;
979 data_m = pr->spm_m >> 16;
980 break;
981 case TEMPLATE_FIELD_SPM2:
982 data = pr->spm >> 32;
983 data_m = pr->spm_m >> 32;
984 break;
985 case TEMPLATE_FIELD_SPM3:
986 data = pr->spm >> 48;
987 data_m = pr->spm_m >> 48;
988 break;
989 case TEMPLATE_FIELD_OTAG:
990 data = pr->otag;
991 data_m = pr->otag_m;
992 break;
993 case TEMPLATE_FIELD_SMAC0:
994 data = pr->smac[4];
995 data = (data << 8) | pr->smac[5];
996 data_m = pr->smac_m[4];
997 data_m = (data_m << 8) | pr->smac_m[5];
998 break;
999 case TEMPLATE_FIELD_SMAC1:
1000 data = pr->smac[2];
1001 data = (data << 8) | pr->smac[3];
1002 data_m = pr->smac_m[2];
1003 data_m = (data_m << 8) | pr->smac_m[3];
1004 break;
1005 case TEMPLATE_FIELD_SMAC2:
1006 data = pr->smac[0];
1007 data = (data << 8) | pr->smac[1];
1008 data_m = pr->smac_m[0];
1009 data_m = (data_m << 8) | pr->smac_m[1];
1010 break;
1011 case TEMPLATE_FIELD_DMAC0:
1012 data = pr->dmac[4];
1013 data = (data << 8) | pr->dmac[5];
1014 data_m = pr->dmac_m[4];
1015 data_m = (data_m << 8) | pr->dmac_m[5];
1016 break;
1017 case TEMPLATE_FIELD_DMAC1:
1018 data = pr->dmac[2];
1019 data = (data << 8) | pr->dmac[3];
1020 data_m = pr->dmac_m[2];
1021 data_m = (data_m << 8) | pr->dmac_m[3];
1022 break;
1023 case TEMPLATE_FIELD_DMAC2:
1024 data = pr->dmac[0];
1025 data = (data << 8) | pr->dmac[1];
1026 data_m = pr->dmac_m[0];
1027 data_m = (data_m << 8) | pr->dmac_m[1];
1028 break;
1029 case TEMPLATE_FIELD_ETHERTYPE:
1030 data = pr->ethertype;
1031 data_m = pr->ethertype_m;
1032 break;
1033 case TEMPLATE_FIELD_ITAG:
1034 data = pr->itag;
1035 data_m = pr->itag_m;
1036 break;
1037 case TEMPLATE_FIELD_SIP0:
1038 if (pr->is_ipv6) {
1039 data = pr->sip6.s6_addr16[7];
1040 data_m = pr->sip6_m.s6_addr16[7];
1041 } else {
1042 data = pr->sip;
1043 data_m = pr->sip_m;
1044 }
1045 break;
1046 case TEMPLATE_FIELD_SIP1:
1047 if (pr->is_ipv6) {
1048 data = pr->sip6.s6_addr16[6];
1049 data_m = pr->sip6_m.s6_addr16[6];
1050 } else {
1051 data = pr->sip >> 16;
1052 data_m = pr->sip_m >> 16;
1053 }
1054 break;
1055 case TEMPLATE_FIELD_SIP2:
1056 case TEMPLATE_FIELD_SIP3:
1057 case TEMPLATE_FIELD_SIP4:
1058 case TEMPLATE_FIELD_SIP5:
1059 case TEMPLATE_FIELD_SIP6:
1060 case TEMPLATE_FIELD_SIP7:
1061 data = pr->sip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)];
1062 data_m = pr->sip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)];
1063 break;
1064 case TEMPLATE_FIELD_DIP0:
1065 if (pr->is_ipv6) {
1066 data = pr->dip6.s6_addr16[7];
1067 data_m = pr->dip6_m.s6_addr16[7];
1068 } else {
1069 data = pr->dip;
1070 data_m = pr->dip_m;
1071 }
1072 break;
1073 case TEMPLATE_FIELD_DIP1:
1074 if (pr->is_ipv6) {
1075 data = pr->dip6.s6_addr16[6];
1076 data_m = pr->dip6_m.s6_addr16[6];
1077 } else {
1078 data = pr->dip >> 16;
1079 data_m = pr->dip_m >> 16;
1080 }
1081 break;
1082 case TEMPLATE_FIELD_DIP2:
1083 case TEMPLATE_FIELD_DIP3:
1084 case TEMPLATE_FIELD_DIP4:
1085 case TEMPLATE_FIELD_DIP5:
1086 case TEMPLATE_FIELD_DIP6:
1087 case TEMPLATE_FIELD_DIP7:
1088 data = pr->dip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)];
1089 data_m = pr->dip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)];
1090 break;
1091 case TEMPLATE_FIELD_IP_TOS_PROTO:
1092 data = pr->tos_proto;
1093 data_m = pr->tos_proto_m;
1094 break;
1095 case TEMPLATE_FIELD_L4_SPORT:
1096 data = pr->sport;
1097 data_m = pr->sport_m;
1098 break;
1099 case TEMPLATE_FIELD_L4_DPORT:
1100 data = pr->dport;
1101 data_m = pr->dport_m;
1102 break;
1103 case TEMPLATE_FIELD_ICMP_IGMP:
1104 data = pr->icmp_igmp;
1105 data_m = pr->icmp_igmp_m;
1106 break;
1107 default:
1108 pr_info("%s: unknown field %d\n", __func__, field_type);
1109 }
1110
1111 /* On the RTL8390, the mask fields are not word aligned! */
1112 if (!(i % 2)) {
1113 r[5 - i / 2] = data;
1114 r[12 - i / 2] |= ((u32)data_m << 8);
1115 } else {
1116 r[5 - i / 2] |= ((u32)data) << 16;
1117 r[12 - i / 2] |= ((u32)data_m) << 24;
1118 r[11 - i / 2] |= ((u32)data_m) >> 8;
1119 }
1120 }
1121 }
1122
1123 /* Creates the intermediate representation of the templated match-fields of the
1124 * PIE rule in the pie_rule structure by reading the raw data fields in the
1125 * raw register space r[].
1126 * The register space configuration size is identical for the RTL8380/90 and RTL9300,
1127 * however the RTL9310 has 2 more registers / fields and the physical field-ids
1128 * On the RTL8390 the template mask registers are not word-aligned!
1129 */
1130 void rtl839x_read_pie_templated(u32 r[], struct pie_rule *pr, enum template_field_id t[])
1131 {
1132 for (int i = 0; i < N_FIXED_FIELDS; i++) {
1133 enum template_field_id field_type = t[i];
1134 u16 data, data_m;
1135
1136 if (!(i % 2)) {
1137 data = r[5 - i / 2];
1138 data_m = r[12 - i / 2];
1139 } else {
1140 data = r[5 - i / 2] >> 16;
1141 data_m = r[12 - i / 2] >> 16;
1142 }
1143
1144 switch (field_type) {
1145 case TEMPLATE_FIELD_SPM0:
1146 pr->spm = (pr->spn << 16) | data;
1147 pr->spm_m = (pr->spn << 16) | data_m;
1148 break;
1149 case TEMPLATE_FIELD_SPM1:
1150 pr->spm = data;
1151 pr->spm_m = data_m;
1152 break;
1153 case TEMPLATE_FIELD_OTAG:
1154 pr->otag = data;
1155 pr->otag_m = data_m;
1156 break;
1157 case TEMPLATE_FIELD_SMAC0:
1158 pr->smac[4] = data >> 8;
1159 pr->smac[5] = data;
1160 pr->smac_m[4] = data >> 8;
1161 pr->smac_m[5] = data;
1162 break;
1163 case TEMPLATE_FIELD_SMAC1:
1164 pr->smac[2] = data >> 8;
1165 pr->smac[3] = data;
1166 pr->smac_m[2] = data >> 8;
1167 pr->smac_m[3] = data;
1168 break;
1169 case TEMPLATE_FIELD_SMAC2:
1170 pr->smac[0] = data >> 8;
1171 pr->smac[1] = data;
1172 pr->smac_m[0] = data >> 8;
1173 pr->smac_m[1] = data;
1174 break;
1175 case TEMPLATE_FIELD_DMAC0:
1176 pr->dmac[4] = data >> 8;
1177 pr->dmac[5] = data;
1178 pr->dmac_m[4] = data >> 8;
1179 pr->dmac_m[5] = data;
1180 break;
1181 case TEMPLATE_FIELD_DMAC1:
1182 pr->dmac[2] = data >> 8;
1183 pr->dmac[3] = data;
1184 pr->dmac_m[2] = data >> 8;
1185 pr->dmac_m[3] = data;
1186 break;
1187 case TEMPLATE_FIELD_DMAC2:
1188 pr->dmac[0] = data >> 8;
1189 pr->dmac[1] = data;
1190 pr->dmac_m[0] = data >> 8;
1191 pr->dmac_m[1] = data;
1192 break;
1193 case TEMPLATE_FIELD_ETHERTYPE:
1194 pr->ethertype = data;
1195 pr->ethertype_m = data_m;
1196 break;
1197 case TEMPLATE_FIELD_ITAG:
1198 pr->itag = data;
1199 pr->itag_m = data_m;
1200 break;
1201 case TEMPLATE_FIELD_SIP0:
1202 pr->sip = data;
1203 pr->sip_m = data_m;
1204 break;
1205 case TEMPLATE_FIELD_SIP1:
1206 pr->sip = (pr->sip << 16) | data;
1207 pr->sip_m = (pr->sip << 16) | data_m;
1208 break;
1209 case TEMPLATE_FIELD_SIP2:
1210 pr->is_ipv6 = true;
1211 /* Make use of limitiations on the position of the match values */
1212 ipv6_addr_set(&pr->sip6, pr->sip, r[5 - i / 2],
1213 r[4 - i / 2], r[3 - i / 2]);
1214 ipv6_addr_set(&pr->sip6_m, pr->sip_m, r[5 - i / 2],
1215 r[4 - i / 2], r[3 - i / 2]);
1216 case TEMPLATE_FIELD_SIP3:
1217 case TEMPLATE_FIELD_SIP4:
1218 case TEMPLATE_FIELD_SIP5:
1219 case TEMPLATE_FIELD_SIP6:
1220 case TEMPLATE_FIELD_SIP7:
1221 break;
1222
1223 case TEMPLATE_FIELD_DIP0:
1224 pr->dip = data;
1225 pr->dip_m = data_m;
1226 break;
1227
1228 case TEMPLATE_FIELD_DIP1:
1229 pr->dip = (pr->dip << 16) | data;
1230 pr->dip_m = (pr->dip << 16) | data_m;
1231 break;
1232
1233 case TEMPLATE_FIELD_DIP2:
1234 pr->is_ipv6 = true;
1235 ipv6_addr_set(&pr->dip6, pr->dip, r[5 - i / 2],
1236 r[4 - i / 2], r[3 - i / 2]);
1237 ipv6_addr_set(&pr->dip6_m, pr->dip_m, r[5 - i / 2],
1238 r[4 - i / 2], r[3 - i / 2]);
1239 case TEMPLATE_FIELD_DIP3:
1240 case TEMPLATE_FIELD_DIP4:
1241 case TEMPLATE_FIELD_DIP5:
1242 case TEMPLATE_FIELD_DIP6:
1243 case TEMPLATE_FIELD_DIP7:
1244 break;
1245 case TEMPLATE_FIELD_IP_TOS_PROTO:
1246 pr->tos_proto = data;
1247 pr->tos_proto_m = data_m;
1248 break;
1249 case TEMPLATE_FIELD_L4_SPORT:
1250 pr->sport = data;
1251 pr->sport_m = data_m;
1252 break;
1253 case TEMPLATE_FIELD_L4_DPORT:
1254 pr->dport = data;
1255 pr->dport_m = data_m;
1256 break;
1257 case TEMPLATE_FIELD_ICMP_IGMP:
1258 pr->icmp_igmp = data;
1259 pr->icmp_igmp_m = data_m;
1260 break;
1261 default:
1262 pr_info("%s: unknown field %d\n", __func__, field_type);
1263 }
1264 }
1265 }
1266
1267 static void rtl839x_read_pie_fixed_fields(u32 r[], struct pie_rule *pr)
1268 {
1269 pr->spmmask_fix = (r[6] >> 30) & 0x3;
1270 pr->spn = (r[6] >> 24) & 0x3f;
1271 pr->mgnt_vlan = (r[6] >> 23) & 1;
1272 pr->dmac_hit_sw = (r[6] >> 22) & 1;
1273 pr->not_first_frag = (r[6] >> 21) & 1;
1274 pr->frame_type_l4 = (r[6] >> 18) & 7;
1275 pr->frame_type = (r[6] >> 16) & 3;
1276 pr->otag_fmt = (r[6] >> 15) & 1;
1277 pr->itag_fmt = (r[6] >> 14) & 1;
1278 pr->otag_exist = (r[6] >> 13) & 1;
1279 pr->itag_exist = (r[6] >> 12) & 1;
1280 pr->frame_type_l2 = (r[6] >> 10) & 3;
1281 pr->tid = (r[6] >> 8) & 3;
1282
1283 pr->spmmask_fix_m = (r[12] >> 6) & 0x3;
1284 pr->spn_m = r[12] & 0x3f;
1285 pr->mgnt_vlan_m = (r[13] >> 31) & 1;
1286 pr->dmac_hit_sw_m = (r[13] >> 30) & 1;
1287 pr->not_first_frag_m = (r[13] >> 29) & 1;
1288 pr->frame_type_l4_m = (r[13] >> 26) & 7;
1289 pr->frame_type_m = (r[13] >> 24) & 3;
1290 pr->otag_fmt_m = (r[13] >> 23) & 1;
1291 pr->itag_fmt_m = (r[13] >> 22) & 1;
1292 pr->otag_exist_m = (r[13] >> 21) & 1;
1293 pr->itag_exist_m = (r[13] >> 20) & 1;
1294 pr->frame_type_l2_m = (r[13] >> 18) & 3;
1295 pr->tid_m = (r[13] >> 16) & 3;
1296
1297 pr->valid = r[13] & BIT(15);
1298 pr->cond_not = r[13] & BIT(14);
1299 pr->cond_and1 = r[13] & BIT(13);
1300 pr->cond_and2 = r[13] & BIT(12);
1301 }
1302
1303 static void rtl839x_write_pie_fixed_fields(u32 r[], struct pie_rule *pr)
1304 {
1305 r[6] = ((u32) (pr->spmmask_fix & 0x3)) << 30;
1306 r[6] |= ((u32) (pr->spn & 0x3f)) << 24;
1307 r[6] |= pr->mgnt_vlan ? BIT(23) : 0;
1308 r[6] |= pr->dmac_hit_sw ? BIT(22) : 0;
1309 r[6] |= pr->not_first_frag ? BIT(21) : 0;
1310 r[6] |= ((u32) (pr->frame_type_l4 & 0x7)) << 18;
1311 r[6] |= ((u32) (pr->frame_type & 0x3)) << 16;
1312 r[6] |= pr->otag_fmt ? BIT(15) : 0;
1313 r[6] |= pr->itag_fmt ? BIT(14) : 0;
1314 r[6] |= pr->otag_exist ? BIT(13) : 0;
1315 r[6] |= pr->itag_exist ? BIT(12) : 0;
1316 r[6] |= ((u32) (pr->frame_type_l2 & 0x3)) << 10;
1317 r[6] |= ((u32) (pr->tid & 0x3)) << 8;
1318
1319 r[12] |= ((u32) (pr->spmmask_fix_m & 0x3)) << 6;
1320 r[12] |= (u32) (pr->spn_m & 0x3f);
1321 r[13] |= pr->mgnt_vlan_m ? BIT(31) : 0;
1322 r[13] |= pr->dmac_hit_sw_m ? BIT(30) : 0;
1323 r[13] |= pr->not_first_frag_m ? BIT(29) : 0;
1324 r[13] |= ((u32) (pr->frame_type_l4_m & 0x7)) << 26;
1325 r[13] |= ((u32) (pr->frame_type_m & 0x3)) << 24;
1326 r[13] |= pr->otag_fmt_m ? BIT(23) : 0;
1327 r[13] |= pr->itag_fmt_m ? BIT(22) : 0;
1328 r[13] |= pr->otag_exist_m ? BIT(21) : 0;
1329 r[13] |= pr->itag_exist_m ? BIT(20) : 0;
1330 r[13] |= ((u32) (pr->frame_type_l2_m & 0x3)) << 18;
1331 r[13] |= ((u32) (pr->tid_m & 0x3)) << 16;
1332
1333 r[13] |= pr->valid ? BIT(15) : 0;
1334 r[13] |= pr->cond_not ? BIT(14) : 0;
1335 r[13] |= pr->cond_and1 ? BIT(13) : 0;
1336 r[13] |= pr->cond_and2 ? BIT(12) : 0;
1337 }
1338
1339 static void rtl839x_write_pie_action(u32 r[], struct pie_rule *pr)
1340 {
1341 if (pr->drop) {
1342 r[13] |= 0x9; /* Set ACT_MASK_FWD & FWD_ACT = DROP */
1343 r[13] |= BIT(3);
1344 } else {
1345 r[13] |= pr->fwd_sel ? BIT(3) : 0;
1346 r[13] |= pr->fwd_act;
1347 }
1348 r[13] |= pr->bypass_sel ? BIT(11) : 0;
1349 r[13] |= pr->mpls_sel ? BIT(10) : 0;
1350 r[13] |= pr->nopri_sel ? BIT(9) : 0;
1351 r[13] |= pr->ovid_sel ? BIT(8) : 0;
1352 r[13] |= pr->ivid_sel ? BIT(7) : 0;
1353 r[13] |= pr->meter_sel ? BIT(6) : 0;
1354 r[13] |= pr->mir_sel ? BIT(5) : 0;
1355 r[13] |= pr->log_sel ? BIT(4) : 0;
1356
1357 r[14] |= ((u32)(pr->fwd_data & 0x3fff)) << 18;
1358 r[14] |= pr->log_octets ? BIT(17) : 0;
1359 r[14] |= ((u32)(pr->log_data & 0x7ff)) << 4;
1360 r[14] |= (pr->mir_data & 0x3) << 3;
1361 r[14] |= ((u32)(pr->meter_data >> 7)) & 0x7;
1362 r[15] |= (u32)(pr->meter_data) << 26;
1363 r[15] |= ((u32)(pr->ivid_act) << 23) & 0x3;
1364 r[15] |= ((u32)(pr->ivid_data) << 9) & 0xfff;
1365 r[15] |= ((u32)(pr->ovid_act) << 6) & 0x3;
1366 r[15] |= ((u32)(pr->ovid_data) >> 4) & 0xff;
1367 r[16] |= ((u32)(pr->ovid_data) & 0xf) << 28;
1368 r[16] |= ((u32)(pr->nopri_data) & 0x7) << 20;
1369 r[16] |= ((u32)(pr->mpls_act) & 0x7) << 20;
1370 r[16] |= ((u32)(pr->mpls_lib_idx) & 0x7) << 20;
1371 r[16] |= pr->bypass_all ? BIT(9) : 0;
1372 r[16] |= pr->bypass_igr_stp ? BIT(8) : 0;
1373 r[16] |= pr->bypass_ibc_sc ? BIT(7) : 0;
1374 }
1375
1376 static void rtl839x_read_pie_action(u32 r[], struct pie_rule *pr)
1377 {
1378 if (r[13] & BIT(3)) { /* ACT_MASK_FWD set, is it a drop? */
1379 if ((r[14] & 0x7) == 1) {
1380 pr->drop = true;
1381 } else {
1382 pr->fwd_sel = true;
1383 pr->fwd_act = r[14] & 0x7;
1384 }
1385 }
1386
1387 pr->bypass_sel = r[13] & BIT(11);
1388 pr->mpls_sel = r[13] & BIT(10);
1389 pr->nopri_sel = r[13] & BIT(9);
1390 pr->ovid_sel = r[13] & BIT(8);
1391 pr->ivid_sel = r[13] & BIT(7);
1392 pr->meter_sel = r[13] & BIT(6);
1393 pr->mir_sel = r[13] & BIT(5);
1394 pr->log_sel = r[13] & BIT(4);
1395
1396 /* TODO: Read in data fields */
1397
1398 pr->bypass_all = r[16] & BIT(9);
1399 pr->bypass_igr_stp = r[16] & BIT(8);
1400 pr->bypass_ibc_sc = r[16] & BIT(7);
1401 }
1402
1403 void rtl839x_pie_rule_dump_raw(u32 r[])
1404 {
1405 pr_info("Raw IACL table entry:\n");
1406 pr_info("Match : %08x %08x %08x %08x %08x %08x\n", r[0], r[1], r[2], r[3], r[4], r[5]);
1407 pr_info("Fixed : %06x\n", r[6] >> 8);
1408 pr_info("Match M: %08x %08x %08x %08x %08x %08x\n",
1409 (r[6] << 24) | (r[7] >> 8), (r[7] << 24) | (r[8] >> 8), (r[8] << 24) | (r[9] >> 8),
1410 (r[9] << 24) | (r[10] >> 8), (r[10] << 24) | (r[11] >> 8),
1411 (r[11] << 24) | (r[12] >> 8));
1412 pr_info("R[13]: %08x\n", r[13]);
1413 pr_info("Fixed M: %06x\n", ((r[12] << 16) | (r[13] >> 16)) & 0xffffff);
1414 pr_info("Valid / not / and1 / and2 : %1x\n", (r[13] >> 12) & 0xf);
1415 pr_info("r 13-16: %08x %08x %08x %08x\n", r[13], r[14], r[15], r[16]);
1416 }
1417
1418 void rtl839x_pie_rule_dump(struct pie_rule *pr)
1419 {
1420 pr_info("Drop: %d, fwd: %d, ovid: %d, ivid: %d, flt: %d, log: %d, rmk: %d, meter: %d tagst: %d, mir: %d, nopri: %d, cpupri: %d, otpid: %d, itpid: %d, shape: %d\n",
1421 pr->drop, pr->fwd_sel, pr->ovid_sel, pr->ivid_sel, pr->flt_sel, pr->log_sel, pr->rmk_sel, pr->log_sel, pr->tagst_sel, pr->mir_sel, pr->nopri_sel,
1422 pr->cpupri_sel, pr->otpid_sel, pr->itpid_sel, pr->shaper_sel);
1423 if (pr->fwd_sel)
1424 pr_info("FWD: %08x\n", pr->fwd_data);
1425 pr_info("TID: %x, %x\n", pr->tid, pr->tid_m);
1426 }
1427
1428 static int rtl839x_pie_rule_read(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr)
1429 {
1430 /* Read IACL table (2) via register 0 */
1431 struct table_reg *q = rtl_table_get(RTL8380_TBL_0, 2);
1432 u32 r[17];
1433 int block = idx / PIE_BLOCK_SIZE;
1434 u32 t_select = sw_r32(RTL839X_ACL_BLK_TMPLTE_CTRL(block));
1435
1436 memset(pr, 0, sizeof(*pr));
1437 rtl_table_read(q, idx);
1438 for (int i = 0; i < 17; i++)
1439 r[i] = sw_r32(rtl_table_data(q, i));
1440
1441 rtl_table_release(q);
1442
1443 rtl839x_read_pie_fixed_fields(r, pr);
1444 if (!pr->valid)
1445 return 0;
1446
1447 pr_debug("%s: template_selectors %08x, tid: %d\n", __func__, t_select, pr->tid);
1448 rtl839x_pie_rule_dump_raw(r);
1449
1450 rtl839x_read_pie_templated(r, pr, fixed_templates[(t_select >> (pr->tid * 3)) & 0x7]);
1451
1452 rtl839x_read_pie_action(r, pr);
1453
1454 return 0;
1455 }
1456
1457 static int rtl839x_pie_rule_write(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr)
1458 {
1459 /* Access IACL table (2) via register 0 */
1460 struct table_reg *q = rtl_table_get(RTL8390_TBL_0, 2);
1461 u32 r[17];
1462 int block = idx / PIE_BLOCK_SIZE;
1463 u32 t_select = sw_r32(RTL839X_ACL_BLK_TMPLTE_CTRL(block));
1464
1465 pr_debug("%s: %d, t_select: %08x\n", __func__, idx, t_select);
1466
1467 for (int i = 0; i < 17; i++)
1468 r[i] = 0;
1469
1470 if (!pr->valid) {
1471 rtl_table_write(q, idx);
1472 rtl_table_release(q);
1473 return 0;
1474 }
1475 rtl839x_write_pie_fixed_fields(r, pr);
1476
1477 pr_debug("%s: template %d\n", __func__, (t_select >> (pr->tid * 3)) & 0x7);
1478 rtl839x_write_pie_templated(r, pr, fixed_templates[(t_select >> (pr->tid * 3)) & 0x7]);
1479
1480 rtl839x_write_pie_action(r, pr);
1481
1482 /* rtl839x_pie_rule_dump_raw(r); */
1483
1484 for (int i = 0; i < 17; i++)
1485 sw_w32(r[i], rtl_table_data(q, i));
1486
1487 rtl_table_write(q, idx);
1488 rtl_table_release(q);
1489
1490 return 0;
1491 }
1492
1493 static bool rtl839x_pie_templ_has(int t, enum template_field_id field_type)
1494 {
1495 for (int i = 0; i < N_FIXED_FIELDS; i++) {
1496 enum template_field_id ft = fixed_templates[t][i];
1497 if (field_type == ft)
1498 return true;
1499 }
1500
1501 return false;
1502 }
1503
1504 static int rtl839x_pie_verify_template(struct rtl838x_switch_priv *priv,
1505 struct pie_rule *pr, int t, int block)
1506 {
1507 int i;
1508
1509 if (!pr->is_ipv6 && pr->sip_m && !rtl839x_pie_templ_has(t, TEMPLATE_FIELD_SIP0))
1510 return -1;
1511
1512 if (!pr->is_ipv6 && pr->dip_m && !rtl839x_pie_templ_has(t, TEMPLATE_FIELD_DIP0))
1513 return -1;
1514
1515 if (pr->is_ipv6) {
1516 if ((pr->sip6_m.s6_addr32[0] ||
1517 pr->sip6_m.s6_addr32[1] ||
1518 pr->sip6_m.s6_addr32[2] ||
1519 pr->sip6_m.s6_addr32[3]) &&
1520 !rtl839x_pie_templ_has(t, TEMPLATE_FIELD_SIP2))
1521 return -1;
1522 if ((pr->dip6_m.s6_addr32[0] ||
1523 pr->dip6_m.s6_addr32[1] ||
1524 pr->dip6_m.s6_addr32[2] ||
1525 pr->dip6_m.s6_addr32[3]) &&
1526 !rtl839x_pie_templ_has(t, TEMPLATE_FIELD_DIP2))
1527 return -1;
1528 }
1529
1530 if (ether_addr_to_u64(pr->smac) && !rtl839x_pie_templ_has(t, TEMPLATE_FIELD_SMAC0))
1531 return -1;
1532
1533 if (ether_addr_to_u64(pr->dmac) && !rtl839x_pie_templ_has(t, TEMPLATE_FIELD_DMAC0))
1534 return -1;
1535
1536 /* TODO: Check more */
1537
1538 i = find_first_zero_bit(&priv->pie_use_bm[block * 4], PIE_BLOCK_SIZE);
1539
1540 if (i >= PIE_BLOCK_SIZE)
1541 return -1;
1542
1543 return i + PIE_BLOCK_SIZE * block;
1544 }
1545
1546 static int rtl839x_pie_rule_add(struct rtl838x_switch_priv *priv, struct pie_rule *pr)
1547 {
1548 int idx, block, j, t;
1549 int min_block = 0;
1550 int max_block = priv->n_pie_blocks / 2;
1551
1552 if (pr->is_egress) {
1553 min_block = max_block;
1554 max_block = priv->n_pie_blocks;
1555 }
1556
1557 mutex_lock(&priv->pie_mutex);
1558
1559 for (block = min_block; block < max_block; block++) {
1560 for (j = 0; j < 2; j++) {
1561 t = (sw_r32(RTL839X_ACL_BLK_TMPLTE_CTRL(block)) >> (j * 3)) & 0x7;
1562 idx = rtl839x_pie_verify_template(priv, pr, t, block);
1563 if (idx >= 0)
1564 break;
1565 }
1566 if (j < 2)
1567 break;
1568 }
1569
1570 if (block >= priv->n_pie_blocks) {
1571 mutex_unlock(&priv->pie_mutex);
1572 return -EOPNOTSUPP;
1573 }
1574
1575 set_bit(idx, priv->pie_use_bm);
1576
1577 pr->valid = true;
1578 pr->tid = j; /* Mapped to template number */
1579 pr->tid_m = 0x3;
1580 pr->id = idx;
1581
1582 rtl839x_pie_lookup_enable(priv, idx);
1583 rtl839x_pie_rule_write(priv, idx, pr);
1584
1585 mutex_unlock(&priv->pie_mutex);
1586
1587 return 0;
1588 }
1589
1590 static void rtl839x_pie_rule_rm(struct rtl838x_switch_priv *priv, struct pie_rule *pr)
1591 {
1592 int idx = pr->id;
1593
1594 rtl839x_pie_rule_del(priv, idx, idx);
1595 clear_bit(idx, priv->pie_use_bm);
1596 }
1597
1598 static void rtl839x_pie_init(struct rtl838x_switch_priv *priv)
1599 {
1600 u32 template_selectors;
1601
1602 mutex_init(&priv->pie_mutex);
1603
1604 /* Power on all PIE blocks */
1605 for (int i = 0; i < priv->n_pie_blocks; i++)
1606 sw_w32_mask(0, BIT(i), RTL839X_PS_ACL_PWR_CTRL);
1607
1608 /* Set ingress and egress ACL blocks to 50/50: first Egress block is 9 */
1609 sw_w32_mask(0x1f, 9, RTL839X_ACL_CTRL); /* Writes 9 to cutline field */
1610
1611 /* Include IPG in metering */
1612 sw_w32(1, RTL839X_METER_GLB_CTRL);
1613
1614 /* Delete all present rules */
1615 rtl839x_pie_rule_del(priv, 0, priv->n_pie_blocks * PIE_BLOCK_SIZE - 1);
1616
1617 /* Enable predefined templates 0, 1 for blocks 0-2 */
1618 template_selectors = 0 | (1 << 3);
1619 for (int i = 0; i < 3; i++)
1620 sw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i));
1621
1622 /* Enable predefined templates 2, 3 for blocks 3-5 */
1623 template_selectors = 2 | (3 << 3);
1624 for (int i = 3; i < 6; i++)
1625 sw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i));
1626
1627 /* Enable predefined templates 1, 4 for blocks 6-8 */
1628 template_selectors = 2 | (3 << 3);
1629 for (int i = 6; i < 9; i++)
1630 sw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i));
1631
1632 /* Enable predefined templates 0, 1 for blocks 9-11 */
1633 template_selectors = 0 | (1 << 3);
1634 for (int i = 9; i < 12; i++)
1635 sw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i));
1636
1637 /* Enable predefined templates 2, 3 for blocks 12-14 */
1638 template_selectors = 2 | (3 << 3);
1639 for (int i = 12; i < 15; i++)
1640 sw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i));
1641
1642 /* Enable predefined templates 1, 4 for blocks 15-17 */
1643 template_selectors = 2 | (3 << 3);
1644 for (int i = 15; i < 18; i++)
1645 sw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i));
1646 }
1647
1648 static u32 rtl839x_packet_cntr_read(int counter)
1649 {
1650 u32 v;
1651
1652 /* Read LOG table (4) via register RTL8390_TBL_0 */
1653 struct table_reg *r = rtl_table_get(RTL8390_TBL_0, 4);
1654
1655 pr_debug("In %s, id %d\n", __func__, counter);
1656 rtl_table_read(r, counter / 2);
1657
1658 /* The table has a size of 2 registers */
1659 if (counter % 2)
1660 v = sw_r32(rtl_table_data(r, 0));
1661 else
1662 v = sw_r32(rtl_table_data(r, 1));
1663
1664 rtl_table_release(r);
1665
1666 return v;
1667 }
1668
1669 static void rtl839x_packet_cntr_clear(int counter)
1670 {
1671 /* Access LOG table (4) via register RTL8390_TBL_0 */
1672 struct table_reg *r = rtl_table_get(RTL8390_TBL_0, 4);
1673
1674 pr_debug("In %s, id %d\n", __func__, counter);
1675 /* The table has a size of 2 registers */
1676 if (counter % 2)
1677 sw_w32(0, rtl_table_data(r, 0));
1678 else
1679 sw_w32(0, rtl_table_data(r, 1));
1680
1681 rtl_table_write(r, counter / 2);
1682
1683 rtl_table_release(r);
1684 }
1685
1686 static void rtl839x_route_read(int idx, struct rtl83xx_route *rt)
1687 {
1688 u64 v;
1689 /* Read ROUTING table (2) via register RTL8390_TBL_1 */
1690 struct table_reg *r = rtl_table_get(RTL8390_TBL_1, 2);
1691
1692 pr_debug("In %s\n", __func__);
1693 rtl_table_read(r, idx);
1694
1695 /* The table has a size of 2 registers */
1696 v = sw_r32(rtl_table_data(r, 0));
1697 v <<= 32;
1698 v |= sw_r32(rtl_table_data(r, 1));
1699 rt->switch_mac_id = (v >> 12) & 0xf;
1700 rt->nh.gw = v >> 16;
1701
1702 rtl_table_release(r);
1703 }
1704
1705 static void rtl839x_route_write(int idx, struct rtl83xx_route *rt)
1706 {
1707 u32 v;
1708
1709 /* Read ROUTING table (2) via register RTL8390_TBL_1 */
1710 struct table_reg *r = rtl_table_get(RTL8390_TBL_1, 2);
1711
1712 pr_debug("In %s\n", __func__);
1713 sw_w32(rt->nh.gw >> 16, rtl_table_data(r, 0));
1714 v = rt->nh.gw << 16;
1715 v |= rt->switch_mac_id << 12;
1716 sw_w32(v, rtl_table_data(r, 1));
1717 rtl_table_write(r, idx);
1718
1719 rtl_table_release(r);
1720 }
1721
1722 /* Configure the switch's own MAC addresses used when routing packets */
1723 static void rtl839x_setup_port_macs(struct rtl838x_switch_priv *priv)
1724 {
1725 struct net_device *dev;
1726 u64 mac;
1727
1728 pr_debug("%s: got port %08x\n", __func__, (u32)priv->ports[priv->cpu_port].dp);
1729 dev = priv->ports[priv->cpu_port].dp->slave;
1730 mac = ether_addr_to_u64(dev->dev_addr);
1731
1732 for (int i = 0; i < 15; i++) {
1733 mac++; /* BUG: VRRP for testing */
1734 sw_w32(mac >> 32, RTL839X_ROUTING_SA_CTRL + i * 8);
1735 sw_w32(mac, RTL839X_ROUTING_SA_CTRL + i * 8 + 4);
1736 }
1737 }
1738
1739 int rtl839x_l3_setup(struct rtl838x_switch_priv *priv)
1740 {
1741 rtl839x_setup_port_macs(priv);
1742
1743 return 0;
1744 }
1745
1746 void rtl839x_vlan_port_keep_tag_set(int port, bool keep_outer, bool keep_inner)
1747 {
1748 sw_w32(FIELD_PREP(RTL839X_VLAN_PORT_TAG_STS_CTRL_OTAG_STS_MASK,
1749 keep_outer ? RTL839X_VLAN_PORT_TAG_STS_TAGGED : RTL839X_VLAN_PORT_TAG_STS_UNTAG) |
1750 FIELD_PREP(RTL839X_VLAN_PORT_TAG_STS_CTRL_ITAG_STS_MASK,
1751 keep_inner ? RTL839X_VLAN_PORT_TAG_STS_TAGGED : RTL839X_VLAN_PORT_TAG_STS_UNTAG),
1752 RTL839X_VLAN_PORT_TAG_STS_CTRL(port));
1753 }
1754
1755 void rtl839x_vlan_port_pvidmode_set(int port, enum pbvlan_type type, enum pbvlan_mode mode)
1756 {
1757 if (type == PBVLAN_TYPE_INNER)
1758 sw_w32_mask(0x3, mode, RTL839X_VLAN_PORT_PB_VLAN + (port << 2));
1759 else
1760 sw_w32_mask(0x3 << 14, mode << 14, RTL839X_VLAN_PORT_PB_VLAN + (port << 2));
1761 }
1762
1763 void rtl839x_vlan_port_pvid_set(int port, enum pbvlan_type type, int pvid)
1764 {
1765 if (type == PBVLAN_TYPE_INNER)
1766 sw_w32_mask(0xfff << 2, pvid << 2, RTL839X_VLAN_PORT_PB_VLAN + (port << 2));
1767 else
1768 sw_w32_mask(0xfff << 16, pvid << 16, RTL839X_VLAN_PORT_PB_VLAN + (port << 2));
1769 }
1770
1771 static int rtl839x_set_ageing_time(unsigned long msec)
1772 {
1773 int t = sw_r32(RTL839X_L2_CTRL_1);
1774
1775 t &= 0x1FFFFF;
1776 t = t * 3 / 5; /* Aging time in seconds. 0: L2 aging disabled */
1777 pr_debug("L2 AGING time: %d sec\n", t);
1778
1779 t = (msec * 5 + 2000) / 3000;
1780 t = t > 0x1FFFFF ? 0x1FFFFF : t;
1781 sw_w32_mask(0x1FFFFF, t, RTL839X_L2_CTRL_1);
1782 pr_debug("Dynamic aging for ports: %x\n", sw_r32(RTL839X_L2_PORT_AGING_OUT));
1783
1784 return 0;
1785 }
1786
1787 static void rtl839x_set_igr_filter(int port, enum igr_filter state)
1788 {
1789 sw_w32_mask(0x3 << ((port & 0xf)<<1), state << ((port & 0xf)<<1),
1790 RTL839X_VLAN_PORT_IGR_FLTR + (((port >> 4) << 2)));
1791 }
1792
1793 static void rtl839x_set_egr_filter(int port, enum egr_filter state)
1794 {
1795 sw_w32_mask(0x1 << (port % 0x20), state << (port % 0x20),
1796 RTL839X_VLAN_PORT_EGR_FLTR + (((port >> 5) << 2)));
1797 }
1798
1799 void rtl839x_set_distribution_algorithm(int group, int algoidx, u32 algomsk)
1800 {
1801 sw_w32_mask(3 << ((group & 0xf) << 1), algoidx << ((group & 0xf) << 1),
1802 RTL839X_TRK_HASH_IDX_CTRL + ((group >> 4) << 2));
1803 sw_w32(algomsk, RTL839X_TRK_HASH_CTRL + (algoidx << 2));
1804 }
1805
1806 void rtl839x_set_receive_management_action(int port, rma_ctrl_t type, action_type_t action)
1807 {
1808 switch(type) {
1809 case BPDU:
1810 sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1),
1811 RTL839X_RMA_BPDU_CTRL + ((port >> 4) << 2));
1812 break;
1813 case PTP:
1814 sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1),
1815 RTL839X_RMA_PTP_CTRL + ((port >> 4) << 2));
1816 break;
1817 case LLTP:
1818 sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1),
1819 RTL839X_RMA_LLTP_CTRL + ((port >> 4) << 2));
1820 break;
1821 default:
1822 break;
1823 }
1824 }
1825
1826 const struct rtl838x_reg rtl839x_reg = {
1827 .mask_port_reg_be = rtl839x_mask_port_reg_be,
1828 .set_port_reg_be = rtl839x_set_port_reg_be,
1829 .get_port_reg_be = rtl839x_get_port_reg_be,
1830 .mask_port_reg_le = rtl839x_mask_port_reg_le,
1831 .set_port_reg_le = rtl839x_set_port_reg_le,
1832 .get_port_reg_le = rtl839x_get_port_reg_le,
1833 .stat_port_rst = RTL839X_STAT_PORT_RST,
1834 .stat_rst = RTL839X_STAT_RST,
1835 .stat_port_std_mib = RTL839X_STAT_PORT_STD_MIB,
1836 .traffic_enable = rtl839x_traffic_enable,
1837 .traffic_disable = rtl839x_traffic_disable,
1838 .traffic_get = rtl839x_traffic_get,
1839 .traffic_set = rtl839x_traffic_set,
1840 .port_iso_ctrl = rtl839x_port_iso_ctrl,
1841 .l2_ctrl_0 = RTL839X_L2_CTRL_0,
1842 .l2_ctrl_1 = RTL839X_L2_CTRL_1,
1843 .l2_port_aging_out = RTL839X_L2_PORT_AGING_OUT,
1844 .set_ageing_time = rtl839x_set_ageing_time,
1845 .smi_poll_ctrl = RTL839X_SMI_PORT_POLLING_CTRL,
1846 .l2_tbl_flush_ctrl = RTL839X_L2_TBL_FLUSH_CTRL,
1847 .exec_tbl0_cmd = rtl839x_exec_tbl0_cmd,
1848 .exec_tbl1_cmd = rtl839x_exec_tbl1_cmd,
1849 .tbl_access_data_0 = rtl839x_tbl_access_data_0,
1850 .isr_glb_src = RTL839X_ISR_GLB_SRC,
1851 .isr_port_link_sts_chg = RTL839X_ISR_PORT_LINK_STS_CHG,
1852 .imr_port_link_sts_chg = RTL839X_IMR_PORT_LINK_STS_CHG,
1853 .imr_glb = RTL839X_IMR_GLB,
1854 .vlan_tables_read = rtl839x_vlan_tables_read,
1855 .vlan_set_tagged = rtl839x_vlan_set_tagged,
1856 .vlan_set_untagged = rtl839x_vlan_set_untagged,
1857 .vlan_profile_dump = rtl839x_vlan_profile_dump,
1858 .vlan_profile_setup = rtl839x_vlan_profile_setup,
1859 .vlan_fwd_on_inner = rtl839x_vlan_fwd_on_inner,
1860 .vlan_port_keep_tag_set = rtl839x_vlan_port_keep_tag_set,
1861 .vlan_port_pvidmode_set = rtl839x_vlan_port_pvidmode_set,
1862 .vlan_port_pvid_set = rtl839x_vlan_port_pvid_set,
1863 .set_vlan_igr_filter = rtl839x_set_igr_filter,
1864 .set_vlan_egr_filter = rtl839x_set_egr_filter,
1865 .enable_learning = rtl839x_enable_learning,
1866 .enable_flood = rtl839x_enable_flood,
1867 .enable_mcast_flood = rtl839x_enable_mcast_flood,
1868 .enable_bcast_flood = rtl839x_enable_bcast_flood,
1869 .set_static_move_action = rtl839x_set_static_move_action,
1870 .stp_get = rtl839x_stp_get,
1871 .stp_set = rtl839x_stp_set,
1872 .mac_force_mode_ctrl = rtl839x_mac_force_mode_ctrl,
1873 .mac_port_ctrl = rtl839x_mac_port_ctrl,
1874 .l2_port_new_salrn = rtl839x_l2_port_new_salrn,
1875 .l2_port_new_sa_fwd = rtl839x_l2_port_new_sa_fwd,
1876 .mir_ctrl = RTL839X_MIR_CTRL,
1877 .mir_dpm = RTL839X_MIR_DPM_CTRL,
1878 .mir_spm = RTL839X_MIR_SPM_CTRL,
1879 .mac_link_sts = RTL839X_MAC_LINK_STS,
1880 .mac_link_dup_sts = RTL839X_MAC_LINK_DUP_STS,
1881 .mac_link_spd_sts = rtl839x_mac_link_spd_sts,
1882 .mac_rx_pause_sts = RTL839X_MAC_RX_PAUSE_STS,
1883 .mac_tx_pause_sts = RTL839X_MAC_TX_PAUSE_STS,
1884 .read_l2_entry_using_hash = rtl839x_read_l2_entry_using_hash,
1885 .write_l2_entry_using_hash = rtl839x_write_l2_entry_using_hash,
1886 .read_cam = rtl839x_read_cam,
1887 .write_cam = rtl839x_write_cam,
1888 .trk_mbr_ctr = rtl839x_trk_mbr_ctr,
1889 .rma_bpdu_fld_pmask = RTL839X_RMA_BPDU_FLD_PMSK,
1890 .spcl_trap_eapol_ctrl = RTL839X_SPCL_TRAP_EAPOL_CTRL,
1891 .init_eee = rtl839x_init_eee,
1892 .port_eee_set = rtl839x_port_eee_set,
1893 .eee_port_ability = rtl839x_eee_port_ability,
1894 .l2_hash_seed = rtl839x_l2_hash_seed,
1895 .l2_hash_key = rtl839x_l2_hash_key,
1896 .read_mcast_pmask = rtl839x_read_mcast_pmask,
1897 .write_mcast_pmask = rtl839x_write_mcast_pmask,
1898 .pie_init = rtl839x_pie_init,
1899 .pie_rule_read = rtl839x_pie_rule_read,
1900 .pie_rule_write = rtl839x_pie_rule_write,
1901 .pie_rule_add = rtl839x_pie_rule_add,
1902 .pie_rule_rm = rtl839x_pie_rule_rm,
1903 .l2_learning_setup = rtl839x_l2_learning_setup,
1904 .packet_cntr_read = rtl839x_packet_cntr_read,
1905 .packet_cntr_clear = rtl839x_packet_cntr_clear,
1906 .route_read = rtl839x_route_read,
1907 .route_write = rtl839x_route_write,
1908 .l3_setup = rtl839x_l3_setup,
1909 .set_distribution_algorithm = rtl839x_set_distribution_algorithm,
1910 .set_receive_management_action = rtl839x_set_receive_management_action,
1911 };
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