1 // SPDX-License-Identifier: GPL-2.0-only
3 #include <asm/mach-rtl838x/mach-rtl83xx.h>
7 #define RTL839X_VLAN_PORT_TAG_STS_UNTAG 0x0
8 #define RTL839X_VLAN_PORT_TAG_STS_TAGGED 0x1
9 #define RTL839X_VLAN_PORT_TAG_STS_PRIORITY_TAGGED 0x2
11 #define RTL839X_VLAN_PORT_TAG_STS_CTRL_BASE 0x6828
13 #define RTL839X_VLAN_PORT_TAG_STS_CTRL(port) \
14 RTL839X_VLAN_PORT_TAG_STS_CTRL_BASE + (port << 2)
15 #define RTL839X_VLAN_PORT_TAG_STS_CTRL_OTAG_STS_MASK GENMASK(7,6)
16 #define RTL839X_VLAN_PORT_TAG_STS_CTRL_ITAG_STS_MASK GENMASK(5,4)
17 #define RTL839X_VLAN_PORT_TAG_STS_CTRL_EGR_P_OTAG_KEEP_MASK GENMASK(3,3)
18 #define RTL839X_VLAN_PORT_TAG_STS_CTRL_EGR_P_ITAG_KEEP_MASK GENMASK(2,2)
19 #define RTL839X_VLAN_PORT_TAG_STS_CTRL_IGR_P_OTAG_KEEP_MASK GENMASK(1,1)
20 #define RTL839X_VLAN_PORT_TAG_STS_CTRL_IGR_P_ITAG_KEEP_MASK GENMASK(0,0)
22 extern struct mutex smi_lock
;
23 extern struct rtl83xx_soc_info soc_info
;
25 /* Definition of the RTL839X-specific template field IDs as used in the PIE */
26 enum template_field_id
{
27 TEMPLATE_FIELD_SPMMASK
= 0,
28 TEMPLATE_FIELD_SPM0
= 1, /* Source portmask ports 0-15 */
29 TEMPLATE_FIELD_SPM1
= 2, /* Source portmask ports 16-31 */
30 TEMPLATE_FIELD_SPM2
= 3, /* Source portmask ports 32-47 */
31 TEMPLATE_FIELD_SPM3
= 4, /* Source portmask ports 48-56 */
32 TEMPLATE_FIELD_DMAC0
= 5, /* Destination MAC [15:0] */
33 TEMPLATE_FIELD_DMAC1
= 6, /* Destination MAC [31:16] */
34 TEMPLATE_FIELD_DMAC2
= 7, /* Destination MAC [47:32] */
35 TEMPLATE_FIELD_SMAC0
= 8, /* Source MAC [15:0] */
36 TEMPLATE_FIELD_SMAC1
= 9, /* Source MAC [31:16] */
37 TEMPLATE_FIELD_SMAC2
= 10, /* Source MAC [47:32] */
38 TEMPLATE_FIELD_ETHERTYPE
= 11, /* Ethernet frame type field */
39 /* Field-ID 12 is not used */
40 TEMPLATE_FIELD_OTAG
= 13,
41 TEMPLATE_FIELD_ITAG
= 14,
42 TEMPLATE_FIELD_SIP0
= 15,
43 TEMPLATE_FIELD_SIP1
= 16,
44 TEMPLATE_FIELD_DIP0
= 17,
45 TEMPLATE_FIELD_DIP1
= 18,
46 TEMPLATE_FIELD_IP_TOS_PROTO
= 19,
47 TEMPLATE_FIELD_IP_FLAG
= 20,
48 TEMPLATE_FIELD_L4_SPORT
= 21,
49 TEMPLATE_FIELD_L4_DPORT
= 22,
50 TEMPLATE_FIELD_L34_HEADER
= 23,
51 TEMPLATE_FIELD_ICMP_IGMP
= 24,
52 TEMPLATE_FIELD_VID_RANG0
= 25,
53 TEMPLATE_FIELD_VID_RANG1
= 26,
54 TEMPLATE_FIELD_L4_PORT_RANG
= 27,
55 TEMPLATE_FIELD_FIELD_SELECTOR_VALID
= 28,
56 TEMPLATE_FIELD_FIELD_SELECTOR_0
= 29,
57 TEMPLATE_FIELD_FIELD_SELECTOR_1
= 30,
58 TEMPLATE_FIELD_FIELD_SELECTOR_2
= 31,
59 TEMPLATE_FIELD_FIELD_SELECTOR_3
= 32,
60 TEMPLATE_FIELD_FIELD_SELECTOR_4
= 33,
61 TEMPLATE_FIELD_FIELD_SELECTOR_5
= 34,
62 TEMPLATE_FIELD_SIP2
= 35,
63 TEMPLATE_FIELD_SIP3
= 36,
64 TEMPLATE_FIELD_SIP4
= 37,
65 TEMPLATE_FIELD_SIP5
= 38,
66 TEMPLATE_FIELD_SIP6
= 39,
67 TEMPLATE_FIELD_SIP7
= 40,
68 TEMPLATE_FIELD_OLABEL
= 41,
69 TEMPLATE_FIELD_ILABEL
= 42,
70 TEMPLATE_FIELD_OILABEL
= 43,
71 TEMPLATE_FIELD_DPMMASK
= 44,
72 TEMPLATE_FIELD_DPM0
= 45,
73 TEMPLATE_FIELD_DPM1
= 46,
74 TEMPLATE_FIELD_DPM2
= 47,
75 TEMPLATE_FIELD_DPM3
= 48,
76 TEMPLATE_FIELD_L2DPM0
= 49,
77 TEMPLATE_FIELD_L2DPM1
= 50,
78 TEMPLATE_FIELD_L2DPM2
= 51,
79 TEMPLATE_FIELD_L2DPM3
= 52,
80 TEMPLATE_FIELD_IVLAN
= 53,
81 TEMPLATE_FIELD_OVLAN
= 54,
82 TEMPLATE_FIELD_FWD_VID
= 55,
83 TEMPLATE_FIELD_DIP2
= 56,
84 TEMPLATE_FIELD_DIP3
= 57,
85 TEMPLATE_FIELD_DIP4
= 58,
86 TEMPLATE_FIELD_DIP5
= 59,
87 TEMPLATE_FIELD_DIP6
= 60,
88 TEMPLATE_FIELD_DIP7
= 61,
91 /* Number of fixed templates predefined in the SoC */
92 #define N_FIXED_TEMPLATES 5
93 static enum template_field_id fixed_templates
[N_FIXED_TEMPLATES
][N_FIXED_FIELDS
] =
96 TEMPLATE_FIELD_SPM0
, TEMPLATE_FIELD_SPM1
, TEMPLATE_FIELD_ITAG
,
97 TEMPLATE_FIELD_SMAC0
, TEMPLATE_FIELD_SMAC1
, TEMPLATE_FIELD_SMAC2
,
98 TEMPLATE_FIELD_DMAC0
, TEMPLATE_FIELD_DMAC1
, TEMPLATE_FIELD_DMAC2
,
99 TEMPLATE_FIELD_ETHERTYPE
, TEMPLATE_FIELD_SPM2
, TEMPLATE_FIELD_SPM3
101 TEMPLATE_FIELD_SIP0
, TEMPLATE_FIELD_SIP1
, TEMPLATE_FIELD_DIP0
,
102 TEMPLATE_FIELD_DIP1
,TEMPLATE_FIELD_IP_TOS_PROTO
, TEMPLATE_FIELD_L4_SPORT
,
103 TEMPLATE_FIELD_L4_DPORT
, TEMPLATE_FIELD_ICMP_IGMP
, TEMPLATE_FIELD_SPM0
,
104 TEMPLATE_FIELD_SPM1
, TEMPLATE_FIELD_SPM2
, TEMPLATE_FIELD_SPM3
106 TEMPLATE_FIELD_DMAC0
, TEMPLATE_FIELD_DMAC1
, TEMPLATE_FIELD_DMAC2
,
107 TEMPLATE_FIELD_ITAG
, TEMPLATE_FIELD_ETHERTYPE
, TEMPLATE_FIELD_IP_TOS_PROTO
,
108 TEMPLATE_FIELD_L4_DPORT
, TEMPLATE_FIELD_L4_SPORT
, TEMPLATE_FIELD_SIP0
,
109 TEMPLATE_FIELD_SIP1
, TEMPLATE_FIELD_DIP0
, TEMPLATE_FIELD_DIP1
111 TEMPLATE_FIELD_DIP0
, TEMPLATE_FIELD_DIP1
, TEMPLATE_FIELD_DIP2
,
112 TEMPLATE_FIELD_DIP3
, TEMPLATE_FIELD_DIP4
, TEMPLATE_FIELD_DIP5
,
113 TEMPLATE_FIELD_DIP6
, TEMPLATE_FIELD_DIP7
, TEMPLATE_FIELD_L4_DPORT
,
114 TEMPLATE_FIELD_L4_SPORT
, TEMPLATE_FIELD_ICMP_IGMP
, TEMPLATE_FIELD_IP_TOS_PROTO
116 TEMPLATE_FIELD_SIP0
, TEMPLATE_FIELD_SIP1
, TEMPLATE_FIELD_SIP2
,
117 TEMPLATE_FIELD_SIP3
, TEMPLATE_FIELD_SIP4
, TEMPLATE_FIELD_SIP5
,
118 TEMPLATE_FIELD_SIP6
, TEMPLATE_FIELD_SIP7
, TEMPLATE_FIELD_SPM0
,
119 TEMPLATE_FIELD_SPM1
, TEMPLATE_FIELD_SPM2
, TEMPLATE_FIELD_SPM3
123 void rtl839x_print_matrix(void)
127 ptr9
= RTL838X_SW_BASE
+ RTL839X_PORT_ISO_CTRL(0);
128 for (int i
= 0; i
< 52; i
+= 4)
129 pr_debug("> %16llx %16llx %16llx %16llx\n",
130 ptr9
[i
+ 0], ptr9
[i
+ 1], ptr9
[i
+ 2], ptr9
[i
+ 3]);
131 pr_debug("CPU_PORT> %16llx\n", ptr9
[52]);
134 static inline int rtl839x_port_iso_ctrl(int p
)
136 return RTL839X_PORT_ISO_CTRL(p
);
139 static inline void rtl839x_exec_tbl0_cmd(u32 cmd
)
141 sw_w32(cmd
, RTL839X_TBL_ACCESS_CTRL_0
);
142 do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_0
) & BIT(16));
145 static inline void rtl839x_exec_tbl1_cmd(u32 cmd
)
147 sw_w32(cmd
, RTL839X_TBL_ACCESS_CTRL_1
);
148 do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_1
) & BIT(16));
151 inline void rtl839x_exec_tbl2_cmd(u32 cmd
)
153 sw_w32(cmd
, RTL839X_TBL_ACCESS_CTRL_2
);
154 do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_2
) & (1 << 9));
157 static inline int rtl839x_tbl_access_data_0(int i
)
159 return RTL839X_TBL_ACCESS_DATA_0(i
);
162 static void rtl839x_vlan_tables_read(u32 vlan
, struct rtl838x_vlan_info
*info
)
165 /* Read VLAN table (0) via register 0 */
166 struct table_reg
*r
= rtl_table_get(RTL8390_TBL_0
, 0);
168 rtl_table_read(r
, vlan
);
169 u
= sw_r32(rtl_table_data(r
, 0));
170 v
= sw_r32(rtl_table_data(r
, 1));
171 w
= sw_r32(rtl_table_data(r
, 2));
172 rtl_table_release(r
);
174 info
->tagged_ports
= u
;
175 info
->tagged_ports
= (info
->tagged_ports
<< 21) | ((v
>> 11) & 0x1fffff);
176 info
->profile_id
= w
>> 30 | ((v
& 1) << 2);
177 info
->hash_mc_fid
= !!(w
& BIT(2));
178 info
->hash_uc_fid
= !!(w
& BIT(3));
179 info
->fid
= (v
>> 3) & 0xff;
181 /* Read UNTAG table (0) via table register 1 */
182 r
= rtl_table_get(RTL8390_TBL_1
, 0);
183 rtl_table_read(r
, vlan
);
184 u
= sw_r32(rtl_table_data(r
, 0));
185 v
= sw_r32(rtl_table_data(r
, 1));
186 rtl_table_release(r
);
188 info
->untagged_ports
= u
;
189 info
->untagged_ports
= (info
->untagged_ports
<< 21) | ((v
>> 11) & 0x1fffff);
192 static void rtl839x_vlan_set_tagged(u32 vlan
, struct rtl838x_vlan_info
*info
)
195 /* Access VLAN table (0) via register 0 */
196 struct table_reg
*r
= rtl_table_get(RTL8390_TBL_0
, 0);
198 u
= info
->tagged_ports
>> 21;
199 v
= info
->tagged_ports
<< 11;
200 v
|= ((u32
)info
->fid
) << 3;
201 v
|= info
->hash_uc_fid
? BIT(2) : 0;
202 v
|= info
->hash_mc_fid
? BIT(1) : 0;
203 v
|= (info
->profile_id
& 0x4) ? 1 : 0;
204 w
= ((u32
)(info
->profile_id
& 3)) << 30;
206 sw_w32(u
, rtl_table_data(r
, 0));
207 sw_w32(v
, rtl_table_data(r
, 1));
208 sw_w32(w
, rtl_table_data(r
, 2));
210 rtl_table_write(r
, vlan
);
211 rtl_table_release(r
);
214 static void rtl839x_vlan_set_untagged(u32 vlan
, u64 portmask
)
218 /* Access UNTAG table (0) via table register 1 */
219 struct table_reg
*r
= rtl_table_get(RTL8390_TBL_1
, 0);
224 sw_w32(u
, rtl_table_data(r
, 0));
225 sw_w32(v
, rtl_table_data(r
, 1));
226 rtl_table_write(r
, vlan
);
228 rtl_table_release(r
);
231 /* Sets the L2 forwarding to be based on either the inner VLAN tag or the outer */
232 static void rtl839x_vlan_fwd_on_inner(int port
, bool is_set
)
235 rtl839x_mask_port_reg_be(BIT_ULL(port
), 0ULL, RTL839X_VLAN_PORT_FWD
);
237 rtl839x_mask_port_reg_be(0ULL, BIT_ULL(port
), RTL839X_VLAN_PORT_FWD
);
240 /* Hash seed is vid (actually rvid) concatenated with the MAC address */
241 static u64
rtl839x_l2_hash_seed(u64 mac
, u32 vid
)
251 /* Applies the same hash algorithm as the one used currently by the ASIC to the seed
252 * and returns a key into the L2 hash table
254 static u32
rtl839x_l2_hash_key(struct rtl838x_switch_priv
*priv
, u64 seed
)
258 if (sw_r32(priv
->r
->l2_ctrl_0
) & 1) {
259 h1
= (u32
) (((seed
>> 60) & 0x3f) ^ ((seed
>> 54) & 0x3f) ^
260 ((seed
>> 36) & 0x3f) ^ ((seed
>> 30) & 0x3f) ^
261 ((seed
>> 12) & 0x3f) ^ ((seed
>> 6) & 0x3f));
262 h2
= (u32
) (((seed
>> 48) & 0x3f) ^ ((seed
>> 42) & 0x3f) ^
263 ((seed
>> 24) & 0x3f) ^ ((seed
>> 18) & 0x3f) ^
268 ((((seed
>> 48) & 0x3f) << 6) | ((seed
>> 54) & 0x3f)) ^
269 ((seed
>> 36) & 0xfff) ^ ((seed
>> 24) & 0xfff) ^
270 ((seed
>> 12) & 0xfff) ^ (seed
& 0xfff);
276 static inline int rtl839x_mac_force_mode_ctrl(int p
)
278 return RTL839X_MAC_FORCE_MODE_CTRL
+ (p
<< 2);
281 static inline int rtl839x_mac_port_ctrl(int p
)
283 return RTL839X_MAC_PORT_CTRL(p
);
286 static inline int rtl839x_l2_port_new_salrn(int p
)
288 return RTL839X_L2_PORT_NEW_SALRN(p
);
291 static inline int rtl839x_l2_port_new_sa_fwd(int p
)
293 return RTL839X_L2_PORT_NEW_SA_FWD(p
);
296 static inline int rtl839x_mac_link_spd_sts(int p
)
298 return RTL839X_MAC_LINK_SPD_STS(p
);
301 static inline int rtl839x_trk_mbr_ctr(int group
)
303 return RTL839X_TRK_MBR_CTR
+ (group
<< 3);
306 static void rtl839x_fill_l2_entry(u32 r
[], struct rtl838x_l2_entry
*e
)
308 /* Table contains different entry types, we need to identify the right one:
309 * Check for MC entries, first
311 e
->is_ip_mc
= !!(r
[2] & BIT(31));
312 e
->is_ipv6_mc
= !!(r
[2] & BIT(30));
313 e
->type
= L2_INVALID
;
314 if (!e
->is_ip_mc
&& !e
->is_ipv6_mc
) {
315 e
->mac
[0] = (r
[0] >> 12);
316 e
->mac
[1] = (r
[0] >> 4);
317 e
->mac
[2] = ((r
[1] >> 28) | (r
[0] << 4));
318 e
->mac
[3] = (r
[1] >> 20);
319 e
->mac
[4] = (r
[1] >> 12);
320 e
->mac
[5] = (r
[1] >> 4);
322 e
->vid
= (r
[2] >> 4) & 0xfff;
323 e
->rvid
= (r
[0] >> 20) & 0xfff;
325 /* Is it a unicast entry? check multicast bit */
326 if (!(e
->mac
[0] & 1)) {
327 e
->is_static
= !!((r
[2] >> 18) & 1);
328 e
->port
= (r
[2] >> 24) & 0x3f;
329 e
->block_da
= !!(r
[2] & (1 << 19));
330 e
->block_sa
= !!(r
[2] & (1 << 20));
331 e
->suspended
= !!(r
[2] & (1 << 17));
332 e
->next_hop
= !!(r
[2] & (1 << 16));
334 pr_debug("Found next hop entry, need to read data\n");
335 e
->nh_vlan_target
= !!(r
[2] & BIT(15));
336 e
->nh_route_id
= (r
[2] >> 4) & 0x1ff;
339 e
->age
= (r
[2] >> 21) & 3;
341 if (!(r
[2] & 0xc0fd0000)) /* Check for valid entry */
344 e
->type
= L2_UNICAST
;
347 e
->type
= L2_MULTICAST
;
348 e
->mc_portmask_index
= (r
[2] >> 6) & 0xfff;
351 } else { /* IPv4 and IPv6 multicast */
352 e
->vid
= e
->rvid
= (r
[0] << 20) & 0xfff;
354 e
->mc_portmask_index
= (r
[2] >> 6) & 0xfff;
358 e
->type
= IP4_MULTICAST
;
362 e
->type
= IP6_MULTICAST
;
364 /* pr_info("%s: vid %d, rvid: %d\n", __func__, e->vid, e->rvid); */
367 /* Fills the 3 SoC table registers r[] with the information in the rtl838x_l2_entry */
368 static void rtl839x_fill_l2_row(u32 r
[], struct rtl838x_l2_entry
*e
)
371 r
[0] = r
[1] = r
[2] = 0;
375 r
[2] = e
->is_ip_mc
? BIT(31) : 0;
376 r
[2] |= e
->is_ipv6_mc
? BIT(30) : 0;
378 if (!e
->is_ip_mc
&& !e
->is_ipv6_mc
) {
379 r
[0] = ((u32
)e
->mac
[0]) << 12;
380 r
[0] |= ((u32
)e
->mac
[1]) << 4;
381 r
[0] |= ((u32
)e
->mac
[2]) >> 4;
382 r
[1] = ((u32
)e
->mac
[2]) << 28;
383 r
[1] |= ((u32
)e
->mac
[3]) << 20;
384 r
[1] |= ((u32
)e
->mac
[4]) << 12;
385 r
[1] |= ((u32
)e
->mac
[5]) << 4;
387 if (!(e
->mac
[0] & 1)) { /* Not multicast */
388 r
[2] |= e
->is_static
? BIT(18) : 0;
389 r
[0] |= ((u32
)e
->rvid
) << 20;
390 r
[2] |= e
->port
<< 24;
391 r
[2] |= e
->block_da
? BIT(19) : 0;
392 r
[2] |= e
->block_sa
? BIT(20) : 0;
393 r
[2] |= e
->suspended
? BIT(17) : 0;
394 r
[2] |= ((u32
)e
->age
) << 21;
397 r
[2] |= e
->nh_vlan_target
? BIT(15) : 0;
398 r
[2] |= (e
->nh_route_id
& 0x7ff) << 4;
402 pr_debug("Write L2 NH: %08x %08x %08x\n", r
[0], r
[1], r
[2]);
403 } else { /* L2 Multicast */
404 r
[0] |= ((u32
)e
->rvid
) << 20;
405 r
[2] |= ((u32
)e
->mc_portmask_index
) << 6;
407 } else { /* IPv4 or IPv6 MC entry */
408 r
[0] = ((u32
)e
->rvid
) << 20;
410 r
[2] |= ((u32
)e
->mc_portmask_index
) << 6;
414 /* Read an L2 UC or MC entry out of a hash bucket of the L2 forwarding table
415 * hash is the id of the bucket and pos is the position of the entry in that bucket
416 * The data read from the SoC is filled into rtl838x_l2_entry
418 static u64
rtl839x_read_l2_entry_using_hash(u32 hash
, u32 pos
, struct rtl838x_l2_entry
*e
)
421 struct table_reg
*q
= rtl_table_get(RTL8390_TBL_L2
, 0);
422 u32 idx
= (0 << 14) | (hash
<< 2) | pos
; /* Search SRAM, with hash and at pos in bucket */
424 rtl_table_read(q
, idx
);
425 for (int i
= 0; i
< 3; i
++)
426 r
[i
] = sw_r32(rtl_table_data(q
, i
));
428 rtl_table_release(q
);
430 rtl839x_fill_l2_entry(r
, e
);
434 return rtl839x_l2_hash_seed(ether_addr_to_u64(&e
->mac
[0]), e
->rvid
);
437 static void rtl839x_write_l2_entry_using_hash(u32 hash
, u32 pos
, struct rtl838x_l2_entry
*e
)
440 struct table_reg
*q
= rtl_table_get(RTL8390_TBL_L2
, 0);
442 u32 idx
= (0 << 14) | (hash
<< 2) | pos
; /* Access SRAM, with hash and at pos in bucket */
444 rtl839x_fill_l2_row(r
, e
);
446 for (int i
= 0; i
< 3; i
++)
447 sw_w32(r
[i
], rtl_table_data(q
, i
));
449 rtl_table_write(q
, idx
);
450 rtl_table_release(q
);
453 static u64
rtl839x_read_cam(int idx
, struct rtl838x_l2_entry
*e
)
456 struct table_reg
*q
= rtl_table_get(RTL8390_TBL_L2
, 1); /* Access L2 Table 1 */
458 rtl_table_read(q
, idx
);
459 for (int i
= 0; i
< 3; i
++)
460 r
[i
] = sw_r32(rtl_table_data(q
, i
));
462 rtl_table_release(q
);
464 rtl839x_fill_l2_entry(r
, e
);
468 pr_debug("Found in CAM: R1 %x R2 %x R3 %x\n", r
[0], r
[1], r
[2]);
470 /* Return MAC with concatenated VID ac concatenated ID */
471 return rtl839x_l2_hash_seed(ether_addr_to_u64(&e
->mac
[0]), e
->rvid
);
474 static void rtl839x_write_cam(int idx
, struct rtl838x_l2_entry
*e
)
477 struct table_reg
*q
= rtl_table_get(RTL8390_TBL_L2
, 1); /* Access L2 Table 1 */
479 rtl839x_fill_l2_row(r
, e
);
481 for (int i
= 0; i
< 3; i
++)
482 sw_w32(r
[i
], rtl_table_data(q
, i
));
484 rtl_table_write(q
, idx
);
485 rtl_table_release(q
);
488 static u64
rtl839x_read_mcast_pmask(int idx
)
491 /* Read MC_PMSK (2) via register RTL8390_TBL_L2 */
492 struct table_reg
*q
= rtl_table_get(RTL8390_TBL_L2
, 2);
494 rtl_table_read(q
, idx
);
495 portmask
= sw_r32(rtl_table_data(q
, 0));
497 portmask
|= sw_r32(rtl_table_data(q
, 1));
498 portmask
>>= 11; /* LSB is bit 11 in data registers */
499 rtl_table_release(q
);
504 static void rtl839x_write_mcast_pmask(int idx
, u64 portmask
)
506 /* Access MC_PMSK (2) via register RTL8380_TBL_L2 */
507 struct table_reg
*q
= rtl_table_get(RTL8390_TBL_L2
, 2);
509 portmask
<<= 11; /* LSB is bit 11 in data registers */
510 sw_w32((u32
)(portmask
>> 32), rtl_table_data(q
, 0));
511 sw_w32((u32
)((portmask
& 0xfffff800)), rtl_table_data(q
, 1));
512 rtl_table_write(q
, idx
);
513 rtl_table_release(q
);
516 static void rtl839x_vlan_profile_setup(int profile
)
519 u32 pmask_id
= UNKNOWN_MC_PMASK
;
521 p
[0] = pmask_id
; /* Use portmaks 0xfff for unknown IPv6 MC flooding */
522 /* Enable L2 Learning BIT 0, portmask UNKNOWN_MC_PMASK for IP/L2-MC traffic flooding */
523 p
[1] = 1 | pmask_id
<< 1 | pmask_id
<< 13;
525 sw_w32(p
[0], RTL839X_VLAN_PROFILE(profile
));
526 sw_w32(p
[1], RTL839X_VLAN_PROFILE(profile
) + 4);
528 rtl839x_write_mcast_pmask(UNKNOWN_MC_PMASK
, 0x001fffffffffffff);
531 u64
rtl839x_traffic_get(int source
)
533 return rtl839x_get_port_reg_be(rtl839x_port_iso_ctrl(source
));
536 void rtl839x_traffic_set(int source
, u64 dest_matrix
)
538 rtl839x_set_port_reg_be(dest_matrix
, rtl839x_port_iso_ctrl(source
));
541 void rtl839x_traffic_enable(int source
, int dest
)
543 rtl839x_mask_port_reg_be(0, BIT_ULL(dest
), rtl839x_port_iso_ctrl(source
));
546 void rtl839x_traffic_disable(int source
, int dest
)
548 rtl839x_mask_port_reg_be(BIT_ULL(dest
), 0, rtl839x_port_iso_ctrl(source
));
551 static void rtl839x_l2_learning_setup(void)
553 /* Set portmask for broadcast (offset bit 12) and unknown unicast (offset 0)
554 * address flooding to the reserved entry in the portmask table used
555 * also for multicast flooding */
556 sw_w32(UNKNOWN_MC_PMASK
<< 12 | UNKNOWN_MC_PMASK
, RTL839X_L2_FLD_PMSK
);
558 /* Limit learning to maximum: 32k entries, after that just flood (bits 0-1) */
559 sw_w32((0x7fff << 2) | 0, RTL839X_L2_LRN_CONSTRT
);
561 /* Do not trap ARP packets to CPU_PORT */
562 sw_w32(0, RTL839X_SPCL_TRAP_ARP_CTRL
);
565 static void rtl839x_enable_learning(int port
, bool enable
)
567 /* Limit learning to maximum: 32k entries */
569 sw_w32_mask(0x7fff << 2, enable
? (0x7fff << 2) : 0,
570 RTL839X_L2_PORT_LRN_CONSTRT
+ (port
<< 2));
573 static void rtl839x_enable_flood(int port
, bool enable
)
580 sw_w32_mask(0x3, enable
? 0 : 1,
581 RTL839X_L2_PORT_LRN_CONSTRT
+ (port
<< 2));
584 static void rtl839x_enable_mcast_flood(int port
, bool enable
)
589 static void rtl839x_enable_bcast_flood(int port
, bool enable
)
594 static void rtl839x_set_static_move_action(int port
, bool forward
)
596 int shift
= MV_ACT_PORT_SHIFT(port
);
597 u32 val
= forward
? MV_ACT_FORWARD
: MV_ACT_DROP
;
599 sw_w32_mask(MV_ACT_MASK
<< shift
, val
<< shift
,
600 RTL839X_L2_PORT_STATIC_MV_ACT(port
));
603 irqreturn_t
rtl839x_switch_irq(int irq
, void *dev_id
)
605 struct dsa_switch
*ds
= dev_id
;
606 u32 status
= sw_r32(RTL839X_ISR_GLB_SRC
);
607 u64 ports
= rtl839x_get_port_reg_le(RTL839X_ISR_PORT_LINK_STS_CHG
);
611 rtl839x_set_port_reg_le(ports
, RTL839X_ISR_PORT_LINK_STS_CHG
);
612 pr_debug("RTL8390 Link change: status: %x, ports %llx\n", status
, ports
);
614 for (int i
= 0; i
< RTL839X_CPU_PORT
; i
++) {
615 if (ports
& BIT_ULL(i
)) {
616 link
= rtl839x_get_port_reg_le(RTL839X_MAC_LINK_STS
);
617 if (link
& BIT_ULL(i
))
618 dsa_port_phylink_mac_change(ds
, i
, true);
620 dsa_port_phylink_mac_change(ds
, i
, false);
628 int rtl8390_sds_power(int mac
, int val
)
630 u32 offset
= (mac
== 48) ? 0x0 : 0x100;
631 u32 mode
= val
? 0 : 1;
633 pr_debug("In %s: mac %d, set %d\n", __func__
, mac
, val
);
635 if ((mac
!= 48) && (mac
!= 49)) {
636 pr_err("%s: not an SFP port: %d\n", __func__
, mac
);
640 /* Set bit 1003. 1000 starts at 7c */
641 sw_w32_mask(BIT(11), mode
<< 11, RTL839X_SDS12_13_PWR0
+ offset
);
646 static int rtl839x_smi_wait_op(int timeout
)
651 ret
= readx_poll_timeout(sw_r32
, RTL839X_PHYREG_ACCESS_CTRL
,
652 val
, !(val
& 0x1), 20, timeout
);
654 pr_err("%s: timeout\n", __func__
);
659 int rtl839x_read_phy(u32 port
, u32 page
, u32 reg
, u32
*val
)
664 if (port
> 63 || page
> 4095 || reg
> 31)
667 /* Take bug on RTL839x Rev <= C into account */
668 if (port
>= RTL839X_CPU_PORT
)
671 mutex_lock(&smi_lock
);
673 sw_w32_mask(0xffff0000, port
<< 16, RTL839X_PHYREG_DATA_CTRL
);
674 v
= reg
<< 5 | page
<< 10 | ((page
== 0x1fff) ? 0x1f : 0) << 23;
675 sw_w32(v
, RTL839X_PHYREG_ACCESS_CTRL
);
677 sw_w32(0x1ff, RTL839X_PHYREG_CTRL
);
680 sw_w32(v
, RTL839X_PHYREG_ACCESS_CTRL
);
682 err
= rtl839x_smi_wait_op(100000);
686 *val
= sw_r32(RTL839X_PHYREG_DATA_CTRL
) & 0xffff;
689 mutex_unlock(&smi_lock
);
694 int rtl839x_write_phy(u32 port
, u32 page
, u32 reg
, u32 val
)
700 if (port
> 63 || page
> 4095 || reg
> 31)
703 /* Take bug on RTL839x Rev <= C into account */
704 if (port
>= RTL839X_CPU_PORT
)
707 mutex_lock(&smi_lock
);
709 /* Set PHY to access */
710 rtl839x_set_port_reg_le(BIT_ULL(port
), RTL839X_PHYREG_PORT_CTRL
);
712 sw_w32_mask(0xffff0000, val
<< 16, RTL839X_PHYREG_DATA_CTRL
);
714 v
= reg
<< 5 | page
<< 10 | ((page
== 0x1fff) ? 0x1f : 0) << 23;
715 sw_w32(v
, RTL839X_PHYREG_ACCESS_CTRL
);
717 sw_w32(0x1ff, RTL839X_PHYREG_CTRL
);
719 v
|= BIT(3) | 1; /* Write operation and execute */
720 sw_w32(v
, RTL839X_PHYREG_ACCESS_CTRL
);
722 err
= rtl839x_smi_wait_op(100000);
726 if (sw_r32(RTL839X_PHYREG_ACCESS_CTRL
) & 0x2)
730 mutex_unlock(&smi_lock
);
735 /* Read an mmd register of the PHY */
736 int rtl839x_read_mmd_phy(u32 port
, u32 devnum
, u32 regnum
, u32
*val
)
741 /* Take bug on RTL839x Rev <= C into account */
742 if (port
>= RTL839X_CPU_PORT
)
745 mutex_lock(&smi_lock
);
747 /* Set PHY to access */
748 sw_w32_mask(0xffff << 16, port
<< 16, RTL839X_PHYREG_DATA_CTRL
);
750 /* Set MMD device number and register to write to */
751 sw_w32(devnum
<< 16 | (regnum
& 0xffff), RTL839X_PHYREG_MMD_CTRL
);
753 v
= BIT(2) | BIT(0); /* MMD-access | EXEC */
754 sw_w32(v
, RTL839X_PHYREG_ACCESS_CTRL
);
756 err
= rtl839x_smi_wait_op(100000);
760 /* There is no error-checking via BIT 1 of v, as it does not seem to be set correctly */
761 *val
= (sw_r32(RTL839X_PHYREG_DATA_CTRL
) & 0xffff);
762 pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__
, port
, regnum
, *val
, err
);
765 mutex_unlock(&smi_lock
);
770 /* Write to an mmd register of the PHY */
771 int rtl839x_write_mmd_phy(u32 port
, u32 devnum
, u32 regnum
, u32 val
)
776 /* Take bug on RTL839x Rev <= C into account */
777 if (port
>= RTL839X_CPU_PORT
)
780 mutex_lock(&smi_lock
);
782 /* Set PHY to access */
783 rtl839x_set_port_reg_le(BIT_ULL(port
), RTL839X_PHYREG_PORT_CTRL
);
785 /* Set data to write */
786 sw_w32_mask(0xffff << 16, val
<< 16, RTL839X_PHYREG_DATA_CTRL
);
788 /* Set MMD device number and register to write to */
789 sw_w32(devnum
<< 16 | (regnum
& 0xffff), RTL839X_PHYREG_MMD_CTRL
);
791 v
= BIT(3) | BIT(2) | BIT(0); /* WRITE | MMD-access | EXEC */
792 sw_w32(v
, RTL839X_PHYREG_ACCESS_CTRL
);
794 err
= rtl839x_smi_wait_op(100000);
798 pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__
, port
, regnum
, val
, err
);
801 mutex_unlock(&smi_lock
);
806 void rtl8390_get_version(struct rtl838x_switch_priv
*priv
)
810 sw_w32_mask(0xf << 28, 0xa << 28, RTL839X_CHIP_INFO
);
811 info
= sw_r32(RTL839X_CHIP_INFO
);
813 model
= sw_r32(RTL839X_MODEL_NAME_INFO
);
814 priv
->version
= RTL8390_VERSION_A
+ ((model
& 0x3f) >> 1);
816 pr_info("RTL839X Chip-Info: %x, version %c\n", info
, priv
->version
);
819 void rtl839x_vlan_profile_dump(int profile
)
823 if (profile
< 0 || profile
> 7)
826 p
[0] = sw_r32(RTL839X_VLAN_PROFILE(profile
));
827 p
[1] = sw_r32(RTL839X_VLAN_PROFILE(profile
) + 4);
829 pr_info("VLAN profile %d: L2 learning: %d, UNKN L2MC FLD PMSK %d, \
830 UNKN IPMC FLD PMSK %d, UNKN IPv6MC FLD PMSK: %d",
831 profile
, p
[1] & 1, (p
[1] >> 1) & 0xfff, (p
[1] >> 13) & 0xfff,
833 pr_info("VLAN profile %d: raw %08x, %08x\n", profile
, p
[0], p
[1]);
836 static void rtl839x_stp_get(struct rtl838x_switch_priv
*priv
, u16 msti
, u32 port_state
[])
838 u32 cmd
= 1 << 16 | /* Execute cmd */
840 5 << 12 | /* Table type 0b101 */
842 priv
->r
->exec_tbl0_cmd(cmd
);
844 for (int i
= 0; i
< 4; i
++)
845 port_state
[i
] = sw_r32(priv
->r
->tbl_access_data_0(i
));
848 static void rtl839x_stp_set(struct rtl838x_switch_priv
*priv
, u16 msti
, u32 port_state
[])
850 u32 cmd
= 1 << 16 | /* Execute cmd */
851 1 << 15 | /* Write */
852 5 << 12 | /* Table type 0b101 */
854 for (int i
= 0; i
< 4; i
++)
855 sw_w32(port_state
[i
], priv
->r
->tbl_access_data_0(i
));
856 priv
->r
->exec_tbl0_cmd(cmd
);
859 /* Enables or disables the EEE/EEEP capability of a port */
860 void rtl839x_port_eee_set(struct rtl838x_switch_priv
*priv
, int port
, bool enable
)
864 /* This works only for Ethernet ports, and on the RTL839X, ports above 47 are SFP */
869 pr_debug("In %s: setting port %d to %d\n", __func__
, port
, enable
);
870 v
= enable
? 0xf : 0x0;
872 /* Set EEE for 100, 500, 1000MBit and 10GBit */
873 sw_w32_mask(0xf << 8, v
<< 8, rtl839x_mac_force_mode_ctrl(port
));
875 /* Set TX/RX EEE state */
876 v
= enable
? 0x3 : 0x0;
877 sw_w32(v
, RTL839X_EEE_CTRL(port
));
879 priv
->ports
[port
].eee_enabled
= enable
;
882 /* Get EEE own capabilities and negotiation result */
883 int rtl839x_eee_port_ability(struct rtl838x_switch_priv
*priv
, struct ethtool_eee
*e
, int port
)
890 link
= rtl839x_get_port_reg_le(RTL839X_MAC_LINK_STS
);
891 if (!(link
& BIT_ULL(port
)))
894 if (sw_r32(rtl839x_mac_force_mode_ctrl(port
)) & BIT(8))
895 e
->advertised
|= ADVERTISED_100baseT_Full
;
897 if (sw_r32(rtl839x_mac_force_mode_ctrl(port
)) & BIT(10))
898 e
->advertised
|= ADVERTISED_1000baseT_Full
;
900 a
= rtl839x_get_port_reg_le(RTL839X_MAC_EEE_ABLTY
);
901 pr_info("Link partner: %016llx\n", a
);
902 if (rtl839x_get_port_reg_le(RTL839X_MAC_EEE_ABLTY
) & BIT_ULL(port
)) {
903 e
->lp_advertised
= ADVERTISED_100baseT_Full
;
904 e
->lp_advertised
|= ADVERTISED_1000baseT_Full
;
911 static void rtl839x_init_eee(struct rtl838x_switch_priv
*priv
, bool enable
)
913 pr_info("Setting up EEE, state: %d\n", enable
);
915 /* Set wake timer for TX and pause timer both to 0x21 */
916 sw_w32_mask(0xff << 20| 0xff, 0x21 << 20| 0x21, RTL839X_EEE_TX_TIMER_GELITE_CTRL
);
917 /* Set pause wake timer for GIGA-EEE to 0x11 */
918 sw_w32_mask(0xff << 20, 0x11 << 20, RTL839X_EEE_TX_TIMER_GIGA_CTRL
);
919 /* Set pause wake timer for 10GBit ports to 0x11 */
920 sw_w32_mask(0xff << 20, 0x11 << 20, RTL839X_EEE_TX_TIMER_10G_CTRL
);
922 /* Setup EEE on all ports */
923 for (int i
= 0; i
< priv
->cpu_port
; i
++) {
924 if (priv
->ports
[i
].phy
)
925 rtl839x_port_eee_set(priv
, i
, enable
);
927 priv
->eee_enabled
= enable
;
930 static void rtl839x_pie_lookup_enable(struct rtl838x_switch_priv
*priv
, int index
)
932 int block
= index
/ PIE_BLOCK_SIZE
;
934 sw_w32_mask(0, BIT(block
), RTL839X_ACL_BLK_LOOKUP_CTRL
);
937 /* Delete a range of Packet Inspection Engine rules */
938 static int rtl839x_pie_rule_del(struct rtl838x_switch_priv
*priv
, int index_from
, int index_to
)
940 u32 v
= (index_from
<< 1)| (index_to
<< 13 ) | BIT(0);
942 pr_debug("%s: from %d to %d\n", __func__
, index_from
, index_to
);
943 mutex_lock(&priv
->reg_mutex
);
945 /* Write from-to and execute bit into control register */
946 sw_w32(v
, RTL839X_ACL_CLR_CTRL
);
948 /* Wait until command has completed */
950 } while (sw_r32(RTL839X_ACL_CLR_CTRL
) & BIT(0));
952 mutex_unlock(&priv
->reg_mutex
);
957 /* Reads the intermediate representation of the templated match-fields of the
958 * PIE rule in the pie_rule structure and fills in the raw data fields in the
959 * raw register space r[].
960 * The register space configuration size is identical for the RTL8380/90 and RTL9300,
961 * however the RTL9310 has 2 more registers / fields and the physical field-ids are different
963 * On the RTL8390 the template mask registers are not word-aligned!
965 static void rtl839x_write_pie_templated(u32 r
[], struct pie_rule
*pr
, enum template_field_id t
[])
967 for (int i
= 0; i
< N_FIXED_FIELDS
; i
++) {
968 enum template_field_id field_type
= t
[i
];
969 u16 data
= 0, data_m
= 0;
971 switch (field_type
) {
972 case TEMPLATE_FIELD_SPM0
:
976 case TEMPLATE_FIELD_SPM1
:
977 data
= pr
->spm
>> 16;
978 data_m
= pr
->spm_m
>> 16;
980 case TEMPLATE_FIELD_SPM2
:
981 data
= pr
->spm
>> 32;
982 data_m
= pr
->spm_m
>> 32;
984 case TEMPLATE_FIELD_SPM3
:
985 data
= pr
->spm
>> 48;
986 data_m
= pr
->spm_m
>> 48;
988 case TEMPLATE_FIELD_OTAG
:
992 case TEMPLATE_FIELD_SMAC0
:
994 data
= (data
<< 8) | pr
->smac
[5];
995 data_m
= pr
->smac_m
[4];
996 data_m
= (data_m
<< 8) | pr
->smac_m
[5];
998 case TEMPLATE_FIELD_SMAC1
:
1000 data
= (data
<< 8) | pr
->smac
[3];
1001 data_m
= pr
->smac_m
[2];
1002 data_m
= (data_m
<< 8) | pr
->smac_m
[3];
1004 case TEMPLATE_FIELD_SMAC2
:
1006 data
= (data
<< 8) | pr
->smac
[1];
1007 data_m
= pr
->smac_m
[0];
1008 data_m
= (data_m
<< 8) | pr
->smac_m
[1];
1010 case TEMPLATE_FIELD_DMAC0
:
1012 data
= (data
<< 8) | pr
->dmac
[5];
1013 data_m
= pr
->dmac_m
[4];
1014 data_m
= (data_m
<< 8) | pr
->dmac_m
[5];
1016 case TEMPLATE_FIELD_DMAC1
:
1018 data
= (data
<< 8) | pr
->dmac
[3];
1019 data_m
= pr
->dmac_m
[2];
1020 data_m
= (data_m
<< 8) | pr
->dmac_m
[3];
1022 case TEMPLATE_FIELD_DMAC2
:
1024 data
= (data
<< 8) | pr
->dmac
[1];
1025 data_m
= pr
->dmac_m
[0];
1026 data_m
= (data_m
<< 8) | pr
->dmac_m
[1];
1028 case TEMPLATE_FIELD_ETHERTYPE
:
1029 data
= pr
->ethertype
;
1030 data_m
= pr
->ethertype_m
;
1032 case TEMPLATE_FIELD_ITAG
:
1034 data_m
= pr
->itag_m
;
1036 case TEMPLATE_FIELD_SIP0
:
1038 data
= pr
->sip6
.s6_addr16
[7];
1039 data_m
= pr
->sip6_m
.s6_addr16
[7];
1045 case TEMPLATE_FIELD_SIP1
:
1047 data
= pr
->sip6
.s6_addr16
[6];
1048 data_m
= pr
->sip6_m
.s6_addr16
[6];
1050 data
= pr
->sip
>> 16;
1051 data_m
= pr
->sip_m
>> 16;
1054 case TEMPLATE_FIELD_SIP2
:
1055 case TEMPLATE_FIELD_SIP3
:
1056 case TEMPLATE_FIELD_SIP4
:
1057 case TEMPLATE_FIELD_SIP5
:
1058 case TEMPLATE_FIELD_SIP6
:
1059 case TEMPLATE_FIELD_SIP7
:
1060 data
= pr
->sip6
.s6_addr16
[5 - (field_type
- TEMPLATE_FIELD_SIP2
)];
1061 data_m
= pr
->sip6_m
.s6_addr16
[5 - (field_type
- TEMPLATE_FIELD_SIP2
)];
1063 case TEMPLATE_FIELD_DIP0
:
1065 data
= pr
->dip6
.s6_addr16
[7];
1066 data_m
= pr
->dip6_m
.s6_addr16
[7];
1072 case TEMPLATE_FIELD_DIP1
:
1074 data
= pr
->dip6
.s6_addr16
[6];
1075 data_m
= pr
->dip6_m
.s6_addr16
[6];
1077 data
= pr
->dip
>> 16;
1078 data_m
= pr
->dip_m
>> 16;
1081 case TEMPLATE_FIELD_DIP2
:
1082 case TEMPLATE_FIELD_DIP3
:
1083 case TEMPLATE_FIELD_DIP4
:
1084 case TEMPLATE_FIELD_DIP5
:
1085 case TEMPLATE_FIELD_DIP6
:
1086 case TEMPLATE_FIELD_DIP7
:
1087 data
= pr
->dip6
.s6_addr16
[5 - (field_type
- TEMPLATE_FIELD_DIP2
)];
1088 data_m
= pr
->dip6_m
.s6_addr16
[5 - (field_type
- TEMPLATE_FIELD_DIP2
)];
1090 case TEMPLATE_FIELD_IP_TOS_PROTO
:
1091 data
= pr
->tos_proto
;
1092 data_m
= pr
->tos_proto_m
;
1094 case TEMPLATE_FIELD_L4_SPORT
:
1096 data_m
= pr
->sport_m
;
1098 case TEMPLATE_FIELD_L4_DPORT
:
1100 data_m
= pr
->dport_m
;
1102 case TEMPLATE_FIELD_ICMP_IGMP
:
1103 data
= pr
->icmp_igmp
;
1104 data_m
= pr
->icmp_igmp_m
;
1107 pr_info("%s: unknown field %d\n", __func__
, field_type
);
1110 /* On the RTL8390, the mask fields are not word aligned! */
1112 r
[5 - i
/ 2] = data
;
1113 r
[12 - i
/ 2] |= ((u32
)data_m
<< 8);
1115 r
[5 - i
/ 2] |= ((u32
)data
) << 16;
1116 r
[12 - i
/ 2] |= ((u32
)data_m
) << 24;
1117 r
[11 - i
/ 2] |= ((u32
)data_m
) >> 8;
1122 /* Creates the intermediate representation of the templated match-fields of the
1123 * PIE rule in the pie_rule structure by reading the raw data fields in the
1124 * raw register space r[].
1125 * The register space configuration size is identical for the RTL8380/90 and RTL9300,
1126 * however the RTL9310 has 2 more registers / fields and the physical field-ids
1127 * On the RTL8390 the template mask registers are not word-aligned!
1129 void rtl839x_read_pie_templated(u32 r
[], struct pie_rule
*pr
, enum template_field_id t
[])
1131 for (int i
= 0; i
< N_FIXED_FIELDS
; i
++) {
1132 enum template_field_id field_type
= t
[i
];
1136 data
= r
[5 - i
/ 2];
1137 data_m
= r
[12 - i
/ 2];
1139 data
= r
[5 - i
/ 2] >> 16;
1140 data_m
= r
[12 - i
/ 2] >> 16;
1143 switch (field_type
) {
1144 case TEMPLATE_FIELD_SPM0
:
1145 pr
->spm
= (pr
->spn
<< 16) | data
;
1146 pr
->spm_m
= (pr
->spn
<< 16) | data_m
;
1148 case TEMPLATE_FIELD_SPM1
:
1152 case TEMPLATE_FIELD_OTAG
:
1154 pr
->otag_m
= data_m
;
1156 case TEMPLATE_FIELD_SMAC0
:
1157 pr
->smac
[4] = data
>> 8;
1159 pr
->smac_m
[4] = data
>> 8;
1160 pr
->smac_m
[5] = data
;
1162 case TEMPLATE_FIELD_SMAC1
:
1163 pr
->smac
[2] = data
>> 8;
1165 pr
->smac_m
[2] = data
>> 8;
1166 pr
->smac_m
[3] = data
;
1168 case TEMPLATE_FIELD_SMAC2
:
1169 pr
->smac
[0] = data
>> 8;
1171 pr
->smac_m
[0] = data
>> 8;
1172 pr
->smac_m
[1] = data
;
1174 case TEMPLATE_FIELD_DMAC0
:
1175 pr
->dmac
[4] = data
>> 8;
1177 pr
->dmac_m
[4] = data
>> 8;
1178 pr
->dmac_m
[5] = data
;
1180 case TEMPLATE_FIELD_DMAC1
:
1181 pr
->dmac
[2] = data
>> 8;
1183 pr
->dmac_m
[2] = data
>> 8;
1184 pr
->dmac_m
[3] = data
;
1186 case TEMPLATE_FIELD_DMAC2
:
1187 pr
->dmac
[0] = data
>> 8;
1189 pr
->dmac_m
[0] = data
>> 8;
1190 pr
->dmac_m
[1] = data
;
1192 case TEMPLATE_FIELD_ETHERTYPE
:
1193 pr
->ethertype
= data
;
1194 pr
->ethertype_m
= data_m
;
1196 case TEMPLATE_FIELD_ITAG
:
1198 pr
->itag_m
= data_m
;
1200 case TEMPLATE_FIELD_SIP0
:
1204 case TEMPLATE_FIELD_SIP1
:
1205 pr
->sip
= (pr
->sip
<< 16) | data
;
1206 pr
->sip_m
= (pr
->sip
<< 16) | data_m
;
1208 case TEMPLATE_FIELD_SIP2
:
1210 /* Make use of limitiations on the position of the match values */
1211 ipv6_addr_set(&pr
->sip6
, pr
->sip
, r
[5 - i
/ 2],
1212 r
[4 - i
/ 2], r
[3 - i
/ 2]);
1213 ipv6_addr_set(&pr
->sip6_m
, pr
->sip_m
, r
[5 - i
/ 2],
1214 r
[4 - i
/ 2], r
[3 - i
/ 2]);
1215 case TEMPLATE_FIELD_SIP3
:
1216 case TEMPLATE_FIELD_SIP4
:
1217 case TEMPLATE_FIELD_SIP5
:
1218 case TEMPLATE_FIELD_SIP6
:
1219 case TEMPLATE_FIELD_SIP7
:
1222 case TEMPLATE_FIELD_DIP0
:
1227 case TEMPLATE_FIELD_DIP1
:
1228 pr
->dip
= (pr
->dip
<< 16) | data
;
1229 pr
->dip_m
= (pr
->dip
<< 16) | data_m
;
1232 case TEMPLATE_FIELD_DIP2
:
1234 ipv6_addr_set(&pr
->dip6
, pr
->dip
, r
[5 - i
/ 2],
1235 r
[4 - i
/ 2], r
[3 - i
/ 2]);
1236 ipv6_addr_set(&pr
->dip6_m
, pr
->dip_m
, r
[5 - i
/ 2],
1237 r
[4 - i
/ 2], r
[3 - i
/ 2]);
1238 case TEMPLATE_FIELD_DIP3
:
1239 case TEMPLATE_FIELD_DIP4
:
1240 case TEMPLATE_FIELD_DIP5
:
1241 case TEMPLATE_FIELD_DIP6
:
1242 case TEMPLATE_FIELD_DIP7
:
1244 case TEMPLATE_FIELD_IP_TOS_PROTO
:
1245 pr
->tos_proto
= data
;
1246 pr
->tos_proto_m
= data_m
;
1248 case TEMPLATE_FIELD_L4_SPORT
:
1250 pr
->sport_m
= data_m
;
1252 case TEMPLATE_FIELD_L4_DPORT
:
1254 pr
->dport_m
= data_m
;
1256 case TEMPLATE_FIELD_ICMP_IGMP
:
1257 pr
->icmp_igmp
= data
;
1258 pr
->icmp_igmp_m
= data_m
;
1261 pr_info("%s: unknown field %d\n", __func__
, field_type
);
1266 static void rtl839x_read_pie_fixed_fields(u32 r
[], struct pie_rule
*pr
)
1268 pr
->spmmask_fix
= (r
[6] >> 30) & 0x3;
1269 pr
->spn
= (r
[6] >> 24) & 0x3f;
1270 pr
->mgnt_vlan
= (r
[6] >> 23) & 1;
1271 pr
->dmac_hit_sw
= (r
[6] >> 22) & 1;
1272 pr
->not_first_frag
= (r
[6] >> 21) & 1;
1273 pr
->frame_type_l4
= (r
[6] >> 18) & 7;
1274 pr
->frame_type
= (r
[6] >> 16) & 3;
1275 pr
->otag_fmt
= (r
[6] >> 15) & 1;
1276 pr
->itag_fmt
= (r
[6] >> 14) & 1;
1277 pr
->otag_exist
= (r
[6] >> 13) & 1;
1278 pr
->itag_exist
= (r
[6] >> 12) & 1;
1279 pr
->frame_type_l2
= (r
[6] >> 10) & 3;
1280 pr
->tid
= (r
[6] >> 8) & 3;
1282 pr
->spmmask_fix_m
= (r
[12] >> 6) & 0x3;
1283 pr
->spn_m
= r
[12] & 0x3f;
1284 pr
->mgnt_vlan_m
= (r
[13] >> 31) & 1;
1285 pr
->dmac_hit_sw_m
= (r
[13] >> 30) & 1;
1286 pr
->not_first_frag_m
= (r
[13] >> 29) & 1;
1287 pr
->frame_type_l4_m
= (r
[13] >> 26) & 7;
1288 pr
->frame_type_m
= (r
[13] >> 24) & 3;
1289 pr
->otag_fmt_m
= (r
[13] >> 23) & 1;
1290 pr
->itag_fmt_m
= (r
[13] >> 22) & 1;
1291 pr
->otag_exist_m
= (r
[13] >> 21) & 1;
1292 pr
->itag_exist_m
= (r
[13] >> 20) & 1;
1293 pr
->frame_type_l2_m
= (r
[13] >> 18) & 3;
1294 pr
->tid_m
= (r
[13] >> 16) & 3;
1296 pr
->valid
= r
[13] & BIT(15);
1297 pr
->cond_not
= r
[13] & BIT(14);
1298 pr
->cond_and1
= r
[13] & BIT(13);
1299 pr
->cond_and2
= r
[13] & BIT(12);
1302 static void rtl839x_write_pie_fixed_fields(u32 r
[], struct pie_rule
*pr
)
1304 r
[6] = ((u32
) (pr
->spmmask_fix
& 0x3)) << 30;
1305 r
[6] |= ((u32
) (pr
->spn
& 0x3f)) << 24;
1306 r
[6] |= pr
->mgnt_vlan
? BIT(23) : 0;
1307 r
[6] |= pr
->dmac_hit_sw
? BIT(22) : 0;
1308 r
[6] |= pr
->not_first_frag
? BIT(21) : 0;
1309 r
[6] |= ((u32
) (pr
->frame_type_l4
& 0x7)) << 18;
1310 r
[6] |= ((u32
) (pr
->frame_type
& 0x3)) << 16;
1311 r
[6] |= pr
->otag_fmt
? BIT(15) : 0;
1312 r
[6] |= pr
->itag_fmt
? BIT(14) : 0;
1313 r
[6] |= pr
->otag_exist
? BIT(13) : 0;
1314 r
[6] |= pr
->itag_exist
? BIT(12) : 0;
1315 r
[6] |= ((u32
) (pr
->frame_type_l2
& 0x3)) << 10;
1316 r
[6] |= ((u32
) (pr
->tid
& 0x3)) << 8;
1318 r
[12] |= ((u32
) (pr
->spmmask_fix_m
& 0x3)) << 6;
1319 r
[12] |= (u32
) (pr
->spn_m
& 0x3f);
1320 r
[13] |= pr
->mgnt_vlan_m
? BIT(31) : 0;
1321 r
[13] |= pr
->dmac_hit_sw_m
? BIT(30) : 0;
1322 r
[13] |= pr
->not_first_frag_m
? BIT(29) : 0;
1323 r
[13] |= ((u32
) (pr
->frame_type_l4_m
& 0x7)) << 26;
1324 r
[13] |= ((u32
) (pr
->frame_type_m
& 0x3)) << 24;
1325 r
[13] |= pr
->otag_fmt_m
? BIT(23) : 0;
1326 r
[13] |= pr
->itag_fmt_m
? BIT(22) : 0;
1327 r
[13] |= pr
->otag_exist_m
? BIT(21) : 0;
1328 r
[13] |= pr
->itag_exist_m
? BIT(20) : 0;
1329 r
[13] |= ((u32
) (pr
->frame_type_l2_m
& 0x3)) << 18;
1330 r
[13] |= ((u32
) (pr
->tid_m
& 0x3)) << 16;
1332 r
[13] |= pr
->valid
? BIT(15) : 0;
1333 r
[13] |= pr
->cond_not
? BIT(14) : 0;
1334 r
[13] |= pr
->cond_and1
? BIT(13) : 0;
1335 r
[13] |= pr
->cond_and2
? BIT(12) : 0;
1338 static void rtl839x_write_pie_action(u32 r
[], struct pie_rule
*pr
)
1341 r
[13] |= 0x9; /* Set ACT_MASK_FWD & FWD_ACT = DROP */
1344 r
[13] |= pr
->fwd_sel
? BIT(3) : 0;
1345 r
[13] |= pr
->fwd_act
;
1347 r
[13] |= pr
->bypass_sel
? BIT(11) : 0;
1348 r
[13] |= pr
->mpls_sel
? BIT(10) : 0;
1349 r
[13] |= pr
->nopri_sel
? BIT(9) : 0;
1350 r
[13] |= pr
->ovid_sel
? BIT(8) : 0;
1351 r
[13] |= pr
->ivid_sel
? BIT(7) : 0;
1352 r
[13] |= pr
->meter_sel
? BIT(6) : 0;
1353 r
[13] |= pr
->mir_sel
? BIT(5) : 0;
1354 r
[13] |= pr
->log_sel
? BIT(4) : 0;
1356 r
[14] |= ((u32
)(pr
->fwd_data
& 0x3fff)) << 18;
1357 r
[14] |= pr
->log_octets
? BIT(17) : 0;
1358 r
[14] |= ((u32
)(pr
->log_data
& 0x7ff)) << 4;
1359 r
[14] |= (pr
->mir_data
& 0x3) << 3;
1360 r
[14] |= ((u32
)(pr
->meter_data
>> 7)) & 0x7;
1361 r
[15] |= (u32
)(pr
->meter_data
) << 26;
1362 r
[15] |= ((u32
)(pr
->ivid_act
) << 23) & 0x3;
1363 r
[15] |= ((u32
)(pr
->ivid_data
) << 9) & 0xfff;
1364 r
[15] |= ((u32
)(pr
->ovid_act
) << 6) & 0x3;
1365 r
[15] |= ((u32
)(pr
->ovid_data
) >> 4) & 0xff;
1366 r
[16] |= ((u32
)(pr
->ovid_data
) & 0xf) << 28;
1367 r
[16] |= ((u32
)(pr
->nopri_data
) & 0x7) << 20;
1368 r
[16] |= ((u32
)(pr
->mpls_act
) & 0x7) << 20;
1369 r
[16] |= ((u32
)(pr
->mpls_lib_idx
) & 0x7) << 20;
1370 r
[16] |= pr
->bypass_all
? BIT(9) : 0;
1371 r
[16] |= pr
->bypass_igr_stp
? BIT(8) : 0;
1372 r
[16] |= pr
->bypass_ibc_sc
? BIT(7) : 0;
1375 static void rtl839x_read_pie_action(u32 r
[], struct pie_rule
*pr
)
1377 if (r
[13] & BIT(3)) { /* ACT_MASK_FWD set, is it a drop? */
1378 if ((r
[14] & 0x7) == 1) {
1382 pr
->fwd_act
= r
[14] & 0x7;
1386 pr
->bypass_sel
= r
[13] & BIT(11);
1387 pr
->mpls_sel
= r
[13] & BIT(10);
1388 pr
->nopri_sel
= r
[13] & BIT(9);
1389 pr
->ovid_sel
= r
[13] & BIT(8);
1390 pr
->ivid_sel
= r
[13] & BIT(7);
1391 pr
->meter_sel
= r
[13] & BIT(6);
1392 pr
->mir_sel
= r
[13] & BIT(5);
1393 pr
->log_sel
= r
[13] & BIT(4);
1395 /* TODO: Read in data fields */
1397 pr
->bypass_all
= r
[16] & BIT(9);
1398 pr
->bypass_igr_stp
= r
[16] & BIT(8);
1399 pr
->bypass_ibc_sc
= r
[16] & BIT(7);
1402 void rtl839x_pie_rule_dump_raw(u32 r
[])
1404 pr_info("Raw IACL table entry:\n");
1405 pr_info("Match : %08x %08x %08x %08x %08x %08x\n", r
[0], r
[1], r
[2], r
[3], r
[4], r
[5]);
1406 pr_info("Fixed : %06x\n", r
[6] >> 8);
1407 pr_info("Match M: %08x %08x %08x %08x %08x %08x\n",
1408 (r
[6] << 24) | (r
[7] >> 8), (r
[7] << 24) | (r
[8] >> 8), (r
[8] << 24) | (r
[9] >> 8),
1409 (r
[9] << 24) | (r
[10] >> 8), (r
[10] << 24) | (r
[11] >> 8),
1410 (r
[11] << 24) | (r
[12] >> 8));
1411 pr_info("R[13]: %08x\n", r
[13]);
1412 pr_info("Fixed M: %06x\n", ((r
[12] << 16) | (r
[13] >> 16)) & 0xffffff);
1413 pr_info("Valid / not / and1 / and2 : %1x\n", (r
[13] >> 12) & 0xf);
1414 pr_info("r 13-16: %08x %08x %08x %08x\n", r
[13], r
[14], r
[15], r
[16]);
1417 void rtl839x_pie_rule_dump(struct pie_rule
*pr
)
1419 pr_info("Drop: %d, fwd: %d, ovid: %d, ivid: %d, flt: %d, log: %d, rmk: %d, meter: %d tagst: %d, mir: %d, nopri: %d, cpupri: %d, otpid: %d, itpid: %d, shape: %d\n",
1420 pr
->drop
, pr
->fwd_sel
, pr
->ovid_sel
, pr
->ivid_sel
, pr
->flt_sel
, pr
->log_sel
, pr
->rmk_sel
, pr
->log_sel
, pr
->tagst_sel
, pr
->mir_sel
, pr
->nopri_sel
,
1421 pr
->cpupri_sel
, pr
->otpid_sel
, pr
->itpid_sel
, pr
->shaper_sel
);
1423 pr_info("FWD: %08x\n", pr
->fwd_data
);
1424 pr_info("TID: %x, %x\n", pr
->tid
, pr
->tid_m
);
1427 static int rtl839x_pie_rule_read(struct rtl838x_switch_priv
*priv
, int idx
, struct pie_rule
*pr
)
1429 /* Read IACL table (2) via register 0 */
1430 struct table_reg
*q
= rtl_table_get(RTL8380_TBL_0
, 2);
1432 int block
= idx
/ PIE_BLOCK_SIZE
;
1433 u32 t_select
= sw_r32(RTL839X_ACL_BLK_TMPLTE_CTRL(block
));
1435 memset(pr
, 0, sizeof(*pr
));
1436 rtl_table_read(q
, idx
);
1437 for (int i
= 0; i
< 17; i
++)
1438 r
[i
] = sw_r32(rtl_table_data(q
, i
));
1440 rtl_table_release(q
);
1442 rtl839x_read_pie_fixed_fields(r
, pr
);
1446 pr_debug("%s: template_selectors %08x, tid: %d\n", __func__
, t_select
, pr
->tid
);
1447 rtl839x_pie_rule_dump_raw(r
);
1449 rtl839x_read_pie_templated(r
, pr
, fixed_templates
[(t_select
>> (pr
->tid
* 3)) & 0x7]);
1451 rtl839x_read_pie_action(r
, pr
);
1456 static int rtl839x_pie_rule_write(struct rtl838x_switch_priv
*priv
, int idx
, struct pie_rule
*pr
)
1458 /* Access IACL table (2) via register 0 */
1459 struct table_reg
*q
= rtl_table_get(RTL8390_TBL_0
, 2);
1461 int block
= idx
/ PIE_BLOCK_SIZE
;
1462 u32 t_select
= sw_r32(RTL839X_ACL_BLK_TMPLTE_CTRL(block
));
1464 pr_debug("%s: %d, t_select: %08x\n", __func__
, idx
, t_select
);
1466 for (int i
= 0; i
< 17; i
++)
1470 rtl_table_write(q
, idx
);
1471 rtl_table_release(q
);
1474 rtl839x_write_pie_fixed_fields(r
, pr
);
1476 pr_debug("%s: template %d\n", __func__
, (t_select
>> (pr
->tid
* 3)) & 0x7);
1477 rtl839x_write_pie_templated(r
, pr
, fixed_templates
[(t_select
>> (pr
->tid
* 3)) & 0x7]);
1479 rtl839x_write_pie_action(r
, pr
);
1481 /* rtl839x_pie_rule_dump_raw(r); */
1483 for (int i
= 0; i
< 17; i
++)
1484 sw_w32(r
[i
], rtl_table_data(q
, i
));
1486 rtl_table_write(q
, idx
);
1487 rtl_table_release(q
);
1492 static bool rtl839x_pie_templ_has(int t
, enum template_field_id field_type
)
1494 for (int i
= 0; i
< N_FIXED_FIELDS
; i
++) {
1495 enum template_field_id ft
= fixed_templates
[t
][i
];
1496 if (field_type
== ft
)
1503 static int rtl839x_pie_verify_template(struct rtl838x_switch_priv
*priv
,
1504 struct pie_rule
*pr
, int t
, int block
)
1508 if (!pr
->is_ipv6
&& pr
->sip_m
&& !rtl839x_pie_templ_has(t
, TEMPLATE_FIELD_SIP0
))
1511 if (!pr
->is_ipv6
&& pr
->dip_m
&& !rtl839x_pie_templ_has(t
, TEMPLATE_FIELD_DIP0
))
1515 if ((pr
->sip6_m
.s6_addr32
[0] ||
1516 pr
->sip6_m
.s6_addr32
[1] ||
1517 pr
->sip6_m
.s6_addr32
[2] ||
1518 pr
->sip6_m
.s6_addr32
[3]) &&
1519 !rtl839x_pie_templ_has(t
, TEMPLATE_FIELD_SIP2
))
1521 if ((pr
->dip6_m
.s6_addr32
[0] ||
1522 pr
->dip6_m
.s6_addr32
[1] ||
1523 pr
->dip6_m
.s6_addr32
[2] ||
1524 pr
->dip6_m
.s6_addr32
[3]) &&
1525 !rtl839x_pie_templ_has(t
, TEMPLATE_FIELD_DIP2
))
1529 if (ether_addr_to_u64(pr
->smac
) && !rtl839x_pie_templ_has(t
, TEMPLATE_FIELD_SMAC0
))
1532 if (ether_addr_to_u64(pr
->dmac
) && !rtl839x_pie_templ_has(t
, TEMPLATE_FIELD_DMAC0
))
1535 /* TODO: Check more */
1537 i
= find_first_zero_bit(&priv
->pie_use_bm
[block
* 4], PIE_BLOCK_SIZE
);
1539 if (i
>= PIE_BLOCK_SIZE
)
1542 return i
+ PIE_BLOCK_SIZE
* block
;
1545 static int rtl839x_pie_rule_add(struct rtl838x_switch_priv
*priv
, struct pie_rule
*pr
)
1547 int idx
, block
, j
, t
;
1549 int max_block
= priv
->n_pie_blocks
/ 2;
1551 if (pr
->is_egress
) {
1552 min_block
= max_block
;
1553 max_block
= priv
->n_pie_blocks
;
1556 mutex_lock(&priv
->pie_mutex
);
1558 for (block
= min_block
; block
< max_block
; block
++) {
1559 for (j
= 0; j
< 2; j
++) {
1560 t
= (sw_r32(RTL839X_ACL_BLK_TMPLTE_CTRL(block
)) >> (j
* 3)) & 0x7;
1561 idx
= rtl839x_pie_verify_template(priv
, pr
, t
, block
);
1569 if (block
>= priv
->n_pie_blocks
) {
1570 mutex_unlock(&priv
->pie_mutex
);
1574 set_bit(idx
, priv
->pie_use_bm
);
1577 pr
->tid
= j
; /* Mapped to template number */
1581 rtl839x_pie_lookup_enable(priv
, idx
);
1582 rtl839x_pie_rule_write(priv
, idx
, pr
);
1584 mutex_unlock(&priv
->pie_mutex
);
1589 static void rtl839x_pie_rule_rm(struct rtl838x_switch_priv
*priv
, struct pie_rule
*pr
)
1593 rtl839x_pie_rule_del(priv
, idx
, idx
);
1594 clear_bit(idx
, priv
->pie_use_bm
);
1597 static void rtl839x_pie_init(struct rtl838x_switch_priv
*priv
)
1599 u32 template_selectors
;
1601 mutex_init(&priv
->pie_mutex
);
1603 /* Power on all PIE blocks */
1604 for (int i
= 0; i
< priv
->n_pie_blocks
; i
++)
1605 sw_w32_mask(0, BIT(i
), RTL839X_PS_ACL_PWR_CTRL
);
1607 /* Set ingress and egress ACL blocks to 50/50: first Egress block is 9 */
1608 sw_w32_mask(0x1f, 9, RTL839X_ACL_CTRL
); /* Writes 9 to cutline field */
1610 /* Include IPG in metering */
1611 sw_w32(1, RTL839X_METER_GLB_CTRL
);
1613 /* Delete all present rules */
1614 rtl839x_pie_rule_del(priv
, 0, priv
->n_pie_blocks
* PIE_BLOCK_SIZE
- 1);
1616 /* Enable predefined templates 0, 1 for blocks 0-2 */
1617 template_selectors
= 0 | (1 << 3);
1618 for (int i
= 0; i
< 3; i
++)
1619 sw_w32(template_selectors
, RTL839X_ACL_BLK_TMPLTE_CTRL(i
));
1621 /* Enable predefined templates 2, 3 for blocks 3-5 */
1622 template_selectors
= 2 | (3 << 3);
1623 for (int i
= 3; i
< 6; i
++)
1624 sw_w32(template_selectors
, RTL839X_ACL_BLK_TMPLTE_CTRL(i
));
1626 /* Enable predefined templates 1, 4 for blocks 6-8 */
1627 template_selectors
= 2 | (3 << 3);
1628 for (int i
= 6; i
< 9; i
++)
1629 sw_w32(template_selectors
, RTL839X_ACL_BLK_TMPLTE_CTRL(i
));
1631 /* Enable predefined templates 0, 1 for blocks 9-11 */
1632 template_selectors
= 0 | (1 << 3);
1633 for (int i
= 9; i
< 12; i
++)
1634 sw_w32(template_selectors
, RTL839X_ACL_BLK_TMPLTE_CTRL(i
));
1636 /* Enable predefined templates 2, 3 for blocks 12-14 */
1637 template_selectors
= 2 | (3 << 3);
1638 for (int i
= 12; i
< 15; i
++)
1639 sw_w32(template_selectors
, RTL839X_ACL_BLK_TMPLTE_CTRL(i
));
1641 /* Enable predefined templates 1, 4 for blocks 15-17 */
1642 template_selectors
= 2 | (3 << 3);
1643 for (int i
= 15; i
< 18; i
++)
1644 sw_w32(template_selectors
, RTL839X_ACL_BLK_TMPLTE_CTRL(i
));
1647 static u32
rtl839x_packet_cntr_read(int counter
)
1651 /* Read LOG table (4) via register RTL8390_TBL_0 */
1652 struct table_reg
*r
= rtl_table_get(RTL8390_TBL_0
, 4);
1654 pr_debug("In %s, id %d\n", __func__
, counter
);
1655 rtl_table_read(r
, counter
/ 2);
1657 /* The table has a size of 2 registers */
1659 v
= sw_r32(rtl_table_data(r
, 0));
1661 v
= sw_r32(rtl_table_data(r
, 1));
1663 rtl_table_release(r
);
1668 static void rtl839x_packet_cntr_clear(int counter
)
1670 /* Access LOG table (4) via register RTL8390_TBL_0 */
1671 struct table_reg
*r
= rtl_table_get(RTL8390_TBL_0
, 4);
1673 pr_debug("In %s, id %d\n", __func__
, counter
);
1674 /* The table has a size of 2 registers */
1676 sw_w32(0, rtl_table_data(r
, 0));
1678 sw_w32(0, rtl_table_data(r
, 1));
1680 rtl_table_write(r
, counter
/ 2);
1682 rtl_table_release(r
);
1685 static void rtl839x_route_read(int idx
, struct rtl83xx_route
*rt
)
1688 /* Read ROUTING table (2) via register RTL8390_TBL_1 */
1689 struct table_reg
*r
= rtl_table_get(RTL8390_TBL_1
, 2);
1691 pr_debug("In %s\n", __func__
);
1692 rtl_table_read(r
, idx
);
1694 /* The table has a size of 2 registers */
1695 v
= sw_r32(rtl_table_data(r
, 0));
1697 v
|= sw_r32(rtl_table_data(r
, 1));
1698 rt
->switch_mac_id
= (v
>> 12) & 0xf;
1699 rt
->nh
.gw
= v
>> 16;
1701 rtl_table_release(r
);
1704 static void rtl839x_route_write(int idx
, struct rtl83xx_route
*rt
)
1708 /* Read ROUTING table (2) via register RTL8390_TBL_1 */
1709 struct table_reg
*r
= rtl_table_get(RTL8390_TBL_1
, 2);
1711 pr_debug("In %s\n", __func__
);
1712 sw_w32(rt
->nh
.gw
>> 16, rtl_table_data(r
, 0));
1713 v
= rt
->nh
.gw
<< 16;
1714 v
|= rt
->switch_mac_id
<< 12;
1715 sw_w32(v
, rtl_table_data(r
, 1));
1716 rtl_table_write(r
, idx
);
1718 rtl_table_release(r
);
1721 /* Configure the switch's own MAC addresses used when routing packets */
1722 static void rtl839x_setup_port_macs(struct rtl838x_switch_priv
*priv
)
1724 struct net_device
*dev
;
1727 pr_debug("%s: got port %08x\n", __func__
, (u32
)priv
->ports
[priv
->cpu_port
].dp
);
1728 dev
= priv
->ports
[priv
->cpu_port
].dp
->slave
;
1729 mac
= ether_addr_to_u64(dev
->dev_addr
);
1731 for (int i
= 0; i
< 15; i
++) {
1732 mac
++; /* BUG: VRRP for testing */
1733 sw_w32(mac
>> 32, RTL839X_ROUTING_SA_CTRL
+ i
* 8);
1734 sw_w32(mac
, RTL839X_ROUTING_SA_CTRL
+ i
* 8 + 4);
1738 int rtl839x_l3_setup(struct rtl838x_switch_priv
*priv
)
1740 rtl839x_setup_port_macs(priv
);
1745 void rtl839x_vlan_port_keep_tag_set(int port
, bool keep_outer
, bool keep_inner
)
1747 sw_w32(FIELD_PREP(RTL839X_VLAN_PORT_TAG_STS_CTRL_OTAG_STS_MASK
,
1748 keep_outer
? RTL839X_VLAN_PORT_TAG_STS_TAGGED
: RTL839X_VLAN_PORT_TAG_STS_UNTAG
) |
1749 FIELD_PREP(RTL839X_VLAN_PORT_TAG_STS_CTRL_ITAG_STS_MASK
,
1750 keep_inner
? RTL839X_VLAN_PORT_TAG_STS_TAGGED
: RTL839X_VLAN_PORT_TAG_STS_UNTAG
),
1751 RTL839X_VLAN_PORT_TAG_STS_CTRL(port
));
1754 void rtl839x_vlan_port_pvidmode_set(int port
, enum pbvlan_type type
, enum pbvlan_mode mode
)
1756 if (type
== PBVLAN_TYPE_INNER
)
1757 sw_w32_mask(0x3, mode
, RTL839X_VLAN_PORT_PB_VLAN
+ (port
<< 2));
1759 sw_w32_mask(0x3 << 14, mode
<< 14, RTL839X_VLAN_PORT_PB_VLAN
+ (port
<< 2));
1762 void rtl839x_vlan_port_pvid_set(int port
, enum pbvlan_type type
, int pvid
)
1764 if (type
== PBVLAN_TYPE_INNER
)
1765 sw_w32_mask(0xfff << 2, pvid
<< 2, RTL839X_VLAN_PORT_PB_VLAN
+ (port
<< 2));
1767 sw_w32_mask(0xfff << 16, pvid
<< 16, RTL839X_VLAN_PORT_PB_VLAN
+ (port
<< 2));
1770 static int rtl839x_set_ageing_time(unsigned long msec
)
1772 int t
= sw_r32(RTL839X_L2_CTRL_1
);
1775 t
= t
* 3 / 5; /* Aging time in seconds. 0: L2 aging disabled */
1776 pr_debug("L2 AGING time: %d sec\n", t
);
1778 t
= (msec
* 5 + 2000) / 3000;
1779 t
= t
> 0x1FFFFF ? 0x1FFFFF : t
;
1780 sw_w32_mask(0x1FFFFF, t
, RTL839X_L2_CTRL_1
);
1781 pr_debug("Dynamic aging for ports: %x\n", sw_r32(RTL839X_L2_PORT_AGING_OUT
));
1786 static void rtl839x_set_igr_filter(int port
, enum igr_filter state
)
1788 sw_w32_mask(0x3 << ((port
& 0xf)<<1), state
<< ((port
& 0xf)<<1),
1789 RTL839X_VLAN_PORT_IGR_FLTR
+ (((port
>> 4) << 2)));
1792 static void rtl839x_set_egr_filter(int port
, enum egr_filter state
)
1794 sw_w32_mask(0x1 << (port
% 0x20), state
<< (port
% 0x20),
1795 RTL839X_VLAN_PORT_EGR_FLTR
+ (((port
>> 5) << 2)));
1798 void rtl839x_set_distribution_algorithm(int group
, int algoidx
, u32 algomsk
)
1800 sw_w32_mask(3 << ((group
& 0xf) << 1), algoidx
<< ((group
& 0xf) << 1),
1801 RTL839X_TRK_HASH_IDX_CTRL
+ ((group
>> 4) << 2));
1802 sw_w32(algomsk
, RTL839X_TRK_HASH_CTRL
+ (algoidx
<< 2));
1805 void rtl839x_set_receive_management_action(int port
, rma_ctrl_t type
, action_type_t action
)
1809 sw_w32_mask(3 << ((port
& 0xf) << 1), (action
& 0x3) << ((port
& 0xf) << 1),
1810 RTL839X_RMA_BPDU_CTRL
+ ((port
>> 4) << 2));
1813 sw_w32_mask(3 << ((port
& 0xf) << 1), (action
& 0x3) << ((port
& 0xf) << 1),
1814 RTL839X_RMA_PTP_CTRL
+ ((port
>> 4) << 2));
1817 sw_w32_mask(3 << ((port
& 0xf) << 1), (action
& 0x3) << ((port
& 0xf) << 1),
1818 RTL839X_RMA_LLTP_CTRL
+ ((port
>> 4) << 2));
1825 const struct rtl838x_reg rtl839x_reg
= {
1826 .mask_port_reg_be
= rtl839x_mask_port_reg_be
,
1827 .set_port_reg_be
= rtl839x_set_port_reg_be
,
1828 .get_port_reg_be
= rtl839x_get_port_reg_be
,
1829 .mask_port_reg_le
= rtl839x_mask_port_reg_le
,
1830 .set_port_reg_le
= rtl839x_set_port_reg_le
,
1831 .get_port_reg_le
= rtl839x_get_port_reg_le
,
1832 .stat_port_rst
= RTL839X_STAT_PORT_RST
,
1833 .stat_rst
= RTL839X_STAT_RST
,
1834 .stat_port_std_mib
= RTL839X_STAT_PORT_STD_MIB
,
1835 .traffic_enable
= rtl839x_traffic_enable
,
1836 .traffic_disable
= rtl839x_traffic_disable
,
1837 .traffic_get
= rtl839x_traffic_get
,
1838 .traffic_set
= rtl839x_traffic_set
,
1839 .port_iso_ctrl
= rtl839x_port_iso_ctrl
,
1840 .l2_ctrl_0
= RTL839X_L2_CTRL_0
,
1841 .l2_ctrl_1
= RTL839X_L2_CTRL_1
,
1842 .l2_port_aging_out
= RTL839X_L2_PORT_AGING_OUT
,
1843 .set_ageing_time
= rtl839x_set_ageing_time
,
1844 .smi_poll_ctrl
= RTL839X_SMI_PORT_POLLING_CTRL
,
1845 .l2_tbl_flush_ctrl
= RTL839X_L2_TBL_FLUSH_CTRL
,
1846 .exec_tbl0_cmd
= rtl839x_exec_tbl0_cmd
,
1847 .exec_tbl1_cmd
= rtl839x_exec_tbl1_cmd
,
1848 .tbl_access_data_0
= rtl839x_tbl_access_data_0
,
1849 .isr_glb_src
= RTL839X_ISR_GLB_SRC
,
1850 .isr_port_link_sts_chg
= RTL839X_ISR_PORT_LINK_STS_CHG
,
1851 .imr_port_link_sts_chg
= RTL839X_IMR_PORT_LINK_STS_CHG
,
1852 .imr_glb
= RTL839X_IMR_GLB
,
1853 .vlan_tables_read
= rtl839x_vlan_tables_read
,
1854 .vlan_set_tagged
= rtl839x_vlan_set_tagged
,
1855 .vlan_set_untagged
= rtl839x_vlan_set_untagged
,
1856 .vlan_profile_dump
= rtl839x_vlan_profile_dump
,
1857 .vlan_profile_setup
= rtl839x_vlan_profile_setup
,
1858 .vlan_fwd_on_inner
= rtl839x_vlan_fwd_on_inner
,
1859 .vlan_port_keep_tag_set
= rtl839x_vlan_port_keep_tag_set
,
1860 .vlan_port_pvidmode_set
= rtl839x_vlan_port_pvidmode_set
,
1861 .vlan_port_pvid_set
= rtl839x_vlan_port_pvid_set
,
1862 .set_vlan_igr_filter
= rtl839x_set_igr_filter
,
1863 .set_vlan_egr_filter
= rtl839x_set_egr_filter
,
1864 .enable_learning
= rtl839x_enable_learning
,
1865 .enable_flood
= rtl839x_enable_flood
,
1866 .enable_mcast_flood
= rtl839x_enable_mcast_flood
,
1867 .enable_bcast_flood
= rtl839x_enable_bcast_flood
,
1868 .set_static_move_action
= rtl839x_set_static_move_action
,
1869 .stp_get
= rtl839x_stp_get
,
1870 .stp_set
= rtl839x_stp_set
,
1871 .mac_force_mode_ctrl
= rtl839x_mac_force_mode_ctrl
,
1872 .mac_port_ctrl
= rtl839x_mac_port_ctrl
,
1873 .l2_port_new_salrn
= rtl839x_l2_port_new_salrn
,
1874 .l2_port_new_sa_fwd
= rtl839x_l2_port_new_sa_fwd
,
1875 .mir_ctrl
= RTL839X_MIR_CTRL
,
1876 .mir_dpm
= RTL839X_MIR_DPM_CTRL
,
1877 .mir_spm
= RTL839X_MIR_SPM_CTRL
,
1878 .mac_link_sts
= RTL839X_MAC_LINK_STS
,
1879 .mac_link_dup_sts
= RTL839X_MAC_LINK_DUP_STS
,
1880 .mac_link_spd_sts
= rtl839x_mac_link_spd_sts
,
1881 .mac_rx_pause_sts
= RTL839X_MAC_RX_PAUSE_STS
,
1882 .mac_tx_pause_sts
= RTL839X_MAC_TX_PAUSE_STS
,
1883 .read_l2_entry_using_hash
= rtl839x_read_l2_entry_using_hash
,
1884 .write_l2_entry_using_hash
= rtl839x_write_l2_entry_using_hash
,
1885 .read_cam
= rtl839x_read_cam
,
1886 .write_cam
= rtl839x_write_cam
,
1887 .trk_mbr_ctr
= rtl839x_trk_mbr_ctr
,
1888 .rma_bpdu_fld_pmask
= RTL839X_RMA_BPDU_FLD_PMSK
,
1889 .spcl_trap_eapol_ctrl
= RTL839X_SPCL_TRAP_EAPOL_CTRL
,
1890 .init_eee
= rtl839x_init_eee
,
1891 .port_eee_set
= rtl839x_port_eee_set
,
1892 .eee_port_ability
= rtl839x_eee_port_ability
,
1893 .l2_hash_seed
= rtl839x_l2_hash_seed
,
1894 .l2_hash_key
= rtl839x_l2_hash_key
,
1895 .read_mcast_pmask
= rtl839x_read_mcast_pmask
,
1896 .write_mcast_pmask
= rtl839x_write_mcast_pmask
,
1897 .pie_init
= rtl839x_pie_init
,
1898 .pie_rule_read
= rtl839x_pie_rule_read
,
1899 .pie_rule_write
= rtl839x_pie_rule_write
,
1900 .pie_rule_add
= rtl839x_pie_rule_add
,
1901 .pie_rule_rm
= rtl839x_pie_rule_rm
,
1902 .l2_learning_setup
= rtl839x_l2_learning_setup
,
1903 .packet_cntr_read
= rtl839x_packet_cntr_read
,
1904 .packet_cntr_clear
= rtl839x_packet_cntr_clear
,
1905 .route_read
= rtl839x_route_read
,
1906 .route_write
= rtl839x_route_write
,
1907 .l3_setup
= rtl839x_l3_setup
,
1908 .set_distribution_algorithm
= rtl839x_set_distribution_algorithm
,
1909 .set_receive_management_action
= rtl839x_set_receive_management_action
,