1 // SPDX-License-Identifier: GPL-2.0-only
3 #include <asm/mach-rtl838x/mach-rtl83xx.h>
6 #define RTL839X_VLAN_PORT_TAG_STS_UNTAG 0x0
7 #define RTL839X_VLAN_PORT_TAG_STS_TAGGED 0x1
8 #define RTL839X_VLAN_PORT_TAG_STS_PRIORITY_TAGGED 0x2
10 #define RTL839X_VLAN_PORT_TAG_STS_CTRL_BASE 0x6828
12 #define RTL839X_VLAN_PORT_TAG_STS_CTRL(port) \
13 RTL839X_VLAN_PORT_TAG_STS_CTRL_BASE + (port << 2)
14 #define RTL839X_VLAN_PORT_TAG_STS_CTRL_OTAG_STS_MASK GENMASK(7,6)
15 #define RTL839X_VLAN_PORT_TAG_STS_CTRL_ITAG_STS_MASK GENMASK(5,4)
16 #define RTL839X_VLAN_PORT_TAG_STS_CTRL_EGR_P_OTAG_KEEP_MASK GENMASK(3,3)
17 #define RTL839X_VLAN_PORT_TAG_STS_CTRL_EGR_P_ITAG_KEEP_MASK GENMASK(2,2)
18 #define RTL839X_VLAN_PORT_TAG_STS_CTRL_IGR_P_OTAG_KEEP_MASK GENMASK(1,1)
19 #define RTL839X_VLAN_PORT_TAG_STS_CTRL_IGR_P_ITAG_KEEP_MASK GENMASK(0,0)
21 extern struct mutex smi_lock
;
22 extern struct rtl83xx_soc_info soc_info
;
24 /* Definition of the RTL839X-specific template field IDs as used in the PIE */
25 enum template_field_id
{
26 TEMPLATE_FIELD_SPMMASK
= 0,
27 TEMPLATE_FIELD_SPM0
= 1, // Source portmask ports 0-15
28 TEMPLATE_FIELD_SPM1
= 2, // Source portmask ports 16-31
29 TEMPLATE_FIELD_SPM2
= 3, // Source portmask ports 32-47
30 TEMPLATE_FIELD_SPM3
= 4, // Source portmask ports 48-56
31 TEMPLATE_FIELD_DMAC0
= 5, // Destination MAC [15:0]
32 TEMPLATE_FIELD_DMAC1
= 6, // Destination MAC [31:16]
33 TEMPLATE_FIELD_DMAC2
= 7, // Destination MAC [47:32]
34 TEMPLATE_FIELD_SMAC0
= 8, // Source MAC [15:0]
35 TEMPLATE_FIELD_SMAC1
= 9, // Source MAC [31:16]
36 TEMPLATE_FIELD_SMAC2
= 10, // Source MAC [47:32]
37 TEMPLATE_FIELD_ETHERTYPE
= 11, // Ethernet frame type field
38 // Field-ID 12 is not used
39 TEMPLATE_FIELD_OTAG
= 13,
40 TEMPLATE_FIELD_ITAG
= 14,
41 TEMPLATE_FIELD_SIP0
= 15,
42 TEMPLATE_FIELD_SIP1
= 16,
43 TEMPLATE_FIELD_DIP0
= 17,
44 TEMPLATE_FIELD_DIP1
= 18,
45 TEMPLATE_FIELD_IP_TOS_PROTO
= 19,
46 TEMPLATE_FIELD_IP_FLAG
= 20,
47 TEMPLATE_FIELD_L4_SPORT
= 21,
48 TEMPLATE_FIELD_L4_DPORT
= 22,
49 TEMPLATE_FIELD_L34_HEADER
= 23,
50 TEMPLATE_FIELD_ICMP_IGMP
= 24,
51 TEMPLATE_FIELD_VID_RANG0
= 25,
52 TEMPLATE_FIELD_VID_RANG1
= 26,
53 TEMPLATE_FIELD_L4_PORT_RANG
= 27,
54 TEMPLATE_FIELD_FIELD_SELECTOR_VALID
= 28,
55 TEMPLATE_FIELD_FIELD_SELECTOR_0
= 29,
56 TEMPLATE_FIELD_FIELD_SELECTOR_1
= 30,
57 TEMPLATE_FIELD_FIELD_SELECTOR_2
= 31,
58 TEMPLATE_FIELD_FIELD_SELECTOR_3
= 32,
59 TEMPLATE_FIELD_FIELD_SELECTOR_4
= 33,
60 TEMPLATE_FIELD_FIELD_SELECTOR_5
= 34,
61 TEMPLATE_FIELD_SIP2
= 35,
62 TEMPLATE_FIELD_SIP3
= 36,
63 TEMPLATE_FIELD_SIP4
= 37,
64 TEMPLATE_FIELD_SIP5
= 38,
65 TEMPLATE_FIELD_SIP6
= 39,
66 TEMPLATE_FIELD_SIP7
= 40,
67 TEMPLATE_FIELD_OLABEL
= 41,
68 TEMPLATE_FIELD_ILABEL
= 42,
69 TEMPLATE_FIELD_OILABEL
= 43,
70 TEMPLATE_FIELD_DPMMASK
= 44,
71 TEMPLATE_FIELD_DPM0
= 45,
72 TEMPLATE_FIELD_DPM1
= 46,
73 TEMPLATE_FIELD_DPM2
= 47,
74 TEMPLATE_FIELD_DPM3
= 48,
75 TEMPLATE_FIELD_L2DPM0
= 49,
76 TEMPLATE_FIELD_L2DPM1
= 50,
77 TEMPLATE_FIELD_L2DPM2
= 51,
78 TEMPLATE_FIELD_L2DPM3
= 52,
79 TEMPLATE_FIELD_IVLAN
= 53,
80 TEMPLATE_FIELD_OVLAN
= 54,
81 TEMPLATE_FIELD_FWD_VID
= 55,
82 TEMPLATE_FIELD_DIP2
= 56,
83 TEMPLATE_FIELD_DIP3
= 57,
84 TEMPLATE_FIELD_DIP4
= 58,
85 TEMPLATE_FIELD_DIP5
= 59,
86 TEMPLATE_FIELD_DIP6
= 60,
87 TEMPLATE_FIELD_DIP7
= 61,
90 // Number of fixed templates predefined in the SoC
91 #define N_FIXED_TEMPLATES 5
92 static enum template_field_id fixed_templates
[N_FIXED_TEMPLATES
][N_FIXED_FIELDS
] =
95 TEMPLATE_FIELD_SPM0
, TEMPLATE_FIELD_SPM1
, TEMPLATE_FIELD_ITAG
,
96 TEMPLATE_FIELD_SMAC0
, TEMPLATE_FIELD_SMAC1
, TEMPLATE_FIELD_SMAC2
,
97 TEMPLATE_FIELD_DMAC0
, TEMPLATE_FIELD_DMAC1
, TEMPLATE_FIELD_DMAC2
,
98 TEMPLATE_FIELD_ETHERTYPE
, TEMPLATE_FIELD_SPM2
, TEMPLATE_FIELD_SPM3
100 TEMPLATE_FIELD_SIP0
, TEMPLATE_FIELD_SIP1
, TEMPLATE_FIELD_DIP0
,
101 TEMPLATE_FIELD_DIP1
,TEMPLATE_FIELD_IP_TOS_PROTO
, TEMPLATE_FIELD_L4_SPORT
,
102 TEMPLATE_FIELD_L4_DPORT
, TEMPLATE_FIELD_ICMP_IGMP
, TEMPLATE_FIELD_SPM0
,
103 TEMPLATE_FIELD_SPM1
, TEMPLATE_FIELD_SPM2
, TEMPLATE_FIELD_SPM3
105 TEMPLATE_FIELD_DMAC0
, TEMPLATE_FIELD_DMAC1
, TEMPLATE_FIELD_DMAC2
,
106 TEMPLATE_FIELD_ITAG
, TEMPLATE_FIELD_ETHERTYPE
, TEMPLATE_FIELD_IP_TOS_PROTO
,
107 TEMPLATE_FIELD_L4_DPORT
, TEMPLATE_FIELD_L4_SPORT
, TEMPLATE_FIELD_SIP0
,
108 TEMPLATE_FIELD_SIP1
, TEMPLATE_FIELD_DIP0
, TEMPLATE_FIELD_DIP1
110 TEMPLATE_FIELD_DIP0
, TEMPLATE_FIELD_DIP1
, TEMPLATE_FIELD_DIP2
,
111 TEMPLATE_FIELD_DIP3
, TEMPLATE_FIELD_DIP4
, TEMPLATE_FIELD_DIP5
,
112 TEMPLATE_FIELD_DIP6
, TEMPLATE_FIELD_DIP7
, TEMPLATE_FIELD_L4_DPORT
,
113 TEMPLATE_FIELD_L4_SPORT
, TEMPLATE_FIELD_ICMP_IGMP
, TEMPLATE_FIELD_IP_TOS_PROTO
115 TEMPLATE_FIELD_SIP0
, TEMPLATE_FIELD_SIP1
, TEMPLATE_FIELD_SIP2
,
116 TEMPLATE_FIELD_SIP3
, TEMPLATE_FIELD_SIP4
, TEMPLATE_FIELD_SIP5
,
117 TEMPLATE_FIELD_SIP6
, TEMPLATE_FIELD_SIP7
, TEMPLATE_FIELD_SPM0
,
118 TEMPLATE_FIELD_SPM1
, TEMPLATE_FIELD_SPM2
, TEMPLATE_FIELD_SPM3
122 void rtl839x_print_matrix(void)
127 ptr9
= RTL838X_SW_BASE
+ RTL839X_PORT_ISO_CTRL(0);
128 for (i
= 0; i
< 52; i
+= 4)
129 pr_debug("> %16llx %16llx %16llx %16llx\n",
130 ptr9
[i
+ 0], ptr9
[i
+ 1], ptr9
[i
+ 2], ptr9
[i
+ 3]);
131 pr_debug("CPU_PORT> %16llx\n", ptr9
[52]);
134 static inline int rtl839x_port_iso_ctrl(int p
)
136 return RTL839X_PORT_ISO_CTRL(p
);
139 static inline void rtl839x_exec_tbl0_cmd(u32 cmd
)
141 sw_w32(cmd
, RTL839X_TBL_ACCESS_CTRL_0
);
142 do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_0
) & BIT(16));
145 static inline void rtl839x_exec_tbl1_cmd(u32 cmd
)
147 sw_w32(cmd
, RTL839X_TBL_ACCESS_CTRL_1
);
148 do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_1
) & BIT(16));
151 inline void rtl839x_exec_tbl2_cmd(u32 cmd
)
153 sw_w32(cmd
, RTL839X_TBL_ACCESS_CTRL_2
);
154 do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_2
) & (1 << 9));
157 static inline int rtl839x_tbl_access_data_0(int i
)
159 return RTL839X_TBL_ACCESS_DATA_0(i
);
162 static void rtl839x_vlan_tables_read(u32 vlan
, struct rtl838x_vlan_info
*info
)
165 // Read VLAN table (0) via register 0
166 struct table_reg
*r
= rtl_table_get(RTL8390_TBL_0
, 0);
168 rtl_table_read(r
, vlan
);
169 u
= sw_r32(rtl_table_data(r
, 0));
170 v
= sw_r32(rtl_table_data(r
, 1));
171 w
= sw_r32(rtl_table_data(r
, 2));
172 rtl_table_release(r
);
174 info
->tagged_ports
= u
;
175 info
->tagged_ports
= (info
->tagged_ports
<< 21) | ((v
>> 11) & 0x1fffff);
176 info
->profile_id
= w
>> 30 | ((v
& 1) << 2);
177 info
->hash_mc_fid
= !!(w
& BIT(2));
178 info
->hash_uc_fid
= !!(w
& BIT(3));
179 info
->fid
= (v
>> 3) & 0xff;
181 // Read UNTAG table (0) via table register 1
182 r
= rtl_table_get(RTL8390_TBL_1
, 0);
183 rtl_table_read(r
, vlan
);
184 u
= sw_r32(rtl_table_data(r
, 0));
185 v
= sw_r32(rtl_table_data(r
, 1));
186 rtl_table_release(r
);
188 info
->untagged_ports
= u
;
189 info
->untagged_ports
= (info
->untagged_ports
<< 21) | ((v
>> 11) & 0x1fffff);
192 static void rtl839x_vlan_set_tagged(u32 vlan
, struct rtl838x_vlan_info
*info
)
195 // Access VLAN table (0) via register 0
196 struct table_reg
*r
= rtl_table_get(RTL8390_TBL_0
, 0);
198 u
= info
->tagged_ports
>> 21;
199 v
= info
->tagged_ports
<< 11;
200 v
|= ((u32
)info
->fid
) << 3;
201 v
|= info
->hash_uc_fid
? BIT(2) : 0;
202 v
|= info
->hash_mc_fid
? BIT(1) : 0;
203 v
|= (info
->profile_id
& 0x4) ? 1 : 0;
204 w
= ((u32
)(info
->profile_id
& 3)) << 30;
206 sw_w32(u
, rtl_table_data(r
, 0));
207 sw_w32(v
, rtl_table_data(r
, 1));
208 sw_w32(w
, rtl_table_data(r
, 2));
210 rtl_table_write(r
, vlan
);
211 rtl_table_release(r
);
214 static void rtl839x_vlan_set_untagged(u32 vlan
, u64 portmask
)
218 // Access UNTAG table (0) via table register 1
219 struct table_reg
*r
= rtl_table_get(RTL8390_TBL_1
, 0);
224 sw_w32(u
, rtl_table_data(r
, 0));
225 sw_w32(v
, rtl_table_data(r
, 1));
226 rtl_table_write(r
, vlan
);
228 rtl_table_release(r
);
231 /* Sets the L2 forwarding to be based on either the inner VLAN tag or the outer
233 static void rtl839x_vlan_fwd_on_inner(int port
, bool is_set
)
236 rtl839x_mask_port_reg_be(BIT_ULL(port
), 0ULL, RTL839X_VLAN_PORT_FWD
);
238 rtl839x_mask_port_reg_be(0ULL, BIT_ULL(port
), RTL839X_VLAN_PORT_FWD
);
242 * Hash seed is vid (actually rvid) concatenated with the MAC address
244 static u64
rtl839x_l2_hash_seed(u64 mac
, u32 vid
)
255 * Applies the same hash algorithm as the one used currently by the ASIC to the seed
256 * and returns a key into the L2 hash table
258 static u32
rtl839x_l2_hash_key(struct rtl838x_switch_priv
*priv
, u64 seed
)
262 if (sw_r32(priv
->r
->l2_ctrl_0
) & 1) {
263 h1
= (u32
) (((seed
>> 60) & 0x3f) ^ ((seed
>> 54) & 0x3f)
264 ^ ((seed
>> 36) & 0x3f) ^ ((seed
>> 30) & 0x3f)
265 ^ ((seed
>> 12) & 0x3f) ^ ((seed
>> 6) & 0x3f));
266 h2
= (u32
) (((seed
>> 48) & 0x3f) ^ ((seed
>> 42) & 0x3f)
267 ^ ((seed
>> 24) & 0x3f) ^ ((seed
>> 18) & 0x3f)
272 ^ ((((seed
>> 48) & 0x3f) << 6) | ((seed
>> 54) & 0x3f))
273 ^ ((seed
>> 36) & 0xfff) ^ ((seed
>> 24) & 0xfff)
274 ^ ((seed
>> 12) & 0xfff) ^ (seed
& 0xfff);
280 static inline int rtl839x_mac_force_mode_ctrl(int p
)
282 return RTL839X_MAC_FORCE_MODE_CTRL
+ (p
<< 2);
285 static inline int rtl839x_mac_port_ctrl(int p
)
287 return RTL839X_MAC_PORT_CTRL(p
);
290 static inline int rtl839x_l2_port_new_salrn(int p
)
292 return RTL839X_L2_PORT_NEW_SALRN(p
);
295 static inline int rtl839x_l2_port_new_sa_fwd(int p
)
297 return RTL839X_L2_PORT_NEW_SA_FWD(p
);
300 static inline int rtl839x_mac_link_spd_sts(int p
)
302 return RTL839X_MAC_LINK_SPD_STS(p
);
305 static inline int rtl839x_trk_mbr_ctr(int group
)
307 return RTL839X_TRK_MBR_CTR
+ (group
<< 3);
310 static void rtl839x_fill_l2_entry(u32 r
[], struct rtl838x_l2_entry
*e
)
312 /* Table contains different entry types, we need to identify the right one:
313 * Check for MC entries, first
315 e
->is_ip_mc
= !!(r
[2] & BIT(31));
316 e
->is_ipv6_mc
= !!(r
[2] & BIT(30));
317 e
->type
= L2_INVALID
;
318 if (!e
->is_ip_mc
&& !e
->is_ipv6_mc
) {
319 e
->mac
[0] = (r
[0] >> 12);
320 e
->mac
[1] = (r
[0] >> 4);
321 e
->mac
[2] = ((r
[1] >> 28) | (r
[0] << 4));
322 e
->mac
[3] = (r
[1] >> 20);
323 e
->mac
[4] = (r
[1] >> 12);
324 e
->mac
[5] = (r
[1] >> 4);
326 e
->vid
= (r
[2] >> 4) & 0xfff;
327 e
->rvid
= (r
[0] >> 20) & 0xfff;
329 /* Is it a unicast entry? check multicast bit */
330 if (!(e
->mac
[0] & 1)) {
331 e
->is_static
= !!((r
[2] >> 18) & 1);
332 e
->port
= (r
[2] >> 24) & 0x3f;
333 e
->block_da
= !!(r
[2] & (1 << 19));
334 e
->block_sa
= !!(r
[2] & (1 << 20));
335 e
->suspended
= !!(r
[2] & (1 << 17));
336 e
->next_hop
= !!(r
[2] & (1 << 16));
338 pr_debug("Found next hop entry, need to read data\n");
339 e
->nh_vlan_target
= !!(r
[2] & BIT(15));
340 e
->nh_route_id
= (r
[2] >> 4) & 0x1ff;
343 e
->age
= (r
[2] >> 21) & 3;
345 if (!(r
[2] & 0xc0fd0000)) /* Check for valid entry */
348 e
->type
= L2_UNICAST
;
351 e
->type
= L2_MULTICAST
;
352 e
->mc_portmask_index
= (r
[2] >> 6) & 0xfff;
355 } else { // IPv4 and IPv6 multicast
356 e
->vid
= e
->rvid
= (r
[0] << 20) & 0xfff;
358 e
->mc_portmask_index
= (r
[2] >> 6) & 0xfff;
362 e
->type
= IP4_MULTICAST
;
366 e
->type
= IP6_MULTICAST
;
368 // pr_info("%s: vid %d, rvid: %d\n", __func__, e->vid, e->rvid);
372 * Fills the 3 SoC table registers r[] with the information in the rtl838x_l2_entry
374 static void rtl839x_fill_l2_row(u32 r
[], struct rtl838x_l2_entry
*e
)
377 r
[0] = r
[1] = r
[2] = 0;
381 r
[2] = e
->is_ip_mc
? BIT(31) : 0;
382 r
[2] |= e
->is_ipv6_mc
? BIT(30) : 0;
384 if (!e
->is_ip_mc
&& !e
->is_ipv6_mc
) {
385 r
[0] = ((u32
)e
->mac
[0]) << 12;
386 r
[0] |= ((u32
)e
->mac
[1]) << 4;
387 r
[0] |= ((u32
)e
->mac
[2]) >> 4;
388 r
[1] = ((u32
)e
->mac
[2]) << 28;
389 r
[1] |= ((u32
)e
->mac
[3]) << 20;
390 r
[1] |= ((u32
)e
->mac
[4]) << 12;
391 r
[1] |= ((u32
)e
->mac
[5]) << 4;
393 if (!(e
->mac
[0] & 1)) { // Not multicast
394 r
[2] |= e
->is_static
? BIT(18) : 0;
395 r
[0] |= ((u32
)e
->rvid
) << 20;
396 r
[2] |= e
->port
<< 24;
397 r
[2] |= e
->block_da
? BIT(19) : 0;
398 r
[2] |= e
->block_sa
? BIT(20) : 0;
399 r
[2] |= e
->suspended
? BIT(17) : 0;
400 r
[2] |= ((u32
)e
->age
) << 21;
403 r
[2] |= e
->nh_vlan_target
? BIT(15) : 0;
404 r
[2] |= (e
->nh_route_id
& 0x7ff) << 4;
408 pr_debug("Write L2 NH: %08x %08x %08x\n", r
[0], r
[1], r
[2]);
409 } else { // L2 Multicast
410 r
[0] |= ((u32
)e
->rvid
) << 20;
411 r
[2] |= ((u32
)e
->mc_portmask_index
) << 6;
413 } else { // IPv4 or IPv6 MC entry
414 r
[0] = ((u32
)e
->rvid
) << 20;
416 r
[2] |= ((u32
)e
->mc_portmask_index
) << 6;
421 * Read an L2 UC or MC entry out of a hash bucket of the L2 forwarding table
422 * hash is the id of the bucket and pos is the position of the entry in that bucket
423 * The data read from the SoC is filled into rtl838x_l2_entry
425 static u64
rtl839x_read_l2_entry_using_hash(u32 hash
, u32 pos
, struct rtl838x_l2_entry
*e
)
428 struct table_reg
*q
= rtl_table_get(RTL8390_TBL_L2
, 0);
429 u32 idx
= (0 << 14) | (hash
<< 2) | pos
; // Search SRAM, with hash and at pos in bucket
432 rtl_table_read(q
, idx
);
433 for (i
= 0; i
< 3; i
++)
434 r
[i
] = sw_r32(rtl_table_data(q
, i
));
436 rtl_table_release(q
);
438 rtl839x_fill_l2_entry(r
, e
);
442 return rtl839x_l2_hash_seed(ether_addr_to_u64(&e
->mac
[0]), e
->rvid
);
445 static void rtl839x_write_l2_entry_using_hash(u32 hash
, u32 pos
, struct rtl838x_l2_entry
*e
)
448 struct table_reg
*q
= rtl_table_get(RTL8390_TBL_L2
, 0);
451 u32 idx
= (0 << 14) | (hash
<< 2) | pos
; // Access SRAM, with hash and at pos in bucket
453 rtl839x_fill_l2_row(r
, e
);
455 for (i
= 0; i
< 3; i
++)
456 sw_w32(r
[i
], rtl_table_data(q
, i
));
458 rtl_table_write(q
, idx
);
459 rtl_table_release(q
);
462 static u64
rtl839x_read_cam(int idx
, struct rtl838x_l2_entry
*e
)
465 struct table_reg
*q
= rtl_table_get(RTL8390_TBL_L2
, 1); // Access L2 Table 1
468 rtl_table_read(q
, idx
);
469 for (i
= 0; i
< 3; i
++)
470 r
[i
] = sw_r32(rtl_table_data(q
, i
));
472 rtl_table_release(q
);
474 rtl839x_fill_l2_entry(r
, e
);
478 pr_debug("Found in CAM: R1 %x R2 %x R3 %x\n", r
[0], r
[1], r
[2]);
480 // Return MAC with concatenated VID ac concatenated ID
481 return rtl839x_l2_hash_seed(ether_addr_to_u64(&e
->mac
[0]), e
->rvid
);
484 static void rtl839x_write_cam(int idx
, struct rtl838x_l2_entry
*e
)
487 struct table_reg
*q
= rtl_table_get(RTL8390_TBL_L2
, 1); // Access L2 Table 1
490 rtl839x_fill_l2_row(r
, e
);
492 for (i
= 0; i
< 3; i
++)
493 sw_w32(r
[i
], rtl_table_data(q
, i
));
495 rtl_table_write(q
, idx
);
496 rtl_table_release(q
);
499 static u64
rtl839x_read_mcast_pmask(int idx
)
502 // Read MC_PMSK (2) via register RTL8390_TBL_L2
503 struct table_reg
*q
= rtl_table_get(RTL8390_TBL_L2
, 2);
505 rtl_table_read(q
, idx
);
506 portmask
= sw_r32(rtl_table_data(q
, 0));
508 portmask
|= sw_r32(rtl_table_data(q
, 1));
509 portmask
>>= 11; // LSB is bit 11 in data registers
510 rtl_table_release(q
);
515 static void rtl839x_write_mcast_pmask(int idx
, u64 portmask
)
517 // Access MC_PMSK (2) via register RTL8380_TBL_L2
518 struct table_reg
*q
= rtl_table_get(RTL8390_TBL_L2
, 2);
520 portmask
<<= 11; // LSB is bit 11 in data registers
521 sw_w32((u32
)(portmask
>> 32), rtl_table_data(q
, 0));
522 sw_w32((u32
)((portmask
& 0xfffff800)), rtl_table_data(q
, 1));
523 rtl_table_write(q
, idx
);
524 rtl_table_release(q
);
527 static void rtl839x_vlan_profile_setup(int profile
)
530 u32 pmask_id
= UNKNOWN_MC_PMASK
;
532 p
[0] = pmask_id
; // Use portmaks 0xfff for unknown IPv6 MC flooding
533 // Enable L2 Learning BIT 0, portmask UNKNOWN_MC_PMASK for IP/L2-MC traffic flooding
534 p
[1] = 1 | pmask_id
<< 1 | pmask_id
<< 13;
536 sw_w32(p
[0], RTL839X_VLAN_PROFILE(profile
));
537 sw_w32(p
[1], RTL839X_VLAN_PROFILE(profile
) + 4);
539 rtl839x_write_mcast_pmask(UNKNOWN_MC_PMASK
, 0x001fffffffffffff);
542 u64
rtl839x_traffic_get(int source
)
544 return rtl839x_get_port_reg_be(rtl839x_port_iso_ctrl(source
));
547 void rtl839x_traffic_set(int source
, u64 dest_matrix
)
549 rtl839x_set_port_reg_be(dest_matrix
, rtl839x_port_iso_ctrl(source
));
552 void rtl839x_traffic_enable(int source
, int dest
)
554 rtl839x_mask_port_reg_be(0, BIT_ULL(dest
), rtl839x_port_iso_ctrl(source
));
557 void rtl839x_traffic_disable(int source
, int dest
)
559 rtl839x_mask_port_reg_be(BIT_ULL(dest
), 0, rtl839x_port_iso_ctrl(source
));
562 static void rtl839x_l2_learning_setup(void)
564 /* Set portmask for broadcast (offset bit 12) and unknown unicast (offset 0)
565 * address flooding to the reserved entry in the portmask table used
566 * also for multicast flooding */
567 sw_w32(UNKNOWN_MC_PMASK
<< 12 | UNKNOWN_MC_PMASK
, RTL839X_L2_FLD_PMSK
);
569 // Limit learning to maximum: 32k entries, after that just flood (bits 0-1)
570 sw_w32((0x7fff << 2) | 0, RTL839X_L2_LRN_CONSTRT
);
572 // Do not trap ARP packets to CPU_PORT
573 sw_w32(0, RTL839X_SPCL_TRAP_ARP_CTRL
);
576 static void rtl839x_enable_learning(int port
, bool enable
)
578 // Limit learning to maximum: 32k entries
580 sw_w32_mask(0x7fff << 2, enable
? (0x7fff << 2) : 0,
581 RTL839X_L2_PORT_LRN_CONSTRT
+ (port
<< 2));
584 static void rtl839x_enable_flood(int port
, bool enable
)
592 sw_w32_mask(0x3, enable
? 0 : 1,
593 RTL839X_L2_PORT_LRN_CONSTRT
+ (port
<< 2));
596 static void rtl839x_enable_mcast_flood(int port
, bool enable
)
601 static void rtl839x_enable_bcast_flood(int port
, bool enable
)
605 irqreturn_t
rtl839x_switch_irq(int irq
, void *dev_id
)
607 struct dsa_switch
*ds
= dev_id
;
608 u32 status
= sw_r32(RTL839X_ISR_GLB_SRC
);
609 u64 ports
= rtl839x_get_port_reg_le(RTL839X_ISR_PORT_LINK_STS_CHG
);
614 rtl839x_set_port_reg_le(ports
, RTL839X_ISR_PORT_LINK_STS_CHG
);
615 pr_debug("RTL8390 Link change: status: %x, ports %llx\n", status
, ports
);
617 for (i
= 0; i
< RTL839X_CPU_PORT
; i
++) {
618 if (ports
& BIT_ULL(i
)) {
619 link
= rtl839x_get_port_reg_le(RTL839X_MAC_LINK_STS
);
620 if (link
& BIT_ULL(i
))
621 dsa_port_phylink_mac_change(ds
, i
, true);
623 dsa_port_phylink_mac_change(ds
, i
, false);
630 int rtl8390_sds_power(int mac
, int val
)
632 u32 offset
= (mac
== 48) ? 0x0 : 0x100;
633 u32 mode
= val
? 0 : 1;
635 pr_debug("In %s: mac %d, set %d\n", __func__
, mac
, val
);
637 if ((mac
!= 48) && (mac
!= 49)) {
638 pr_err("%s: not an SFP port: %d\n", __func__
, mac
);
642 // Set bit 1003. 1000 starts at 7c
643 sw_w32_mask(BIT(11), mode
<< 11, RTL839X_SDS12_13_PWR0
+ offset
);
648 static int rtl839x_smi_wait_op(int timeout
)
653 ret
= readx_poll_timeout(sw_r32
, RTL839X_PHYREG_ACCESS_CTRL
,
654 val
, !(val
& 0x1), 20, timeout
);
656 pr_err("%s: timeout\n", __func__
);
661 int rtl839x_read_phy(u32 port
, u32 page
, u32 reg
, u32
*val
)
666 if (port
> 63 || page
> 4095 || reg
> 31)
669 // Take bug on RTL839x Rev <= C into account
670 if (port
>= RTL839X_CPU_PORT
)
673 mutex_lock(&smi_lock
);
675 sw_w32_mask(0xffff0000, port
<< 16, RTL839X_PHYREG_DATA_CTRL
);
676 v
= reg
<< 5 | page
<< 10 | ((page
== 0x1fff) ? 0x1f : 0) << 23;
677 sw_w32(v
, RTL839X_PHYREG_ACCESS_CTRL
);
679 sw_w32(0x1ff, RTL839X_PHYREG_CTRL
);
682 sw_w32(v
, RTL839X_PHYREG_ACCESS_CTRL
);
684 err
= rtl839x_smi_wait_op(100000);
688 *val
= sw_r32(RTL839X_PHYREG_DATA_CTRL
) & 0xffff;
691 mutex_unlock(&smi_lock
);
695 int rtl839x_write_phy(u32 port
, u32 page
, u32 reg
, u32 val
)
701 if (port
> 63 || page
> 4095 || reg
> 31)
704 // Take bug on RTL839x Rev <= C into account
705 if (port
>= RTL839X_CPU_PORT
)
708 mutex_lock(&smi_lock
);
711 rtl839x_set_port_reg_le(BIT_ULL(port
), RTL839X_PHYREG_PORT_CTRL
);
713 sw_w32_mask(0xffff0000, val
<< 16, RTL839X_PHYREG_DATA_CTRL
);
715 v
= reg
<< 5 | page
<< 10 | ((page
== 0x1fff) ? 0x1f : 0) << 23;
716 sw_w32(v
, RTL839X_PHYREG_ACCESS_CTRL
);
718 sw_w32(0x1ff, RTL839X_PHYREG_CTRL
);
720 v
|= BIT(3) | 1; /* Write operation and execute */
721 sw_w32(v
, RTL839X_PHYREG_ACCESS_CTRL
);
723 err
= rtl839x_smi_wait_op(100000);
727 if (sw_r32(RTL839X_PHYREG_ACCESS_CTRL
) & 0x2)
731 mutex_unlock(&smi_lock
);
736 * Read an mmd register of the PHY
738 int rtl839x_read_mmd_phy(u32 port
, u32 devnum
, u32 regnum
, u32
*val
)
743 // Take bug on RTL839x Rev <= C into account
744 if (port
>= RTL839X_CPU_PORT
)
747 mutex_lock(&smi_lock
);
750 sw_w32_mask(0xffff << 16, port
<< 16, RTL839X_PHYREG_DATA_CTRL
);
752 // Set MMD device number and register to write to
753 sw_w32(devnum
<< 16 | (regnum
& 0xffff), RTL839X_PHYREG_MMD_CTRL
);
755 v
= BIT(2) | BIT(0); // MMD-access | EXEC
756 sw_w32(v
, RTL839X_PHYREG_ACCESS_CTRL
);
758 err
= rtl839x_smi_wait_op(100000);
762 // There is no error-checking via BIT 1 of v, as it does not seem to be set correctly
763 *val
= (sw_r32(RTL839X_PHYREG_DATA_CTRL
) & 0xffff);
764 pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__
, port
, regnum
, *val
, err
);
767 mutex_unlock(&smi_lock
);
772 * Write to an mmd register of the PHY
774 int rtl839x_write_mmd_phy(u32 port
, u32 devnum
, u32 regnum
, u32 val
)
779 // Take bug on RTL839x Rev <= C into account
780 if (port
>= RTL839X_CPU_PORT
)
783 mutex_lock(&smi_lock
);
786 rtl839x_set_port_reg_le(BIT_ULL(port
), RTL839X_PHYREG_PORT_CTRL
);
789 sw_w32_mask(0xffff << 16, val
<< 16, RTL839X_PHYREG_DATA_CTRL
);
791 // Set MMD device number and register to write to
792 sw_w32(devnum
<< 16 | (regnum
& 0xffff), RTL839X_PHYREG_MMD_CTRL
);
794 v
= BIT(3) | BIT(2) | BIT(0); // WRITE | MMD-access | EXEC
795 sw_w32(v
, RTL839X_PHYREG_ACCESS_CTRL
);
797 err
= rtl839x_smi_wait_op(100000);
801 pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__
, port
, regnum
, val
, err
);
804 mutex_unlock(&smi_lock
);
808 void rtl8390_get_version(struct rtl838x_switch_priv
*priv
)
812 sw_w32_mask(0xf << 28, 0xa << 28, RTL839X_CHIP_INFO
);
813 info
= sw_r32(RTL839X_CHIP_INFO
);
815 model
= sw_r32(RTL839X_MODEL_NAME_INFO
);
816 priv
->version
= RTL8390_VERSION_A
+ ((model
& 0x3f) >> 1);
818 pr_info("RTL839X Chip-Info: %x, version %c\n", info
, priv
->version
);
821 void rtl839x_vlan_profile_dump(int profile
)
825 if (profile
< 0 || profile
> 7)
828 p
[0] = sw_r32(RTL839X_VLAN_PROFILE(profile
));
829 p
[1] = sw_r32(RTL839X_VLAN_PROFILE(profile
) + 4);
831 pr_info("VLAN profile %d: L2 learning: %d, UNKN L2MC FLD PMSK %d, \
832 UNKN IPMC FLD PMSK %d, UNKN IPv6MC FLD PMSK: %d",
833 profile
, p
[1] & 1, (p
[1] >> 1) & 0xfff, (p
[1] >> 13) & 0xfff,
835 pr_info("VLAN profile %d: raw %08x, %08x\n", profile
, p
[0], p
[1]);
838 static void rtl839x_stp_get(struct rtl838x_switch_priv
*priv
, u16 msti
, u32 port_state
[])
841 u32 cmd
= 1 << 16 /* Execute cmd */
843 | 5 << 12 /* Table type 0b101 */
845 priv
->r
->exec_tbl0_cmd(cmd
);
847 for (i
= 0; i
< 4; i
++)
848 port_state
[i
] = sw_r32(priv
->r
->tbl_access_data_0(i
));
851 static void rtl839x_stp_set(struct rtl838x_switch_priv
*priv
, u16 msti
, u32 port_state
[])
854 u32 cmd
= 1 << 16 /* Execute cmd */
855 | 1 << 15 /* Write */
856 | 5 << 12 /* Table type 0b101 */
858 for (i
= 0; i
< 4; i
++)
859 sw_w32(port_state
[i
], priv
->r
->tbl_access_data_0(i
));
860 priv
->r
->exec_tbl0_cmd(cmd
);
864 * Enables or disables the EEE/EEEP capability of a port
866 void rtl839x_port_eee_set(struct rtl838x_switch_priv
*priv
, int port
, bool enable
)
870 // This works only for Ethernet ports, and on the RTL839X, ports above 47 are SFP
875 pr_debug("In %s: setting port %d to %d\n", __func__
, port
, enable
);
876 v
= enable
? 0xf : 0x0;
878 // Set EEE for 100, 500, 1000MBit and 10GBit
879 sw_w32_mask(0xf << 8, v
<< 8, rtl839x_mac_force_mode_ctrl(port
));
881 // Set TX/RX EEE state
882 v
= enable
? 0x3 : 0x0;
883 sw_w32(v
, RTL839X_EEE_CTRL(port
));
885 priv
->ports
[port
].eee_enabled
= enable
;
889 * Get EEE own capabilities and negotiation result
891 int rtl839x_eee_port_ability(struct rtl838x_switch_priv
*priv
, struct ethtool_eee
*e
, int port
)
898 link
= rtl839x_get_port_reg_le(RTL839X_MAC_LINK_STS
);
899 if (!(link
& BIT_ULL(port
)))
902 if (sw_r32(rtl839x_mac_force_mode_ctrl(port
)) & BIT(8))
903 e
->advertised
|= ADVERTISED_100baseT_Full
;
905 if (sw_r32(rtl839x_mac_force_mode_ctrl(port
)) & BIT(10))
906 e
->advertised
|= ADVERTISED_1000baseT_Full
;
908 a
= rtl839x_get_port_reg_le(RTL839X_MAC_EEE_ABLTY
);
909 pr_info("Link partner: %016llx\n", a
);
910 if (rtl839x_get_port_reg_le(RTL839X_MAC_EEE_ABLTY
) & BIT_ULL(port
)) {
911 e
->lp_advertised
= ADVERTISED_100baseT_Full
;
912 e
->lp_advertised
|= ADVERTISED_1000baseT_Full
;
919 static void rtl839x_init_eee(struct rtl838x_switch_priv
*priv
, bool enable
)
923 pr_info("Setting up EEE, state: %d\n", enable
);
925 // Set wake timer for TX and pause timer both to 0x21
926 sw_w32_mask(0xff << 20| 0xff, 0x21 << 20| 0x21, RTL839X_EEE_TX_TIMER_GELITE_CTRL
);
927 // Set pause wake timer for GIGA-EEE to 0x11
928 sw_w32_mask(0xff << 20, 0x11 << 20, RTL839X_EEE_TX_TIMER_GIGA_CTRL
);
929 // Set pause wake timer for 10GBit ports to 0x11
930 sw_w32_mask(0xff << 20, 0x11 << 20, RTL839X_EEE_TX_TIMER_10G_CTRL
);
932 // Setup EEE on all ports
933 for (i
= 0; i
< priv
->cpu_port
; i
++) {
934 if (priv
->ports
[i
].phy
)
935 rtl839x_port_eee_set(priv
, i
, enable
);
937 priv
->eee_enabled
= enable
;
940 static void rtl839x_pie_lookup_enable(struct rtl838x_switch_priv
*priv
, int index
)
942 int block
= index
/ PIE_BLOCK_SIZE
;
944 sw_w32_mask(0, BIT(block
), RTL839X_ACL_BLK_LOOKUP_CTRL
);
948 * Delete a range of Packet Inspection Engine rules
950 static int rtl839x_pie_rule_del(struct rtl838x_switch_priv
*priv
, int index_from
, int index_to
)
952 u32 v
= (index_from
<< 1)| (index_to
<< 13 ) | BIT(0);
954 pr_debug("%s: from %d to %d\n", __func__
, index_from
, index_to
);
955 mutex_lock(&priv
->reg_mutex
);
957 // Write from-to and execute bit into control register
958 sw_w32(v
, RTL839X_ACL_CLR_CTRL
);
960 // Wait until command has completed
962 } while (sw_r32(RTL839X_ACL_CLR_CTRL
) & BIT(0));
964 mutex_unlock(&priv
->reg_mutex
);
969 * Reads the intermediate representation of the templated match-fields of the
970 * PIE rule in the pie_rule structure and fills in the raw data fields in the
971 * raw register space r[].
972 * The register space configuration size is identical for the RTL8380/90 and RTL9300,
973 * however the RTL9310 has 2 more registers / fields and the physical field-ids are different
975 * On the RTL8390 the template mask registers are not word-aligned!
977 static void rtl839x_write_pie_templated(u32 r
[], struct pie_rule
*pr
, enum template_field_id t
[])
980 enum template_field_id field_type
;
983 for (i
= 0; i
< N_FIXED_FIELDS
; i
++) {
987 switch (field_type
) {
988 case TEMPLATE_FIELD_SPM0
:
992 case TEMPLATE_FIELD_SPM1
:
993 data
= pr
->spm
>> 16;
994 data_m
= pr
->spm_m
>> 16;
996 case TEMPLATE_FIELD_SPM2
:
997 data
= pr
->spm
>> 32;
998 data_m
= pr
->spm_m
>> 32;
1000 case TEMPLATE_FIELD_SPM3
:
1001 data
= pr
->spm
>> 48;
1002 data_m
= pr
->spm_m
>> 48;
1004 case TEMPLATE_FIELD_OTAG
:
1006 data_m
= pr
->otag_m
;
1008 case TEMPLATE_FIELD_SMAC0
:
1010 data
= (data
<< 8) | pr
->smac
[5];
1011 data_m
= pr
->smac_m
[4];
1012 data_m
= (data_m
<< 8) | pr
->smac_m
[5];
1014 case TEMPLATE_FIELD_SMAC1
:
1016 data
= (data
<< 8) | pr
->smac
[3];
1017 data_m
= pr
->smac_m
[2];
1018 data_m
= (data_m
<< 8) | pr
->smac_m
[3];
1020 case TEMPLATE_FIELD_SMAC2
:
1022 data
= (data
<< 8) | pr
->smac
[1];
1023 data_m
= pr
->smac_m
[0];
1024 data_m
= (data_m
<< 8) | pr
->smac_m
[1];
1026 case TEMPLATE_FIELD_DMAC0
:
1028 data
= (data
<< 8) | pr
->dmac
[5];
1029 data_m
= pr
->dmac_m
[4];
1030 data_m
= (data_m
<< 8) | pr
->dmac_m
[5];
1032 case TEMPLATE_FIELD_DMAC1
:
1034 data
= (data
<< 8) | pr
->dmac
[3];
1035 data_m
= pr
->dmac_m
[2];
1036 data_m
= (data_m
<< 8) | pr
->dmac_m
[3];
1038 case TEMPLATE_FIELD_DMAC2
:
1040 data
= (data
<< 8) | pr
->dmac
[1];
1041 data_m
= pr
->dmac_m
[0];
1042 data_m
= (data_m
<< 8) | pr
->dmac_m
[1];
1044 case TEMPLATE_FIELD_ETHERTYPE
:
1045 data
= pr
->ethertype
;
1046 data_m
= pr
->ethertype_m
;
1048 case TEMPLATE_FIELD_ITAG
:
1050 data_m
= pr
->itag_m
;
1052 case TEMPLATE_FIELD_SIP0
:
1054 data
= pr
->sip6
.s6_addr16
[7];
1055 data_m
= pr
->sip6_m
.s6_addr16
[7];
1061 case TEMPLATE_FIELD_SIP1
:
1063 data
= pr
->sip6
.s6_addr16
[6];
1064 data_m
= pr
->sip6_m
.s6_addr16
[6];
1066 data
= pr
->sip
>> 16;
1067 data_m
= pr
->sip_m
>> 16;
1071 case TEMPLATE_FIELD_SIP2
:
1072 case TEMPLATE_FIELD_SIP3
:
1073 case TEMPLATE_FIELD_SIP4
:
1074 case TEMPLATE_FIELD_SIP5
:
1075 case TEMPLATE_FIELD_SIP6
:
1076 case TEMPLATE_FIELD_SIP7
:
1077 data
= pr
->sip6
.s6_addr16
[5 - (field_type
- TEMPLATE_FIELD_SIP2
)];
1078 data_m
= pr
->sip6_m
.s6_addr16
[5 - (field_type
- TEMPLATE_FIELD_SIP2
)];
1081 case TEMPLATE_FIELD_DIP0
:
1083 data
= pr
->dip6
.s6_addr16
[7];
1084 data_m
= pr
->dip6_m
.s6_addr16
[7];
1091 case TEMPLATE_FIELD_DIP1
:
1093 data
= pr
->dip6
.s6_addr16
[6];
1094 data_m
= pr
->dip6_m
.s6_addr16
[6];
1096 data
= pr
->dip
>> 16;
1097 data_m
= pr
->dip_m
>> 16;
1101 case TEMPLATE_FIELD_DIP2
:
1102 case TEMPLATE_FIELD_DIP3
:
1103 case TEMPLATE_FIELD_DIP4
:
1104 case TEMPLATE_FIELD_DIP5
:
1105 case TEMPLATE_FIELD_DIP6
:
1106 case TEMPLATE_FIELD_DIP7
:
1107 data
= pr
->dip6
.s6_addr16
[5 - (field_type
- TEMPLATE_FIELD_DIP2
)];
1108 data_m
= pr
->dip6_m
.s6_addr16
[5 - (field_type
- TEMPLATE_FIELD_DIP2
)];
1111 case TEMPLATE_FIELD_IP_TOS_PROTO
:
1112 data
= pr
->tos_proto
;
1113 data_m
= pr
->tos_proto_m
;
1115 case TEMPLATE_FIELD_L4_SPORT
:
1117 data_m
= pr
->sport_m
;
1119 case TEMPLATE_FIELD_L4_DPORT
:
1121 data_m
= pr
->dport_m
;
1123 case TEMPLATE_FIELD_ICMP_IGMP
:
1124 data
= pr
->icmp_igmp
;
1125 data_m
= pr
->icmp_igmp_m
;
1128 pr_info("%s: unknown field %d\n", __func__
, field_type
);
1131 // On the RTL8390, the mask fields are not word aligned!
1133 r
[5 - i
/ 2] = data
;
1134 r
[12 - i
/ 2] |= ((u32
)data_m
<< 8);
1136 r
[5 - i
/ 2] |= ((u32
)data
) << 16;
1137 r
[12 - i
/ 2] |= ((u32
)data_m
) << 24;
1138 r
[11 - i
/ 2] |= ((u32
)data_m
) >> 8;
1144 * Creates the intermediate representation of the templated match-fields of the
1145 * PIE rule in the pie_rule structure by reading the raw data fields in the
1146 * raw register space r[].
1147 * The register space configuration size is identical for the RTL8380/90 and RTL9300,
1148 * however the RTL9310 has 2 more registers / fields and the physical field-ids
1149 * On the RTL8390 the template mask registers are not word-aligned!
1151 void rtl839x_read_pie_templated(u32 r
[], struct pie_rule
*pr
, enum template_field_id t
[])
1154 enum template_field_id field_type
;
1157 for (i
= 0; i
< N_FIXED_FIELDS
; i
++) {
1160 data
= r
[5 - i
/ 2];
1161 data_m
= r
[12 - i
/ 2];
1163 data
= r
[5 - i
/ 2] >> 16;
1164 data_m
= r
[12 - i
/ 2] >> 16;
1167 switch (field_type
) {
1168 case TEMPLATE_FIELD_SPM0
:
1169 pr
->spm
= (pr
->spn
<< 16) | data
;
1170 pr
->spm_m
= (pr
->spn
<< 16) | data_m
;
1172 case TEMPLATE_FIELD_SPM1
:
1176 case TEMPLATE_FIELD_OTAG
:
1178 pr
->otag_m
= data_m
;
1180 case TEMPLATE_FIELD_SMAC0
:
1181 pr
->smac
[4] = data
>> 8;
1183 pr
->smac_m
[4] = data
>> 8;
1184 pr
->smac_m
[5] = data
;
1186 case TEMPLATE_FIELD_SMAC1
:
1187 pr
->smac
[2] = data
>> 8;
1189 pr
->smac_m
[2] = data
>> 8;
1190 pr
->smac_m
[3] = data
;
1192 case TEMPLATE_FIELD_SMAC2
:
1193 pr
->smac
[0] = data
>> 8;
1195 pr
->smac_m
[0] = data
>> 8;
1196 pr
->smac_m
[1] = data
;
1198 case TEMPLATE_FIELD_DMAC0
:
1199 pr
->dmac
[4] = data
>> 8;
1201 pr
->dmac_m
[4] = data
>> 8;
1202 pr
->dmac_m
[5] = data
;
1204 case TEMPLATE_FIELD_DMAC1
:
1205 pr
->dmac
[2] = data
>> 8;
1207 pr
->dmac_m
[2] = data
>> 8;
1208 pr
->dmac_m
[3] = data
;
1210 case TEMPLATE_FIELD_DMAC2
:
1211 pr
->dmac
[0] = data
>> 8;
1213 pr
->dmac_m
[0] = data
>> 8;
1214 pr
->dmac_m
[1] = data
;
1216 case TEMPLATE_FIELD_ETHERTYPE
:
1217 pr
->ethertype
= data
;
1218 pr
->ethertype_m
= data_m
;
1220 case TEMPLATE_FIELD_ITAG
:
1222 pr
->itag_m
= data_m
;
1224 case TEMPLATE_FIELD_SIP0
:
1228 case TEMPLATE_FIELD_SIP1
:
1229 pr
->sip
= (pr
->sip
<< 16) | data
;
1230 pr
->sip_m
= (pr
->sip
<< 16) | data_m
;
1232 case TEMPLATE_FIELD_SIP2
:
1234 // Make use of limitiations on the position of the match values
1235 ipv6_addr_set(&pr
->sip6
, pr
->sip
, r
[5 - i
/ 2],
1236 r
[4 - i
/ 2], r
[3 - i
/ 2]);
1237 ipv6_addr_set(&pr
->sip6_m
, pr
->sip_m
, r
[5 - i
/ 2],
1238 r
[4 - i
/ 2], r
[3 - i
/ 2]);
1239 case TEMPLATE_FIELD_SIP3
:
1240 case TEMPLATE_FIELD_SIP4
:
1241 case TEMPLATE_FIELD_SIP5
:
1242 case TEMPLATE_FIELD_SIP6
:
1243 case TEMPLATE_FIELD_SIP7
:
1246 case TEMPLATE_FIELD_DIP0
:
1251 case TEMPLATE_FIELD_DIP1
:
1252 pr
->dip
= (pr
->dip
<< 16) | data
;
1253 pr
->dip_m
= (pr
->dip
<< 16) | data_m
;
1256 case TEMPLATE_FIELD_DIP2
:
1258 ipv6_addr_set(&pr
->dip6
, pr
->dip
, r
[5 - i
/ 2],
1259 r
[4 - i
/ 2], r
[3 - i
/ 2]);
1260 ipv6_addr_set(&pr
->dip6_m
, pr
->dip_m
, r
[5 - i
/ 2],
1261 r
[4 - i
/ 2], r
[3 - i
/ 2]);
1262 case TEMPLATE_FIELD_DIP3
:
1263 case TEMPLATE_FIELD_DIP4
:
1264 case TEMPLATE_FIELD_DIP5
:
1265 case TEMPLATE_FIELD_DIP6
:
1266 case TEMPLATE_FIELD_DIP7
:
1268 case TEMPLATE_FIELD_IP_TOS_PROTO
:
1269 pr
->tos_proto
= data
;
1270 pr
->tos_proto_m
= data_m
;
1272 case TEMPLATE_FIELD_L4_SPORT
:
1274 pr
->sport_m
= data_m
;
1276 case TEMPLATE_FIELD_L4_DPORT
:
1278 pr
->dport_m
= data_m
;
1280 case TEMPLATE_FIELD_ICMP_IGMP
:
1281 pr
->icmp_igmp
= data
;
1282 pr
->icmp_igmp_m
= data_m
;
1285 pr_info("%s: unknown field %d\n", __func__
, field_type
);
1290 static void rtl839x_read_pie_fixed_fields(u32 r
[], struct pie_rule
*pr
)
1292 pr
->spmmask_fix
= (r
[6] >> 30) & 0x3;
1293 pr
->spn
= (r
[6] >> 24) & 0x3f;
1294 pr
->mgnt_vlan
= (r
[6] >> 23) & 1;
1295 pr
->dmac_hit_sw
= (r
[6] >> 22) & 1;
1296 pr
->not_first_frag
= (r
[6] >> 21) & 1;
1297 pr
->frame_type_l4
= (r
[6] >> 18) & 7;
1298 pr
->frame_type
= (r
[6] >> 16) & 3;
1299 pr
->otag_fmt
= (r
[6] >> 15) & 1;
1300 pr
->itag_fmt
= (r
[6] >> 14) & 1;
1301 pr
->otag_exist
= (r
[6] >> 13) & 1;
1302 pr
->itag_exist
= (r
[6] >> 12) & 1;
1303 pr
->frame_type_l2
= (r
[6] >> 10) & 3;
1304 pr
->tid
= (r
[6] >> 8) & 3;
1306 pr
->spmmask_fix_m
= (r
[12] >> 6) & 0x3;
1307 pr
->spn_m
= r
[12] & 0x3f;
1308 pr
->mgnt_vlan_m
= (r
[13] >> 31) & 1;
1309 pr
->dmac_hit_sw_m
= (r
[13] >> 30) & 1;
1310 pr
->not_first_frag_m
= (r
[13] >> 29) & 1;
1311 pr
->frame_type_l4_m
= (r
[13] >> 26) & 7;
1312 pr
->frame_type_m
= (r
[13] >> 24) & 3;
1313 pr
->otag_fmt_m
= (r
[13] >> 23) & 1;
1314 pr
->itag_fmt_m
= (r
[13] >> 22) & 1;
1315 pr
->otag_exist_m
= (r
[13] >> 21) & 1;
1316 pr
->itag_exist_m
= (r
[13] >> 20) & 1;
1317 pr
->frame_type_l2_m
= (r
[13] >> 18) & 3;
1318 pr
->tid_m
= (r
[13] >> 16) & 3;
1320 pr
->valid
= r
[13] & BIT(15);
1321 pr
->cond_not
= r
[13] & BIT(14);
1322 pr
->cond_and1
= r
[13] & BIT(13);
1323 pr
->cond_and2
= r
[13] & BIT(12);
1326 static void rtl839x_write_pie_fixed_fields(u32 r
[], struct pie_rule
*pr
)
1328 r
[6] = ((u32
) (pr
->spmmask_fix
& 0x3)) << 30;
1329 r
[6] |= ((u32
) (pr
->spn
& 0x3f)) << 24;
1330 r
[6] |= pr
->mgnt_vlan
? BIT(23) : 0;
1331 r
[6] |= pr
->dmac_hit_sw
? BIT(22) : 0;
1332 r
[6] |= pr
->not_first_frag
? BIT(21) : 0;
1333 r
[6] |= ((u32
) (pr
->frame_type_l4
& 0x7)) << 18;
1334 r
[6] |= ((u32
) (pr
->frame_type
& 0x3)) << 16;
1335 r
[6] |= pr
->otag_fmt
? BIT(15) : 0;
1336 r
[6] |= pr
->itag_fmt
? BIT(14) : 0;
1337 r
[6] |= pr
->otag_exist
? BIT(13) : 0;
1338 r
[6] |= pr
->itag_exist
? BIT(12) : 0;
1339 r
[6] |= ((u32
) (pr
->frame_type_l2
& 0x3)) << 10;
1340 r
[6] |= ((u32
) (pr
->tid
& 0x3)) << 8;
1342 r
[12] |= ((u32
) (pr
->spmmask_fix_m
& 0x3)) << 6;
1343 r
[12] |= (u32
) (pr
->spn_m
& 0x3f);
1344 r
[13] |= pr
->mgnt_vlan_m
? BIT(31) : 0;
1345 r
[13] |= pr
->dmac_hit_sw_m
? BIT(30) : 0;
1346 r
[13] |= pr
->not_first_frag_m
? BIT(29) : 0;
1347 r
[13] |= ((u32
) (pr
->frame_type_l4_m
& 0x7)) << 26;
1348 r
[13] |= ((u32
) (pr
->frame_type_m
& 0x3)) << 24;
1349 r
[13] |= pr
->otag_fmt_m
? BIT(23) : 0;
1350 r
[13] |= pr
->itag_fmt_m
? BIT(22) : 0;
1351 r
[13] |= pr
->otag_exist_m
? BIT(21) : 0;
1352 r
[13] |= pr
->itag_exist_m
? BIT(20) : 0;
1353 r
[13] |= ((u32
) (pr
->frame_type_l2_m
& 0x3)) << 18;
1354 r
[13] |= ((u32
) (pr
->tid_m
& 0x3)) << 16;
1356 r
[13] |= pr
->valid
? BIT(15) : 0;
1357 r
[13] |= pr
->cond_not
? BIT(14) : 0;
1358 r
[13] |= pr
->cond_and1
? BIT(13) : 0;
1359 r
[13] |= pr
->cond_and2
? BIT(12) : 0;
1362 static void rtl839x_write_pie_action(u32 r
[], struct pie_rule
*pr
)
1365 r
[13] |= 0x9; // Set ACT_MASK_FWD & FWD_ACT = DROP
1368 r
[13] |= pr
->fwd_sel
? BIT(3) : 0;
1369 r
[13] |= pr
->fwd_act
;
1371 r
[13] |= pr
->bypass_sel
? BIT(11) : 0;
1372 r
[13] |= pr
->mpls_sel
? BIT(10) : 0;
1373 r
[13] |= pr
->nopri_sel
? BIT(9) : 0;
1374 r
[13] |= pr
->ovid_sel
? BIT(8) : 0;
1375 r
[13] |= pr
->ivid_sel
? BIT(7) : 0;
1376 r
[13] |= pr
->meter_sel
? BIT(6) : 0;
1377 r
[13] |= pr
->mir_sel
? BIT(5) : 0;
1378 r
[13] |= pr
->log_sel
? BIT(4) : 0;
1380 r
[14] |= ((u32
)(pr
->fwd_data
& 0x3fff)) << 18;
1381 r
[14] |= pr
->log_octets
? BIT(17) : 0;
1382 r
[14] |= ((u32
)(pr
->log_data
& 0x7ff)) << 4;
1383 r
[14] |= (pr
->mir_data
& 0x3) << 3;
1384 r
[14] |= ((u32
)(pr
->meter_data
>> 7)) & 0x7;
1385 r
[15] |= (u32
)(pr
->meter_data
) << 26;
1386 r
[15] |= ((u32
)(pr
->ivid_act
) << 23) & 0x3;
1387 r
[15] |= ((u32
)(pr
->ivid_data
) << 9) & 0xfff;
1388 r
[15] |= ((u32
)(pr
->ovid_act
) << 6) & 0x3;
1389 r
[15] |= ((u32
)(pr
->ovid_data
) >> 4) & 0xff;
1390 r
[16] |= ((u32
)(pr
->ovid_data
) & 0xf) << 28;
1391 r
[16] |= ((u32
)(pr
->nopri_data
) & 0x7) << 20;
1392 r
[16] |= ((u32
)(pr
->mpls_act
) & 0x7) << 20;
1393 r
[16] |= ((u32
)(pr
->mpls_lib_idx
) & 0x7) << 20;
1394 r
[16] |= pr
->bypass_all
? BIT(9) : 0;
1395 r
[16] |= pr
->bypass_igr_stp
? BIT(8) : 0;
1396 r
[16] |= pr
->bypass_ibc_sc
? BIT(7) : 0;
1399 static void rtl839x_read_pie_action(u32 r
[], struct pie_rule
*pr
)
1401 if (r
[13] & BIT(3)) { // ACT_MASK_FWD set, is it a drop?
1402 if ((r
[14] & 0x7) == 1) {
1406 pr
->fwd_act
= r
[14] & 0x7;
1410 pr
->bypass_sel
= r
[13] & BIT(11);
1411 pr
->mpls_sel
= r
[13] & BIT(10);
1412 pr
->nopri_sel
= r
[13] & BIT(9);
1413 pr
->ovid_sel
= r
[13] & BIT(8);
1414 pr
->ivid_sel
= r
[13] & BIT(7);
1415 pr
->meter_sel
= r
[13] & BIT(6);
1416 pr
->mir_sel
= r
[13] & BIT(5);
1417 pr
->log_sel
= r
[13] & BIT(4);
1419 // TODO: Read in data fields
1421 pr
->bypass_all
= r
[16] & BIT(9);
1422 pr
->bypass_igr_stp
= r
[16] & BIT(8);
1423 pr
->bypass_ibc_sc
= r
[16] & BIT(7);
1426 void rtl839x_pie_rule_dump_raw(u32 r
[])
1428 pr_info("Raw IACL table entry:\n");
1429 pr_info("Match : %08x %08x %08x %08x %08x %08x\n", r
[0], r
[1], r
[2], r
[3], r
[4], r
[5]);
1430 pr_info("Fixed : %06x\n", r
[6] >> 8);
1431 pr_info("Match M: %08x %08x %08x %08x %08x %08x\n",
1432 (r
[6] << 24) | (r
[7] >> 8), (r
[7] << 24) | (r
[8] >> 8), (r
[8] << 24) | (r
[9] >> 8),
1433 (r
[9] << 24) | (r
[10] >> 8), (r
[10] << 24) | (r
[11] >> 8),
1434 (r
[11] << 24) | (r
[12] >> 8));
1435 pr_info("R[13]: %08x\n", r
[13]);
1436 pr_info("Fixed M: %06x\n", ((r
[12] << 16) | (r
[13] >> 16)) & 0xffffff);
1437 pr_info("Valid / not / and1 / and2 : %1x\n", (r
[13] >> 12) & 0xf);
1438 pr_info("r 13-16: %08x %08x %08x %08x\n", r
[13], r
[14], r
[15], r
[16]);
1441 void rtl839x_pie_rule_dump(struct pie_rule
*pr
)
1443 pr_info("Drop: %d, fwd: %d, ovid: %d, ivid: %d, flt: %d, log: %d, rmk: %d, meter: %d tagst: %d, mir: %d, nopri: %d, cpupri: %d, otpid: %d, itpid: %d, shape: %d\n",
1444 pr
->drop
, pr
->fwd_sel
, pr
->ovid_sel
, pr
->ivid_sel
, pr
->flt_sel
, pr
->log_sel
, pr
->rmk_sel
, pr
->log_sel
, pr
->tagst_sel
, pr
->mir_sel
, pr
->nopri_sel
,
1445 pr
->cpupri_sel
, pr
->otpid_sel
, pr
->itpid_sel
, pr
->shaper_sel
);
1447 pr_info("FWD: %08x\n", pr
->fwd_data
);
1448 pr_info("TID: %x, %x\n", pr
->tid
, pr
->tid_m
);
1451 static int rtl839x_pie_rule_read(struct rtl838x_switch_priv
*priv
, int idx
, struct pie_rule
*pr
)
1453 // Read IACL table (2) via register 0
1454 struct table_reg
*q
= rtl_table_get(RTL8380_TBL_0
, 2);
1457 int block
= idx
/ PIE_BLOCK_SIZE
;
1458 u32 t_select
= sw_r32(RTL839X_ACL_BLK_TMPLTE_CTRL(block
));
1460 memset(pr
, 0, sizeof(*pr
));
1461 rtl_table_read(q
, idx
);
1462 for (i
= 0; i
< 17; i
++)
1463 r
[i
] = sw_r32(rtl_table_data(q
, i
));
1465 rtl_table_release(q
);
1467 rtl839x_read_pie_fixed_fields(r
, pr
);
1471 pr_debug("%s: template_selectors %08x, tid: %d\n", __func__
, t_select
, pr
->tid
);
1472 rtl839x_pie_rule_dump_raw(r
);
1474 rtl839x_read_pie_templated(r
, pr
, fixed_templates
[(t_select
>> (pr
->tid
* 3)) & 0x7]);
1476 rtl839x_read_pie_action(r
, pr
);
1481 static int rtl839x_pie_rule_write(struct rtl838x_switch_priv
*priv
, int idx
, struct pie_rule
*pr
)
1483 // Access IACL table (2) via register 0
1484 struct table_reg
*q
= rtl_table_get(RTL8390_TBL_0
, 2);
1487 int block
= idx
/ PIE_BLOCK_SIZE
;
1488 u32 t_select
= sw_r32(RTL839X_ACL_BLK_TMPLTE_CTRL(block
));
1490 pr_debug("%s: %d, t_select: %08x\n", __func__
, idx
, t_select
);
1492 for (i
= 0; i
< 17; i
++)
1496 rtl_table_write(q
, idx
);
1497 rtl_table_release(q
);
1500 rtl839x_write_pie_fixed_fields(r
, pr
);
1502 pr_debug("%s: template %d\n", __func__
, (t_select
>> (pr
->tid
* 3)) & 0x7);
1503 rtl839x_write_pie_templated(r
, pr
, fixed_templates
[(t_select
>> (pr
->tid
* 3)) & 0x7]);
1505 rtl839x_write_pie_action(r
, pr
);
1507 // rtl839x_pie_rule_dump_raw(r);
1509 for (i
= 0; i
< 17; i
++)
1510 sw_w32(r
[i
], rtl_table_data(q
, i
));
1512 rtl_table_write(q
, idx
);
1513 rtl_table_release(q
);
1518 static bool rtl839x_pie_templ_has(int t
, enum template_field_id field_type
)
1521 enum template_field_id ft
;
1523 for (i
= 0; i
< N_FIXED_FIELDS
; i
++) {
1524 ft
= fixed_templates
[t
][i
];
1525 if (field_type
== ft
)
1532 static int rtl839x_pie_verify_template(struct rtl838x_switch_priv
*priv
,
1533 struct pie_rule
*pr
, int t
, int block
)
1537 if (!pr
->is_ipv6
&& pr
->sip_m
&& !rtl839x_pie_templ_has(t
, TEMPLATE_FIELD_SIP0
))
1540 if (!pr
->is_ipv6
&& pr
->dip_m
&& !rtl839x_pie_templ_has(t
, TEMPLATE_FIELD_DIP0
))
1544 if ((pr
->sip6_m
.s6_addr32
[0] || pr
->sip6_m
.s6_addr32
[1]
1545 || pr
->sip6_m
.s6_addr32
[2] || pr
->sip6_m
.s6_addr32
[3])
1546 && !rtl839x_pie_templ_has(t
, TEMPLATE_FIELD_SIP2
))
1548 if ((pr
->dip6_m
.s6_addr32
[0] || pr
->dip6_m
.s6_addr32
[1]
1549 || pr
->dip6_m
.s6_addr32
[2] || pr
->dip6_m
.s6_addr32
[3])
1550 && !rtl839x_pie_templ_has(t
, TEMPLATE_FIELD_DIP2
))
1554 if (ether_addr_to_u64(pr
->smac
) && !rtl839x_pie_templ_has(t
, TEMPLATE_FIELD_SMAC0
))
1557 if (ether_addr_to_u64(pr
->dmac
) && !rtl839x_pie_templ_has(t
, TEMPLATE_FIELD_DMAC0
))
1562 i
= find_first_zero_bit(&priv
->pie_use_bm
[block
* 4], PIE_BLOCK_SIZE
);
1564 if (i
>= PIE_BLOCK_SIZE
)
1567 return i
+ PIE_BLOCK_SIZE
* block
;
1570 static int rtl839x_pie_rule_add(struct rtl838x_switch_priv
*priv
, struct pie_rule
*pr
)
1572 int idx
, block
, j
, t
;
1574 int max_block
= priv
->n_pie_blocks
/ 2;
1576 if (pr
->is_egress
) {
1577 min_block
= max_block
;
1578 max_block
= priv
->n_pie_blocks
;
1581 mutex_lock(&priv
->pie_mutex
);
1583 for (block
= min_block
; block
< max_block
; block
++) {
1584 for (j
= 0; j
< 2; j
++) {
1585 t
= (sw_r32(RTL839X_ACL_BLK_TMPLTE_CTRL(block
)) >> (j
* 3)) & 0x7;
1586 idx
= rtl839x_pie_verify_template(priv
, pr
, t
, block
);
1594 if (block
>= priv
->n_pie_blocks
) {
1595 mutex_unlock(&priv
->pie_mutex
);
1599 set_bit(idx
, priv
->pie_use_bm
);
1602 pr
->tid
= j
; // Mapped to template number
1606 rtl839x_pie_lookup_enable(priv
, idx
);
1607 rtl839x_pie_rule_write(priv
, idx
, pr
);
1609 mutex_unlock(&priv
->pie_mutex
);
1613 static void rtl839x_pie_rule_rm(struct rtl838x_switch_priv
*priv
, struct pie_rule
*pr
)
1617 rtl839x_pie_rule_del(priv
, idx
, idx
);
1618 clear_bit(idx
, priv
->pie_use_bm
);
1621 static void rtl839x_pie_init(struct rtl838x_switch_priv
*priv
)
1624 u32 template_selectors
;
1626 mutex_init(&priv
->pie_mutex
);
1628 // Power on all PIE blocks
1629 for (i
= 0; i
< priv
->n_pie_blocks
; i
++)
1630 sw_w32_mask(0, BIT(i
), RTL839X_PS_ACL_PWR_CTRL
);
1632 // Set ingress and egress ACL blocks to 50/50: first Egress block is 9
1633 sw_w32_mask(0x1f, 9, RTL839X_ACL_CTRL
); // Writes 9 to cutline field
1635 // Include IPG in metering
1636 sw_w32(1, RTL839X_METER_GLB_CTRL
);
1638 // Delete all present rules
1639 rtl839x_pie_rule_del(priv
, 0, priv
->n_pie_blocks
* PIE_BLOCK_SIZE
- 1);
1641 // Enable predefined templates 0, 1 for blocks 0-2
1642 template_selectors
= 0 | (1 << 3);
1643 for (i
= 0; i
< 3; i
++)
1644 sw_w32(template_selectors
, RTL839X_ACL_BLK_TMPLTE_CTRL(i
));
1646 // Enable predefined templates 2, 3 for blocks 3-5
1647 template_selectors
= 2 | (3 << 3);
1648 for (i
= 3; i
< 6; i
++)
1649 sw_w32(template_selectors
, RTL839X_ACL_BLK_TMPLTE_CTRL(i
));
1651 // Enable predefined templates 1, 4 for blocks 6-8
1652 template_selectors
= 2 | (3 << 3);
1653 for (i
= 6; i
< 9; i
++)
1654 sw_w32(template_selectors
, RTL839X_ACL_BLK_TMPLTE_CTRL(i
));
1656 // Enable predefined templates 0, 1 for blocks 9-11
1657 template_selectors
= 0 | (1 << 3);
1658 for (i
= 9; i
< 12; i
++)
1659 sw_w32(template_selectors
, RTL839X_ACL_BLK_TMPLTE_CTRL(i
));
1661 // Enable predefined templates 2, 3 for blocks 12-14
1662 template_selectors
= 2 | (3 << 3);
1663 for (i
= 12; i
< 15; i
++)
1664 sw_w32(template_selectors
, RTL839X_ACL_BLK_TMPLTE_CTRL(i
));
1666 // Enable predefined templates 1, 4 for blocks 15-17
1667 template_selectors
= 2 | (3 << 3);
1668 for (i
= 15; i
< 18; i
++)
1669 sw_w32(template_selectors
, RTL839X_ACL_BLK_TMPLTE_CTRL(i
));
1672 static u32
rtl839x_packet_cntr_read(int counter
)
1676 // Read LOG table (4) via register RTL8390_TBL_0
1677 struct table_reg
*r
= rtl_table_get(RTL8390_TBL_0
, 4);
1679 pr_debug("In %s, id %d\n", __func__
, counter
);
1680 rtl_table_read(r
, counter
/ 2);
1682 // The table has a size of 2 registers
1684 v
= sw_r32(rtl_table_data(r
, 0));
1686 v
= sw_r32(rtl_table_data(r
, 1));
1688 rtl_table_release(r
);
1693 static void rtl839x_packet_cntr_clear(int counter
)
1695 // Access LOG table (4) via register RTL8390_TBL_0
1696 struct table_reg
*r
= rtl_table_get(RTL8390_TBL_0
, 4);
1698 pr_debug("In %s, id %d\n", __func__
, counter
);
1699 // The table has a size of 2 registers
1701 sw_w32(0, rtl_table_data(r
, 0));
1703 sw_w32(0, rtl_table_data(r
, 1));
1705 rtl_table_write(r
, counter
/ 2);
1707 rtl_table_release(r
);
1710 static void rtl839x_route_read(int idx
, struct rtl83xx_route
*rt
)
1713 // Read ROUTING table (2) via register RTL8390_TBL_1
1714 struct table_reg
*r
= rtl_table_get(RTL8390_TBL_1
, 2);
1716 pr_debug("In %s\n", __func__
);
1717 rtl_table_read(r
, idx
);
1719 // The table has a size of 2 registers
1720 v
= sw_r32(rtl_table_data(r
, 0));
1722 v
|= sw_r32(rtl_table_data(r
, 1));
1723 rt
->switch_mac_id
= (v
>> 12) & 0xf;
1724 rt
->nh
.gw
= v
>> 16;
1726 rtl_table_release(r
);
1729 static void rtl839x_route_write(int idx
, struct rtl83xx_route
*rt
)
1733 // Read ROUTING table (2) via register RTL8390_TBL_1
1734 struct table_reg
*r
= rtl_table_get(RTL8390_TBL_1
, 2);
1736 pr_debug("In %s\n", __func__
);
1737 sw_w32(rt
->nh
.gw
>> 16, rtl_table_data(r
, 0));
1738 v
= rt
->nh
.gw
<< 16;
1739 v
|= rt
->switch_mac_id
<< 12;
1740 sw_w32(v
, rtl_table_data(r
, 1));
1741 rtl_table_write(r
, idx
);
1743 rtl_table_release(r
);
1747 * Configure the switch's own MAC addresses used when routing packets
1749 static void rtl839x_setup_port_macs(struct rtl838x_switch_priv
*priv
)
1752 struct net_device
*dev
;
1755 pr_debug("%s: got port %08x\n", __func__
, (u32
)priv
->ports
[priv
->cpu_port
].dp
);
1756 dev
= priv
->ports
[priv
->cpu_port
].dp
->slave
;
1757 mac
= ether_addr_to_u64(dev
->dev_addr
);
1759 for (i
= 0; i
< 15; i
++) {
1760 mac
++; // BUG: VRRP for testing
1761 sw_w32(mac
>> 32, RTL839X_ROUTING_SA_CTRL
+ i
* 8);
1762 sw_w32(mac
, RTL839X_ROUTING_SA_CTRL
+ i
* 8 + 4);
1766 int rtl839x_l3_setup(struct rtl838x_switch_priv
*priv
)
1768 rtl839x_setup_port_macs(priv
);
1773 void rtl839x_vlan_port_keep_tag_set(int port
, bool keep_outer
, bool keep_inner
)
1775 sw_w32(FIELD_PREP(RTL839X_VLAN_PORT_TAG_STS_CTRL_OTAG_STS_MASK
,
1776 keep_outer
? RTL839X_VLAN_PORT_TAG_STS_TAGGED
: RTL839X_VLAN_PORT_TAG_STS_UNTAG
) |
1777 FIELD_PREP(RTL839X_VLAN_PORT_TAG_STS_CTRL_ITAG_STS_MASK
,
1778 keep_inner
? RTL839X_VLAN_PORT_TAG_STS_TAGGED
: RTL839X_VLAN_PORT_TAG_STS_UNTAG
),
1779 RTL839X_VLAN_PORT_TAG_STS_CTRL(port
));
1782 void rtl839x_vlan_port_pvidmode_set(int port
, enum pbvlan_type type
, enum pbvlan_mode mode
)
1784 if (type
== PBVLAN_TYPE_INNER
)
1785 sw_w32_mask(0x3, mode
, RTL839X_VLAN_PORT_PB_VLAN
+ (port
<< 2));
1787 sw_w32_mask(0x3 << 14, mode
<< 14, RTL839X_VLAN_PORT_PB_VLAN
+ (port
<< 2));
1790 void rtl839x_vlan_port_pvid_set(int port
, enum pbvlan_type type
, int pvid
)
1792 if (type
== PBVLAN_TYPE_INNER
)
1793 sw_w32_mask(0xfff << 2, pvid
<< 2, RTL839X_VLAN_PORT_PB_VLAN
+ (port
<< 2));
1795 sw_w32_mask(0xfff << 16, pvid
<< 16, RTL839X_VLAN_PORT_PB_VLAN
+ (port
<< 2));
1798 static int rtl839x_set_ageing_time(unsigned long msec
)
1800 int t
= sw_r32(RTL839X_L2_CTRL_1
);
1803 t
= t
* 3 / 5; /* Aging time in seconds. 0: L2 aging disabled */
1804 pr_debug("L2 AGING time: %d sec\n", t
);
1806 t
= (msec
* 5 + 2000) / 3000;
1807 t
= t
> 0x1FFFFF ? 0x1FFFFF : t
;
1808 sw_w32_mask(0x1FFFFF, t
, RTL839X_L2_CTRL_1
);
1809 pr_debug("Dynamic aging for ports: %x\n", sw_r32(RTL839X_L2_PORT_AGING_OUT
));
1814 static void rtl839x_set_igr_filter(int port
, enum igr_filter state
)
1816 sw_w32_mask(0x3 << ((port
& 0xf)<<1), state
<< ((port
& 0xf)<<1),
1817 RTL839X_VLAN_PORT_IGR_FLTR
+ (((port
>> 4) << 2)));
1820 static void rtl839x_set_egr_filter(int port
, enum egr_filter state
)
1822 sw_w32_mask(0x1 << (port
% 0x20), state
<< (port
% 0x20),
1823 RTL839X_VLAN_PORT_EGR_FLTR
+ (((port
>> 5) << 2)));
1826 void rtl839x_set_distribution_algorithm(int group
, int algoidx
, u32 algomsk
)
1828 sw_w32_mask(3 << ((group
& 0xf) << 1), algoidx
<< ((group
& 0xf) << 1),
1829 RTL839X_TRK_HASH_IDX_CTRL
+ ((group
>> 4) << 2));
1830 sw_w32(algomsk
, RTL839X_TRK_HASH_CTRL
+ (algoidx
<< 2));
1833 void rtl839x_set_receive_management_action(int port
, rma_ctrl_t type
, action_type_t action
)
1837 sw_w32_mask(3 << ((port
& 0xf) << 1), (action
& 0x3) << ((port
& 0xf) << 1),
1838 RTL839X_RMA_BPDU_CTRL
+ ((port
>> 4) << 2));
1841 sw_w32_mask(3 << ((port
& 0xf) << 1), (action
& 0x3) << ((port
& 0xf) << 1),
1842 RTL839X_RMA_PTP_CTRL
+ ((port
>> 4) << 2));
1845 sw_w32_mask(3 << ((port
& 0xf) << 1), (action
& 0x3) << ((port
& 0xf) << 1),
1846 RTL839X_RMA_LLTP_CTRL
+ ((port
>> 4) << 2));
1853 const struct rtl838x_reg rtl839x_reg
= {
1854 .mask_port_reg_be
= rtl839x_mask_port_reg_be
,
1855 .set_port_reg_be
= rtl839x_set_port_reg_be
,
1856 .get_port_reg_be
= rtl839x_get_port_reg_be
,
1857 .mask_port_reg_le
= rtl839x_mask_port_reg_le
,
1858 .set_port_reg_le
= rtl839x_set_port_reg_le
,
1859 .get_port_reg_le
= rtl839x_get_port_reg_le
,
1860 .stat_port_rst
= RTL839X_STAT_PORT_RST
,
1861 .stat_rst
= RTL839X_STAT_RST
,
1862 .stat_port_std_mib
= RTL839X_STAT_PORT_STD_MIB
,
1863 .traffic_enable
= rtl839x_traffic_enable
,
1864 .traffic_disable
= rtl839x_traffic_disable
,
1865 .traffic_get
= rtl839x_traffic_get
,
1866 .traffic_set
= rtl839x_traffic_set
,
1867 .port_iso_ctrl
= rtl839x_port_iso_ctrl
,
1868 .l2_ctrl_0
= RTL839X_L2_CTRL_0
,
1869 .l2_ctrl_1
= RTL839X_L2_CTRL_1
,
1870 .l2_port_aging_out
= RTL839X_L2_PORT_AGING_OUT
,
1871 .set_ageing_time
= rtl839x_set_ageing_time
,
1872 .smi_poll_ctrl
= RTL839X_SMI_PORT_POLLING_CTRL
,
1873 .l2_tbl_flush_ctrl
= RTL839X_L2_TBL_FLUSH_CTRL
,
1874 .exec_tbl0_cmd
= rtl839x_exec_tbl0_cmd
,
1875 .exec_tbl1_cmd
= rtl839x_exec_tbl1_cmd
,
1876 .tbl_access_data_0
= rtl839x_tbl_access_data_0
,
1877 .isr_glb_src
= RTL839X_ISR_GLB_SRC
,
1878 .isr_port_link_sts_chg
= RTL839X_ISR_PORT_LINK_STS_CHG
,
1879 .imr_port_link_sts_chg
= RTL839X_IMR_PORT_LINK_STS_CHG
,
1880 .imr_glb
= RTL839X_IMR_GLB
,
1881 .vlan_tables_read
= rtl839x_vlan_tables_read
,
1882 .vlan_set_tagged
= rtl839x_vlan_set_tagged
,
1883 .vlan_set_untagged
= rtl839x_vlan_set_untagged
,
1884 .vlan_profile_dump
= rtl839x_vlan_profile_dump
,
1885 .vlan_profile_setup
= rtl839x_vlan_profile_setup
,
1886 .vlan_fwd_on_inner
= rtl839x_vlan_fwd_on_inner
,
1887 .vlan_port_keep_tag_set
= rtl839x_vlan_port_keep_tag_set
,
1888 .vlan_port_pvidmode_set
= rtl839x_vlan_port_pvidmode_set
,
1889 .vlan_port_pvid_set
= rtl839x_vlan_port_pvid_set
,
1890 .set_vlan_igr_filter
= rtl839x_set_igr_filter
,
1891 .set_vlan_egr_filter
= rtl839x_set_egr_filter
,
1892 .enable_learning
= rtl839x_enable_learning
,
1893 .enable_flood
= rtl839x_enable_flood
,
1894 .enable_mcast_flood
= rtl839x_enable_mcast_flood
,
1895 .enable_bcast_flood
= rtl839x_enable_bcast_flood
,
1896 .stp_get
= rtl839x_stp_get
,
1897 .stp_set
= rtl839x_stp_set
,
1898 .mac_force_mode_ctrl
= rtl839x_mac_force_mode_ctrl
,
1899 .mac_port_ctrl
= rtl839x_mac_port_ctrl
,
1900 .l2_port_new_salrn
= rtl839x_l2_port_new_salrn
,
1901 .l2_port_new_sa_fwd
= rtl839x_l2_port_new_sa_fwd
,
1902 .mir_ctrl
= RTL839X_MIR_CTRL
,
1903 .mir_dpm
= RTL839X_MIR_DPM_CTRL
,
1904 .mir_spm
= RTL839X_MIR_SPM_CTRL
,
1905 .mac_link_sts
= RTL839X_MAC_LINK_STS
,
1906 .mac_link_dup_sts
= RTL839X_MAC_LINK_DUP_STS
,
1907 .mac_link_spd_sts
= rtl839x_mac_link_spd_sts
,
1908 .mac_rx_pause_sts
= RTL839X_MAC_RX_PAUSE_STS
,
1909 .mac_tx_pause_sts
= RTL839X_MAC_TX_PAUSE_STS
,
1910 .read_l2_entry_using_hash
= rtl839x_read_l2_entry_using_hash
,
1911 .write_l2_entry_using_hash
= rtl839x_write_l2_entry_using_hash
,
1912 .read_cam
= rtl839x_read_cam
,
1913 .write_cam
= rtl839x_write_cam
,
1914 .trk_mbr_ctr
= rtl839x_trk_mbr_ctr
,
1915 .rma_bpdu_fld_pmask
= RTL839X_RMA_BPDU_FLD_PMSK
,
1916 .spcl_trap_eapol_ctrl
= RTL839X_SPCL_TRAP_EAPOL_CTRL
,
1917 .init_eee
= rtl839x_init_eee
,
1918 .port_eee_set
= rtl839x_port_eee_set
,
1919 .eee_port_ability
= rtl839x_eee_port_ability
,
1920 .l2_hash_seed
= rtl839x_l2_hash_seed
,
1921 .l2_hash_key
= rtl839x_l2_hash_key
,
1922 .read_mcast_pmask
= rtl839x_read_mcast_pmask
,
1923 .write_mcast_pmask
= rtl839x_write_mcast_pmask
,
1924 .pie_init
= rtl839x_pie_init
,
1925 .pie_rule_read
= rtl839x_pie_rule_read
,
1926 .pie_rule_write
= rtl839x_pie_rule_write
,
1927 .pie_rule_add
= rtl839x_pie_rule_add
,
1928 .pie_rule_rm
= rtl839x_pie_rule_rm
,
1929 .l2_learning_setup
= rtl839x_l2_learning_setup
,
1930 .packet_cntr_read
= rtl839x_packet_cntr_read
,
1931 .packet_cntr_clear
= rtl839x_packet_cntr_clear
,
1932 .route_read
= rtl839x_route_read
,
1933 .route_write
= rtl839x_route_write
,
1934 .l3_setup
= rtl839x_l3_setup
,
1935 .set_distribution_algorithm
= rtl839x_set_distribution_algorithm
,
1936 .set_receive_management_action
= rtl839x_set_receive_management_action
,