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realtek: Reduce variable scopes
[openwrt/staging/nbd.git] / target / linux / realtek / files-5.15 / drivers / net / dsa / rtl83xx / rtl838x.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <asm/mach-rtl838x/mach-rtl83xx.h>
4 #include <linux/iopoll.h>
5 #include <net/nexthop.h>
6
7 #include "rtl83xx.h"
8
9 #define RTL838X_VLAN_PORT_TAG_STS_UNTAG 0x0
10 #define RTL838X_VLAN_PORT_TAG_STS_TAGGED 0x1
11 #define RTL838X_VLAN_PORT_TAG_STS_PRIORITY_TAGGED 0x2
12
13 #define RTL838X_VLAN_PORT_TAG_STS_CTRL_BASE 0xA530
14 /* port 0-28 */
15 #define RTL838X_VLAN_PORT_TAG_STS_CTRL(port) \
16 RTL838X_VLAN_PORT_TAG_STS_CTRL_BASE + (port << 2)
17
18 #define RTL838X_VLAN_PORT_TAG_STS_CTRL_EGR_P_OTAG_KEEP_MASK GENMASK(11,10)
19 #define RTL838X_VLAN_PORT_TAG_STS_CTRL_EGR_P_ITAG_KEEP_MASK GENMASK(9,8)
20 #define RTL838X_VLAN_PORT_TAG_STS_CTRL_IGR_P_OTAG_KEEP_MASK GENMASK(7,6)
21 #define RTL838X_VLAN_PORT_TAG_STS_CTRL_IGR_P_ITAG_KEEP_MASK GENMASK(5,4)
22 #define RTL838X_VLAN_PORT_TAG_STS_CTRL_OTAG_STS_MASK GENMASK(3,2)
23 #define RTL838X_VLAN_PORT_TAG_STS_CTRL_ITAG_STS_MASK GENMASK(1,0)
24
25 extern struct mutex smi_lock;
26
27 /* see_dal_maple_acl_log2PhyTmplteField and src/app/diag_v2/src/diag_acl.c */
28 /* Definition of the RTL838X-specific template field IDs as used in the PIE */
29 enum template_field_id {
30 TEMPLATE_FIELD_SPMMASK = 0,
31 TEMPLATE_FIELD_SPM0 = 1, /* Source portmask ports 0-15 */
32 TEMPLATE_FIELD_SPM1 = 2, /* Source portmask ports 16-28 */
33 TEMPLATE_FIELD_RANGE_CHK = 3,
34 TEMPLATE_FIELD_DMAC0 = 4, /* Destination MAC [15:0] */
35 TEMPLATE_FIELD_DMAC1 = 5, /* Destination MAC [31:16] */
36 TEMPLATE_FIELD_DMAC2 = 6, /* Destination MAC [47:32] */
37 TEMPLATE_FIELD_SMAC0 = 7, /* Source MAC [15:0] */
38 TEMPLATE_FIELD_SMAC1 = 8, /* Source MAC [31:16] */
39 TEMPLATE_FIELD_SMAC2 = 9, /* Source MAC [47:32] */
40 TEMPLATE_FIELD_ETHERTYPE = 10, /* Ethernet typ */
41 TEMPLATE_FIELD_OTAG = 11, /* Outer VLAN tag */
42 TEMPLATE_FIELD_ITAG = 12, /* Inner VLAN tag */
43 TEMPLATE_FIELD_SIP0 = 13, /* IPv4 or IPv6 source IP[15:0] or ARP/RARP */
44 /* source protocol address in header */
45 TEMPLATE_FIELD_SIP1 = 14, /* IPv4 or IPv6 source IP[31:16] or ARP/RARP */
46 TEMPLATE_FIELD_DIP0 = 15, /* IPv4 or IPv6 destination IP[15:0] */
47 TEMPLATE_FIELD_DIP1 = 16, /* IPv4 or IPv6 destination IP[31:16] */
48 TEMPLATE_FIELD_IP_TOS_PROTO = 17, /* IPv4 TOS/IPv6 traffic class and */
49 /* IPv4 proto/IPv6 next header fields */
50 TEMPLATE_FIELD_L34_HEADER = 18, /* packet with extra tag and IPv6 with auth, dest, */
51 /* frag, route, hop-by-hop option header, */
52 /* IGMP type, TCP flag */
53 TEMPLATE_FIELD_L4_SPORT = 19, /* TCP/UDP source port */
54 TEMPLATE_FIELD_L4_DPORT = 20, /* TCP/UDP destination port */
55 TEMPLATE_FIELD_ICMP_IGMP = 21,
56 TEMPLATE_FIELD_IP_RANGE = 22,
57 TEMPLATE_FIELD_FIELD_SELECTOR_VALID = 23, /* Field selector mask */
58 TEMPLATE_FIELD_FIELD_SELECTOR_0 = 24,
59 TEMPLATE_FIELD_FIELD_SELECTOR_1 = 25,
60 TEMPLATE_FIELD_FIELD_SELECTOR_2 = 26,
61 TEMPLATE_FIELD_FIELD_SELECTOR_3 = 27,
62 TEMPLATE_FIELD_SIP2 = 28, /* IPv6 source IP[47:32] */
63 TEMPLATE_FIELD_SIP3 = 29, /* IPv6 source IP[63:48] */
64 TEMPLATE_FIELD_SIP4 = 30, /* IPv6 source IP[79:64] */
65 TEMPLATE_FIELD_SIP5 = 31, /* IPv6 source IP[95:80] */
66 TEMPLATE_FIELD_SIP6 = 32, /* IPv6 source IP[111:96] */
67 TEMPLATE_FIELD_SIP7 = 33, /* IPv6 source IP[127:112] */
68 TEMPLATE_FIELD_DIP2 = 34, /* IPv6 destination IP[47:32] */
69 TEMPLATE_FIELD_DIP3 = 35, /* IPv6 destination IP[63:48] */
70 TEMPLATE_FIELD_DIP4 = 36, /* IPv6 destination IP[79:64] */
71 TEMPLATE_FIELD_DIP5 = 37, /* IPv6 destination IP[95:80] */
72 TEMPLATE_FIELD_DIP6 = 38, /* IPv6 destination IP[111:96] */
73 TEMPLATE_FIELD_DIP7 = 39, /* IPv6 destination IP[127:112] */
74 TEMPLATE_FIELD_FWD_VID = 40, /* Forwarding VLAN-ID */
75 TEMPLATE_FIELD_FLOW_LABEL = 41,
76 };
77
78 /* The RTL838X SoCs use 5 fixed templates with definitions for which data fields are to
79 * be copied from the Ethernet Frame header into the 12 User-definable fields of the Packet
80 * Inspection Engine's buffer. The following defines the field contents for each of the fixed
81 * templates. Additionally, 3 user-definable templates can be set up via the definitions
82 * in RTL838X_ACL_TMPLTE_CTRL control registers.
83 * TODO: See all src/app/diag_v2/src/diag_pie.c
84 */
85 #define N_FIXED_TEMPLATES 5
86 static enum template_field_id fixed_templates[N_FIXED_TEMPLATES][N_FIXED_FIELDS] =
87 {
88 {
89 TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1, TEMPLATE_FIELD_OTAG,
90 TEMPLATE_FIELD_SMAC0, TEMPLATE_FIELD_SMAC1, TEMPLATE_FIELD_SMAC2,
91 TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2,
92 TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_ITAG, TEMPLATE_FIELD_RANGE_CHK
93 }, {
94 TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0,
95 TEMPLATE_FIELD_DIP1,TEMPLATE_FIELD_IP_TOS_PROTO, TEMPLATE_FIELD_L4_SPORT,
96 TEMPLATE_FIELD_L4_DPORT, TEMPLATE_FIELD_ICMP_IGMP, TEMPLATE_FIELD_ITAG,
97 TEMPLATE_FIELD_RANGE_CHK, TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1
98 }, {
99 TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2,
100 TEMPLATE_FIELD_ITAG, TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_IP_TOS_PROTO,
101 TEMPLATE_FIELD_L4_DPORT, TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_SIP0,
102 TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0, TEMPLATE_FIELD_DIP1
103 }, {
104 TEMPLATE_FIELD_DIP0, TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_DIP2,
105 TEMPLATE_FIELD_DIP3, TEMPLATE_FIELD_DIP4, TEMPLATE_FIELD_DIP5,
106 TEMPLATE_FIELD_DIP6, TEMPLATE_FIELD_DIP7, TEMPLATE_FIELD_L4_DPORT,
107 TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_ICMP_IGMP, TEMPLATE_FIELD_IP_TOS_PROTO
108 }, {
109 TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_SIP2,
110 TEMPLATE_FIELD_SIP3, TEMPLATE_FIELD_SIP4, TEMPLATE_FIELD_SIP5,
111 TEMPLATE_FIELD_SIP6, TEMPLATE_FIELD_SIP7, TEMPLATE_FIELD_ITAG,
112 TEMPLATE_FIELD_RANGE_CHK, TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1
113 },
114 };
115
116 void rtl838x_print_matrix(void)
117 {
118 unsigned volatile int *ptr8;
119
120 ptr8 = RTL838X_SW_BASE + RTL838X_PORT_ISO_CTRL(0);
121 for (int i = 0; i < 28; i += 8)
122 pr_debug("> %8x %8x %8x %8x %8x %8x %8x %8x\n",
123 ptr8[i + 0], ptr8[i + 1], ptr8[i + 2], ptr8[i + 3],
124 ptr8[i + 4], ptr8[i + 5], ptr8[i + 6], ptr8[i + 7]);
125 pr_debug("CPU_PORT> %8x\n", ptr8[28]);
126 }
127
128 static inline int rtl838x_port_iso_ctrl(int p)
129 {
130 return RTL838X_PORT_ISO_CTRL(p);
131 }
132
133 static inline void rtl838x_exec_tbl0_cmd(u32 cmd)
134 {
135 sw_w32(cmd, RTL838X_TBL_ACCESS_CTRL_0);
136 do { } while (sw_r32(RTL838X_TBL_ACCESS_CTRL_0) & BIT(15));
137 }
138
139 static inline void rtl838x_exec_tbl1_cmd(u32 cmd)
140 {
141 sw_w32(cmd, RTL838X_TBL_ACCESS_CTRL_1);
142 do { } while (sw_r32(RTL838X_TBL_ACCESS_CTRL_1) & BIT(15));
143 }
144
145 static inline int rtl838x_tbl_access_data_0(int i)
146 {
147 return RTL838X_TBL_ACCESS_DATA_0(i);
148 }
149
150 static void rtl838x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info)
151 {
152 u32 v;
153 /* Read VLAN table (0) via register 0 */
154 struct table_reg *r = rtl_table_get(RTL8380_TBL_0, 0);
155
156 rtl_table_read(r, vlan);
157 info->tagged_ports = sw_r32(rtl_table_data(r, 0));
158 v = sw_r32(rtl_table_data(r, 1));
159 pr_debug("VLAN_READ %d: %016llx %08x\n", vlan, info->tagged_ports, v);
160 rtl_table_release(r);
161
162 info->profile_id = v & 0x7;
163 info->hash_mc_fid = !!(v & 0x8);
164 info->hash_uc_fid = !!(v & 0x10);
165 info->fid = (v >> 5) & 0x3f;
166
167 /* Read UNTAG table (0) via table register 1 */
168 r = rtl_table_get(RTL8380_TBL_1, 0);
169 rtl_table_read(r, vlan);
170 info->untagged_ports = sw_r32(rtl_table_data(r, 0));
171 rtl_table_release(r);
172 }
173
174 static void rtl838x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info)
175 {
176 u32 v;
177 /* Access VLAN table (0) via register 0 */
178 struct table_reg *r = rtl_table_get(RTL8380_TBL_0, 0);
179
180 sw_w32(info->tagged_ports, rtl_table_data(r, 0));
181
182 v = info->profile_id;
183 v |= info->hash_mc_fid ? 0x8 : 0;
184 v |= info->hash_uc_fid ? 0x10 : 0;
185 v |= ((u32)info->fid) << 5;
186 sw_w32(v, rtl_table_data(r, 1));
187
188 rtl_table_write(r, vlan);
189 rtl_table_release(r);
190 }
191
192 static void rtl838x_vlan_set_untagged(u32 vlan, u64 portmask)
193 {
194 /* Access UNTAG table (0) via register 1 */
195 struct table_reg *r = rtl_table_get(RTL8380_TBL_1, 0);
196
197 sw_w32(portmask & 0x1fffffff, rtl_table_data(r, 0));
198 rtl_table_write(r, vlan);
199 rtl_table_release(r);
200 }
201
202 /* Sets the L2 forwarding to be based on either the inner VLAN tag or the outer
203 */
204 static void rtl838x_vlan_fwd_on_inner(int port, bool is_set)
205 {
206 if (is_set)
207 sw_w32_mask(BIT(port), 0, RTL838X_VLAN_PORT_FWD);
208 else
209 sw_w32_mask(0, BIT(port), RTL838X_VLAN_PORT_FWD);
210 }
211
212 static u64 rtl838x_l2_hash_seed(u64 mac, u32 vid)
213 {
214 return mac << 12 | vid;
215 }
216
217 /* Applies the same hash algorithm as the one used currently by the ASIC to the seed
218 * and returns a key into the L2 hash table
219 */
220 static u32 rtl838x_l2_hash_key(struct rtl838x_switch_priv *priv, u64 seed)
221 {
222 u32 h1, h2, h3, h;
223
224 if (sw_r32(priv->r->l2_ctrl_0) & 1) {
225 h1 = (seed >> 11) & 0x7ff;
226 h1 = ((h1 & 0x1f) << 6) | ((h1 >> 5) & 0x3f);
227
228 h2 = (seed >> 33) & 0x7ff;
229 h2 = ((h2 & 0x3f) << 5) | ((h2 >> 6) & 0x1f);
230
231 h3 = (seed >> 44) & 0x7ff;
232 h3 = ((h3 & 0x7f) << 4) | ((h3 >> 7) & 0xf);
233
234 h = h1 ^ h2 ^ h3 ^ ((seed >> 55) & 0x1ff);
235 h ^= ((seed >> 22) & 0x7ff) ^ (seed & 0x7ff);
236 } else {
237 h = ((seed >> 55) & 0x1ff) ^ ((seed >> 44) & 0x7ff) ^
238 ((seed >> 33) & 0x7ff) ^ ((seed >> 22) & 0x7ff) ^
239 ((seed >> 11) & 0x7ff) ^ (seed & 0x7ff);
240 }
241
242 return h;
243 }
244
245 static inline int rtl838x_mac_force_mode_ctrl(int p)
246 {
247 return RTL838X_MAC_FORCE_MODE_CTRL + (p << 2);
248 }
249
250 static inline int rtl838x_mac_port_ctrl(int p)
251 {
252 return RTL838X_MAC_PORT_CTRL(p);
253 }
254
255 static inline int rtl838x_l2_port_new_salrn(int p)
256 {
257 return RTL838X_L2_PORT_NEW_SALRN(p);
258 }
259
260 static inline int rtl838x_l2_port_new_sa_fwd(int p)
261 {
262 return RTL838X_L2_PORT_NEW_SA_FWD(p);
263 }
264
265 static inline int rtl838x_mac_link_spd_sts(int p)
266 {
267 return RTL838X_MAC_LINK_SPD_STS(p);
268 }
269
270 inline static int rtl838x_trk_mbr_ctr(int group)
271 {
272 return RTL838X_TRK_MBR_CTR + (group << 2);
273 }
274
275 /* Fills an L2 entry structure from the SoC registers */
276 static void rtl838x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e)
277 {
278 /* Table contains different entry types, we need to identify the right one:
279 * Check for MC entries, first
280 * In contrast to the RTL93xx SoCs, there is no valid bit, use heuristics to
281 * identify valid entries
282 */
283 e->is_ip_mc = !!(r[0] & BIT(22));
284 e->is_ipv6_mc = !!(r[0] & BIT(21));
285 e->type = L2_INVALID;
286
287 if (!e->is_ip_mc && !e->is_ipv6_mc) {
288 e->mac[0] = (r[1] >> 20);
289 e->mac[1] = (r[1] >> 12);
290 e->mac[2] = (r[1] >> 4);
291 e->mac[3] = (r[1] & 0xf) << 4 | (r[2] >> 28);
292 e->mac[4] = (r[2] >> 20);
293 e->mac[5] = (r[2] >> 12);
294
295 e->rvid = r[2] & 0xfff;
296 e->vid = r[0] & 0xfff;
297
298 /* Is it a unicast entry? check multicast bit */
299 if (!(e->mac[0] & 1)) {
300 e->is_static = !!((r[0] >> 19) & 1);
301 e->port = (r[0] >> 12) & 0x1f;
302 e->block_da = !!(r[1] & BIT(30));
303 e->block_sa = !!(r[1] & BIT(31));
304 e->suspended = !!(r[1] & BIT(29));
305 e->next_hop = !!(r[1] & BIT(28));
306 if (e->next_hop) {
307 pr_debug("Found next hop entry, need to read extra data\n");
308 e->nh_vlan_target = !!(r[0] & BIT(9));
309 e->nh_route_id = r[0] & 0x1ff;
310 e->vid = e->rvid;
311 }
312 e->age = (r[0] >> 17) & 0x3;
313 e->valid = true;
314
315 /* A valid entry has one of mutli-cast, aging, sa/da-blocking,
316 * next-hop or static entry bit set
317 */
318 if (!(r[0] & 0x007c0000) && !(r[1] & 0xd0000000))
319 e->valid = false;
320 else
321 e->type = L2_UNICAST;
322 } else { /* L2 multicast */
323 pr_debug("Got L2 MC entry: %08x %08x %08x\n", r[0], r[1], r[2]);
324 e->valid = true;
325 e->type = L2_MULTICAST;
326 e->mc_portmask_index = (r[0] >> 12) & 0x1ff;
327 }
328 } else { /* IPv4 and IPv6 multicast */
329 e->valid = true;
330 e->mc_portmask_index = (r[0] >> 12) & 0x1ff;
331 e->mc_gip = (r[1] << 20) | (r[2] >> 12);
332 e->rvid = r[2] & 0xfff;
333 }
334 if (e->is_ip_mc)
335 e->type = IP4_MULTICAST;
336 if (e->is_ipv6_mc)
337 e->type = IP6_MULTICAST;
338 }
339
340 /* Fills the 3 SoC table registers r[] with the information of in the rtl838x_l2_entry */
341 static void rtl838x_fill_l2_row(u32 r[], struct rtl838x_l2_entry *e)
342 {
343 u64 mac = ether_addr_to_u64(e->mac);
344
345 if (!e->valid) {
346 r[0] = r[1] = r[2] = 0;
347 return;
348 }
349
350 r[0] = e->is_ip_mc ? BIT(22) : 0;
351 r[0] |= e->is_ipv6_mc ? BIT(21) : 0;
352
353 if (!e->is_ip_mc && !e->is_ipv6_mc) {
354 r[1] = mac >> 20;
355 r[2] = (mac & 0xfffff) << 12;
356
357 /* Is it a unicast entry? check multicast bit */
358 if (!(e->mac[0] & 1)) {
359 r[0] |= e->is_static ? BIT(19) : 0;
360 r[0] |= (e->port & 0x3f) << 12;
361 r[0] |= e->vid;
362 r[1] |= e->block_da ? BIT(30) : 0;
363 r[1] |= e->block_sa ? BIT(31) : 0;
364 r[1] |= e->suspended ? BIT(29) : 0;
365 r[2] |= e->rvid & 0xfff;
366 if (e->next_hop) {
367 r[1] |= BIT(28);
368 r[0] |= e->nh_vlan_target ? BIT(9) : 0;
369 r[0] |= e->nh_route_id & 0x1ff;
370 }
371 r[0] |= (e->age & 0x3) << 17;
372 } else { /* L2 Multicast */
373 r[0] |= (e->mc_portmask_index & 0x1ff) << 12;
374 r[2] |= e->rvid & 0xfff;
375 r[0] |= e->vid & 0xfff;
376 pr_debug("FILL MC: %08x %08x %08x\n", r[0], r[1], r[2]);
377 }
378 } else { /* IPv4 and IPv6 multicast */
379 r[0] |= (e->mc_portmask_index & 0x1ff) << 12;
380 r[1] = e->mc_gip >> 20;
381 r[2] = e->mc_gip << 12;
382 r[2] |= e->rvid;
383 }
384 }
385
386 /* Read an L2 UC or MC entry out of a hash bucket of the L2 forwarding table
387 * hash is the id of the bucket and pos is the position of the entry in that bucket
388 * The data read from the SoC is filled into rtl838x_l2_entry
389 */
390 static u64 rtl838x_read_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e)
391 {
392 u32 r[3];
393 struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 0); /* Access L2 Table 0 */
394 u32 idx = (0 << 14) | (hash << 2) | pos; /* Search SRAM, with hash and at pos in bucket */
395
396 rtl_table_read(q, idx);
397 for (int i = 0; i < 3; i++)
398 r[i] = sw_r32(rtl_table_data(q, i));
399
400 rtl_table_release(q);
401
402 rtl838x_fill_l2_entry(r, e);
403 if (!e->valid)
404 return 0;
405
406 return (((u64) r[1]) << 32) | (r[2]); /* mac and vid concatenated as hash seed */
407 }
408
409 static void rtl838x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e)
410 {
411 u32 r[3];
412 struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 0);
413
414 u32 idx = (0 << 14) | (hash << 2) | pos; /* Access SRAM, with hash and at pos in bucket */
415
416 rtl838x_fill_l2_row(r, e);
417
418 for (int i = 0; i < 3; i++)
419 sw_w32(r[i], rtl_table_data(q, i));
420
421 rtl_table_write(q, idx);
422 rtl_table_release(q);
423 }
424
425 static u64 rtl838x_read_cam(int idx, struct rtl838x_l2_entry *e)
426 {
427 u32 r[3];
428 struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 1); /* Access L2 Table 1 */
429
430 rtl_table_read(q, idx);
431 for (int i = 0; i < 3; i++)
432 r[i] = sw_r32(rtl_table_data(q, i));
433
434 rtl_table_release(q);
435
436 rtl838x_fill_l2_entry(r, e);
437 if (!e->valid)
438 return 0;
439
440 pr_debug("Found in CAM: R1 %x R2 %x R3 %x\n", r[0], r[1], r[2]);
441
442 /* Return MAC with concatenated VID ac concatenated ID */
443 return (((u64) r[1]) << 32) | r[2];
444 }
445
446 static void rtl838x_write_cam(int idx, struct rtl838x_l2_entry *e)
447 {
448 u32 r[3];
449 struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 1); /* Access L2 Table 1 */
450
451 rtl838x_fill_l2_row(r, e);
452
453 for (int i = 0; i < 3; i++)
454 sw_w32(r[i], rtl_table_data(q, i));
455
456 rtl_table_write(q, idx);
457 rtl_table_release(q);
458 }
459
460 static u64 rtl838x_read_mcast_pmask(int idx)
461 {
462 u32 portmask;
463 /* Read MC_PMSK (2) via register RTL8380_TBL_L2 */
464 struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 2);
465
466 rtl_table_read(q, idx);
467 portmask = sw_r32(rtl_table_data(q, 0));
468 rtl_table_release(q);
469
470 return portmask;
471 }
472
473 static void rtl838x_write_mcast_pmask(int idx, u64 portmask)
474 {
475 /* Access MC_PMSK (2) via register RTL8380_TBL_L2 */
476 struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 2);
477
478 sw_w32(((u32)portmask) & 0x1fffffff, rtl_table_data(q, 0));
479 rtl_table_write(q, idx);
480 rtl_table_release(q);
481 }
482
483 static void rtl838x_vlan_profile_setup(int profile)
484 {
485 u32 pmask_id = UNKNOWN_MC_PMASK;
486 /* Enable L2 Learning BIT 0, portmask UNKNOWN_MC_PMASK for unknown MC traffic flooding */
487 u32 p = 1 | pmask_id << 1 | pmask_id << 10 | pmask_id << 19;
488
489 sw_w32(p, RTL838X_VLAN_PROFILE(profile));
490
491 /* RTL8380 and RTL8390 use an index into the portmask table to set the
492 * unknown multicast portmask, setup a default at a safe location
493 * On RTL93XX, the portmask is directly set in the profile,
494 * see e.g. rtl9300_vlan_profile_setup
495 */
496 rtl838x_write_mcast_pmask(UNKNOWN_MC_PMASK, 0x1fffffff);
497 }
498
499 static void rtl838x_l2_learning_setup(void)
500 {
501 /* Set portmask for broadcast traffic and unknown unicast address flooding
502 * to the reserved entry in the portmask table used also for
503 * multicast flooding */
504 sw_w32(UNKNOWN_MC_PMASK << 12 | UNKNOWN_MC_PMASK, RTL838X_L2_FLD_PMSK);
505
506 /* Enable learning constraint system-wide (bit 0), per-port (bit 1)
507 * and per vlan (bit 2) */
508 sw_w32(0x7, RTL838X_L2_LRN_CONSTRT_EN);
509
510 /* Limit learning to maximum: 16k entries, after that just flood (bits 0-1) */
511 sw_w32((0x3fff << 2) | 0, RTL838X_L2_LRN_CONSTRT);
512
513 /* Do not trap ARP packets to CPU_PORT */
514 sw_w32(0, RTL838X_SPCL_TRAP_ARP_CTRL);
515 }
516
517 static void rtl838x_enable_learning(int port, bool enable)
518 {
519 /* Limit learning to maximum: 16k entries */
520
521 sw_w32_mask(0x3fff << 2, enable ? (0x3fff << 2) : 0,
522 RTL838X_L2_PORT_LRN_CONSTRT + (port << 2));
523 }
524
525 static void rtl838x_enable_flood(int port, bool enable)
526 {
527 /* 0: Forward
528 * 1: Disable
529 * 2: to CPU
530 * 3: Copy to CPU
531 */
532 sw_w32_mask(0x3, enable ? 0 : 1,
533 RTL838X_L2_PORT_LRN_CONSTRT + (port << 2));
534 }
535
536 static void rtl838x_enable_mcast_flood(int port, bool enable)
537 {
538
539 }
540
541 static void rtl838x_enable_bcast_flood(int port, bool enable)
542 {
543
544 }
545
546 static void rtl838x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
547 {
548 u32 cmd = 1 << 15 | /* Execute cmd */
549 1 << 14 | /* Read */
550 2 << 12 | /* Table type 0b10 */
551 (msti & 0xfff);
552 priv->r->exec_tbl0_cmd(cmd);
553
554 for (int i = 0; i < 2; i++)
555 port_state[i] = sw_r32(priv->r->tbl_access_data_0(i));
556 }
557
558 static void rtl838x_stp_set(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
559 {
560 u32 cmd = 1 << 15 | /* Execute cmd */
561 0 << 14 | /* Write */
562 2 << 12 | /* Table type 0b10 */
563 (msti & 0xfff);
564
565 for (int i = 0; i < 2; i++)
566 sw_w32(port_state[i], priv->r->tbl_access_data_0(i));
567 priv->r->exec_tbl0_cmd(cmd);
568 }
569
570 u64 rtl838x_traffic_get(int source)
571 {
572 return rtl838x_get_port_reg(rtl838x_port_iso_ctrl(source));
573 }
574
575 void rtl838x_traffic_set(int source, u64 dest_matrix)
576 {
577 rtl838x_set_port_reg(dest_matrix, rtl838x_port_iso_ctrl(source));
578 }
579
580 void rtl838x_traffic_enable(int source, int dest)
581 {
582 rtl838x_mask_port_reg(0, BIT(dest), rtl838x_port_iso_ctrl(source));
583 }
584
585 void rtl838x_traffic_disable(int source, int dest)
586 {
587 rtl838x_mask_port_reg(BIT(dest), 0, rtl838x_port_iso_ctrl(source));
588 }
589
590 /* Enables or disables the EEE/EEEP capability of a port */
591 static void rtl838x_port_eee_set(struct rtl838x_switch_priv *priv, int port, bool enable)
592 {
593 u32 v;
594
595 /* This works only for Ethernet ports, and on the RTL838X, ports from 24 are SFP */
596 if (port >= 24)
597 return;
598
599 pr_debug("In %s: setting port %d to %d\n", __func__, port, enable);
600 v = enable ? 0x3 : 0x0;
601
602 /* Set EEE state for 100 (bit 9) & 1000MBit (bit 10) */
603 sw_w32_mask(0x3 << 9, v << 9, priv->r->mac_force_mode_ctrl(port));
604
605 /* Set TX/RX EEE state */
606 if (enable) {
607 sw_w32_mask(0, BIT(port), RTL838X_EEE_PORT_TX_EN);
608 sw_w32_mask(0, BIT(port), RTL838X_EEE_PORT_RX_EN);
609 } else {
610 sw_w32_mask(BIT(port), 0, RTL838X_EEE_PORT_TX_EN);
611 sw_w32_mask(BIT(port), 0, RTL838X_EEE_PORT_RX_EN);
612 }
613 priv->ports[port].eee_enabled = enable;
614 }
615
616
617 /* Get EEE own capabilities and negotiation result */
618 static int rtl838x_eee_port_ability(struct rtl838x_switch_priv *priv,
619 struct ethtool_eee *e, int port)
620 {
621 u64 link;
622
623 if (port >= 24)
624 return 0;
625
626 link = rtl839x_get_port_reg_le(RTL838X_MAC_LINK_STS);
627 if (!(link & BIT(port)))
628 return 0;
629
630 if (sw_r32(rtl838x_mac_force_mode_ctrl(port)) & BIT(9))
631 e->advertised |= ADVERTISED_100baseT_Full;
632
633 if (sw_r32(rtl838x_mac_force_mode_ctrl(port)) & BIT(10))
634 e->advertised |= ADVERTISED_1000baseT_Full;
635
636 if (sw_r32(RTL838X_MAC_EEE_ABLTY) & BIT(port)) {
637 e->lp_advertised = ADVERTISED_100baseT_Full;
638 e->lp_advertised |= ADVERTISED_1000baseT_Full;
639 return 1;
640 }
641
642 return 0;
643 }
644
645 static void rtl838x_init_eee(struct rtl838x_switch_priv *priv, bool enable)
646 {
647 pr_info("Setting up EEE, state: %d\n", enable);
648 sw_w32_mask(0x4, 0, RTL838X_SMI_GLB_CTRL);
649
650 /* Set timers for EEE */
651 sw_w32(0x5001411, RTL838X_EEE_TX_TIMER_GIGA_CTRL);
652 sw_w32(0x5001417, RTL838X_EEE_TX_TIMER_GELITE_CTRL);
653
654 /* Enable EEE MAC support on ports */
655 for (int i = 0; i < priv->cpu_port; i++) {
656 if (priv->ports[i].phy)
657 rtl838x_port_eee_set(priv, i, enable);
658 }
659 priv->eee_enabled = enable;
660 }
661
662 static void rtl838x_pie_lookup_enable(struct rtl838x_switch_priv *priv, int index)
663 {
664 int block = index / PIE_BLOCK_SIZE;
665 u32 block_state = sw_r32(RTL838X_ACL_BLK_LOOKUP_CTRL);
666
667 /* Make sure rule-lookup is enabled in the block */
668 if (!(block_state & BIT(block)))
669 sw_w32(block_state | BIT(block), RTL838X_ACL_BLK_LOOKUP_CTRL);
670 }
671
672 static void rtl838x_pie_rule_del(struct rtl838x_switch_priv *priv, int index_from, int index_to)
673 {
674 int block_from = index_from / PIE_BLOCK_SIZE;
675 int block_to = index_to / PIE_BLOCK_SIZE;
676 u32 v = (index_from << 1)| (index_to << 12 ) | BIT(0);
677 u32 block_state;
678
679 pr_debug("%s: from %d to %d\n", __func__, index_from, index_to);
680 mutex_lock(&priv->reg_mutex);
681
682 /* Remember currently active blocks */
683 block_state = sw_r32(RTL838X_ACL_BLK_LOOKUP_CTRL);
684
685 /* Make sure rule-lookup is disabled in the relevant blocks */
686 for (int block = block_from; block <= block_to; block++) {
687 if (block_state & BIT(block))
688 sw_w32(block_state & (~BIT(block)), RTL838X_ACL_BLK_LOOKUP_CTRL);
689 }
690
691 /* Write from-to and execute bit into control register */
692 sw_w32(v, RTL838X_ACL_CLR_CTRL);
693
694 /* Wait until command has completed */
695 do {
696 } while (sw_r32(RTL838X_ACL_CLR_CTRL) & BIT(0));
697
698 /* Re-enable rule lookup */
699 for (int block = block_from; block <= block_to; block++) {
700 if (!(block_state & BIT(block)))
701 sw_w32(block_state | BIT(block), RTL838X_ACL_BLK_LOOKUP_CTRL);
702 }
703
704 mutex_unlock(&priv->reg_mutex);
705 }
706
707 /* Reads the intermediate representation of the templated match-fields of the
708 * PIE rule in the pie_rule structure and fills in the raw data fields in the
709 * raw register space r[].
710 * The register space configuration size is identical for the RTL8380/90 and RTL9300,
711 * however the RTL9310 has 2 more registers / fields and the physical field-ids
712 * are specific to every platform.
713 */
714 static void rtl838x_write_pie_templated(u32 r[], struct pie_rule *pr, enum template_field_id t[])
715 {
716 for (int i = 0; i < N_FIXED_FIELDS; i++) {
717 enum template_field_id field_type = t[i];
718 u16 data = 0, data_m = 0;
719
720 switch (field_type) {
721 case TEMPLATE_FIELD_SPM0:
722 data = pr->spm;
723 data_m = pr->spm_m;
724 break;
725 case TEMPLATE_FIELD_SPM1:
726 data = pr->spm >> 16;
727 data_m = pr->spm_m >> 16;
728 break;
729 case TEMPLATE_FIELD_OTAG:
730 data = pr->otag;
731 data_m = pr->otag_m;
732 break;
733 case TEMPLATE_FIELD_SMAC0:
734 data = pr->smac[4];
735 data = (data << 8) | pr->smac[5];
736 data_m = pr->smac_m[4];
737 data_m = (data_m << 8) | pr->smac_m[5];
738 break;
739 case TEMPLATE_FIELD_SMAC1:
740 data = pr->smac[2];
741 data = (data << 8) | pr->smac[3];
742 data_m = pr->smac_m[2];
743 data_m = (data_m << 8) | pr->smac_m[3];
744 break;
745 case TEMPLATE_FIELD_SMAC2:
746 data = pr->smac[0];
747 data = (data << 8) | pr->smac[1];
748 data_m = pr->smac_m[0];
749 data_m = (data_m << 8) | pr->smac_m[1];
750 break;
751 case TEMPLATE_FIELD_DMAC0:
752 data = pr->dmac[4];
753 data = (data << 8) | pr->dmac[5];
754 data_m = pr->dmac_m[4];
755 data_m = (data_m << 8) | pr->dmac_m[5];
756 break;
757 case TEMPLATE_FIELD_DMAC1:
758 data = pr->dmac[2];
759 data = (data << 8) | pr->dmac[3];
760 data_m = pr->dmac_m[2];
761 data_m = (data_m << 8) | pr->dmac_m[3];
762 break;
763 case TEMPLATE_FIELD_DMAC2:
764 data = pr->dmac[0];
765 data = (data << 8) | pr->dmac[1];
766 data_m = pr->dmac_m[0];
767 data_m = (data_m << 8) | pr->dmac_m[1];
768 break;
769 case TEMPLATE_FIELD_ETHERTYPE:
770 data = pr->ethertype;
771 data_m = pr->ethertype_m;
772 break;
773 case TEMPLATE_FIELD_ITAG:
774 data = pr->itag;
775 data_m = pr->itag_m;
776 break;
777 case TEMPLATE_FIELD_RANGE_CHK:
778 data = pr->field_range_check;
779 data_m = pr->field_range_check_m;
780 break;
781 case TEMPLATE_FIELD_SIP0:
782 if (pr->is_ipv6) {
783 data = pr->sip6.s6_addr16[7];
784 data_m = pr->sip6_m.s6_addr16[7];
785 } else {
786 data = pr->sip;
787 data_m = pr->sip_m;
788 }
789 break;
790 case TEMPLATE_FIELD_SIP1:
791 if (pr->is_ipv6) {
792 data = pr->sip6.s6_addr16[6];
793 data_m = pr->sip6_m.s6_addr16[6];
794 } else {
795 data = pr->sip >> 16;
796 data_m = pr->sip_m >> 16;
797 }
798 break;
799 case TEMPLATE_FIELD_SIP2:
800 case TEMPLATE_FIELD_SIP3:
801 case TEMPLATE_FIELD_SIP4:
802 case TEMPLATE_FIELD_SIP5:
803 case TEMPLATE_FIELD_SIP6:
804 case TEMPLATE_FIELD_SIP7:
805 data = pr->sip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)];
806 data_m = pr->sip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)];
807 break;
808 case TEMPLATE_FIELD_DIP0:
809 if (pr->is_ipv6) {
810 data = pr->dip6.s6_addr16[7];
811 data_m = pr->dip6_m.s6_addr16[7];
812 } else {
813 data = pr->dip;
814 data_m = pr->dip_m;
815 }
816 break;
817 case TEMPLATE_FIELD_DIP1:
818 if (pr->is_ipv6) {
819 data = pr->dip6.s6_addr16[6];
820 data_m = pr->dip6_m.s6_addr16[6];
821 } else {
822 data = pr->dip >> 16;
823 data_m = pr->dip_m >> 16;
824 }
825 break;
826 case TEMPLATE_FIELD_DIP2:
827 case TEMPLATE_FIELD_DIP3:
828 case TEMPLATE_FIELD_DIP4:
829 case TEMPLATE_FIELD_DIP5:
830 case TEMPLATE_FIELD_DIP6:
831 case TEMPLATE_FIELD_DIP7:
832 data = pr->dip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)];
833 data_m = pr->dip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)];
834 break;
835 case TEMPLATE_FIELD_IP_TOS_PROTO:
836 data = pr->tos_proto;
837 data_m = pr->tos_proto_m;
838 break;
839 case TEMPLATE_FIELD_L4_SPORT:
840 data = pr->sport;
841 data_m = pr->sport_m;
842 break;
843 case TEMPLATE_FIELD_L4_DPORT:
844 data = pr->dport;
845 data_m = pr->dport_m;
846 break;
847 case TEMPLATE_FIELD_ICMP_IGMP:
848 data = pr->icmp_igmp;
849 data_m = pr->icmp_igmp_m;
850 break;
851 default:
852 pr_info("%s: unknown field %d\n", __func__, field_type);
853 continue;
854 }
855 if (!(i % 2)) {
856 r[5 - i / 2] = data;
857 r[12 - i / 2] = data_m;
858 } else {
859 r[5 - i / 2] |= ((u32)data) << 16;
860 r[12 - i / 2] |= ((u32)data_m) << 16;
861 }
862 }
863 }
864
865 /* Creates the intermediate representation of the templated match-fields of the
866 * PIE rule in the pie_rule structure by reading the raw data fields in the
867 * raw register space r[].
868 * The register space configuration size is identical for the RTL8380/90 and RTL9300,
869 * however the RTL9310 has 2 more registers / fields and the physical field-ids
870 */
871 static void rtl838x_read_pie_templated(u32 r[], struct pie_rule *pr, enum template_field_id t[])
872 {
873 for (int i = 0; i < N_FIXED_FIELDS; i++) {
874 enum template_field_id field_type = t[i];
875 u16 data, data_m;
876
877 field_type = t[i];
878 if (!(i % 2)) {
879 data = r[5 - i / 2];
880 data_m = r[12 - i / 2];
881 } else {
882 data = r[5 - i / 2] >> 16;
883 data_m = r[12 - i / 2] >> 16;
884 }
885
886 switch (field_type) {
887 case TEMPLATE_FIELD_SPM0:
888 pr->spm = (pr->spn << 16) | data;
889 pr->spm_m = (pr->spn << 16) | data_m;
890 break;
891 case TEMPLATE_FIELD_SPM1:
892 pr->spm = data;
893 pr->spm_m = data_m;
894 break;
895 case TEMPLATE_FIELD_OTAG:
896 pr->otag = data;
897 pr->otag_m = data_m;
898 break;
899 case TEMPLATE_FIELD_SMAC0:
900 pr->smac[4] = data >> 8;
901 pr->smac[5] = data;
902 pr->smac_m[4] = data >> 8;
903 pr->smac_m[5] = data;
904 break;
905 case TEMPLATE_FIELD_SMAC1:
906 pr->smac[2] = data >> 8;
907 pr->smac[3] = data;
908 pr->smac_m[2] = data >> 8;
909 pr->smac_m[3] = data;
910 break;
911 case TEMPLATE_FIELD_SMAC2:
912 pr->smac[0] = data >> 8;
913 pr->smac[1] = data;
914 pr->smac_m[0] = data >> 8;
915 pr->smac_m[1] = data;
916 break;
917 case TEMPLATE_FIELD_DMAC0:
918 pr->dmac[4] = data >> 8;
919 pr->dmac[5] = data;
920 pr->dmac_m[4] = data >> 8;
921 pr->dmac_m[5] = data;
922 break;
923 case TEMPLATE_FIELD_DMAC1:
924 pr->dmac[2] = data >> 8;
925 pr->dmac[3] = data;
926 pr->dmac_m[2] = data >> 8;
927 pr->dmac_m[3] = data;
928 break;
929 case TEMPLATE_FIELD_DMAC2:
930 pr->dmac[0] = data >> 8;
931 pr->dmac[1] = data;
932 pr->dmac_m[0] = data >> 8;
933 pr->dmac_m[1] = data;
934 break;
935 case TEMPLATE_FIELD_ETHERTYPE:
936 pr->ethertype = data;
937 pr->ethertype_m = data_m;
938 break;
939 case TEMPLATE_FIELD_ITAG:
940 pr->itag = data;
941 pr->itag_m = data_m;
942 break;
943 case TEMPLATE_FIELD_RANGE_CHK:
944 pr->field_range_check = data;
945 pr->field_range_check_m = data_m;
946 break;
947 case TEMPLATE_FIELD_SIP0:
948 pr->sip = data;
949 pr->sip_m = data_m;
950 break;
951 case TEMPLATE_FIELD_SIP1:
952 pr->sip = (pr->sip << 16) | data;
953 pr->sip_m = (pr->sip << 16) | data_m;
954 break;
955 case TEMPLATE_FIELD_SIP2:
956 pr->is_ipv6 = true;
957 /* Make use of limitiations on the position of the match values */
958 ipv6_addr_set(&pr->sip6, pr->sip, r[5 - i / 2],
959 r[4 - i / 2], r[3 - i / 2]);
960 ipv6_addr_set(&pr->sip6_m, pr->sip_m, r[5 - i / 2],
961 r[4 - i / 2], r[3 - i / 2]);
962 case TEMPLATE_FIELD_SIP3:
963 case TEMPLATE_FIELD_SIP4:
964 case TEMPLATE_FIELD_SIP5:
965 case TEMPLATE_FIELD_SIP6:
966 case TEMPLATE_FIELD_SIP7:
967 break;
968 case TEMPLATE_FIELD_DIP0:
969 pr->dip = data;
970 pr->dip_m = data_m;
971 break;
972 case TEMPLATE_FIELD_DIP1:
973 pr->dip = (pr->dip << 16) | data;
974 pr->dip_m = (pr->dip << 16) | data_m;
975 break;
976 case TEMPLATE_FIELD_DIP2:
977 pr->is_ipv6 = true;
978 ipv6_addr_set(&pr->dip6, pr->dip, r[5 - i / 2],
979 r[4 - i / 2], r[3 - i / 2]);
980 ipv6_addr_set(&pr->dip6_m, pr->dip_m, r[5 - i / 2],
981 r[4 - i / 2], r[3 - i / 2]);
982 case TEMPLATE_FIELD_DIP3:
983 case TEMPLATE_FIELD_DIP4:
984 case TEMPLATE_FIELD_DIP5:
985 case TEMPLATE_FIELD_DIP6:
986 case TEMPLATE_FIELD_DIP7:
987 break;
988 case TEMPLATE_FIELD_IP_TOS_PROTO:
989 pr->tos_proto = data;
990 pr->tos_proto_m = data_m;
991 break;
992 case TEMPLATE_FIELD_L4_SPORT:
993 pr->sport = data;
994 pr->sport_m = data_m;
995 break;
996 case TEMPLATE_FIELD_L4_DPORT:
997 pr->dport = data;
998 pr->dport_m = data_m;
999 break;
1000 case TEMPLATE_FIELD_ICMP_IGMP:
1001 pr->icmp_igmp = data;
1002 pr->icmp_igmp_m = data_m;
1003 break;
1004 default:
1005 pr_info("%s: unknown field %d\n", __func__, field_type);
1006 }
1007 }
1008 }
1009
1010 static void rtl838x_read_pie_fixed_fields(u32 r[], struct pie_rule *pr)
1011 {
1012 pr->spmmask_fix = (r[6] >> 22) & 0x3;
1013 pr->spn = (r[6] >> 16) & 0x3f;
1014 pr->mgnt_vlan = (r[6] >> 15) & 1;
1015 pr->dmac_hit_sw = (r[6] >> 14) & 1;
1016 pr->not_first_frag = (r[6] >> 13) & 1;
1017 pr->frame_type_l4 = (r[6] >> 10) & 7;
1018 pr->frame_type = (r[6] >> 8) & 3;
1019 pr->otag_fmt = (r[6] >> 7) & 1;
1020 pr->itag_fmt = (r[6] >> 6) & 1;
1021 pr->otag_exist = (r[6] >> 5) & 1;
1022 pr->itag_exist = (r[6] >> 4) & 1;
1023 pr->frame_type_l2 = (r[6] >> 2) & 3;
1024 pr->tid = r[6] & 3;
1025
1026 pr->spmmask_fix_m = (r[13] >> 22) & 0x3;
1027 pr->spn_m = (r[13] >> 16) & 0x3f;
1028 pr->mgnt_vlan_m = (r[13] >> 15) & 1;
1029 pr->dmac_hit_sw_m = (r[13] >> 14) & 1;
1030 pr->not_first_frag_m = (r[13] >> 13) & 1;
1031 pr->frame_type_l4_m = (r[13] >> 10) & 7;
1032 pr->frame_type_m = (r[13] >> 8) & 3;
1033 pr->otag_fmt_m = (r[13] >> 7) & 1;
1034 pr->itag_fmt_m = (r[13] >> 6) & 1;
1035 pr->otag_exist_m = (r[13] >> 5) & 1;
1036 pr->itag_exist_m = (r[13] >> 4) & 1;
1037 pr->frame_type_l2_m = (r[13] >> 2) & 3;
1038 pr->tid_m = r[13] & 3;
1039
1040 pr->valid = r[14] & BIT(31);
1041 pr->cond_not = r[14] & BIT(30);
1042 pr->cond_and1 = r[14] & BIT(29);
1043 pr->cond_and2 = r[14] & BIT(28);
1044 pr->ivalid = r[14] & BIT(27);
1045
1046 pr->drop = (r[17] >> 14) & 3;
1047 pr->fwd_sel = r[17] & BIT(13);
1048 pr->ovid_sel = r[17] & BIT(12);
1049 pr->ivid_sel = r[17] & BIT(11);
1050 pr->flt_sel = r[17] & BIT(10);
1051 pr->log_sel = r[17] & BIT(9);
1052 pr->rmk_sel = r[17] & BIT(8);
1053 pr->meter_sel = r[17] & BIT(7);
1054 pr->tagst_sel = r[17] & BIT(6);
1055 pr->mir_sel = r[17] & BIT(5);
1056 pr->nopri_sel = r[17] & BIT(4);
1057 pr->cpupri_sel = r[17] & BIT(3);
1058 pr->otpid_sel = r[17] & BIT(2);
1059 pr->itpid_sel = r[17] & BIT(1);
1060 pr->shaper_sel = r[17] & BIT(0);
1061 }
1062
1063 static void rtl838x_write_pie_fixed_fields(u32 r[], struct pie_rule *pr)
1064 {
1065 r[6] = ((u32) (pr->spmmask_fix & 0x3)) << 22;
1066 r[6] |= ((u32) (pr->spn & 0x3f)) << 16;
1067 r[6] |= pr->mgnt_vlan ? BIT(15) : 0;
1068 r[6] |= pr->dmac_hit_sw ? BIT(14) : 0;
1069 r[6] |= pr->not_first_frag ? BIT(13) : 0;
1070 r[6] |= ((u32) (pr->frame_type_l4 & 0x7)) << 10;
1071 r[6] |= ((u32) (pr->frame_type & 0x3)) << 8;
1072 r[6] |= pr->otag_fmt ? BIT(7) : 0;
1073 r[6] |= pr->itag_fmt ? BIT(6) : 0;
1074 r[6] |= pr->otag_exist ? BIT(5) : 0;
1075 r[6] |= pr->itag_exist ? BIT(4) : 0;
1076 r[6] |= ((u32) (pr->frame_type_l2 & 0x3)) << 2;
1077 r[6] |= ((u32) (pr->tid & 0x3));
1078
1079 r[13] = ((u32) (pr->spmmask_fix_m & 0x3)) << 22;
1080 r[13] |= ((u32) (pr->spn_m & 0x3f)) << 16;
1081 r[13] |= pr->mgnt_vlan_m ? BIT(15) : 0;
1082 r[13] |= pr->dmac_hit_sw_m ? BIT(14) : 0;
1083 r[13] |= pr->not_first_frag_m ? BIT(13) : 0;
1084 r[13] |= ((u32) (pr->frame_type_l4_m & 0x7)) << 10;
1085 r[13] |= ((u32) (pr->frame_type_m & 0x3)) << 8;
1086 r[13] |= pr->otag_fmt_m ? BIT(7) : 0;
1087 r[13] |= pr->itag_fmt_m ? BIT(6) : 0;
1088 r[13] |= pr->otag_exist_m ? BIT(5) : 0;
1089 r[13] |= pr->itag_exist_m ? BIT(4) : 0;
1090 r[13] |= ((u32) (pr->frame_type_l2_m & 0x3)) << 2;
1091 r[13] |= ((u32) (pr->tid_m & 0x3));
1092
1093 r[14] = pr->valid ? BIT(31) : 0;
1094 r[14] |= pr->cond_not ? BIT(30) : 0;
1095 r[14] |= pr->cond_and1 ? BIT(29) : 0;
1096 r[14] |= pr->cond_and2 ? BIT(28) : 0;
1097 r[14] |= pr->ivalid ? BIT(27) : 0;
1098
1099 if (pr->drop)
1100 r[17] = 0x1 << 14; /* Standard drop action */
1101 else
1102 r[17] = 0;
1103 r[17] |= pr->fwd_sel ? BIT(13) : 0;
1104 r[17] |= pr->ovid_sel ? BIT(12) : 0;
1105 r[17] |= pr->ivid_sel ? BIT(11) : 0;
1106 r[17] |= pr->flt_sel ? BIT(10) : 0;
1107 r[17] |= pr->log_sel ? BIT(9) : 0;
1108 r[17] |= pr->rmk_sel ? BIT(8) : 0;
1109 r[17] |= pr->meter_sel ? BIT(7) : 0;
1110 r[17] |= pr->tagst_sel ? BIT(6) : 0;
1111 r[17] |= pr->mir_sel ? BIT(5) : 0;
1112 r[17] |= pr->nopri_sel ? BIT(4) : 0;
1113 r[17] |= pr->cpupri_sel ? BIT(3) : 0;
1114 r[17] |= pr->otpid_sel ? BIT(2) : 0;
1115 r[17] |= pr->itpid_sel ? BIT(1) : 0;
1116 r[17] |= pr->shaper_sel ? BIT(0) : 0;
1117 }
1118
1119 static int rtl838x_write_pie_action(u32 r[], struct pie_rule *pr)
1120 {
1121 u16 *aif = (u16 *)&r[17];
1122 u16 data;
1123 int fields_used = 0;
1124
1125 aif--;
1126
1127 pr_debug("%s, at %08x\n", __func__, (u32)aif);
1128 /* Multiple actions can be linked to a match of a PIE rule,
1129 * they have different precedence depending on their type and this precedence
1130 * defines which Action Information Field (0-4) in the IACL table stores
1131 * the additional data of the action (like e.g. the port number a packet is
1132 * forwarded to) */
1133 /* TODO: count bits in selectors to limit to a maximum number of actions */
1134 if (pr->fwd_sel) { /* Forwarding action */
1135 data = pr->fwd_act << 13;
1136 data |= pr->fwd_data;
1137 data |= pr->bypass_all ? BIT(12) : 0;
1138 data |= pr->bypass_ibc_sc ? BIT(11) : 0;
1139 data |= pr->bypass_igr_stp ? BIT(10) : 0;
1140 *aif-- = data;
1141 fields_used++;
1142 }
1143
1144 if (pr->ovid_sel) { /* Outer VID action */
1145 data = (pr->ovid_act & 0x3) << 12;
1146 data |= pr->ovid_data;
1147 *aif-- = data;
1148 fields_used++;
1149 }
1150
1151 if (pr->ivid_sel) { /* Inner VID action */
1152 data = (pr->ivid_act & 0x3) << 12;
1153 data |= pr->ivid_data;
1154 *aif-- = data;
1155 fields_used++;
1156 }
1157
1158 if (pr->flt_sel) { /* Filter action */
1159 *aif-- = pr->flt_data;
1160 fields_used++;
1161 }
1162
1163 if (pr->log_sel) { /* Log action */
1164 if (fields_used >= 4)
1165 return -1;
1166 *aif-- = pr->log_data;
1167 fields_used++;
1168 }
1169
1170 if (pr->rmk_sel) { /* Remark action */
1171 if (fields_used >= 4)
1172 return -1;
1173 *aif-- = pr->rmk_data;
1174 fields_used++;
1175 }
1176
1177 if (pr->meter_sel) { /* Meter action */
1178 if (fields_used >= 4)
1179 return -1;
1180 *aif-- = pr->meter_data;
1181 fields_used++;
1182 }
1183
1184 if (pr->tagst_sel) { /* Egress Tag Status action */
1185 if (fields_used >= 4)
1186 return -1;
1187 *aif-- = pr->tagst_data;
1188 fields_used++;
1189 }
1190
1191 if (pr->mir_sel) { /* Mirror action */
1192 if (fields_used >= 4)
1193 return -1;
1194 *aif-- = pr->mir_data;
1195 fields_used++;
1196 }
1197
1198 if (pr->nopri_sel) { /* Normal Priority action */
1199 if (fields_used >= 4)
1200 return -1;
1201 *aif-- = pr->nopri_data;
1202 fields_used++;
1203 }
1204
1205 if (pr->cpupri_sel) { /* CPU Priority action */
1206 if (fields_used >= 4)
1207 return -1;
1208 *aif-- = pr->nopri_data;
1209 fields_used++;
1210 }
1211
1212 if (pr->otpid_sel) { /* OTPID action */
1213 if (fields_used >= 4)
1214 return -1;
1215 *aif-- = pr->otpid_data;
1216 fields_used++;
1217 }
1218
1219 if (pr->itpid_sel) { /* ITPID action */
1220 if (fields_used >= 4)
1221 return -1;
1222 *aif-- = pr->itpid_data;
1223 fields_used++;
1224 }
1225
1226 if (pr->shaper_sel) { /* Traffic shaper action */
1227 if (fields_used >= 4)
1228 return -1;
1229 *aif-- = pr->shaper_data;
1230 fields_used++;
1231 }
1232
1233 return 0;
1234 }
1235
1236 static void rtl838x_read_pie_action(u32 r[], struct pie_rule *pr)
1237 {
1238 u16 *aif = (u16 *)&r[17];
1239
1240 aif--;
1241
1242 pr_debug("%s, at %08x\n", __func__, (u32)aif);
1243 if (pr->drop)
1244 pr_debug("%s: Action Drop: %d", __func__, pr->drop);
1245
1246 if (pr->fwd_sel){ /* Forwarding action */
1247 pr->fwd_act = *aif >> 13;
1248 pr->fwd_data = *aif--;
1249 pr->bypass_all = pr->fwd_data & BIT(12);
1250 pr->bypass_ibc_sc = pr->fwd_data & BIT(11);
1251 pr->bypass_igr_stp = pr->fwd_data & BIT(10);
1252 if (pr->bypass_all || pr->bypass_ibc_sc || pr->bypass_igr_stp)
1253 pr->bypass_sel = true;
1254 }
1255 if (pr->ovid_sel) /* Outer VID action */
1256 pr->ovid_data = *aif--;
1257 if (pr->ivid_sel) /* Inner VID action */
1258 pr->ivid_data = *aif--;
1259 if (pr->flt_sel) /* Filter action */
1260 pr->flt_data = *aif--;
1261 if (pr->log_sel) /* Log action */
1262 pr->log_data = *aif--;
1263 if (pr->rmk_sel) /* Remark action */
1264 pr->rmk_data = *aif--;
1265 if (pr->meter_sel) /* Meter action */
1266 pr->meter_data = *aif--;
1267 if (pr->tagst_sel) /* Egress Tag Status action */
1268 pr->tagst_data = *aif--;
1269 if (pr->mir_sel) /* Mirror action */
1270 pr->mir_data = *aif--;
1271 if (pr->nopri_sel) /* Normal Priority action */
1272 pr->nopri_data = *aif--;
1273 if (pr->cpupri_sel) /* CPU Priority action */
1274 pr->nopri_data = *aif--;
1275 if (pr->otpid_sel) /* OTPID action */
1276 pr->otpid_data = *aif--;
1277 if (pr->itpid_sel) /* ITPID action */
1278 pr->itpid_data = *aif--;
1279 if (pr->shaper_sel) /* Traffic shaper action */
1280 pr->shaper_data = *aif--;
1281 }
1282
1283 static void rtl838x_pie_rule_dump_raw(u32 r[])
1284 {
1285 pr_info("Raw IACL table entry:\n");
1286 pr_info("Match : %08x %08x %08x %08x %08x %08x\n", r[0], r[1], r[2], r[3], r[4], r[5]);
1287 pr_info("Fixed : %08x\n", r[6]);
1288 pr_info("Match M: %08x %08x %08x %08x %08x %08x\n", r[7], r[8], r[9], r[10], r[11], r[12]);
1289 pr_info("Fixed M: %08x\n", r[13]);
1290 pr_info("AIF : %08x %08x %08x\n", r[14], r[15], r[16]);
1291 pr_info("Sel : %08x\n", r[17]);
1292 }
1293
1294 static void rtl838x_pie_rule_dump(struct pie_rule *pr)
1295 {
1296 pr_info("Drop: %d, fwd: %d, ovid: %d, ivid: %d, flt: %d, log: %d, rmk: %d, meter: %d tagst: %d, mir: %d, nopri: %d, cpupri: %d, otpid: %d, itpid: %d, shape: %d\n",
1297 pr->drop, pr->fwd_sel, pr->ovid_sel, pr->ivid_sel, pr->flt_sel, pr->log_sel, pr->rmk_sel, pr->log_sel, pr->tagst_sel, pr->mir_sel, pr->nopri_sel,
1298 pr->cpupri_sel, pr->otpid_sel, pr->itpid_sel, pr->shaper_sel);
1299 if (pr->fwd_sel)
1300 pr_info("FWD: %08x\n", pr->fwd_data);
1301 pr_info("TID: %x, %x\n", pr->tid, pr->tid_m);
1302 }
1303
1304 static int rtl838x_pie_rule_read(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr)
1305 {
1306 /* Read IACL table (1) via register 0 */
1307 struct table_reg *q = rtl_table_get(RTL8380_TBL_0, 1);
1308 u32 r[18];
1309 int block = idx / PIE_BLOCK_SIZE;
1310 u32 t_select = sw_r32(RTL838X_ACL_BLK_TMPLTE_CTRL(block));
1311
1312 memset(pr, 0, sizeof(*pr));
1313 rtl_table_read(q, idx);
1314 for (int i = 0; i < 18; i++)
1315 r[i] = sw_r32(rtl_table_data(q, i));
1316
1317 rtl_table_release(q);
1318
1319 rtl838x_read_pie_fixed_fields(r, pr);
1320 if (!pr->valid)
1321 return 0;
1322
1323 pr_info("%s: template_selectors %08x, tid: %d\n", __func__, t_select, pr->tid);
1324 rtl838x_pie_rule_dump_raw(r);
1325
1326 rtl838x_read_pie_templated(r, pr, fixed_templates[(t_select >> (pr->tid * 3)) & 0x7]);
1327
1328 rtl838x_read_pie_action(r, pr);
1329
1330 return 0;
1331 }
1332
1333 static int rtl838x_pie_rule_write(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr)
1334 {
1335 /* Access IACL table (1) via register 0 */
1336 struct table_reg *q = rtl_table_get(RTL8380_TBL_0, 1);
1337 u32 r[18];
1338 int err = 0;
1339 int block = idx / PIE_BLOCK_SIZE;
1340 u32 t_select = sw_r32(RTL838X_ACL_BLK_TMPLTE_CTRL(block));
1341
1342 pr_debug("%s: %d, t_select: %08x\n", __func__, idx, t_select);
1343
1344 for (int i = 0; i < 18; i++)
1345 r[i] = 0;
1346
1347 if (!pr->valid)
1348 goto err_out;
1349
1350 rtl838x_write_pie_fixed_fields(r, pr);
1351
1352 pr_debug("%s: template %d\n", __func__, (t_select >> (pr->tid * 3)) & 0x7);
1353 rtl838x_write_pie_templated(r, pr, fixed_templates[(t_select >> (pr->tid * 3)) & 0x7]);
1354
1355 if (rtl838x_write_pie_action(r, pr)) {
1356 pr_err("Rule actions too complex\n");
1357 goto err_out;
1358 }
1359
1360 /* rtl838x_pie_rule_dump_raw(r); */
1361
1362 for (int i = 0; i < 18; i++)
1363 sw_w32(r[i], rtl_table_data(q, i));
1364
1365 err_out:
1366 rtl_table_write(q, idx);
1367 rtl_table_release(q);
1368
1369 return err;
1370 }
1371
1372 static bool rtl838x_pie_templ_has(int t, enum template_field_id field_type)
1373 {
1374 enum template_field_id ft;
1375
1376 for (int i = 0; i < N_FIXED_FIELDS; i++) {
1377 ft = fixed_templates[t][i];
1378 if (field_type == ft)
1379 return true;
1380 }
1381
1382 return false;
1383 }
1384
1385 static int rtl838x_pie_verify_template(struct rtl838x_switch_priv *priv,
1386 struct pie_rule *pr, int t, int block)
1387 {
1388 int i;
1389
1390 if (!pr->is_ipv6 && pr->sip_m && !rtl838x_pie_templ_has(t, TEMPLATE_FIELD_SIP0))
1391 return -1;
1392
1393 if (!pr->is_ipv6 && pr->dip_m && !rtl838x_pie_templ_has(t, TEMPLATE_FIELD_DIP0))
1394 return -1;
1395
1396 if (pr->is_ipv6) {
1397 if ((pr->sip6_m.s6_addr32[0] ||
1398 pr->sip6_m.s6_addr32[1] ||
1399 pr->sip6_m.s6_addr32[2] ||
1400 pr->sip6_m.s6_addr32[3]) &&
1401 !rtl838x_pie_templ_has(t, TEMPLATE_FIELD_SIP2))
1402 return -1;
1403 if ((pr->dip6_m.s6_addr32[0] ||
1404 pr->dip6_m.s6_addr32[1] ||
1405 pr->dip6_m.s6_addr32[2] ||
1406 pr->dip6_m.s6_addr32[3]) &&
1407 !rtl838x_pie_templ_has(t, TEMPLATE_FIELD_DIP2))
1408 return -1;
1409 }
1410
1411 if (ether_addr_to_u64(pr->smac) && !rtl838x_pie_templ_has(t, TEMPLATE_FIELD_SMAC0))
1412 return -1;
1413
1414 if (ether_addr_to_u64(pr->dmac) && !rtl838x_pie_templ_has(t, TEMPLATE_FIELD_DMAC0))
1415 return -1;
1416
1417 /* TODO: Check more */
1418
1419 i = find_first_zero_bit(&priv->pie_use_bm[block * 4], PIE_BLOCK_SIZE);
1420
1421 if (i >= PIE_BLOCK_SIZE)
1422 return -1;
1423
1424 return i + PIE_BLOCK_SIZE * block;
1425 }
1426
1427 static int rtl838x_pie_rule_add(struct rtl838x_switch_priv *priv, struct pie_rule *pr)
1428 {
1429 int idx, block, j;
1430
1431 pr_debug("In %s\n", __func__);
1432
1433 mutex_lock(&priv->pie_mutex);
1434
1435 for (block = 0; block < priv->n_pie_blocks; block++) {
1436 for (j = 0; j < 3; j++) {
1437 int t = (sw_r32(RTL838X_ACL_BLK_TMPLTE_CTRL(block)) >> (j * 3)) & 0x7;
1438 pr_debug("Testing block %d, template %d, template id %d\n", block, j, t);
1439 idx = rtl838x_pie_verify_template(priv, pr, t, block);
1440 if (idx >= 0)
1441 break;
1442 }
1443 if (j < 3)
1444 break;
1445 }
1446
1447 if (block >= priv->n_pie_blocks) {
1448 mutex_unlock(&priv->pie_mutex);
1449 return -EOPNOTSUPP;
1450 }
1451
1452 pr_debug("Using block: %d, index %d, template-id %d\n", block, idx, j);
1453 set_bit(idx, priv->pie_use_bm);
1454
1455 pr->valid = true;
1456 pr->tid = j; /* Mapped to template number */
1457 pr->tid_m = 0x3;
1458 pr->id = idx;
1459
1460 rtl838x_pie_lookup_enable(priv, idx);
1461 rtl838x_pie_rule_write(priv, idx, pr);
1462
1463 mutex_unlock(&priv->pie_mutex);
1464
1465 return 0;
1466 }
1467
1468 static void rtl838x_pie_rule_rm(struct rtl838x_switch_priv *priv, struct pie_rule *pr)
1469 {
1470 int idx = pr->id;
1471
1472 rtl838x_pie_rule_del(priv, idx, idx);
1473 clear_bit(idx, priv->pie_use_bm);
1474 }
1475
1476 /* Initializes the Packet Inspection Engine:
1477 * powers it up, enables default matching templates for all blocks
1478 * and clears all rules possibly installed by u-boot
1479 */
1480 static void rtl838x_pie_init(struct rtl838x_switch_priv *priv)
1481 {
1482 u32 template_selectors;
1483
1484 mutex_init(&priv->pie_mutex);
1485
1486 /* Enable ACL lookup on all ports, including CPU_PORT */
1487 for (int i = 0; i <= priv->cpu_port; i++)
1488 sw_w32(1, RTL838X_ACL_PORT_LOOKUP_CTRL(i));
1489
1490 /* Power on all PIE blocks */
1491 for (int i = 0; i < priv->n_pie_blocks; i++)
1492 sw_w32_mask(0, BIT(i), RTL838X_ACL_BLK_PWR_CTRL);
1493
1494 /* Include IPG in metering */
1495 sw_w32(1, RTL838X_METER_GLB_CTRL);
1496
1497 /* Delete all present rules */
1498 rtl838x_pie_rule_del(priv, 0, priv->n_pie_blocks * PIE_BLOCK_SIZE - 1);
1499
1500 /* Routing bypasses source port filter: disable write-protection, first */
1501 sw_w32_mask(0, 3, RTL838X_INT_RW_CTRL);
1502 sw_w32_mask(0, 1, RTL838X_DMY_REG27);
1503 sw_w32_mask(3, 0, RTL838X_INT_RW_CTRL);
1504
1505 /* Enable predefined templates 0, 1 and 2 for even blocks */
1506 template_selectors = 0 | (1 << 3) | (2 << 6);
1507 for (int i = 0; i < 6; i += 2)
1508 sw_w32(template_selectors, RTL838X_ACL_BLK_TMPLTE_CTRL(i));
1509
1510 /* Enable predefined templates 0, 3 and 4 (IPv6 support) for odd blocks */
1511 template_selectors = 0 | (3 << 3) | (4 << 6);
1512 for (int i = 1; i < priv->n_pie_blocks; i += 2)
1513 sw_w32(template_selectors, RTL838X_ACL_BLK_TMPLTE_CTRL(i));
1514
1515 /* Group each pair of physical blocks together to a logical block */
1516 sw_w32(0b10101010101, RTL838X_ACL_BLK_GROUP_CTRL);
1517 }
1518
1519 static u32 rtl838x_packet_cntr_read(int counter)
1520 {
1521 u32 v;
1522
1523 /* Read LOG table (3) via register RTL8380_TBL_0 */
1524 struct table_reg *r = rtl_table_get(RTL8380_TBL_0, 3);
1525
1526 pr_debug("In %s, id %d\n", __func__, counter);
1527 rtl_table_read(r, counter / 2);
1528
1529 pr_debug("Registers: %08x %08x\n",
1530 sw_r32(rtl_table_data(r, 0)), sw_r32(rtl_table_data(r, 1)));
1531 /* The table has a size of 2 registers */
1532 if (counter % 2)
1533 v = sw_r32(rtl_table_data(r, 0));
1534 else
1535 v = sw_r32(rtl_table_data(r, 1));
1536
1537 rtl_table_release(r);
1538
1539 return v;
1540 }
1541
1542 static void rtl838x_packet_cntr_clear(int counter)
1543 {
1544 /* Access LOG table (3) via register RTL8380_TBL_0 */
1545 struct table_reg *r = rtl_table_get(RTL8380_TBL_0, 3);
1546
1547 pr_debug("In %s, id %d\n", __func__, counter);
1548 /* The table has a size of 2 registers */
1549 if (counter % 2)
1550 sw_w32(0, rtl_table_data(r, 0));
1551 else
1552 sw_w32(0, rtl_table_data(r, 1));
1553
1554 rtl_table_write(r, counter / 2);
1555
1556 rtl_table_release(r);
1557 }
1558
1559 static void rtl838x_route_read(int idx, struct rtl83xx_route *rt)
1560 {
1561 /* Read ROUTING table (2) via register RTL8380_TBL_1 */
1562 struct table_reg *r = rtl_table_get(RTL8380_TBL_1, 2);
1563
1564 pr_debug("In %s, id %d\n", __func__, idx);
1565 rtl_table_read(r, idx);
1566
1567 /* The table has a size of 2 registers */
1568 rt->nh.gw = sw_r32(rtl_table_data(r, 0));
1569 rt->nh.gw <<= 32;
1570 rt->nh.gw |= sw_r32(rtl_table_data(r, 1));
1571
1572 rtl_table_release(r);
1573 }
1574
1575 static void rtl838x_route_write(int idx, struct rtl83xx_route *rt)
1576 {
1577 /* Access ROUTING table (2) via register RTL8380_TBL_1 */
1578 struct table_reg *r = rtl_table_get(RTL8380_TBL_1, 2);
1579
1580 pr_debug("In %s, id %d, gw: %016llx\n", __func__, idx, rt->nh.gw);
1581 sw_w32(rt->nh.gw >> 32, rtl_table_data(r, 0));
1582 sw_w32(rt->nh.gw, rtl_table_data(r, 1));
1583 rtl_table_write(r, idx);
1584
1585 rtl_table_release(r);
1586 }
1587
1588 static int rtl838x_l3_setup(struct rtl838x_switch_priv *priv)
1589 {
1590 /* Nothing to be done */
1591 return 0;
1592 }
1593
1594 void rtl838x_vlan_port_keep_tag_set(int port, bool keep_outer, bool keep_inner)
1595 {
1596 sw_w32(FIELD_PREP(RTL838X_VLAN_PORT_TAG_STS_CTRL_OTAG_STS_MASK,
1597 keep_outer ? RTL838X_VLAN_PORT_TAG_STS_TAGGED : RTL838X_VLAN_PORT_TAG_STS_UNTAG) |
1598 FIELD_PREP(RTL838X_VLAN_PORT_TAG_STS_CTRL_ITAG_STS_MASK,
1599 keep_inner ? RTL838X_VLAN_PORT_TAG_STS_TAGGED : RTL838X_VLAN_PORT_TAG_STS_UNTAG),
1600 RTL838X_VLAN_PORT_TAG_STS_CTRL(port));
1601 }
1602
1603 void rtl838x_vlan_port_pvidmode_set(int port, enum pbvlan_type type, enum pbvlan_mode mode)
1604 {
1605 if (type == PBVLAN_TYPE_INNER)
1606 sw_w32_mask(0x3, mode, RTL838X_VLAN_PORT_PB_VLAN + (port << 2));
1607 else
1608 sw_w32_mask(0x3 << 14, mode << 14, RTL838X_VLAN_PORT_PB_VLAN + (port << 2));
1609 }
1610
1611 void rtl838x_vlan_port_pvid_set(int port, enum pbvlan_type type, int pvid)
1612 {
1613 if (type == PBVLAN_TYPE_INNER)
1614 sw_w32_mask(0xfff << 2, pvid << 2, RTL838X_VLAN_PORT_PB_VLAN + (port << 2));
1615 else
1616 sw_w32_mask(0xfff << 16, pvid << 16, RTL838X_VLAN_PORT_PB_VLAN + (port << 2));
1617 }
1618
1619 static int rtl838x_set_ageing_time(unsigned long msec)
1620 {
1621 int t = sw_r32(RTL838X_L2_CTRL_1);
1622
1623 t &= 0x7FFFFF;
1624 t = t * 128 / 625; /* Aging time in seconds. 0: L2 aging disabled */
1625 pr_debug("L2 AGING time: %d sec\n", t);
1626
1627 t = (msec * 625 + 127000) / 128000;
1628 t = t > 0x7FFFFF ? 0x7FFFFF : t;
1629 sw_w32_mask(0x7FFFFF, t, RTL838X_L2_CTRL_1);
1630 pr_debug("Dynamic aging for ports: %x\n", sw_r32(RTL838X_L2_PORT_AGING_OUT));
1631
1632 return 0;
1633 }
1634
1635 static void rtl838x_set_igr_filter(int port, enum igr_filter state)
1636 {
1637 sw_w32_mask(0x3 << ((port & 0xf)<<1), state << ((port & 0xf)<<1),
1638 RTL838X_VLAN_PORT_IGR_FLTR + (((port >> 4) << 2)));
1639 }
1640
1641 static void rtl838x_set_egr_filter(int port, enum egr_filter state)
1642 {
1643 sw_w32_mask(0x1 << (port % 0x1d), state << (port % 0x1d),
1644 RTL838X_VLAN_PORT_EGR_FLTR + (((port / 29) << 2)));
1645 }
1646
1647 void rtl838x_set_distribution_algorithm(int group, int algoidx, u32 algomsk)
1648 {
1649 algoidx &= 1; /* RTL838X only supports 2 concurrent algorithms */
1650 sw_w32_mask(1 << (group % 8), algoidx << (group % 8),
1651 RTL838X_TRK_HASH_IDX_CTRL + ((group >> 3) << 2));
1652 sw_w32(algomsk, RTL838X_TRK_HASH_CTRL + (algoidx << 2));
1653 }
1654
1655 void rtl838x_set_receive_management_action(int port, rma_ctrl_t type, action_type_t action)
1656 {
1657 switch(type) {
1658 case BPDU:
1659 sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1),
1660 RTL838X_RMA_BPDU_CTRL + ((port >> 4) << 2));
1661 break;
1662 case PTP:
1663 sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1),
1664 RTL838X_RMA_PTP_CTRL + ((port >> 4) << 2));
1665 break;
1666 case LLTP:
1667 sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1),
1668 RTL838X_RMA_LLTP_CTRL + ((port >> 4) << 2));
1669 break;
1670 default:
1671 break;
1672 }
1673 }
1674
1675 const struct rtl838x_reg rtl838x_reg = {
1676 .mask_port_reg_be = rtl838x_mask_port_reg,
1677 .set_port_reg_be = rtl838x_set_port_reg,
1678 .get_port_reg_be = rtl838x_get_port_reg,
1679 .mask_port_reg_le = rtl838x_mask_port_reg,
1680 .set_port_reg_le = rtl838x_set_port_reg,
1681 .get_port_reg_le = rtl838x_get_port_reg,
1682 .stat_port_rst = RTL838X_STAT_PORT_RST,
1683 .stat_rst = RTL838X_STAT_RST,
1684 .stat_port_std_mib = RTL838X_STAT_PORT_STD_MIB,
1685 .port_iso_ctrl = rtl838x_port_iso_ctrl,
1686 .traffic_enable = rtl838x_traffic_enable,
1687 .traffic_disable = rtl838x_traffic_disable,
1688 .traffic_get = rtl838x_traffic_get,
1689 .traffic_set = rtl838x_traffic_set,
1690 .l2_ctrl_0 = RTL838X_L2_CTRL_0,
1691 .l2_ctrl_1 = RTL838X_L2_CTRL_1,
1692 .l2_port_aging_out = RTL838X_L2_PORT_AGING_OUT,
1693 .set_ageing_time = rtl838x_set_ageing_time,
1694 .smi_poll_ctrl = RTL838X_SMI_POLL_CTRL,
1695 .l2_tbl_flush_ctrl = RTL838X_L2_TBL_FLUSH_CTRL,
1696 .exec_tbl0_cmd = rtl838x_exec_tbl0_cmd,
1697 .exec_tbl1_cmd = rtl838x_exec_tbl1_cmd,
1698 .tbl_access_data_0 = rtl838x_tbl_access_data_0,
1699 .isr_glb_src = RTL838X_ISR_GLB_SRC,
1700 .isr_port_link_sts_chg = RTL838X_ISR_PORT_LINK_STS_CHG,
1701 .imr_port_link_sts_chg = RTL838X_IMR_PORT_LINK_STS_CHG,
1702 .imr_glb = RTL838X_IMR_GLB,
1703 .vlan_tables_read = rtl838x_vlan_tables_read,
1704 .vlan_set_tagged = rtl838x_vlan_set_tagged,
1705 .vlan_set_untagged = rtl838x_vlan_set_untagged,
1706 .mac_force_mode_ctrl = rtl838x_mac_force_mode_ctrl,
1707 .vlan_profile_dump = rtl838x_vlan_profile_dump,
1708 .vlan_profile_setup = rtl838x_vlan_profile_setup,
1709 .vlan_fwd_on_inner = rtl838x_vlan_fwd_on_inner,
1710 .set_vlan_igr_filter = rtl838x_set_igr_filter,
1711 .set_vlan_egr_filter = rtl838x_set_egr_filter,
1712 .enable_learning = rtl838x_enable_learning,
1713 .enable_flood = rtl838x_enable_flood,
1714 .enable_mcast_flood = rtl838x_enable_mcast_flood,
1715 .enable_bcast_flood = rtl838x_enable_bcast_flood,
1716 .stp_get = rtl838x_stp_get,
1717 .stp_set = rtl838x_stp_set,
1718 .mac_port_ctrl = rtl838x_mac_port_ctrl,
1719 .l2_port_new_salrn = rtl838x_l2_port_new_salrn,
1720 .l2_port_new_sa_fwd = rtl838x_l2_port_new_sa_fwd,
1721 .mir_ctrl = RTL838X_MIR_CTRL,
1722 .mir_dpm = RTL838X_MIR_DPM_CTRL,
1723 .mir_spm = RTL838X_MIR_SPM_CTRL,
1724 .mac_link_sts = RTL838X_MAC_LINK_STS,
1725 .mac_link_dup_sts = RTL838X_MAC_LINK_DUP_STS,
1726 .mac_link_spd_sts = rtl838x_mac_link_spd_sts,
1727 .mac_rx_pause_sts = RTL838X_MAC_RX_PAUSE_STS,
1728 .mac_tx_pause_sts = RTL838X_MAC_TX_PAUSE_STS,
1729 .read_l2_entry_using_hash = rtl838x_read_l2_entry_using_hash,
1730 .write_l2_entry_using_hash = rtl838x_write_l2_entry_using_hash,
1731 .read_cam = rtl838x_read_cam,
1732 .write_cam = rtl838x_write_cam,
1733 .vlan_port_keep_tag_set = rtl838x_vlan_port_keep_tag_set,
1734 .vlan_port_pvidmode_set = rtl838x_vlan_port_pvidmode_set,
1735 .vlan_port_pvid_set = rtl838x_vlan_port_pvid_set,
1736 .trk_mbr_ctr = rtl838x_trk_mbr_ctr,
1737 .rma_bpdu_fld_pmask = RTL838X_RMA_BPDU_FLD_PMSK,
1738 .spcl_trap_eapol_ctrl = RTL838X_SPCL_TRAP_EAPOL_CTRL,
1739 .init_eee = rtl838x_init_eee,
1740 .port_eee_set = rtl838x_port_eee_set,
1741 .eee_port_ability = rtl838x_eee_port_ability,
1742 .l2_hash_seed = rtl838x_l2_hash_seed,
1743 .l2_hash_key = rtl838x_l2_hash_key,
1744 .read_mcast_pmask = rtl838x_read_mcast_pmask,
1745 .write_mcast_pmask = rtl838x_write_mcast_pmask,
1746 .pie_init = rtl838x_pie_init,
1747 .pie_rule_read = rtl838x_pie_rule_read,
1748 .pie_rule_write = rtl838x_pie_rule_write,
1749 .pie_rule_add = rtl838x_pie_rule_add,
1750 .pie_rule_rm = rtl838x_pie_rule_rm,
1751 .l2_learning_setup = rtl838x_l2_learning_setup,
1752 .packet_cntr_read = rtl838x_packet_cntr_read,
1753 .packet_cntr_clear = rtl838x_packet_cntr_clear,
1754 .route_read = rtl838x_route_read,
1755 .route_write = rtl838x_route_write,
1756 .l3_setup = rtl838x_l3_setup,
1757 .set_distribution_algorithm = rtl838x_set_distribution_algorithm,
1758 .set_receive_management_action = rtl838x_set_receive_management_action,
1759 };
1760
1761 irqreturn_t rtl838x_switch_irq(int irq, void *dev_id)
1762 {
1763 struct dsa_switch *ds = dev_id;
1764 u32 status = sw_r32(RTL838X_ISR_GLB_SRC);
1765 u32 ports = sw_r32(RTL838X_ISR_PORT_LINK_STS_CHG);
1766 u32 link;
1767
1768 /* Clear status */
1769 sw_w32(ports, RTL838X_ISR_PORT_LINK_STS_CHG);
1770 pr_info("RTL8380 Link change: status: %x, ports %x\n", status, ports);
1771
1772 for (int i = 0; i < 28; i++) {
1773 if (ports & BIT(i)) {
1774 link = sw_r32(RTL838X_MAC_LINK_STS);
1775 if (link & BIT(i))
1776 dsa_port_phylink_mac_change(ds, i, true);
1777 else
1778 dsa_port_phylink_mac_change(ds, i, false);
1779 }
1780 }
1781
1782 return IRQ_HANDLED;
1783 }
1784
1785 int rtl838x_smi_wait_op(int timeout)
1786 {
1787 int ret = 0;
1788 u32 val;
1789
1790 ret = readx_poll_timeout(sw_r32, RTL838X_SMI_ACCESS_PHY_CTRL_1,
1791 val, !(val & 0x1), 20, timeout);
1792 if (ret)
1793 pr_err("%s: timeout\n", __func__);
1794
1795 return ret;
1796 }
1797
1798 /* Reads a register in a page from the PHY */
1799 int rtl838x_read_phy(u32 port, u32 page, u32 reg, u32 *val)
1800 {
1801 int err = -ETIMEDOUT;
1802 u32 v;
1803 u32 park_page;
1804
1805 if (port > 31) {
1806 *val = 0xffff;
1807 return 0;
1808 }
1809
1810 if (page > 4095 || reg > 31)
1811 return -ENOTSUPP;
1812
1813 mutex_lock(&smi_lock);
1814
1815 if (rtl838x_smi_wait_op(100000))
1816 goto timeout;
1817
1818 sw_w32_mask(0xffff0000, port << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);
1819
1820 park_page = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1) & ((0x1f << 15) | 0x2);
1821 v = reg << 20 | page << 3;
1822 sw_w32(v | park_page, RTL838X_SMI_ACCESS_PHY_CTRL_1);
1823 sw_w32_mask(0, 1, RTL838X_SMI_ACCESS_PHY_CTRL_1);
1824
1825 if (rtl838x_smi_wait_op(100000))
1826 goto timeout;
1827
1828 *val = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_2) & 0xffff;
1829
1830 err = 0;
1831
1832 timeout:
1833 mutex_unlock(&smi_lock);
1834
1835 return -ETIMEDOUT;
1836 }
1837
1838 /* Write to a register in a page of the PHY */
1839 int rtl838x_write_phy(u32 port, u32 page, u32 reg, u32 val)
1840 {
1841 int err = -ETIMEDOUT;
1842 u32 v;
1843 u32 park_page;
1844
1845 val &= 0xffff;
1846 if (port > 31 || page > 4095 || reg > 31)
1847 return -ENOTSUPP;
1848
1849 mutex_lock(&smi_lock);
1850 if (rtl838x_smi_wait_op(100000))
1851 goto timeout;
1852
1853 sw_w32(BIT(port), RTL838X_SMI_ACCESS_PHY_CTRL_0);
1854 mdelay(10);
1855
1856 sw_w32_mask(0xffff0000, val << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);
1857
1858 park_page = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1) & ((0x1f << 15) | 0x2);
1859 v = reg << 20 | page << 3 | 0x4;
1860 sw_w32(v | park_page, RTL838X_SMI_ACCESS_PHY_CTRL_1);
1861 sw_w32_mask(0, 1, RTL838X_SMI_ACCESS_PHY_CTRL_1);
1862
1863 if (rtl838x_smi_wait_op(100000))
1864 goto timeout;
1865
1866 err = 0;
1867
1868 timeout:
1869 mutex_unlock(&smi_lock);
1870
1871 return -ETIMEDOUT;
1872 }
1873
1874 /* Read an mmd register of a PHY */
1875 int rtl838x_read_mmd_phy(u32 port, u32 addr, u32 reg, u32 *val)
1876 {
1877 int err = -ETIMEDOUT;
1878 u32 v;
1879
1880 mutex_lock(&smi_lock);
1881
1882 if (rtl838x_smi_wait_op(100000))
1883 goto timeout;
1884
1885 sw_w32(1 << port, RTL838X_SMI_ACCESS_PHY_CTRL_0);
1886 mdelay(10);
1887
1888 sw_w32_mask(0xffff0000, port << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);
1889
1890 v = addr << 16 | reg;
1891 sw_w32(v, RTL838X_SMI_ACCESS_PHY_CTRL_3);
1892
1893 /* mmd-access | read | cmd-start */
1894 v = 1 << 1 | 0 << 2 | 1;
1895 sw_w32(v, RTL838X_SMI_ACCESS_PHY_CTRL_1);
1896
1897 if (rtl838x_smi_wait_op(100000))
1898 goto timeout;
1899
1900 *val = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_2) & 0xffff;
1901
1902 err = 0;
1903
1904 timeout:
1905 mutex_unlock(&smi_lock);
1906
1907 return err;
1908 }
1909
1910 /* Write to an mmd register of a PHY */
1911 int rtl838x_write_mmd_phy(u32 port, u32 addr, u32 reg, u32 val)
1912 {
1913 int err = -ETIMEDOUT;
1914 u32 v;
1915
1916 pr_debug("MMD write: port %d, dev %d, reg %d, val %x\n", port, addr, reg, val);
1917 val &= 0xffff;
1918 mutex_lock(&smi_lock);
1919
1920 if (rtl838x_smi_wait_op(100000))
1921 goto timeout;
1922
1923 sw_w32(1 << port, RTL838X_SMI_ACCESS_PHY_CTRL_0);
1924 mdelay(10);
1925
1926 sw_w32_mask(0xffff0000, val << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);
1927
1928 sw_w32_mask(0x1f << 16, addr << 16, RTL838X_SMI_ACCESS_PHY_CTRL_3);
1929 sw_w32_mask(0xffff, reg, RTL838X_SMI_ACCESS_PHY_CTRL_3);
1930 /* mmd-access | write | cmd-start */
1931 v = 1 << 1 | 1 << 2 | 1;
1932 sw_w32(v, RTL838X_SMI_ACCESS_PHY_CTRL_1);
1933
1934 if (rtl838x_smi_wait_op(100000))
1935 goto timeout;
1936
1937 err = 0;
1938
1939 timeout:
1940 mutex_unlock(&smi_lock);
1941 return err;
1942 }
1943
1944 void rtl8380_get_version(struct rtl838x_switch_priv *priv)
1945 {
1946 u32 rw_save, info_save;
1947 u32 info;
1948
1949 rw_save = sw_r32(RTL838X_INT_RW_CTRL);
1950 sw_w32(rw_save | 0x3, RTL838X_INT_RW_CTRL);
1951
1952 info_save = sw_r32(RTL838X_CHIP_INFO);
1953 sw_w32(info_save | 0xA0000000, RTL838X_CHIP_INFO);
1954
1955 info = sw_r32(RTL838X_CHIP_INFO);
1956 sw_w32(info_save, RTL838X_CHIP_INFO);
1957 sw_w32(rw_save, RTL838X_INT_RW_CTRL);
1958
1959 if ((info & 0xFFFF) == 0x6275) {
1960 if (((info >> 16) & 0x1F) == 0x1)
1961 priv->version = RTL8380_VERSION_A;
1962 else if (((info >> 16) & 0x1F) == 0x2)
1963 priv->version = RTL8380_VERSION_B;
1964 else
1965 priv->version = RTL8380_VERSION_B;
1966 } else {
1967 priv->version = '-';
1968 }
1969 }
1970
1971 void rtl838x_vlan_profile_dump(int profile)
1972 {
1973 u32 p;
1974
1975 if (profile < 0 || profile > 7)
1976 return;
1977
1978 p = sw_r32(RTL838X_VLAN_PROFILE(profile));
1979
1980 pr_info("VLAN profile %d: L2 learning: %d, UNKN L2MC FLD PMSK %d, \
1981 UNKN IPMC FLD PMSK %d, UNKN IPv6MC FLD PMSK: %d",
1982 profile, p & 1, (p >> 1) & 0x1ff, (p >> 10) & 0x1ff, (p >> 19) & 0x1ff);
1983 }
1984
1985 void rtl8380_sds_rst(int mac)
1986 {
1987 u32 offset = (mac == 24) ? 0 : 0x100;
1988
1989 sw_w32_mask(1 << 11, 0, RTL838X_SDS4_FIB_REG0 + offset);
1990 sw_w32_mask(0x3, 0, RTL838X_SDS4_REG28 + offset);
1991 sw_w32_mask(0x3, 0x3, RTL838X_SDS4_REG28 + offset);
1992 sw_w32_mask(0, 0x1 << 6, RTL838X_SDS4_DUMMY0 + offset);
1993 sw_w32_mask(0x1 << 6, 0, RTL838X_SDS4_DUMMY0 + offset);
1994 pr_debug("SERDES reset: %d\n", mac);
1995 }
1996
1997 int rtl8380_sds_power(int mac, int val)
1998 {
1999 u32 mode = (val == 1) ? 0x4 : 0x9;
2000 u32 offset = (mac == 24) ? 5 : 0;
2001
2002 if ((mac != 24) && (mac != 26)) {
2003 pr_err("%s: not a fibre port: %d\n", __func__, mac);
2004 return -1;
2005 }
2006
2007 sw_w32_mask(0x1f << offset, mode << offset, RTL838X_SDS_MODE_SEL);
2008
2009 rtl8380_sds_rst(mac);
2010
2011 return 0;
2012 }
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