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realtek: Add missing headers
[openwrt/staging/jow.git] / target / linux / realtek / files-5.15 / drivers / net / dsa / rtl83xx / rtl838x.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <asm/mach-rtl838x/mach-rtl83xx.h>
4 #include <linux/etherdevice.h>
5 #include <linux/iopoll.h>
6 #include <net/nexthop.h>
7
8 #include "rtl83xx.h"
9
10 #define RTL838X_VLAN_PORT_TAG_STS_UNTAG 0x0
11 #define RTL838X_VLAN_PORT_TAG_STS_TAGGED 0x1
12 #define RTL838X_VLAN_PORT_TAG_STS_PRIORITY_TAGGED 0x2
13
14 #define RTL838X_VLAN_PORT_TAG_STS_CTRL_BASE 0xA530
15 /* port 0-28 */
16 #define RTL838X_VLAN_PORT_TAG_STS_CTRL(port) \
17 RTL838X_VLAN_PORT_TAG_STS_CTRL_BASE + (port << 2)
18
19 #define RTL838X_VLAN_PORT_TAG_STS_CTRL_EGR_P_OTAG_KEEP_MASK GENMASK(11,10)
20 #define RTL838X_VLAN_PORT_TAG_STS_CTRL_EGR_P_ITAG_KEEP_MASK GENMASK(9,8)
21 #define RTL838X_VLAN_PORT_TAG_STS_CTRL_IGR_P_OTAG_KEEP_MASK GENMASK(7,6)
22 #define RTL838X_VLAN_PORT_TAG_STS_CTRL_IGR_P_ITAG_KEEP_MASK GENMASK(5,4)
23 #define RTL838X_VLAN_PORT_TAG_STS_CTRL_OTAG_STS_MASK GENMASK(3,2)
24 #define RTL838X_VLAN_PORT_TAG_STS_CTRL_ITAG_STS_MASK GENMASK(1,0)
25
26 extern struct mutex smi_lock;
27
28 /* see_dal_maple_acl_log2PhyTmplteField and src/app/diag_v2/src/diag_acl.c */
29 /* Definition of the RTL838X-specific template field IDs as used in the PIE */
30 enum template_field_id {
31 TEMPLATE_FIELD_SPMMASK = 0,
32 TEMPLATE_FIELD_SPM0 = 1, /* Source portmask ports 0-15 */
33 TEMPLATE_FIELD_SPM1 = 2, /* Source portmask ports 16-28 */
34 TEMPLATE_FIELD_RANGE_CHK = 3,
35 TEMPLATE_FIELD_DMAC0 = 4, /* Destination MAC [15:0] */
36 TEMPLATE_FIELD_DMAC1 = 5, /* Destination MAC [31:16] */
37 TEMPLATE_FIELD_DMAC2 = 6, /* Destination MAC [47:32] */
38 TEMPLATE_FIELD_SMAC0 = 7, /* Source MAC [15:0] */
39 TEMPLATE_FIELD_SMAC1 = 8, /* Source MAC [31:16] */
40 TEMPLATE_FIELD_SMAC2 = 9, /* Source MAC [47:32] */
41 TEMPLATE_FIELD_ETHERTYPE = 10, /* Ethernet typ */
42 TEMPLATE_FIELD_OTAG = 11, /* Outer VLAN tag */
43 TEMPLATE_FIELD_ITAG = 12, /* Inner VLAN tag */
44 TEMPLATE_FIELD_SIP0 = 13, /* IPv4 or IPv6 source IP[15:0] or ARP/RARP */
45 /* source protocol address in header */
46 TEMPLATE_FIELD_SIP1 = 14, /* IPv4 or IPv6 source IP[31:16] or ARP/RARP */
47 TEMPLATE_FIELD_DIP0 = 15, /* IPv4 or IPv6 destination IP[15:0] */
48 TEMPLATE_FIELD_DIP1 = 16, /* IPv4 or IPv6 destination IP[31:16] */
49 TEMPLATE_FIELD_IP_TOS_PROTO = 17, /* IPv4 TOS/IPv6 traffic class and */
50 /* IPv4 proto/IPv6 next header fields */
51 TEMPLATE_FIELD_L34_HEADER = 18, /* packet with extra tag and IPv6 with auth, dest, */
52 /* frag, route, hop-by-hop option header, */
53 /* IGMP type, TCP flag */
54 TEMPLATE_FIELD_L4_SPORT = 19, /* TCP/UDP source port */
55 TEMPLATE_FIELD_L4_DPORT = 20, /* TCP/UDP destination port */
56 TEMPLATE_FIELD_ICMP_IGMP = 21,
57 TEMPLATE_FIELD_IP_RANGE = 22,
58 TEMPLATE_FIELD_FIELD_SELECTOR_VALID = 23, /* Field selector mask */
59 TEMPLATE_FIELD_FIELD_SELECTOR_0 = 24,
60 TEMPLATE_FIELD_FIELD_SELECTOR_1 = 25,
61 TEMPLATE_FIELD_FIELD_SELECTOR_2 = 26,
62 TEMPLATE_FIELD_FIELD_SELECTOR_3 = 27,
63 TEMPLATE_FIELD_SIP2 = 28, /* IPv6 source IP[47:32] */
64 TEMPLATE_FIELD_SIP3 = 29, /* IPv6 source IP[63:48] */
65 TEMPLATE_FIELD_SIP4 = 30, /* IPv6 source IP[79:64] */
66 TEMPLATE_FIELD_SIP5 = 31, /* IPv6 source IP[95:80] */
67 TEMPLATE_FIELD_SIP6 = 32, /* IPv6 source IP[111:96] */
68 TEMPLATE_FIELD_SIP7 = 33, /* IPv6 source IP[127:112] */
69 TEMPLATE_FIELD_DIP2 = 34, /* IPv6 destination IP[47:32] */
70 TEMPLATE_FIELD_DIP3 = 35, /* IPv6 destination IP[63:48] */
71 TEMPLATE_FIELD_DIP4 = 36, /* IPv6 destination IP[79:64] */
72 TEMPLATE_FIELD_DIP5 = 37, /* IPv6 destination IP[95:80] */
73 TEMPLATE_FIELD_DIP6 = 38, /* IPv6 destination IP[111:96] */
74 TEMPLATE_FIELD_DIP7 = 39, /* IPv6 destination IP[127:112] */
75 TEMPLATE_FIELD_FWD_VID = 40, /* Forwarding VLAN-ID */
76 TEMPLATE_FIELD_FLOW_LABEL = 41,
77 };
78
79 /* The RTL838X SoCs use 5 fixed templates with definitions for which data fields are to
80 * be copied from the Ethernet Frame header into the 12 User-definable fields of the Packet
81 * Inspection Engine's buffer. The following defines the field contents for each of the fixed
82 * templates. Additionally, 3 user-definable templates can be set up via the definitions
83 * in RTL838X_ACL_TMPLTE_CTRL control registers.
84 * TODO: See all src/app/diag_v2/src/diag_pie.c
85 */
86 #define N_FIXED_TEMPLATES 5
87 static enum template_field_id fixed_templates[N_FIXED_TEMPLATES][N_FIXED_FIELDS] =
88 {
89 {
90 TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1, TEMPLATE_FIELD_OTAG,
91 TEMPLATE_FIELD_SMAC0, TEMPLATE_FIELD_SMAC1, TEMPLATE_FIELD_SMAC2,
92 TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2,
93 TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_ITAG, TEMPLATE_FIELD_RANGE_CHK
94 }, {
95 TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0,
96 TEMPLATE_FIELD_DIP1,TEMPLATE_FIELD_IP_TOS_PROTO, TEMPLATE_FIELD_L4_SPORT,
97 TEMPLATE_FIELD_L4_DPORT, TEMPLATE_FIELD_ICMP_IGMP, TEMPLATE_FIELD_ITAG,
98 TEMPLATE_FIELD_RANGE_CHK, TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1
99 }, {
100 TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2,
101 TEMPLATE_FIELD_ITAG, TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_IP_TOS_PROTO,
102 TEMPLATE_FIELD_L4_DPORT, TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_SIP0,
103 TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0, TEMPLATE_FIELD_DIP1
104 }, {
105 TEMPLATE_FIELD_DIP0, TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_DIP2,
106 TEMPLATE_FIELD_DIP3, TEMPLATE_FIELD_DIP4, TEMPLATE_FIELD_DIP5,
107 TEMPLATE_FIELD_DIP6, TEMPLATE_FIELD_DIP7, TEMPLATE_FIELD_L4_DPORT,
108 TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_ICMP_IGMP, TEMPLATE_FIELD_IP_TOS_PROTO
109 }, {
110 TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_SIP2,
111 TEMPLATE_FIELD_SIP3, TEMPLATE_FIELD_SIP4, TEMPLATE_FIELD_SIP5,
112 TEMPLATE_FIELD_SIP6, TEMPLATE_FIELD_SIP7, TEMPLATE_FIELD_ITAG,
113 TEMPLATE_FIELD_RANGE_CHK, TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1
114 },
115 };
116
117 void rtl838x_print_matrix(void)
118 {
119 unsigned volatile int *ptr8;
120
121 ptr8 = RTL838X_SW_BASE + RTL838X_PORT_ISO_CTRL(0);
122 for (int i = 0; i < 28; i += 8)
123 pr_debug("> %8x %8x %8x %8x %8x %8x %8x %8x\n",
124 ptr8[i + 0], ptr8[i + 1], ptr8[i + 2], ptr8[i + 3],
125 ptr8[i + 4], ptr8[i + 5], ptr8[i + 6], ptr8[i + 7]);
126 pr_debug("CPU_PORT> %8x\n", ptr8[28]);
127 }
128
129 static inline int rtl838x_port_iso_ctrl(int p)
130 {
131 return RTL838X_PORT_ISO_CTRL(p);
132 }
133
134 static inline void rtl838x_exec_tbl0_cmd(u32 cmd)
135 {
136 sw_w32(cmd, RTL838X_TBL_ACCESS_CTRL_0);
137 do { } while (sw_r32(RTL838X_TBL_ACCESS_CTRL_0) & BIT(15));
138 }
139
140 static inline void rtl838x_exec_tbl1_cmd(u32 cmd)
141 {
142 sw_w32(cmd, RTL838X_TBL_ACCESS_CTRL_1);
143 do { } while (sw_r32(RTL838X_TBL_ACCESS_CTRL_1) & BIT(15));
144 }
145
146 static inline int rtl838x_tbl_access_data_0(int i)
147 {
148 return RTL838X_TBL_ACCESS_DATA_0(i);
149 }
150
151 static void rtl838x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info)
152 {
153 u32 v;
154 /* Read VLAN table (0) via register 0 */
155 struct table_reg *r = rtl_table_get(RTL8380_TBL_0, 0);
156
157 rtl_table_read(r, vlan);
158 info->tagged_ports = sw_r32(rtl_table_data(r, 0));
159 v = sw_r32(rtl_table_data(r, 1));
160 pr_debug("VLAN_READ %d: %016llx %08x\n", vlan, info->tagged_ports, v);
161 rtl_table_release(r);
162
163 info->profile_id = v & 0x7;
164 info->hash_mc_fid = !!(v & 0x8);
165 info->hash_uc_fid = !!(v & 0x10);
166 info->fid = (v >> 5) & 0x3f;
167
168 /* Read UNTAG table (0) via table register 1 */
169 r = rtl_table_get(RTL8380_TBL_1, 0);
170 rtl_table_read(r, vlan);
171 info->untagged_ports = sw_r32(rtl_table_data(r, 0));
172 rtl_table_release(r);
173 }
174
175 static void rtl838x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info)
176 {
177 u32 v;
178 /* Access VLAN table (0) via register 0 */
179 struct table_reg *r = rtl_table_get(RTL8380_TBL_0, 0);
180
181 sw_w32(info->tagged_ports, rtl_table_data(r, 0));
182
183 v = info->profile_id;
184 v |= info->hash_mc_fid ? 0x8 : 0;
185 v |= info->hash_uc_fid ? 0x10 : 0;
186 v |= ((u32)info->fid) << 5;
187 sw_w32(v, rtl_table_data(r, 1));
188
189 rtl_table_write(r, vlan);
190 rtl_table_release(r);
191 }
192
193 static void rtl838x_vlan_set_untagged(u32 vlan, u64 portmask)
194 {
195 /* Access UNTAG table (0) via register 1 */
196 struct table_reg *r = rtl_table_get(RTL8380_TBL_1, 0);
197
198 sw_w32(portmask & 0x1fffffff, rtl_table_data(r, 0));
199 rtl_table_write(r, vlan);
200 rtl_table_release(r);
201 }
202
203 /* Sets the L2 forwarding to be based on either the inner VLAN tag or the outer
204 */
205 static void rtl838x_vlan_fwd_on_inner(int port, bool is_set)
206 {
207 if (is_set)
208 sw_w32_mask(BIT(port), 0, RTL838X_VLAN_PORT_FWD);
209 else
210 sw_w32_mask(0, BIT(port), RTL838X_VLAN_PORT_FWD);
211 }
212
213 static u64 rtl838x_l2_hash_seed(u64 mac, u32 vid)
214 {
215 return mac << 12 | vid;
216 }
217
218 /* Applies the same hash algorithm as the one used currently by the ASIC to the seed
219 * and returns a key into the L2 hash table
220 */
221 static u32 rtl838x_l2_hash_key(struct rtl838x_switch_priv *priv, u64 seed)
222 {
223 u32 h1, h2, h3, h;
224
225 if (sw_r32(priv->r->l2_ctrl_0) & 1) {
226 h1 = (seed >> 11) & 0x7ff;
227 h1 = ((h1 & 0x1f) << 6) | ((h1 >> 5) & 0x3f);
228
229 h2 = (seed >> 33) & 0x7ff;
230 h2 = ((h2 & 0x3f) << 5) | ((h2 >> 6) & 0x1f);
231
232 h3 = (seed >> 44) & 0x7ff;
233 h3 = ((h3 & 0x7f) << 4) | ((h3 >> 7) & 0xf);
234
235 h = h1 ^ h2 ^ h3 ^ ((seed >> 55) & 0x1ff);
236 h ^= ((seed >> 22) & 0x7ff) ^ (seed & 0x7ff);
237 } else {
238 h = ((seed >> 55) & 0x1ff) ^ ((seed >> 44) & 0x7ff) ^
239 ((seed >> 33) & 0x7ff) ^ ((seed >> 22) & 0x7ff) ^
240 ((seed >> 11) & 0x7ff) ^ (seed & 0x7ff);
241 }
242
243 return h;
244 }
245
246 static inline int rtl838x_mac_force_mode_ctrl(int p)
247 {
248 return RTL838X_MAC_FORCE_MODE_CTRL + (p << 2);
249 }
250
251 static inline int rtl838x_mac_port_ctrl(int p)
252 {
253 return RTL838X_MAC_PORT_CTRL(p);
254 }
255
256 static inline int rtl838x_l2_port_new_salrn(int p)
257 {
258 return RTL838X_L2_PORT_NEW_SALRN(p);
259 }
260
261 static inline int rtl838x_l2_port_new_sa_fwd(int p)
262 {
263 return RTL838X_L2_PORT_NEW_SA_FWD(p);
264 }
265
266 static inline int rtl838x_mac_link_spd_sts(int p)
267 {
268 return RTL838X_MAC_LINK_SPD_STS(p);
269 }
270
271 inline static int rtl838x_trk_mbr_ctr(int group)
272 {
273 return RTL838X_TRK_MBR_CTR + (group << 2);
274 }
275
276 /* Fills an L2 entry structure from the SoC registers */
277 static void rtl838x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e)
278 {
279 /* Table contains different entry types, we need to identify the right one:
280 * Check for MC entries, first
281 * In contrast to the RTL93xx SoCs, there is no valid bit, use heuristics to
282 * identify valid entries
283 */
284 e->is_ip_mc = !!(r[0] & BIT(22));
285 e->is_ipv6_mc = !!(r[0] & BIT(21));
286 e->type = L2_INVALID;
287
288 if (!e->is_ip_mc && !e->is_ipv6_mc) {
289 e->mac[0] = (r[1] >> 20);
290 e->mac[1] = (r[1] >> 12);
291 e->mac[2] = (r[1] >> 4);
292 e->mac[3] = (r[1] & 0xf) << 4 | (r[2] >> 28);
293 e->mac[4] = (r[2] >> 20);
294 e->mac[5] = (r[2] >> 12);
295
296 e->rvid = r[2] & 0xfff;
297 e->vid = r[0] & 0xfff;
298
299 /* Is it a unicast entry? check multicast bit */
300 if (!(e->mac[0] & 1)) {
301 e->is_static = !!((r[0] >> 19) & 1);
302 e->port = (r[0] >> 12) & 0x1f;
303 e->block_da = !!(r[1] & BIT(30));
304 e->block_sa = !!(r[1] & BIT(31));
305 e->suspended = !!(r[1] & BIT(29));
306 e->next_hop = !!(r[1] & BIT(28));
307 if (e->next_hop) {
308 pr_debug("Found next hop entry, need to read extra data\n");
309 e->nh_vlan_target = !!(r[0] & BIT(9));
310 e->nh_route_id = r[0] & 0x1ff;
311 e->vid = e->rvid;
312 }
313 e->age = (r[0] >> 17) & 0x3;
314 e->valid = true;
315
316 /* A valid entry has one of mutli-cast, aging, sa/da-blocking,
317 * next-hop or static entry bit set
318 */
319 if (!(r[0] & 0x007c0000) && !(r[1] & 0xd0000000))
320 e->valid = false;
321 else
322 e->type = L2_UNICAST;
323 } else { /* L2 multicast */
324 pr_debug("Got L2 MC entry: %08x %08x %08x\n", r[0], r[1], r[2]);
325 e->valid = true;
326 e->type = L2_MULTICAST;
327 e->mc_portmask_index = (r[0] >> 12) & 0x1ff;
328 }
329 } else { /* IPv4 and IPv6 multicast */
330 e->valid = true;
331 e->mc_portmask_index = (r[0] >> 12) & 0x1ff;
332 e->mc_gip = (r[1] << 20) | (r[2] >> 12);
333 e->rvid = r[2] & 0xfff;
334 }
335 if (e->is_ip_mc)
336 e->type = IP4_MULTICAST;
337 if (e->is_ipv6_mc)
338 e->type = IP6_MULTICAST;
339 }
340
341 /* Fills the 3 SoC table registers r[] with the information of in the rtl838x_l2_entry */
342 static void rtl838x_fill_l2_row(u32 r[], struct rtl838x_l2_entry *e)
343 {
344 u64 mac = ether_addr_to_u64(e->mac);
345
346 if (!e->valid) {
347 r[0] = r[1] = r[2] = 0;
348 return;
349 }
350
351 r[0] = e->is_ip_mc ? BIT(22) : 0;
352 r[0] |= e->is_ipv6_mc ? BIT(21) : 0;
353
354 if (!e->is_ip_mc && !e->is_ipv6_mc) {
355 r[1] = mac >> 20;
356 r[2] = (mac & 0xfffff) << 12;
357
358 /* Is it a unicast entry? check multicast bit */
359 if (!(e->mac[0] & 1)) {
360 r[0] |= e->is_static ? BIT(19) : 0;
361 r[0] |= (e->port & 0x3f) << 12;
362 r[0] |= e->vid;
363 r[1] |= e->block_da ? BIT(30) : 0;
364 r[1] |= e->block_sa ? BIT(31) : 0;
365 r[1] |= e->suspended ? BIT(29) : 0;
366 r[2] |= e->rvid & 0xfff;
367 if (e->next_hop) {
368 r[1] |= BIT(28);
369 r[0] |= e->nh_vlan_target ? BIT(9) : 0;
370 r[0] |= e->nh_route_id & 0x1ff;
371 }
372 r[0] |= (e->age & 0x3) << 17;
373 } else { /* L2 Multicast */
374 r[0] |= (e->mc_portmask_index & 0x1ff) << 12;
375 r[2] |= e->rvid & 0xfff;
376 r[0] |= e->vid & 0xfff;
377 pr_debug("FILL MC: %08x %08x %08x\n", r[0], r[1], r[2]);
378 }
379 } else { /* IPv4 and IPv6 multicast */
380 r[0] |= (e->mc_portmask_index & 0x1ff) << 12;
381 r[1] = e->mc_gip >> 20;
382 r[2] = e->mc_gip << 12;
383 r[2] |= e->rvid;
384 }
385 }
386
387 /* Read an L2 UC or MC entry out of a hash bucket of the L2 forwarding table
388 * hash is the id of the bucket and pos is the position of the entry in that bucket
389 * The data read from the SoC is filled into rtl838x_l2_entry
390 */
391 static u64 rtl838x_read_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e)
392 {
393 u32 r[3];
394 struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 0); /* Access L2 Table 0 */
395 u32 idx = (0 << 14) | (hash << 2) | pos; /* Search SRAM, with hash and at pos in bucket */
396
397 rtl_table_read(q, idx);
398 for (int i = 0; i < 3; i++)
399 r[i] = sw_r32(rtl_table_data(q, i));
400
401 rtl_table_release(q);
402
403 rtl838x_fill_l2_entry(r, e);
404 if (!e->valid)
405 return 0;
406
407 return (((u64) r[1]) << 32) | (r[2]); /* mac and vid concatenated as hash seed */
408 }
409
410 static void rtl838x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e)
411 {
412 u32 r[3];
413 struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 0);
414
415 u32 idx = (0 << 14) | (hash << 2) | pos; /* Access SRAM, with hash and at pos in bucket */
416
417 rtl838x_fill_l2_row(r, e);
418
419 for (int i = 0; i < 3; i++)
420 sw_w32(r[i], rtl_table_data(q, i));
421
422 rtl_table_write(q, idx);
423 rtl_table_release(q);
424 }
425
426 static u64 rtl838x_read_cam(int idx, struct rtl838x_l2_entry *e)
427 {
428 u32 r[3];
429 struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 1); /* Access L2 Table 1 */
430
431 rtl_table_read(q, idx);
432 for (int i = 0; i < 3; i++)
433 r[i] = sw_r32(rtl_table_data(q, i));
434
435 rtl_table_release(q);
436
437 rtl838x_fill_l2_entry(r, e);
438 if (!e->valid)
439 return 0;
440
441 pr_debug("Found in CAM: R1 %x R2 %x R3 %x\n", r[0], r[1], r[2]);
442
443 /* Return MAC with concatenated VID ac concatenated ID */
444 return (((u64) r[1]) << 32) | r[2];
445 }
446
447 static void rtl838x_write_cam(int idx, struct rtl838x_l2_entry *e)
448 {
449 u32 r[3];
450 struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 1); /* Access L2 Table 1 */
451
452 rtl838x_fill_l2_row(r, e);
453
454 for (int i = 0; i < 3; i++)
455 sw_w32(r[i], rtl_table_data(q, i));
456
457 rtl_table_write(q, idx);
458 rtl_table_release(q);
459 }
460
461 static u64 rtl838x_read_mcast_pmask(int idx)
462 {
463 u32 portmask;
464 /* Read MC_PMSK (2) via register RTL8380_TBL_L2 */
465 struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 2);
466
467 rtl_table_read(q, idx);
468 portmask = sw_r32(rtl_table_data(q, 0));
469 rtl_table_release(q);
470
471 return portmask;
472 }
473
474 static void rtl838x_write_mcast_pmask(int idx, u64 portmask)
475 {
476 /* Access MC_PMSK (2) via register RTL8380_TBL_L2 */
477 struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 2);
478
479 sw_w32(((u32)portmask) & 0x1fffffff, rtl_table_data(q, 0));
480 rtl_table_write(q, idx);
481 rtl_table_release(q);
482 }
483
484 static void rtl838x_vlan_profile_setup(int profile)
485 {
486 u32 pmask_id = UNKNOWN_MC_PMASK;
487 /* Enable L2 Learning BIT 0, portmask UNKNOWN_MC_PMASK for unknown MC traffic flooding */
488 u32 p = 1 | pmask_id << 1 | pmask_id << 10 | pmask_id << 19;
489
490 sw_w32(p, RTL838X_VLAN_PROFILE(profile));
491
492 /* RTL8380 and RTL8390 use an index into the portmask table to set the
493 * unknown multicast portmask, setup a default at a safe location
494 * On RTL93XX, the portmask is directly set in the profile,
495 * see e.g. rtl9300_vlan_profile_setup
496 */
497 rtl838x_write_mcast_pmask(UNKNOWN_MC_PMASK, 0x1fffffff);
498 }
499
500 static void rtl838x_l2_learning_setup(void)
501 {
502 /* Set portmask for broadcast traffic and unknown unicast address flooding
503 * to the reserved entry in the portmask table used also for
504 * multicast flooding */
505 sw_w32(UNKNOWN_MC_PMASK << 12 | UNKNOWN_MC_PMASK, RTL838X_L2_FLD_PMSK);
506
507 /* Enable learning constraint system-wide (bit 0), per-port (bit 1)
508 * and per vlan (bit 2) */
509 sw_w32(0x7, RTL838X_L2_LRN_CONSTRT_EN);
510
511 /* Limit learning to maximum: 16k entries, after that just flood (bits 0-1) */
512 sw_w32((0x3fff << 2) | 0, RTL838X_L2_LRN_CONSTRT);
513
514 /* Do not trap ARP packets to CPU_PORT */
515 sw_w32(0, RTL838X_SPCL_TRAP_ARP_CTRL);
516 }
517
518 static void rtl838x_enable_learning(int port, bool enable)
519 {
520 /* Limit learning to maximum: 16k entries */
521
522 sw_w32_mask(0x3fff << 2, enable ? (0x3fff << 2) : 0,
523 RTL838X_L2_PORT_LRN_CONSTRT + (port << 2));
524 }
525
526 static void rtl838x_enable_flood(int port, bool enable)
527 {
528 /* 0: Forward
529 * 1: Disable
530 * 2: to CPU
531 * 3: Copy to CPU
532 */
533 sw_w32_mask(0x3, enable ? 0 : 1,
534 RTL838X_L2_PORT_LRN_CONSTRT + (port << 2));
535 }
536
537 static void rtl838x_enable_mcast_flood(int port, bool enable)
538 {
539
540 }
541
542 static void rtl838x_enable_bcast_flood(int port, bool enable)
543 {
544
545 }
546
547 static void rtl838x_set_static_move_action(int port, bool forward)
548 {
549 int shift = MV_ACT_PORT_SHIFT(port);
550 u32 val = forward ? MV_ACT_FORWARD : MV_ACT_DROP;
551
552 sw_w32_mask(MV_ACT_MASK << shift, val << shift,
553 RTL838X_L2_PORT_STATIC_MV_ACT(port));
554 }
555
556 static void rtl838x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
557 {
558 u32 cmd = 1 << 15 | /* Execute cmd */
559 1 << 14 | /* Read */
560 2 << 12 | /* Table type 0b10 */
561 (msti & 0xfff);
562 priv->r->exec_tbl0_cmd(cmd);
563
564 for (int i = 0; i < 2; i++)
565 port_state[i] = sw_r32(priv->r->tbl_access_data_0(i));
566 }
567
568 static void rtl838x_stp_set(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
569 {
570 u32 cmd = 1 << 15 | /* Execute cmd */
571 0 << 14 | /* Write */
572 2 << 12 | /* Table type 0b10 */
573 (msti & 0xfff);
574
575 for (int i = 0; i < 2; i++)
576 sw_w32(port_state[i], priv->r->tbl_access_data_0(i));
577 priv->r->exec_tbl0_cmd(cmd);
578 }
579
580 u64 rtl838x_traffic_get(int source)
581 {
582 return rtl838x_get_port_reg(rtl838x_port_iso_ctrl(source));
583 }
584
585 void rtl838x_traffic_set(int source, u64 dest_matrix)
586 {
587 rtl838x_set_port_reg(dest_matrix, rtl838x_port_iso_ctrl(source));
588 }
589
590 void rtl838x_traffic_enable(int source, int dest)
591 {
592 rtl838x_mask_port_reg(0, BIT(dest), rtl838x_port_iso_ctrl(source));
593 }
594
595 void rtl838x_traffic_disable(int source, int dest)
596 {
597 rtl838x_mask_port_reg(BIT(dest), 0, rtl838x_port_iso_ctrl(source));
598 }
599
600 /* Enables or disables the EEE/EEEP capability of a port */
601 static void rtl838x_port_eee_set(struct rtl838x_switch_priv *priv, int port, bool enable)
602 {
603 u32 v;
604
605 /* This works only for Ethernet ports, and on the RTL838X, ports from 24 are SFP */
606 if (port >= 24)
607 return;
608
609 pr_debug("In %s: setting port %d to %d\n", __func__, port, enable);
610 v = enable ? 0x3 : 0x0;
611
612 /* Set EEE state for 100 (bit 9) & 1000MBit (bit 10) */
613 sw_w32_mask(0x3 << 9, v << 9, priv->r->mac_force_mode_ctrl(port));
614
615 /* Set TX/RX EEE state */
616 if (enable) {
617 sw_w32_mask(0, BIT(port), RTL838X_EEE_PORT_TX_EN);
618 sw_w32_mask(0, BIT(port), RTL838X_EEE_PORT_RX_EN);
619 } else {
620 sw_w32_mask(BIT(port), 0, RTL838X_EEE_PORT_TX_EN);
621 sw_w32_mask(BIT(port), 0, RTL838X_EEE_PORT_RX_EN);
622 }
623 priv->ports[port].eee_enabled = enable;
624 }
625
626
627 /* Get EEE own capabilities and negotiation result */
628 static int rtl838x_eee_port_ability(struct rtl838x_switch_priv *priv,
629 struct ethtool_eee *e, int port)
630 {
631 u64 link;
632
633 if (port >= 24)
634 return 0;
635
636 link = rtl839x_get_port_reg_le(RTL838X_MAC_LINK_STS);
637 if (!(link & BIT(port)))
638 return 0;
639
640 if (sw_r32(rtl838x_mac_force_mode_ctrl(port)) & BIT(9))
641 e->advertised |= ADVERTISED_100baseT_Full;
642
643 if (sw_r32(rtl838x_mac_force_mode_ctrl(port)) & BIT(10))
644 e->advertised |= ADVERTISED_1000baseT_Full;
645
646 if (sw_r32(RTL838X_MAC_EEE_ABLTY) & BIT(port)) {
647 e->lp_advertised = ADVERTISED_100baseT_Full;
648 e->lp_advertised |= ADVERTISED_1000baseT_Full;
649 return 1;
650 }
651
652 return 0;
653 }
654
655 static void rtl838x_init_eee(struct rtl838x_switch_priv *priv, bool enable)
656 {
657 pr_info("Setting up EEE, state: %d\n", enable);
658 sw_w32_mask(0x4, 0, RTL838X_SMI_GLB_CTRL);
659
660 /* Set timers for EEE */
661 sw_w32(0x5001411, RTL838X_EEE_TX_TIMER_GIGA_CTRL);
662 sw_w32(0x5001417, RTL838X_EEE_TX_TIMER_GELITE_CTRL);
663
664 /* Enable EEE MAC support on ports */
665 for (int i = 0; i < priv->cpu_port; i++) {
666 if (priv->ports[i].phy)
667 rtl838x_port_eee_set(priv, i, enable);
668 }
669 priv->eee_enabled = enable;
670 }
671
672 static void rtl838x_pie_lookup_enable(struct rtl838x_switch_priv *priv, int index)
673 {
674 int block = index / PIE_BLOCK_SIZE;
675 u32 block_state = sw_r32(RTL838X_ACL_BLK_LOOKUP_CTRL);
676
677 /* Make sure rule-lookup is enabled in the block */
678 if (!(block_state & BIT(block)))
679 sw_w32(block_state | BIT(block), RTL838X_ACL_BLK_LOOKUP_CTRL);
680 }
681
682 static void rtl838x_pie_rule_del(struct rtl838x_switch_priv *priv, int index_from, int index_to)
683 {
684 int block_from = index_from / PIE_BLOCK_SIZE;
685 int block_to = index_to / PIE_BLOCK_SIZE;
686 u32 v = (index_from << 1)| (index_to << 12 ) | BIT(0);
687 u32 block_state;
688
689 pr_debug("%s: from %d to %d\n", __func__, index_from, index_to);
690 mutex_lock(&priv->reg_mutex);
691
692 /* Remember currently active blocks */
693 block_state = sw_r32(RTL838X_ACL_BLK_LOOKUP_CTRL);
694
695 /* Make sure rule-lookup is disabled in the relevant blocks */
696 for (int block = block_from; block <= block_to; block++) {
697 if (block_state & BIT(block))
698 sw_w32(block_state & (~BIT(block)), RTL838X_ACL_BLK_LOOKUP_CTRL);
699 }
700
701 /* Write from-to and execute bit into control register */
702 sw_w32(v, RTL838X_ACL_CLR_CTRL);
703
704 /* Wait until command has completed */
705 do {
706 } while (sw_r32(RTL838X_ACL_CLR_CTRL) & BIT(0));
707
708 /* Re-enable rule lookup */
709 for (int block = block_from; block <= block_to; block++) {
710 if (!(block_state & BIT(block)))
711 sw_w32(block_state | BIT(block), RTL838X_ACL_BLK_LOOKUP_CTRL);
712 }
713
714 mutex_unlock(&priv->reg_mutex);
715 }
716
717 /* Reads the intermediate representation of the templated match-fields of the
718 * PIE rule in the pie_rule structure and fills in the raw data fields in the
719 * raw register space r[].
720 * The register space configuration size is identical for the RTL8380/90 and RTL9300,
721 * however the RTL9310 has 2 more registers / fields and the physical field-ids
722 * are specific to every platform.
723 */
724 static void rtl838x_write_pie_templated(u32 r[], struct pie_rule *pr, enum template_field_id t[])
725 {
726 for (int i = 0; i < N_FIXED_FIELDS; i++) {
727 enum template_field_id field_type = t[i];
728 u16 data = 0, data_m = 0;
729
730 switch (field_type) {
731 case TEMPLATE_FIELD_SPM0:
732 data = pr->spm;
733 data_m = pr->spm_m;
734 break;
735 case TEMPLATE_FIELD_SPM1:
736 data = pr->spm >> 16;
737 data_m = pr->spm_m >> 16;
738 break;
739 case TEMPLATE_FIELD_OTAG:
740 data = pr->otag;
741 data_m = pr->otag_m;
742 break;
743 case TEMPLATE_FIELD_SMAC0:
744 data = pr->smac[4];
745 data = (data << 8) | pr->smac[5];
746 data_m = pr->smac_m[4];
747 data_m = (data_m << 8) | pr->smac_m[5];
748 break;
749 case TEMPLATE_FIELD_SMAC1:
750 data = pr->smac[2];
751 data = (data << 8) | pr->smac[3];
752 data_m = pr->smac_m[2];
753 data_m = (data_m << 8) | pr->smac_m[3];
754 break;
755 case TEMPLATE_FIELD_SMAC2:
756 data = pr->smac[0];
757 data = (data << 8) | pr->smac[1];
758 data_m = pr->smac_m[0];
759 data_m = (data_m << 8) | pr->smac_m[1];
760 break;
761 case TEMPLATE_FIELD_DMAC0:
762 data = pr->dmac[4];
763 data = (data << 8) | pr->dmac[5];
764 data_m = pr->dmac_m[4];
765 data_m = (data_m << 8) | pr->dmac_m[5];
766 break;
767 case TEMPLATE_FIELD_DMAC1:
768 data = pr->dmac[2];
769 data = (data << 8) | pr->dmac[3];
770 data_m = pr->dmac_m[2];
771 data_m = (data_m << 8) | pr->dmac_m[3];
772 break;
773 case TEMPLATE_FIELD_DMAC2:
774 data = pr->dmac[0];
775 data = (data << 8) | pr->dmac[1];
776 data_m = pr->dmac_m[0];
777 data_m = (data_m << 8) | pr->dmac_m[1];
778 break;
779 case TEMPLATE_FIELD_ETHERTYPE:
780 data = pr->ethertype;
781 data_m = pr->ethertype_m;
782 break;
783 case TEMPLATE_FIELD_ITAG:
784 data = pr->itag;
785 data_m = pr->itag_m;
786 break;
787 case TEMPLATE_FIELD_RANGE_CHK:
788 data = pr->field_range_check;
789 data_m = pr->field_range_check_m;
790 break;
791 case TEMPLATE_FIELD_SIP0:
792 if (pr->is_ipv6) {
793 data = pr->sip6.s6_addr16[7];
794 data_m = pr->sip6_m.s6_addr16[7];
795 } else {
796 data = pr->sip;
797 data_m = pr->sip_m;
798 }
799 break;
800 case TEMPLATE_FIELD_SIP1:
801 if (pr->is_ipv6) {
802 data = pr->sip6.s6_addr16[6];
803 data_m = pr->sip6_m.s6_addr16[6];
804 } else {
805 data = pr->sip >> 16;
806 data_m = pr->sip_m >> 16;
807 }
808 break;
809 case TEMPLATE_FIELD_SIP2:
810 case TEMPLATE_FIELD_SIP3:
811 case TEMPLATE_FIELD_SIP4:
812 case TEMPLATE_FIELD_SIP5:
813 case TEMPLATE_FIELD_SIP6:
814 case TEMPLATE_FIELD_SIP7:
815 data = pr->sip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)];
816 data_m = pr->sip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)];
817 break;
818 case TEMPLATE_FIELD_DIP0:
819 if (pr->is_ipv6) {
820 data = pr->dip6.s6_addr16[7];
821 data_m = pr->dip6_m.s6_addr16[7];
822 } else {
823 data = pr->dip;
824 data_m = pr->dip_m;
825 }
826 break;
827 case TEMPLATE_FIELD_DIP1:
828 if (pr->is_ipv6) {
829 data = pr->dip6.s6_addr16[6];
830 data_m = pr->dip6_m.s6_addr16[6];
831 } else {
832 data = pr->dip >> 16;
833 data_m = pr->dip_m >> 16;
834 }
835 break;
836 case TEMPLATE_FIELD_DIP2:
837 case TEMPLATE_FIELD_DIP3:
838 case TEMPLATE_FIELD_DIP4:
839 case TEMPLATE_FIELD_DIP5:
840 case TEMPLATE_FIELD_DIP6:
841 case TEMPLATE_FIELD_DIP7:
842 data = pr->dip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)];
843 data_m = pr->dip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)];
844 break;
845 case TEMPLATE_FIELD_IP_TOS_PROTO:
846 data = pr->tos_proto;
847 data_m = pr->tos_proto_m;
848 break;
849 case TEMPLATE_FIELD_L4_SPORT:
850 data = pr->sport;
851 data_m = pr->sport_m;
852 break;
853 case TEMPLATE_FIELD_L4_DPORT:
854 data = pr->dport;
855 data_m = pr->dport_m;
856 break;
857 case TEMPLATE_FIELD_ICMP_IGMP:
858 data = pr->icmp_igmp;
859 data_m = pr->icmp_igmp_m;
860 break;
861 default:
862 pr_info("%s: unknown field %d\n", __func__, field_type);
863 continue;
864 }
865 if (!(i % 2)) {
866 r[5 - i / 2] = data;
867 r[12 - i / 2] = data_m;
868 } else {
869 r[5 - i / 2] |= ((u32)data) << 16;
870 r[12 - i / 2] |= ((u32)data_m) << 16;
871 }
872 }
873 }
874
875 /* Creates the intermediate representation of the templated match-fields of the
876 * PIE rule in the pie_rule structure by reading the raw data fields in the
877 * raw register space r[].
878 * The register space configuration size is identical for the RTL8380/90 and RTL9300,
879 * however the RTL9310 has 2 more registers / fields and the physical field-ids
880 */
881 static void rtl838x_read_pie_templated(u32 r[], struct pie_rule *pr, enum template_field_id t[])
882 {
883 for (int i = 0; i < N_FIXED_FIELDS; i++) {
884 enum template_field_id field_type = t[i];
885 u16 data, data_m;
886
887 field_type = t[i];
888 if (!(i % 2)) {
889 data = r[5 - i / 2];
890 data_m = r[12 - i / 2];
891 } else {
892 data = r[5 - i / 2] >> 16;
893 data_m = r[12 - i / 2] >> 16;
894 }
895
896 switch (field_type) {
897 case TEMPLATE_FIELD_SPM0:
898 pr->spm = (pr->spn << 16) | data;
899 pr->spm_m = (pr->spn << 16) | data_m;
900 break;
901 case TEMPLATE_FIELD_SPM1:
902 pr->spm = data;
903 pr->spm_m = data_m;
904 break;
905 case TEMPLATE_FIELD_OTAG:
906 pr->otag = data;
907 pr->otag_m = data_m;
908 break;
909 case TEMPLATE_FIELD_SMAC0:
910 pr->smac[4] = data >> 8;
911 pr->smac[5] = data;
912 pr->smac_m[4] = data >> 8;
913 pr->smac_m[5] = data;
914 break;
915 case TEMPLATE_FIELD_SMAC1:
916 pr->smac[2] = data >> 8;
917 pr->smac[3] = data;
918 pr->smac_m[2] = data >> 8;
919 pr->smac_m[3] = data;
920 break;
921 case TEMPLATE_FIELD_SMAC2:
922 pr->smac[0] = data >> 8;
923 pr->smac[1] = data;
924 pr->smac_m[0] = data >> 8;
925 pr->smac_m[1] = data;
926 break;
927 case TEMPLATE_FIELD_DMAC0:
928 pr->dmac[4] = data >> 8;
929 pr->dmac[5] = data;
930 pr->dmac_m[4] = data >> 8;
931 pr->dmac_m[5] = data;
932 break;
933 case TEMPLATE_FIELD_DMAC1:
934 pr->dmac[2] = data >> 8;
935 pr->dmac[3] = data;
936 pr->dmac_m[2] = data >> 8;
937 pr->dmac_m[3] = data;
938 break;
939 case TEMPLATE_FIELD_DMAC2:
940 pr->dmac[0] = data >> 8;
941 pr->dmac[1] = data;
942 pr->dmac_m[0] = data >> 8;
943 pr->dmac_m[1] = data;
944 break;
945 case TEMPLATE_FIELD_ETHERTYPE:
946 pr->ethertype = data;
947 pr->ethertype_m = data_m;
948 break;
949 case TEMPLATE_FIELD_ITAG:
950 pr->itag = data;
951 pr->itag_m = data_m;
952 break;
953 case TEMPLATE_FIELD_RANGE_CHK:
954 pr->field_range_check = data;
955 pr->field_range_check_m = data_m;
956 break;
957 case TEMPLATE_FIELD_SIP0:
958 pr->sip = data;
959 pr->sip_m = data_m;
960 break;
961 case TEMPLATE_FIELD_SIP1:
962 pr->sip = (pr->sip << 16) | data;
963 pr->sip_m = (pr->sip << 16) | data_m;
964 break;
965 case TEMPLATE_FIELD_SIP2:
966 pr->is_ipv6 = true;
967 /* Make use of limitiations on the position of the match values */
968 ipv6_addr_set(&pr->sip6, pr->sip, r[5 - i / 2],
969 r[4 - i / 2], r[3 - i / 2]);
970 ipv6_addr_set(&pr->sip6_m, pr->sip_m, r[5 - i / 2],
971 r[4 - i / 2], r[3 - i / 2]);
972 case TEMPLATE_FIELD_SIP3:
973 case TEMPLATE_FIELD_SIP4:
974 case TEMPLATE_FIELD_SIP5:
975 case TEMPLATE_FIELD_SIP6:
976 case TEMPLATE_FIELD_SIP7:
977 break;
978 case TEMPLATE_FIELD_DIP0:
979 pr->dip = data;
980 pr->dip_m = data_m;
981 break;
982 case TEMPLATE_FIELD_DIP1:
983 pr->dip = (pr->dip << 16) | data;
984 pr->dip_m = (pr->dip << 16) | data_m;
985 break;
986 case TEMPLATE_FIELD_DIP2:
987 pr->is_ipv6 = true;
988 ipv6_addr_set(&pr->dip6, pr->dip, r[5 - i / 2],
989 r[4 - i / 2], r[3 - i / 2]);
990 ipv6_addr_set(&pr->dip6_m, pr->dip_m, r[5 - i / 2],
991 r[4 - i / 2], r[3 - i / 2]);
992 case TEMPLATE_FIELD_DIP3:
993 case TEMPLATE_FIELD_DIP4:
994 case TEMPLATE_FIELD_DIP5:
995 case TEMPLATE_FIELD_DIP6:
996 case TEMPLATE_FIELD_DIP7:
997 break;
998 case TEMPLATE_FIELD_IP_TOS_PROTO:
999 pr->tos_proto = data;
1000 pr->tos_proto_m = data_m;
1001 break;
1002 case TEMPLATE_FIELD_L4_SPORT:
1003 pr->sport = data;
1004 pr->sport_m = data_m;
1005 break;
1006 case TEMPLATE_FIELD_L4_DPORT:
1007 pr->dport = data;
1008 pr->dport_m = data_m;
1009 break;
1010 case TEMPLATE_FIELD_ICMP_IGMP:
1011 pr->icmp_igmp = data;
1012 pr->icmp_igmp_m = data_m;
1013 break;
1014 default:
1015 pr_info("%s: unknown field %d\n", __func__, field_type);
1016 }
1017 }
1018 }
1019
1020 static void rtl838x_read_pie_fixed_fields(u32 r[], struct pie_rule *pr)
1021 {
1022 pr->spmmask_fix = (r[6] >> 22) & 0x3;
1023 pr->spn = (r[6] >> 16) & 0x3f;
1024 pr->mgnt_vlan = (r[6] >> 15) & 1;
1025 pr->dmac_hit_sw = (r[6] >> 14) & 1;
1026 pr->not_first_frag = (r[6] >> 13) & 1;
1027 pr->frame_type_l4 = (r[6] >> 10) & 7;
1028 pr->frame_type = (r[6] >> 8) & 3;
1029 pr->otag_fmt = (r[6] >> 7) & 1;
1030 pr->itag_fmt = (r[6] >> 6) & 1;
1031 pr->otag_exist = (r[6] >> 5) & 1;
1032 pr->itag_exist = (r[6] >> 4) & 1;
1033 pr->frame_type_l2 = (r[6] >> 2) & 3;
1034 pr->tid = r[6] & 3;
1035
1036 pr->spmmask_fix_m = (r[13] >> 22) & 0x3;
1037 pr->spn_m = (r[13] >> 16) & 0x3f;
1038 pr->mgnt_vlan_m = (r[13] >> 15) & 1;
1039 pr->dmac_hit_sw_m = (r[13] >> 14) & 1;
1040 pr->not_first_frag_m = (r[13] >> 13) & 1;
1041 pr->frame_type_l4_m = (r[13] >> 10) & 7;
1042 pr->frame_type_m = (r[13] >> 8) & 3;
1043 pr->otag_fmt_m = (r[13] >> 7) & 1;
1044 pr->itag_fmt_m = (r[13] >> 6) & 1;
1045 pr->otag_exist_m = (r[13] >> 5) & 1;
1046 pr->itag_exist_m = (r[13] >> 4) & 1;
1047 pr->frame_type_l2_m = (r[13] >> 2) & 3;
1048 pr->tid_m = r[13] & 3;
1049
1050 pr->valid = r[14] & BIT(31);
1051 pr->cond_not = r[14] & BIT(30);
1052 pr->cond_and1 = r[14] & BIT(29);
1053 pr->cond_and2 = r[14] & BIT(28);
1054 pr->ivalid = r[14] & BIT(27);
1055
1056 pr->drop = (r[17] >> 14) & 3;
1057 pr->fwd_sel = r[17] & BIT(13);
1058 pr->ovid_sel = r[17] & BIT(12);
1059 pr->ivid_sel = r[17] & BIT(11);
1060 pr->flt_sel = r[17] & BIT(10);
1061 pr->log_sel = r[17] & BIT(9);
1062 pr->rmk_sel = r[17] & BIT(8);
1063 pr->meter_sel = r[17] & BIT(7);
1064 pr->tagst_sel = r[17] & BIT(6);
1065 pr->mir_sel = r[17] & BIT(5);
1066 pr->nopri_sel = r[17] & BIT(4);
1067 pr->cpupri_sel = r[17] & BIT(3);
1068 pr->otpid_sel = r[17] & BIT(2);
1069 pr->itpid_sel = r[17] & BIT(1);
1070 pr->shaper_sel = r[17] & BIT(0);
1071 }
1072
1073 static void rtl838x_write_pie_fixed_fields(u32 r[], struct pie_rule *pr)
1074 {
1075 r[6] = ((u32) (pr->spmmask_fix & 0x3)) << 22;
1076 r[6] |= ((u32) (pr->spn & 0x3f)) << 16;
1077 r[6] |= pr->mgnt_vlan ? BIT(15) : 0;
1078 r[6] |= pr->dmac_hit_sw ? BIT(14) : 0;
1079 r[6] |= pr->not_first_frag ? BIT(13) : 0;
1080 r[6] |= ((u32) (pr->frame_type_l4 & 0x7)) << 10;
1081 r[6] |= ((u32) (pr->frame_type & 0x3)) << 8;
1082 r[6] |= pr->otag_fmt ? BIT(7) : 0;
1083 r[6] |= pr->itag_fmt ? BIT(6) : 0;
1084 r[6] |= pr->otag_exist ? BIT(5) : 0;
1085 r[6] |= pr->itag_exist ? BIT(4) : 0;
1086 r[6] |= ((u32) (pr->frame_type_l2 & 0x3)) << 2;
1087 r[6] |= ((u32) (pr->tid & 0x3));
1088
1089 r[13] = ((u32) (pr->spmmask_fix_m & 0x3)) << 22;
1090 r[13] |= ((u32) (pr->spn_m & 0x3f)) << 16;
1091 r[13] |= pr->mgnt_vlan_m ? BIT(15) : 0;
1092 r[13] |= pr->dmac_hit_sw_m ? BIT(14) : 0;
1093 r[13] |= pr->not_first_frag_m ? BIT(13) : 0;
1094 r[13] |= ((u32) (pr->frame_type_l4_m & 0x7)) << 10;
1095 r[13] |= ((u32) (pr->frame_type_m & 0x3)) << 8;
1096 r[13] |= pr->otag_fmt_m ? BIT(7) : 0;
1097 r[13] |= pr->itag_fmt_m ? BIT(6) : 0;
1098 r[13] |= pr->otag_exist_m ? BIT(5) : 0;
1099 r[13] |= pr->itag_exist_m ? BIT(4) : 0;
1100 r[13] |= ((u32) (pr->frame_type_l2_m & 0x3)) << 2;
1101 r[13] |= ((u32) (pr->tid_m & 0x3));
1102
1103 r[14] = pr->valid ? BIT(31) : 0;
1104 r[14] |= pr->cond_not ? BIT(30) : 0;
1105 r[14] |= pr->cond_and1 ? BIT(29) : 0;
1106 r[14] |= pr->cond_and2 ? BIT(28) : 0;
1107 r[14] |= pr->ivalid ? BIT(27) : 0;
1108
1109 if (pr->drop)
1110 r[17] = 0x1 << 14; /* Standard drop action */
1111 else
1112 r[17] = 0;
1113 r[17] |= pr->fwd_sel ? BIT(13) : 0;
1114 r[17] |= pr->ovid_sel ? BIT(12) : 0;
1115 r[17] |= pr->ivid_sel ? BIT(11) : 0;
1116 r[17] |= pr->flt_sel ? BIT(10) : 0;
1117 r[17] |= pr->log_sel ? BIT(9) : 0;
1118 r[17] |= pr->rmk_sel ? BIT(8) : 0;
1119 r[17] |= pr->meter_sel ? BIT(7) : 0;
1120 r[17] |= pr->tagst_sel ? BIT(6) : 0;
1121 r[17] |= pr->mir_sel ? BIT(5) : 0;
1122 r[17] |= pr->nopri_sel ? BIT(4) : 0;
1123 r[17] |= pr->cpupri_sel ? BIT(3) : 0;
1124 r[17] |= pr->otpid_sel ? BIT(2) : 0;
1125 r[17] |= pr->itpid_sel ? BIT(1) : 0;
1126 r[17] |= pr->shaper_sel ? BIT(0) : 0;
1127 }
1128
1129 static int rtl838x_write_pie_action(u32 r[], struct pie_rule *pr)
1130 {
1131 u16 *aif = (u16 *)&r[17];
1132 u16 data;
1133 int fields_used = 0;
1134
1135 aif--;
1136
1137 pr_debug("%s, at %08x\n", __func__, (u32)aif);
1138 /* Multiple actions can be linked to a match of a PIE rule,
1139 * they have different precedence depending on their type and this precedence
1140 * defines which Action Information Field (0-4) in the IACL table stores
1141 * the additional data of the action (like e.g. the port number a packet is
1142 * forwarded to) */
1143 /* TODO: count bits in selectors to limit to a maximum number of actions */
1144 if (pr->fwd_sel) { /* Forwarding action */
1145 data = pr->fwd_act << 13;
1146 data |= pr->fwd_data;
1147 data |= pr->bypass_all ? BIT(12) : 0;
1148 data |= pr->bypass_ibc_sc ? BIT(11) : 0;
1149 data |= pr->bypass_igr_stp ? BIT(10) : 0;
1150 *aif-- = data;
1151 fields_used++;
1152 }
1153
1154 if (pr->ovid_sel) { /* Outer VID action */
1155 data = (pr->ovid_act & 0x3) << 12;
1156 data |= pr->ovid_data;
1157 *aif-- = data;
1158 fields_used++;
1159 }
1160
1161 if (pr->ivid_sel) { /* Inner VID action */
1162 data = (pr->ivid_act & 0x3) << 12;
1163 data |= pr->ivid_data;
1164 *aif-- = data;
1165 fields_used++;
1166 }
1167
1168 if (pr->flt_sel) { /* Filter action */
1169 *aif-- = pr->flt_data;
1170 fields_used++;
1171 }
1172
1173 if (pr->log_sel) { /* Log action */
1174 if (fields_used >= 4)
1175 return -1;
1176 *aif-- = pr->log_data;
1177 fields_used++;
1178 }
1179
1180 if (pr->rmk_sel) { /* Remark action */
1181 if (fields_used >= 4)
1182 return -1;
1183 *aif-- = pr->rmk_data;
1184 fields_used++;
1185 }
1186
1187 if (pr->meter_sel) { /* Meter action */
1188 if (fields_used >= 4)
1189 return -1;
1190 *aif-- = pr->meter_data;
1191 fields_used++;
1192 }
1193
1194 if (pr->tagst_sel) { /* Egress Tag Status action */
1195 if (fields_used >= 4)
1196 return -1;
1197 *aif-- = pr->tagst_data;
1198 fields_used++;
1199 }
1200
1201 if (pr->mir_sel) { /* Mirror action */
1202 if (fields_used >= 4)
1203 return -1;
1204 *aif-- = pr->mir_data;
1205 fields_used++;
1206 }
1207
1208 if (pr->nopri_sel) { /* Normal Priority action */
1209 if (fields_used >= 4)
1210 return -1;
1211 *aif-- = pr->nopri_data;
1212 fields_used++;
1213 }
1214
1215 if (pr->cpupri_sel) { /* CPU Priority action */
1216 if (fields_used >= 4)
1217 return -1;
1218 *aif-- = pr->nopri_data;
1219 fields_used++;
1220 }
1221
1222 if (pr->otpid_sel) { /* OTPID action */
1223 if (fields_used >= 4)
1224 return -1;
1225 *aif-- = pr->otpid_data;
1226 fields_used++;
1227 }
1228
1229 if (pr->itpid_sel) { /* ITPID action */
1230 if (fields_used >= 4)
1231 return -1;
1232 *aif-- = pr->itpid_data;
1233 fields_used++;
1234 }
1235
1236 if (pr->shaper_sel) { /* Traffic shaper action */
1237 if (fields_used >= 4)
1238 return -1;
1239 *aif-- = pr->shaper_data;
1240 fields_used++;
1241 }
1242
1243 return 0;
1244 }
1245
1246 static void rtl838x_read_pie_action(u32 r[], struct pie_rule *pr)
1247 {
1248 u16 *aif = (u16 *)&r[17];
1249
1250 aif--;
1251
1252 pr_debug("%s, at %08x\n", __func__, (u32)aif);
1253 if (pr->drop)
1254 pr_debug("%s: Action Drop: %d", __func__, pr->drop);
1255
1256 if (pr->fwd_sel){ /* Forwarding action */
1257 pr->fwd_act = *aif >> 13;
1258 pr->fwd_data = *aif--;
1259 pr->bypass_all = pr->fwd_data & BIT(12);
1260 pr->bypass_ibc_sc = pr->fwd_data & BIT(11);
1261 pr->bypass_igr_stp = pr->fwd_data & BIT(10);
1262 if (pr->bypass_all || pr->bypass_ibc_sc || pr->bypass_igr_stp)
1263 pr->bypass_sel = true;
1264 }
1265 if (pr->ovid_sel) /* Outer VID action */
1266 pr->ovid_data = *aif--;
1267 if (pr->ivid_sel) /* Inner VID action */
1268 pr->ivid_data = *aif--;
1269 if (pr->flt_sel) /* Filter action */
1270 pr->flt_data = *aif--;
1271 if (pr->log_sel) /* Log action */
1272 pr->log_data = *aif--;
1273 if (pr->rmk_sel) /* Remark action */
1274 pr->rmk_data = *aif--;
1275 if (pr->meter_sel) /* Meter action */
1276 pr->meter_data = *aif--;
1277 if (pr->tagst_sel) /* Egress Tag Status action */
1278 pr->tagst_data = *aif--;
1279 if (pr->mir_sel) /* Mirror action */
1280 pr->mir_data = *aif--;
1281 if (pr->nopri_sel) /* Normal Priority action */
1282 pr->nopri_data = *aif--;
1283 if (pr->cpupri_sel) /* CPU Priority action */
1284 pr->nopri_data = *aif--;
1285 if (pr->otpid_sel) /* OTPID action */
1286 pr->otpid_data = *aif--;
1287 if (pr->itpid_sel) /* ITPID action */
1288 pr->itpid_data = *aif--;
1289 if (pr->shaper_sel) /* Traffic shaper action */
1290 pr->shaper_data = *aif--;
1291 }
1292
1293 static void rtl838x_pie_rule_dump_raw(u32 r[])
1294 {
1295 pr_info("Raw IACL table entry:\n");
1296 pr_info("Match : %08x %08x %08x %08x %08x %08x\n", r[0], r[1], r[2], r[3], r[4], r[5]);
1297 pr_info("Fixed : %08x\n", r[6]);
1298 pr_info("Match M: %08x %08x %08x %08x %08x %08x\n", r[7], r[8], r[9], r[10], r[11], r[12]);
1299 pr_info("Fixed M: %08x\n", r[13]);
1300 pr_info("AIF : %08x %08x %08x\n", r[14], r[15], r[16]);
1301 pr_info("Sel : %08x\n", r[17]);
1302 }
1303
1304 // Currently not used
1305 // static void rtl838x_pie_rule_dump(struct pie_rule *pr)
1306 // {
1307 // pr_info("Drop: %d, fwd: %d, ovid: %d, ivid: %d, flt: %d, log: %d, rmk: %d, meter: %d tagst: %d, mir: %d, nopri: %d, cpupri: %d, otpid: %d, itpid: %d, shape: %d\n",
1308 // pr->drop, pr->fwd_sel, pr->ovid_sel, pr->ivid_sel, pr->flt_sel, pr->log_sel, pr->rmk_sel, pr->log_sel, pr->tagst_sel, pr->mir_sel, pr->nopri_sel,
1309 // pr->cpupri_sel, pr->otpid_sel, pr->itpid_sel, pr->shaper_sel);
1310 // if (pr->fwd_sel)
1311 // pr_info("FWD: %08x\n", pr->fwd_data);
1312 // pr_info("TID: %x, %x\n", pr->tid, pr->tid_m);
1313 // }
1314
1315 static int rtl838x_pie_rule_read(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr)
1316 {
1317 /* Read IACL table (1) via register 0 */
1318 struct table_reg *q = rtl_table_get(RTL8380_TBL_0, 1);
1319 u32 r[18];
1320 int block = idx / PIE_BLOCK_SIZE;
1321 u32 t_select = sw_r32(RTL838X_ACL_BLK_TMPLTE_CTRL(block));
1322
1323 memset(pr, 0, sizeof(*pr));
1324 rtl_table_read(q, idx);
1325 for (int i = 0; i < 18; i++)
1326 r[i] = sw_r32(rtl_table_data(q, i));
1327
1328 rtl_table_release(q);
1329
1330 rtl838x_read_pie_fixed_fields(r, pr);
1331 if (!pr->valid)
1332 return 0;
1333
1334 pr_info("%s: template_selectors %08x, tid: %d\n", __func__, t_select, pr->tid);
1335 rtl838x_pie_rule_dump_raw(r);
1336
1337 rtl838x_read_pie_templated(r, pr, fixed_templates[(t_select >> (pr->tid * 3)) & 0x7]);
1338
1339 rtl838x_read_pie_action(r, pr);
1340
1341 return 0;
1342 }
1343
1344 static int rtl838x_pie_rule_write(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr)
1345 {
1346 /* Access IACL table (1) via register 0 */
1347 struct table_reg *q = rtl_table_get(RTL8380_TBL_0, 1);
1348 u32 r[18];
1349 int err;
1350 int block = idx / PIE_BLOCK_SIZE;
1351 u32 t_select = sw_r32(RTL838X_ACL_BLK_TMPLTE_CTRL(block));
1352
1353 pr_debug("%s: %d, t_select: %08x\n", __func__, idx, t_select);
1354
1355 for (int i = 0; i < 18; i++)
1356 r[i] = 0;
1357
1358 if (!pr->valid) {
1359 err = -EINVAL;
1360 pr_err("Rule invalid\n");
1361 goto errout;
1362 }
1363
1364 rtl838x_write_pie_fixed_fields(r, pr);
1365
1366 pr_debug("%s: template %d\n", __func__, (t_select >> (pr->tid * 3)) & 0x7);
1367 rtl838x_write_pie_templated(r, pr, fixed_templates[(t_select >> (pr->tid * 3)) & 0x7]);
1368
1369 err = rtl838x_write_pie_action(r, pr);
1370 if (err) {
1371 pr_err("Rule actions too complex\n");
1372 goto errout;
1373 }
1374
1375 /* rtl838x_pie_rule_dump_raw(r); */
1376
1377 for (int i = 0; i < 18; i++)
1378 sw_w32(r[i], rtl_table_data(q, i));
1379
1380 errout:
1381 rtl_table_write(q, idx);
1382 rtl_table_release(q);
1383
1384 return err;
1385 }
1386
1387 static bool rtl838x_pie_templ_has(int t, enum template_field_id field_type)
1388 {
1389 enum template_field_id ft;
1390
1391 for (int i = 0; i < N_FIXED_FIELDS; i++) {
1392 ft = fixed_templates[t][i];
1393 if (field_type == ft)
1394 return true;
1395 }
1396
1397 return false;
1398 }
1399
1400 static int rtl838x_pie_verify_template(struct rtl838x_switch_priv *priv,
1401 struct pie_rule *pr, int t, int block)
1402 {
1403 int i;
1404
1405 if (!pr->is_ipv6 && pr->sip_m && !rtl838x_pie_templ_has(t, TEMPLATE_FIELD_SIP0))
1406 return -1;
1407
1408 if (!pr->is_ipv6 && pr->dip_m && !rtl838x_pie_templ_has(t, TEMPLATE_FIELD_DIP0))
1409 return -1;
1410
1411 if (pr->is_ipv6) {
1412 if ((pr->sip6_m.s6_addr32[0] ||
1413 pr->sip6_m.s6_addr32[1] ||
1414 pr->sip6_m.s6_addr32[2] ||
1415 pr->sip6_m.s6_addr32[3]) &&
1416 !rtl838x_pie_templ_has(t, TEMPLATE_FIELD_SIP2))
1417 return -1;
1418 if ((pr->dip6_m.s6_addr32[0] ||
1419 pr->dip6_m.s6_addr32[1] ||
1420 pr->dip6_m.s6_addr32[2] ||
1421 pr->dip6_m.s6_addr32[3]) &&
1422 !rtl838x_pie_templ_has(t, TEMPLATE_FIELD_DIP2))
1423 return -1;
1424 }
1425
1426 if (ether_addr_to_u64(pr->smac) && !rtl838x_pie_templ_has(t, TEMPLATE_FIELD_SMAC0))
1427 return -1;
1428
1429 if (ether_addr_to_u64(pr->dmac) && !rtl838x_pie_templ_has(t, TEMPLATE_FIELD_DMAC0))
1430 return -1;
1431
1432 /* TODO: Check more */
1433
1434 i = find_first_zero_bit(&priv->pie_use_bm[block * 4], PIE_BLOCK_SIZE);
1435
1436 if (i >= PIE_BLOCK_SIZE)
1437 return -1;
1438
1439 return i + PIE_BLOCK_SIZE * block;
1440 }
1441
1442 static int rtl838x_pie_rule_add(struct rtl838x_switch_priv *priv, struct pie_rule *pr)
1443 {
1444 int idx, block, j;
1445
1446 pr_debug("In %s\n", __func__);
1447
1448 mutex_lock(&priv->pie_mutex);
1449
1450 for (block = 0; block < priv->n_pie_blocks; block++) {
1451 for (j = 0; j < 3; j++) {
1452 int t = (sw_r32(RTL838X_ACL_BLK_TMPLTE_CTRL(block)) >> (j * 3)) & 0x7;
1453 pr_debug("Testing block %d, template %d, template id %d\n", block, j, t);
1454 idx = rtl838x_pie_verify_template(priv, pr, t, block);
1455 if (idx >= 0)
1456 break;
1457 }
1458 if (j < 3)
1459 break;
1460 }
1461
1462 if (block >= priv->n_pie_blocks) {
1463 mutex_unlock(&priv->pie_mutex);
1464 return -EOPNOTSUPP;
1465 }
1466
1467 pr_debug("Using block: %d, index %d, template-id %d\n", block, idx, j);
1468 set_bit(idx, priv->pie_use_bm);
1469
1470 pr->valid = true;
1471 pr->tid = j; /* Mapped to template number */
1472 pr->tid_m = 0x3;
1473 pr->id = idx;
1474
1475 rtl838x_pie_lookup_enable(priv, idx);
1476 rtl838x_pie_rule_write(priv, idx, pr);
1477
1478 mutex_unlock(&priv->pie_mutex);
1479
1480 return 0;
1481 }
1482
1483 static void rtl838x_pie_rule_rm(struct rtl838x_switch_priv *priv, struct pie_rule *pr)
1484 {
1485 int idx = pr->id;
1486
1487 rtl838x_pie_rule_del(priv, idx, idx);
1488 clear_bit(idx, priv->pie_use_bm);
1489 }
1490
1491 /* Initializes the Packet Inspection Engine:
1492 * powers it up, enables default matching templates for all blocks
1493 * and clears all rules possibly installed by u-boot
1494 */
1495 static void rtl838x_pie_init(struct rtl838x_switch_priv *priv)
1496 {
1497 u32 template_selectors;
1498
1499 mutex_init(&priv->pie_mutex);
1500
1501 /* Enable ACL lookup on all ports, including CPU_PORT */
1502 for (int i = 0; i <= priv->cpu_port; i++)
1503 sw_w32(1, RTL838X_ACL_PORT_LOOKUP_CTRL(i));
1504
1505 /* Power on all PIE blocks */
1506 for (int i = 0; i < priv->n_pie_blocks; i++)
1507 sw_w32_mask(0, BIT(i), RTL838X_ACL_BLK_PWR_CTRL);
1508
1509 /* Include IPG in metering */
1510 sw_w32(1, RTL838X_METER_GLB_CTRL);
1511
1512 /* Delete all present rules */
1513 rtl838x_pie_rule_del(priv, 0, priv->n_pie_blocks * PIE_BLOCK_SIZE - 1);
1514
1515 /* Routing bypasses source port filter: disable write-protection, first */
1516 sw_w32_mask(0, 3, RTL838X_INT_RW_CTRL);
1517 sw_w32_mask(0, 1, RTL838X_DMY_REG27);
1518 sw_w32_mask(3, 0, RTL838X_INT_RW_CTRL);
1519
1520 /* Enable predefined templates 0, 1 and 2 for even blocks */
1521 template_selectors = 0 | (1 << 3) | (2 << 6);
1522 for (int i = 0; i < 6; i += 2)
1523 sw_w32(template_selectors, RTL838X_ACL_BLK_TMPLTE_CTRL(i));
1524
1525 /* Enable predefined templates 0, 3 and 4 (IPv6 support) for odd blocks */
1526 template_selectors = 0 | (3 << 3) | (4 << 6);
1527 for (int i = 1; i < priv->n_pie_blocks; i += 2)
1528 sw_w32(template_selectors, RTL838X_ACL_BLK_TMPLTE_CTRL(i));
1529
1530 /* Group each pair of physical blocks together to a logical block */
1531 sw_w32(0b10101010101, RTL838X_ACL_BLK_GROUP_CTRL);
1532 }
1533
1534 static u32 rtl838x_packet_cntr_read(int counter)
1535 {
1536 u32 v;
1537
1538 /* Read LOG table (3) via register RTL8380_TBL_0 */
1539 struct table_reg *r = rtl_table_get(RTL8380_TBL_0, 3);
1540
1541 pr_debug("In %s, id %d\n", __func__, counter);
1542 rtl_table_read(r, counter / 2);
1543
1544 pr_debug("Registers: %08x %08x\n",
1545 sw_r32(rtl_table_data(r, 0)), sw_r32(rtl_table_data(r, 1)));
1546 /* The table has a size of 2 registers */
1547 if (counter % 2)
1548 v = sw_r32(rtl_table_data(r, 0));
1549 else
1550 v = sw_r32(rtl_table_data(r, 1));
1551
1552 rtl_table_release(r);
1553
1554 return v;
1555 }
1556
1557 static void rtl838x_packet_cntr_clear(int counter)
1558 {
1559 /* Access LOG table (3) via register RTL8380_TBL_0 */
1560 struct table_reg *r = rtl_table_get(RTL8380_TBL_0, 3);
1561
1562 pr_debug("In %s, id %d\n", __func__, counter);
1563 /* The table has a size of 2 registers */
1564 if (counter % 2)
1565 sw_w32(0, rtl_table_data(r, 0));
1566 else
1567 sw_w32(0, rtl_table_data(r, 1));
1568
1569 rtl_table_write(r, counter / 2);
1570
1571 rtl_table_release(r);
1572 }
1573
1574 static void rtl838x_route_read(int idx, struct rtl83xx_route *rt)
1575 {
1576 /* Read ROUTING table (2) via register RTL8380_TBL_1 */
1577 struct table_reg *r = rtl_table_get(RTL8380_TBL_1, 2);
1578
1579 pr_debug("In %s, id %d\n", __func__, idx);
1580 rtl_table_read(r, idx);
1581
1582 /* The table has a size of 2 registers */
1583 rt->nh.gw = sw_r32(rtl_table_data(r, 0));
1584 rt->nh.gw <<= 32;
1585 rt->nh.gw |= sw_r32(rtl_table_data(r, 1));
1586
1587 rtl_table_release(r);
1588 }
1589
1590 static void rtl838x_route_write(int idx, struct rtl83xx_route *rt)
1591 {
1592 /* Access ROUTING table (2) via register RTL8380_TBL_1 */
1593 struct table_reg *r = rtl_table_get(RTL8380_TBL_1, 2);
1594
1595 pr_debug("In %s, id %d, gw: %016llx\n", __func__, idx, rt->nh.gw);
1596 sw_w32(rt->nh.gw >> 32, rtl_table_data(r, 0));
1597 sw_w32(rt->nh.gw, rtl_table_data(r, 1));
1598 rtl_table_write(r, idx);
1599
1600 rtl_table_release(r);
1601 }
1602
1603 static int rtl838x_l3_setup(struct rtl838x_switch_priv *priv)
1604 {
1605 /* Nothing to be done */
1606 return 0;
1607 }
1608
1609 void rtl838x_vlan_port_keep_tag_set(int port, bool keep_outer, bool keep_inner)
1610 {
1611 sw_w32(FIELD_PREP(RTL838X_VLAN_PORT_TAG_STS_CTRL_OTAG_STS_MASK,
1612 keep_outer ? RTL838X_VLAN_PORT_TAG_STS_TAGGED : RTL838X_VLAN_PORT_TAG_STS_UNTAG) |
1613 FIELD_PREP(RTL838X_VLAN_PORT_TAG_STS_CTRL_ITAG_STS_MASK,
1614 keep_inner ? RTL838X_VLAN_PORT_TAG_STS_TAGGED : RTL838X_VLAN_PORT_TAG_STS_UNTAG),
1615 RTL838X_VLAN_PORT_TAG_STS_CTRL(port));
1616 }
1617
1618 void rtl838x_vlan_port_pvidmode_set(int port, enum pbvlan_type type, enum pbvlan_mode mode)
1619 {
1620 if (type == PBVLAN_TYPE_INNER)
1621 sw_w32_mask(0x3, mode, RTL838X_VLAN_PORT_PB_VLAN + (port << 2));
1622 else
1623 sw_w32_mask(0x3 << 14, mode << 14, RTL838X_VLAN_PORT_PB_VLAN + (port << 2));
1624 }
1625
1626 void rtl838x_vlan_port_pvid_set(int port, enum pbvlan_type type, int pvid)
1627 {
1628 if (type == PBVLAN_TYPE_INNER)
1629 sw_w32_mask(0xfff << 2, pvid << 2, RTL838X_VLAN_PORT_PB_VLAN + (port << 2));
1630 else
1631 sw_w32_mask(0xfff << 16, pvid << 16, RTL838X_VLAN_PORT_PB_VLAN + (port << 2));
1632 }
1633
1634 static int rtl838x_set_ageing_time(unsigned long msec)
1635 {
1636 int t = sw_r32(RTL838X_L2_CTRL_1);
1637
1638 t &= 0x7FFFFF;
1639 t = t * 128 / 625; /* Aging time in seconds. 0: L2 aging disabled */
1640 pr_debug("L2 AGING time: %d sec\n", t);
1641
1642 t = (msec * 625 + 127000) / 128000;
1643 t = t > 0x7FFFFF ? 0x7FFFFF : t;
1644 sw_w32_mask(0x7FFFFF, t, RTL838X_L2_CTRL_1);
1645 pr_debug("Dynamic aging for ports: %x\n", sw_r32(RTL838X_L2_PORT_AGING_OUT));
1646
1647 return 0;
1648 }
1649
1650 static void rtl838x_set_igr_filter(int port, enum igr_filter state)
1651 {
1652 sw_w32_mask(0x3 << ((port & 0xf)<<1), state << ((port & 0xf)<<1),
1653 RTL838X_VLAN_PORT_IGR_FLTR + (((port >> 4) << 2)));
1654 }
1655
1656 static void rtl838x_set_egr_filter(int port, enum egr_filter state)
1657 {
1658 sw_w32_mask(0x1 << (port % 0x1d), state << (port % 0x1d),
1659 RTL838X_VLAN_PORT_EGR_FLTR + (((port / 29) << 2)));
1660 }
1661
1662 void rtl838x_set_distribution_algorithm(int group, int algoidx, u32 algomsk)
1663 {
1664 algoidx &= 1; /* RTL838X only supports 2 concurrent algorithms */
1665 sw_w32_mask(1 << (group % 8), algoidx << (group % 8),
1666 RTL838X_TRK_HASH_IDX_CTRL + ((group >> 3) << 2));
1667 sw_w32(algomsk, RTL838X_TRK_HASH_CTRL + (algoidx << 2));
1668 }
1669
1670 void rtl838x_set_receive_management_action(int port, rma_ctrl_t type, action_type_t action)
1671 {
1672 switch(type) {
1673 case BPDU:
1674 sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1),
1675 RTL838X_RMA_BPDU_CTRL + ((port >> 4) << 2));
1676 break;
1677 case PTP:
1678 sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1),
1679 RTL838X_RMA_PTP_CTRL + ((port >> 4) << 2));
1680 break;
1681 case LLTP:
1682 sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1),
1683 RTL838X_RMA_LLTP_CTRL + ((port >> 4) << 2));
1684 break;
1685 default:
1686 break;
1687 }
1688 }
1689
1690 const struct rtl838x_reg rtl838x_reg = {
1691 .mask_port_reg_be = rtl838x_mask_port_reg,
1692 .set_port_reg_be = rtl838x_set_port_reg,
1693 .get_port_reg_be = rtl838x_get_port_reg,
1694 .mask_port_reg_le = rtl838x_mask_port_reg,
1695 .set_port_reg_le = rtl838x_set_port_reg,
1696 .get_port_reg_le = rtl838x_get_port_reg,
1697 .stat_port_rst = RTL838X_STAT_PORT_RST,
1698 .stat_rst = RTL838X_STAT_RST,
1699 .stat_port_std_mib = RTL838X_STAT_PORT_STD_MIB,
1700 .port_iso_ctrl = rtl838x_port_iso_ctrl,
1701 .traffic_enable = rtl838x_traffic_enable,
1702 .traffic_disable = rtl838x_traffic_disable,
1703 .traffic_get = rtl838x_traffic_get,
1704 .traffic_set = rtl838x_traffic_set,
1705 .l2_ctrl_0 = RTL838X_L2_CTRL_0,
1706 .l2_ctrl_1 = RTL838X_L2_CTRL_1,
1707 .l2_port_aging_out = RTL838X_L2_PORT_AGING_OUT,
1708 .set_ageing_time = rtl838x_set_ageing_time,
1709 .smi_poll_ctrl = RTL838X_SMI_POLL_CTRL,
1710 .l2_tbl_flush_ctrl = RTL838X_L2_TBL_FLUSH_CTRL,
1711 .exec_tbl0_cmd = rtl838x_exec_tbl0_cmd,
1712 .exec_tbl1_cmd = rtl838x_exec_tbl1_cmd,
1713 .tbl_access_data_0 = rtl838x_tbl_access_data_0,
1714 .isr_glb_src = RTL838X_ISR_GLB_SRC,
1715 .isr_port_link_sts_chg = RTL838X_ISR_PORT_LINK_STS_CHG,
1716 .imr_port_link_sts_chg = RTL838X_IMR_PORT_LINK_STS_CHG,
1717 .imr_glb = RTL838X_IMR_GLB,
1718 .vlan_tables_read = rtl838x_vlan_tables_read,
1719 .vlan_set_tagged = rtl838x_vlan_set_tagged,
1720 .vlan_set_untagged = rtl838x_vlan_set_untagged,
1721 .mac_force_mode_ctrl = rtl838x_mac_force_mode_ctrl,
1722 .vlan_profile_dump = rtl838x_vlan_profile_dump,
1723 .vlan_profile_setup = rtl838x_vlan_profile_setup,
1724 .vlan_fwd_on_inner = rtl838x_vlan_fwd_on_inner,
1725 .set_vlan_igr_filter = rtl838x_set_igr_filter,
1726 .set_vlan_egr_filter = rtl838x_set_egr_filter,
1727 .enable_learning = rtl838x_enable_learning,
1728 .enable_flood = rtl838x_enable_flood,
1729 .enable_mcast_flood = rtl838x_enable_mcast_flood,
1730 .enable_bcast_flood = rtl838x_enable_bcast_flood,
1731 .set_static_move_action = rtl838x_set_static_move_action,
1732 .stp_get = rtl838x_stp_get,
1733 .stp_set = rtl838x_stp_set,
1734 .mac_port_ctrl = rtl838x_mac_port_ctrl,
1735 .l2_port_new_salrn = rtl838x_l2_port_new_salrn,
1736 .l2_port_new_sa_fwd = rtl838x_l2_port_new_sa_fwd,
1737 .mir_ctrl = RTL838X_MIR_CTRL,
1738 .mir_dpm = RTL838X_MIR_DPM_CTRL,
1739 .mir_spm = RTL838X_MIR_SPM_CTRL,
1740 .mac_link_sts = RTL838X_MAC_LINK_STS,
1741 .mac_link_dup_sts = RTL838X_MAC_LINK_DUP_STS,
1742 .mac_link_spd_sts = rtl838x_mac_link_spd_sts,
1743 .mac_rx_pause_sts = RTL838X_MAC_RX_PAUSE_STS,
1744 .mac_tx_pause_sts = RTL838X_MAC_TX_PAUSE_STS,
1745 .read_l2_entry_using_hash = rtl838x_read_l2_entry_using_hash,
1746 .write_l2_entry_using_hash = rtl838x_write_l2_entry_using_hash,
1747 .read_cam = rtl838x_read_cam,
1748 .write_cam = rtl838x_write_cam,
1749 .vlan_port_keep_tag_set = rtl838x_vlan_port_keep_tag_set,
1750 .vlan_port_pvidmode_set = rtl838x_vlan_port_pvidmode_set,
1751 .vlan_port_pvid_set = rtl838x_vlan_port_pvid_set,
1752 .trk_mbr_ctr = rtl838x_trk_mbr_ctr,
1753 .rma_bpdu_fld_pmask = RTL838X_RMA_BPDU_FLD_PMSK,
1754 .spcl_trap_eapol_ctrl = RTL838X_SPCL_TRAP_EAPOL_CTRL,
1755 .init_eee = rtl838x_init_eee,
1756 .port_eee_set = rtl838x_port_eee_set,
1757 .eee_port_ability = rtl838x_eee_port_ability,
1758 .l2_hash_seed = rtl838x_l2_hash_seed,
1759 .l2_hash_key = rtl838x_l2_hash_key,
1760 .read_mcast_pmask = rtl838x_read_mcast_pmask,
1761 .write_mcast_pmask = rtl838x_write_mcast_pmask,
1762 .pie_init = rtl838x_pie_init,
1763 .pie_rule_read = rtl838x_pie_rule_read,
1764 .pie_rule_write = rtl838x_pie_rule_write,
1765 .pie_rule_add = rtl838x_pie_rule_add,
1766 .pie_rule_rm = rtl838x_pie_rule_rm,
1767 .l2_learning_setup = rtl838x_l2_learning_setup,
1768 .packet_cntr_read = rtl838x_packet_cntr_read,
1769 .packet_cntr_clear = rtl838x_packet_cntr_clear,
1770 .route_read = rtl838x_route_read,
1771 .route_write = rtl838x_route_write,
1772 .l3_setup = rtl838x_l3_setup,
1773 .set_distribution_algorithm = rtl838x_set_distribution_algorithm,
1774 .set_receive_management_action = rtl838x_set_receive_management_action,
1775 };
1776
1777 irqreturn_t rtl838x_switch_irq(int irq, void *dev_id)
1778 {
1779 struct dsa_switch *ds = dev_id;
1780 u32 status = sw_r32(RTL838X_ISR_GLB_SRC);
1781 u32 ports = sw_r32(RTL838X_ISR_PORT_LINK_STS_CHG);
1782 u32 link;
1783
1784 /* Clear status */
1785 sw_w32(ports, RTL838X_ISR_PORT_LINK_STS_CHG);
1786 pr_info("RTL8380 Link change: status: %x, ports %x\n", status, ports);
1787
1788 for (int i = 0; i < 28; i++) {
1789 if (ports & BIT(i)) {
1790 link = sw_r32(RTL838X_MAC_LINK_STS);
1791 if (link & BIT(i))
1792 dsa_port_phylink_mac_change(ds, i, true);
1793 else
1794 dsa_port_phylink_mac_change(ds, i, false);
1795 }
1796 }
1797
1798 return IRQ_HANDLED;
1799 }
1800
1801 int rtl838x_smi_wait_op(int timeout)
1802 {
1803 int ret = 0;
1804 u32 val;
1805
1806 ret = readx_poll_timeout(sw_r32, RTL838X_SMI_ACCESS_PHY_CTRL_1,
1807 val, !(val & 0x1), 20, timeout);
1808 if (ret)
1809 pr_err("%s: timeout\n", __func__);
1810
1811 return ret;
1812 }
1813
1814 /* Reads a register in a page from the PHY */
1815 int rtl838x_read_phy(u32 port, u32 page, u32 reg, u32 *val)
1816 {
1817 int err;
1818 u32 v;
1819 u32 park_page;
1820
1821 if (port > 31) {
1822 *val = 0xffff;
1823 return 0;
1824 }
1825
1826 if (page > 4095 || reg > 31)
1827 return -ENOTSUPP;
1828
1829 mutex_lock(&smi_lock);
1830
1831 err = rtl838x_smi_wait_op(100000);
1832 if (err)
1833 goto errout;
1834
1835 sw_w32_mask(0xffff0000, port << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);
1836
1837 park_page = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1) & ((0x1f << 15) | 0x2);
1838 v = reg << 20 | page << 3;
1839 sw_w32(v | park_page, RTL838X_SMI_ACCESS_PHY_CTRL_1);
1840 sw_w32_mask(0, 1, RTL838X_SMI_ACCESS_PHY_CTRL_1);
1841
1842 err = rtl838x_smi_wait_op(100000);
1843 if (err)
1844 goto errout;
1845
1846 *val = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_2) & 0xffff;
1847
1848 err = 0;
1849
1850 errout:
1851 mutex_unlock(&smi_lock);
1852
1853 return err;
1854 }
1855
1856 /* Write to a register in a page of the PHY */
1857 int rtl838x_write_phy(u32 port, u32 page, u32 reg, u32 val)
1858 {
1859 int err;
1860 u32 v;
1861 u32 park_page;
1862
1863 val &= 0xffff;
1864 if (port > 31 || page > 4095 || reg > 31)
1865 return -ENOTSUPP;
1866
1867 mutex_lock(&smi_lock);
1868 err = rtl838x_smi_wait_op(100000);
1869 if (err)
1870 goto errout;
1871
1872 sw_w32(BIT(port), RTL838X_SMI_ACCESS_PHY_CTRL_0);
1873 mdelay(10);
1874
1875 sw_w32_mask(0xffff0000, val << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);
1876
1877 park_page = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1) & ((0x1f << 15) | 0x2);
1878 v = reg << 20 | page << 3 | 0x4;
1879 sw_w32(v | park_page, RTL838X_SMI_ACCESS_PHY_CTRL_1);
1880 sw_w32_mask(0, 1, RTL838X_SMI_ACCESS_PHY_CTRL_1);
1881
1882 err = rtl838x_smi_wait_op(100000);
1883 if (err)
1884 goto errout;
1885
1886 err = 0;
1887
1888 errout:
1889 mutex_unlock(&smi_lock);
1890
1891 return err;
1892 }
1893
1894 /* Read an mmd register of a PHY */
1895 int rtl838x_read_mmd_phy(u32 port, u32 addr, u32 reg, u32 *val)
1896 {
1897 int err;
1898 u32 v;
1899
1900 mutex_lock(&smi_lock);
1901
1902 err = rtl838x_smi_wait_op(100000);
1903 if (err)
1904 goto errout;
1905
1906 sw_w32(1 << port, RTL838X_SMI_ACCESS_PHY_CTRL_0);
1907 mdelay(10);
1908
1909 sw_w32_mask(0xffff0000, port << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);
1910
1911 v = addr << 16 | reg;
1912 sw_w32(v, RTL838X_SMI_ACCESS_PHY_CTRL_3);
1913
1914 /* mmd-access | read | cmd-start */
1915 v = 1 << 1 | 0 << 2 | 1;
1916 sw_w32(v, RTL838X_SMI_ACCESS_PHY_CTRL_1);
1917
1918 err = rtl838x_smi_wait_op(100000);
1919 if (err)
1920 goto errout;
1921
1922 *val = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_2) & 0xffff;
1923
1924 err = 0;
1925
1926 errout:
1927 mutex_unlock(&smi_lock);
1928
1929 return err;
1930 }
1931
1932 /* Write to an mmd register of a PHY */
1933 int rtl838x_write_mmd_phy(u32 port, u32 addr, u32 reg, u32 val)
1934 {
1935 int err;
1936 u32 v;
1937
1938 pr_debug("MMD write: port %d, dev %d, reg %d, val %x\n", port, addr, reg, val);
1939 val &= 0xffff;
1940 mutex_lock(&smi_lock);
1941
1942 err = rtl838x_smi_wait_op(100000);
1943 if (err)
1944 goto errout;
1945
1946 sw_w32(1 << port, RTL838X_SMI_ACCESS_PHY_CTRL_0);
1947 mdelay(10);
1948
1949 sw_w32_mask(0xffff0000, val << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);
1950
1951 sw_w32_mask(0x1f << 16, addr << 16, RTL838X_SMI_ACCESS_PHY_CTRL_3);
1952 sw_w32_mask(0xffff, reg, RTL838X_SMI_ACCESS_PHY_CTRL_3);
1953 /* mmd-access | write | cmd-start */
1954 v = 1 << 1 | 1 << 2 | 1;
1955 sw_w32(v, RTL838X_SMI_ACCESS_PHY_CTRL_1);
1956
1957 err = rtl838x_smi_wait_op(100000);
1958 if (err)
1959 goto errout;
1960
1961 err = 0;
1962
1963 errout:
1964 mutex_unlock(&smi_lock);
1965 return err;
1966 }
1967
1968 void rtl8380_get_version(struct rtl838x_switch_priv *priv)
1969 {
1970 u32 rw_save, info_save;
1971 u32 info;
1972
1973 rw_save = sw_r32(RTL838X_INT_RW_CTRL);
1974 sw_w32(rw_save | 0x3, RTL838X_INT_RW_CTRL);
1975
1976 info_save = sw_r32(RTL838X_CHIP_INFO);
1977 sw_w32(info_save | 0xA0000000, RTL838X_CHIP_INFO);
1978
1979 info = sw_r32(RTL838X_CHIP_INFO);
1980 sw_w32(info_save, RTL838X_CHIP_INFO);
1981 sw_w32(rw_save, RTL838X_INT_RW_CTRL);
1982
1983 if ((info & 0xFFFF) == 0x6275) {
1984 if (((info >> 16) & 0x1F) == 0x1)
1985 priv->version = RTL8380_VERSION_A;
1986 else if (((info >> 16) & 0x1F) == 0x2)
1987 priv->version = RTL8380_VERSION_B;
1988 else
1989 priv->version = RTL8380_VERSION_B;
1990 } else {
1991 priv->version = '-';
1992 }
1993 }
1994
1995 void rtl838x_vlan_profile_dump(int profile)
1996 {
1997 u32 p;
1998
1999 if (profile < 0 || profile > 7)
2000 return;
2001
2002 p = sw_r32(RTL838X_VLAN_PROFILE(profile));
2003
2004 pr_info("VLAN profile %d: L2 learning: %d, UNKN L2MC FLD PMSK %d, \
2005 UNKN IPMC FLD PMSK %d, UNKN IPv6MC FLD PMSK: %d",
2006 profile, p & 1, (p >> 1) & 0x1ff, (p >> 10) & 0x1ff, (p >> 19) & 0x1ff);
2007 }
2008
2009 void rtl8380_sds_rst(int mac)
2010 {
2011 u32 offset = (mac == 24) ? 0 : 0x100;
2012
2013 sw_w32_mask(1 << 11, 0, RTL838X_SDS4_FIB_REG0 + offset);
2014 sw_w32_mask(0x3, 0, RTL838X_SDS4_REG28 + offset);
2015 sw_w32_mask(0x3, 0x3, RTL838X_SDS4_REG28 + offset);
2016 sw_w32_mask(0, 0x1 << 6, RTL838X_SDS4_DUMMY0 + offset);
2017 sw_w32_mask(0x1 << 6, 0, RTL838X_SDS4_DUMMY0 + offset);
2018 pr_debug("SERDES reset: %d\n", mac);
2019 }
2020
2021 int rtl8380_sds_power(int mac, int val)
2022 {
2023 u32 mode = (val == 1) ? 0x4 : 0x9;
2024 u32 offset = (mac == 24) ? 5 : 0;
2025
2026 if ((mac != 24) && (mac != 26)) {
2027 pr_err("%s: not a fibre port: %d\n", __func__, mac);
2028 return -1;
2029 }
2030
2031 sw_w32_mask(0x1f << offset, mode << offset, RTL838X_SDS_MODE_SEL);
2032
2033 rtl8380_sds_rst(mac);
2034
2035 return 0;
2036 }
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