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7eebb2107f848d548aa1fb658f1920f0473a5987
[openwrt/staging/jow.git] / target / linux / realtek / files-5.15 / drivers / net / dsa / rtl83xx / dsa.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <net/dsa.h>
4 #include <linux/if_bridge.h>
5 #include <asm/mach-rtl838x/mach-rtl83xx.h>
6
7 #include "rtl83xx.h"
8
9 extern struct rtl83xx_soc_info soc_info;
10
11 static void rtl83xx_init_stats(struct rtl838x_switch_priv *priv)
12 {
13 mutex_lock(&priv->reg_mutex);
14
15 /* Enable statistics module: all counters plus debug.
16 * On RTL839x all counters are enabled by default
17 */
18 if (priv->family_id == RTL8380_FAMILY_ID)
19 sw_w32_mask(0, 3, RTL838X_STAT_CTRL);
20
21 /* Reset statistics counters */
22 sw_w32_mask(0, 1, priv->r->stat_rst);
23
24 mutex_unlock(&priv->reg_mutex);
25 }
26
27 static void rtl83xx_enable_phy_polling(struct rtl838x_switch_priv *priv)
28 {
29 u64 v = 0;
30
31 msleep(1000);
32 /* Enable all ports with a PHY, including the SFP-ports */
33 for (int i = 0; i < priv->cpu_port; i++) {
34 if (priv->ports[i].phy)
35 v |= BIT_ULL(i);
36 }
37
38 pr_info("%s: %16llx\n", __func__, v);
39 priv->r->set_port_reg_le(v, priv->r->smi_poll_ctrl);
40
41 /* PHY update complete, there is no global PHY polling enable bit on the 9300 */
42 if (priv->family_id == RTL8390_FAMILY_ID)
43 sw_w32_mask(0, BIT(7), RTL839X_SMI_GLB_CTRL);
44 else if(priv->family_id == RTL9300_FAMILY_ID)
45 sw_w32_mask(0, 0x8000, RTL838X_SMI_GLB_CTRL);
46 }
47
48 const struct rtl83xx_mib_desc rtl83xx_mib[] = {
49 MIB_DESC(2, 0xf8, "ifInOctets"),
50 MIB_DESC(2, 0xf0, "ifOutOctets"),
51 MIB_DESC(1, 0xec, "dot1dTpPortInDiscards"),
52 MIB_DESC(1, 0xe8, "ifInUcastPkts"),
53 MIB_DESC(1, 0xe4, "ifInMulticastPkts"),
54 MIB_DESC(1, 0xe0, "ifInBroadcastPkts"),
55 MIB_DESC(1, 0xdc, "ifOutUcastPkts"),
56 MIB_DESC(1, 0xd8, "ifOutMulticastPkts"),
57 MIB_DESC(1, 0xd4, "ifOutBroadcastPkts"),
58 MIB_DESC(1, 0xd0, "ifOutDiscards"),
59 MIB_DESC(1, 0xcc, ".3SingleCollisionFrames"),
60 MIB_DESC(1, 0xc8, ".3MultipleCollisionFrames"),
61 MIB_DESC(1, 0xc4, ".3DeferredTransmissions"),
62 MIB_DESC(1, 0xc0, ".3LateCollisions"),
63 MIB_DESC(1, 0xbc, ".3ExcessiveCollisions"),
64 MIB_DESC(1, 0xb8, ".3SymbolErrors"),
65 MIB_DESC(1, 0xb4, ".3ControlInUnknownOpcodes"),
66 MIB_DESC(1, 0xb0, ".3InPauseFrames"),
67 MIB_DESC(1, 0xac, ".3OutPauseFrames"),
68 MIB_DESC(1, 0xa8, "DropEvents"),
69 MIB_DESC(1, 0xa4, "tx_BroadcastPkts"),
70 MIB_DESC(1, 0xa0, "tx_MulticastPkts"),
71 MIB_DESC(1, 0x9c, "CRCAlignErrors"),
72 MIB_DESC(1, 0x98, "tx_UndersizePkts"),
73 MIB_DESC(1, 0x94, "rx_UndersizePkts"),
74 MIB_DESC(1, 0x90, "rx_UndersizedropPkts"),
75 MIB_DESC(1, 0x8c, "tx_OversizePkts"),
76 MIB_DESC(1, 0x88, "rx_OversizePkts"),
77 MIB_DESC(1, 0x84, "Fragments"),
78 MIB_DESC(1, 0x80, "Jabbers"),
79 MIB_DESC(1, 0x7c, "Collisions"),
80 MIB_DESC(1, 0x78, "tx_Pkts64Octets"),
81 MIB_DESC(1, 0x74, "rx_Pkts64Octets"),
82 MIB_DESC(1, 0x70, "tx_Pkts65to127Octets"),
83 MIB_DESC(1, 0x6c, "rx_Pkts65to127Octets"),
84 MIB_DESC(1, 0x68, "tx_Pkts128to255Octets"),
85 MIB_DESC(1, 0x64, "rx_Pkts128to255Octets"),
86 MIB_DESC(1, 0x60, "tx_Pkts256to511Octets"),
87 MIB_DESC(1, 0x5c, "rx_Pkts256to511Octets"),
88 MIB_DESC(1, 0x58, "tx_Pkts512to1023Octets"),
89 MIB_DESC(1, 0x54, "rx_Pkts512to1023Octets"),
90 MIB_DESC(1, 0x50, "tx_Pkts1024to1518Octets"),
91 MIB_DESC(1, 0x4c, "rx_StatsPkts1024to1518Octets"),
92 MIB_DESC(1, 0x48, "tx_Pkts1519toMaxOctets"),
93 MIB_DESC(1, 0x44, "rx_Pkts1519toMaxOctets"),
94 MIB_DESC(1, 0x40, "rxMacDiscards")
95 };
96
97
98 /* DSA callbacks */
99
100
101 static enum dsa_tag_protocol rtl83xx_get_tag_protocol(struct dsa_switch *ds,
102 int port,
103 enum dsa_tag_protocol mprot)
104 {
105 /* The switch does not tag the frames, instead internally the header
106 * structure for each packet is tagged accordingly.
107 */
108 return DSA_TAG_PROTO_TRAILER;
109 }
110
111 /* Initialize all VLANS */
112 static void rtl83xx_vlan_setup(struct rtl838x_switch_priv *priv)
113 {
114 struct rtl838x_vlan_info info;
115
116 pr_info("In %s\n", __func__);
117
118 priv->r->vlan_profile_setup(0);
119 priv->r->vlan_profile_setup(1);
120 pr_info("UNKNOWN_MC_PMASK: %016llx\n", priv->r->read_mcast_pmask(UNKNOWN_MC_PMASK));
121 priv->r->vlan_profile_dump(0);
122
123 info.fid = 0; /* Default Forwarding ID / MSTI */
124 info.hash_uc_fid = false; /* Do not build the L2 lookup hash with FID, but VID */
125 info.hash_mc_fid = false; /* Do the same for Multicast packets */
126 info.profile_id = 0; /* Use default Vlan Profile 0 */
127 info.tagged_ports = 0; /* Initially no port members */
128 if (priv->family_id == RTL9310_FAMILY_ID) {
129 info.if_id = 0;
130 info.multicast_grp_mask = 0;
131 info.l2_tunnel_list_id = -1;
132 }
133
134 /* Initialize all vlans 0-4095 */
135 for (int i = 0; i < MAX_VLANS; i ++)
136 priv->r->vlan_set_tagged(i, &info);
137
138 /* reset PVIDs; defaults to 1 on reset */
139 for (int i = 0; i <= priv->ds->num_ports; i++) {
140 priv->r->vlan_port_pvid_set(i, PBVLAN_TYPE_INNER, 0);
141 priv->r->vlan_port_pvid_set(i, PBVLAN_TYPE_OUTER, 0);
142 priv->r->vlan_port_pvidmode_set(i, PBVLAN_TYPE_INNER, PBVLAN_MODE_UNTAG_AND_PRITAG);
143 priv->r->vlan_port_pvidmode_set(i, PBVLAN_TYPE_OUTER, PBVLAN_MODE_UNTAG_AND_PRITAG);
144 }
145
146 /* Set forwarding action based on inner VLAN tag */
147 for (int i = 0; i < priv->cpu_port; i++)
148 priv->r->vlan_fwd_on_inner(i, true);
149 }
150
151 static void rtl83xx_setup_bpdu_traps(struct rtl838x_switch_priv *priv)
152 {
153 for (int i = 0; i < priv->cpu_port; i++)
154 priv->r->set_receive_management_action(i, BPDU, COPY2CPU);
155 }
156
157 static void rtl83xx_port_set_salrn(struct rtl838x_switch_priv *priv,
158 int port, bool enable)
159 {
160 int shift = SALRN_PORT_SHIFT(port);
161 int val = enable ? SALRN_MODE_HARDWARE : SALRN_MODE_DISABLED;
162
163 sw_w32_mask(SALRN_MODE_MASK << shift, val << shift,
164 priv->r->l2_port_new_salrn(port));
165 }
166
167 static int rtl83xx_setup(struct dsa_switch *ds)
168 {
169 struct rtl838x_switch_priv *priv = ds->priv;
170 u64 port_bitmap = BIT_ULL(priv->cpu_port);
171
172 pr_debug("%s called\n", __func__);
173
174 /* Disable MAC polling the PHY so that we can start configuration */
175 priv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl);
176
177 for (int i = 0; i < ds->num_ports; i++)
178 priv->ports[i].enable = false;
179 priv->ports[priv->cpu_port].enable = true;
180
181 /* Isolate ports from each other: traffic only CPU <-> port */
182 /* Setting bit j in register RTL838X_PORT_ISO_CTRL(i) allows
183 * traffic from source port i to destination port j
184 */
185 for (int i = 0; i < priv->cpu_port; i++) {
186 if (priv->ports[i].phy) {
187 priv->r->set_port_reg_be(BIT_ULL(priv->cpu_port) | BIT_ULL(i),
188 priv->r->port_iso_ctrl(i));
189 port_bitmap |= BIT_ULL(i);
190 }
191 }
192 priv->r->set_port_reg_be(port_bitmap, priv->r->port_iso_ctrl(priv->cpu_port));
193
194 if (priv->family_id == RTL8380_FAMILY_ID)
195 rtl838x_print_matrix();
196 else
197 rtl839x_print_matrix();
198
199 rtl83xx_init_stats(priv);
200
201 rtl83xx_vlan_setup(priv);
202
203 rtl83xx_setup_bpdu_traps(priv);
204
205 ds->configure_vlan_while_not_filtering = true;
206
207 priv->r->l2_learning_setup();
208
209 rtl83xx_port_set_salrn(priv, priv->cpu_port, false);
210 ds->assisted_learning_on_cpu_port = true;
211
212 /* Make sure all frames sent to the switch's MAC are trapped to the CPU-port
213 * 0: FWD, 1: DROP, 2: TRAP2CPU
214 */
215 if (priv->family_id == RTL8380_FAMILY_ID)
216 sw_w32(0x2, RTL838X_SPCL_TRAP_SWITCH_MAC_CTRL);
217 else
218 sw_w32(0x2, RTL839X_SPCL_TRAP_SWITCH_MAC_CTRL);
219
220 /* Enable MAC Polling PHY again */
221 rtl83xx_enable_phy_polling(priv);
222 pr_debug("Please wait until PHY is settled\n");
223 msleep(1000);
224 priv->r->pie_init(priv);
225
226 return 0;
227 }
228
229 static int rtl93xx_setup(struct dsa_switch *ds)
230 {
231 struct rtl838x_switch_priv *priv = ds->priv;
232 u32 port_bitmap = BIT(priv->cpu_port);
233
234 pr_info("%s called\n", __func__);
235
236 /* Disable MAC polling the PHY so that we can start configuration */
237 if (priv->family_id == RTL9300_FAMILY_ID)
238 sw_w32(0, RTL930X_SMI_POLL_CTRL);
239
240 if (priv->family_id == RTL9310_FAMILY_ID) {
241 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL);
242 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL + 4);
243 }
244
245 /* Disable all ports except CPU port */
246 for (int i = 0; i < ds->num_ports; i++)
247 priv->ports[i].enable = false;
248 priv->ports[priv->cpu_port].enable = true;
249
250 for (int i = 0; i < priv->cpu_port; i++) {
251 if (priv->ports[i].phy) {
252 priv->r->traffic_set(i, BIT_ULL(priv->cpu_port) | BIT_ULL(i));
253 port_bitmap |= BIT_ULL(i);
254 }
255 }
256 priv->r->traffic_set(priv->cpu_port, port_bitmap);
257
258 rtl930x_print_matrix();
259
260 /* TODO: Initialize statistics */
261
262 rtl83xx_vlan_setup(priv);
263
264 ds->configure_vlan_while_not_filtering = true;
265
266 priv->r->l2_learning_setup();
267
268 rtl83xx_port_set_salrn(priv, priv->cpu_port, false);
269 ds->assisted_learning_on_cpu_port = true;
270
271 rtl83xx_enable_phy_polling(priv);
272
273 priv->r->pie_init(priv);
274
275 priv->r->led_init(priv);
276
277 return 0;
278 }
279
280 static int rtl93xx_get_sds(struct phy_device *phydev)
281 {
282 struct device *dev = &phydev->mdio.dev;
283 struct device_node *dn;
284 u32 sds_num;
285
286 if (!dev)
287 return -1;
288 if (dev->of_node) {
289 dn = dev->of_node;
290 if (of_property_read_u32(dn, "sds", &sds_num))
291 sds_num = -1;
292 } else {
293 dev_err(dev, "No DT node.\n");
294 return -1;
295 }
296
297 return sds_num;
298 }
299
300 static void rtl83xx_phylink_validate(struct dsa_switch *ds, int port,
301 unsigned long *supported,
302 struct phylink_link_state *state)
303 {
304 struct rtl838x_switch_priv *priv = ds->priv;
305 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
306
307 pr_debug("In %s port %d, state is %d", __func__, port, state->interface);
308
309 if (!phy_interface_mode_is_rgmii(state->interface) &&
310 state->interface != PHY_INTERFACE_MODE_NA &&
311 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
312 state->interface != PHY_INTERFACE_MODE_MII &&
313 state->interface != PHY_INTERFACE_MODE_REVMII &&
314 state->interface != PHY_INTERFACE_MODE_GMII &&
315 state->interface != PHY_INTERFACE_MODE_QSGMII &&
316 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
317 state->interface != PHY_INTERFACE_MODE_SGMII) {
318 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
319 dev_err(ds->dev,
320 "Unsupported interface: %d for port %d\n",
321 state->interface, port);
322 return;
323 }
324
325 /* Allow all the expected bits */
326 phylink_set(mask, Autoneg);
327 phylink_set_port_modes(mask);
328 phylink_set(mask, Pause);
329 phylink_set(mask, Asym_Pause);
330
331 /* With the exclusion of MII and Reverse MII, we support Gigabit,
332 * including Half duplex
333 */
334 if (state->interface != PHY_INTERFACE_MODE_MII &&
335 state->interface != PHY_INTERFACE_MODE_REVMII) {
336 phylink_set(mask, 1000baseT_Full);
337 phylink_set(mask, 1000baseT_Half);
338 }
339
340 /* On both the 8380 and 8382, ports 24-27 are SFP ports */
341 if (port >= 24 && port <= 27 && priv->family_id == RTL8380_FAMILY_ID)
342 phylink_set(mask, 1000baseX_Full);
343
344 /* On the RTL839x family of SoCs, ports 48 to 51 are SFP ports */
345 if (port >= 48 && port <= 51 && priv->family_id == RTL8390_FAMILY_ID)
346 phylink_set(mask, 1000baseX_Full);
347
348 phylink_set(mask, 10baseT_Half);
349 phylink_set(mask, 10baseT_Full);
350 phylink_set(mask, 100baseT_Half);
351 phylink_set(mask, 100baseT_Full);
352
353 bitmap_and(supported, supported, mask,
354 __ETHTOOL_LINK_MODE_MASK_NBITS);
355 bitmap_and(state->advertising, state->advertising, mask,
356 __ETHTOOL_LINK_MODE_MASK_NBITS);
357 }
358
359 static void rtl93xx_phylink_validate(struct dsa_switch *ds, int port,
360 unsigned long *supported,
361 struct phylink_link_state *state)
362 {
363 struct rtl838x_switch_priv *priv = ds->priv;
364 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
365
366 pr_debug("In %s port %d, state is %d (%s)", __func__, port, state->interface,
367 phy_modes(state->interface));
368
369 if (!phy_interface_mode_is_rgmii(state->interface) &&
370 state->interface != PHY_INTERFACE_MODE_NA &&
371 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
372 state->interface != PHY_INTERFACE_MODE_MII &&
373 state->interface != PHY_INTERFACE_MODE_REVMII &&
374 state->interface != PHY_INTERFACE_MODE_GMII &&
375 state->interface != PHY_INTERFACE_MODE_QSGMII &&
376 state->interface != PHY_INTERFACE_MODE_XGMII &&
377 state->interface != PHY_INTERFACE_MODE_HSGMII &&
378 state->interface != PHY_INTERFACE_MODE_10GBASER &&
379 state->interface != PHY_INTERFACE_MODE_10GKR &&
380 state->interface != PHY_INTERFACE_MODE_USXGMII &&
381 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
382 state->interface != PHY_INTERFACE_MODE_SGMII) {
383 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
384 dev_err(ds->dev,
385 "Unsupported interface: %d for port %d\n",
386 state->interface, port);
387 return;
388 }
389
390 /* Allow all the expected bits */
391 phylink_set(mask, Autoneg);
392 phylink_set_port_modes(mask);
393 phylink_set(mask, Pause);
394 phylink_set(mask, Asym_Pause);
395
396 /* With the exclusion of MII and Reverse MII, we support Gigabit,
397 * including Half duplex
398 */
399 if (state->interface != PHY_INTERFACE_MODE_MII &&
400 state->interface != PHY_INTERFACE_MODE_REVMII) {
401 phylink_set(mask, 1000baseT_Full);
402 phylink_set(mask, 1000baseT_Half);
403 }
404
405 /* Internal phys of the RTL93xx family provide 10G */
406 if (priv->ports[port].phy_is_integrated &&
407 state->interface == PHY_INTERFACE_MODE_1000BASEX) {
408 phylink_set(mask, 1000baseX_Full);
409 } else if (priv->ports[port].phy_is_integrated) {
410 phylink_set(mask, 1000baseX_Full);
411 phylink_set(mask, 10000baseKR_Full);
412 phylink_set(mask, 10000baseSR_Full);
413 phylink_set(mask, 10000baseCR_Full);
414 }
415 if (state->interface == PHY_INTERFACE_MODE_INTERNAL) {
416 phylink_set(mask, 1000baseX_Full);
417 phylink_set(mask, 1000baseT_Full);
418 phylink_set(mask, 10000baseKR_Full);
419 phylink_set(mask, 10000baseT_Full);
420 phylink_set(mask, 10000baseSR_Full);
421 phylink_set(mask, 10000baseCR_Full);
422 }
423
424 if (state->interface == PHY_INTERFACE_MODE_USXGMII)
425 phylink_set(mask, 10000baseT_Full);
426
427 phylink_set(mask, 10baseT_Half);
428 phylink_set(mask, 10baseT_Full);
429 phylink_set(mask, 100baseT_Half);
430 phylink_set(mask, 100baseT_Full);
431
432 bitmap_and(supported, supported, mask,
433 __ETHTOOL_LINK_MODE_MASK_NBITS);
434 bitmap_and(state->advertising, state->advertising, mask,
435 __ETHTOOL_LINK_MODE_MASK_NBITS);
436 pr_debug("%s leaving supported: %*pb", __func__, __ETHTOOL_LINK_MODE_MASK_NBITS, supported);
437 }
438
439 static int rtl83xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
440 struct phylink_link_state *state)
441 {
442 struct rtl838x_switch_priv *priv = ds->priv;
443 u64 speed;
444 u64 link;
445
446 if (port < 0 || port > priv->cpu_port)
447 return -EINVAL;
448
449 state->link = 0;
450 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
451 if (link & BIT_ULL(port))
452 state->link = 1;
453 pr_debug("%s: link state port %d: %llx\n", __func__, port, link & BIT_ULL(port));
454
455 state->duplex = 0;
456 if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
457 state->duplex = 1;
458
459 speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
460 speed >>= (port % 16) << 1;
461 switch (speed & 0x3) {
462 case 0:
463 state->speed = SPEED_10;
464 break;
465 case 1:
466 state->speed = SPEED_100;
467 break;
468 case 2:
469 state->speed = SPEED_1000;
470 break;
471 case 3:
472 if (priv->family_id == RTL9300_FAMILY_ID
473 && (port == 24 || port == 26)) /* Internal serdes */
474 state->speed = SPEED_2500;
475 else
476 state->speed = SPEED_100; /* Is in fact 500Mbit */
477 }
478
479 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
480 if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
481 state->pause |= MLO_PAUSE_RX;
482 if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
483 state->pause |= MLO_PAUSE_TX;
484
485 return 1;
486 }
487
488 static int rtl93xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
489 struct phylink_link_state *state)
490 {
491 struct rtl838x_switch_priv *priv = ds->priv;
492 u64 speed;
493 u64 link;
494 u64 media;
495
496 if (port < 0 || port > priv->cpu_port)
497 return -EINVAL;
498
499 /* On the RTL9300 for at least the RTL8226B PHY, the MAC-side link
500 * state needs to be read twice in order to read a correct result.
501 * This would not be necessary for ports connected e.g. to RTL8218D
502 * PHYs.
503 */
504 state->link = 0;
505 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
506 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
507 if (link & BIT_ULL(port))
508 state->link = 1;
509
510 if (priv->family_id == RTL9310_FAMILY_ID)
511 media = priv->r->get_port_reg_le(RTL931X_MAC_LINK_MEDIA_STS);
512
513 if (priv->family_id == RTL9300_FAMILY_ID)
514 media = sw_r32(RTL930X_MAC_LINK_MEDIA_STS);
515
516 if (media & BIT_ULL(port))
517 state->link = 1;
518
519 pr_debug("%s: link state port %d: %llx, media %llx\n", __func__, port,
520 link & BIT_ULL(port), media);
521
522 state->duplex = 0;
523 if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
524 state->duplex = 1;
525
526 speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
527 speed >>= (port % 8) << 2;
528 switch (speed & 0xf) {
529 case 0:
530 state->speed = SPEED_10;
531 break;
532 case 1:
533 state->speed = SPEED_100;
534 break;
535 case 2:
536 case 7:
537 state->speed = SPEED_1000;
538 break;
539 case 4:
540 state->speed = SPEED_10000;
541 break;
542 case 5:
543 case 8:
544 state->speed = SPEED_2500;
545 break;
546 case 6:
547 state->speed = SPEED_5000;
548 break;
549 default:
550 pr_err("%s: unknown speed: %d\n", __func__, (u32)speed & 0xf);
551 }
552
553 if (priv->family_id == RTL9310_FAMILY_ID
554 && (port >= 52 || port <= 55)) { /* Internal serdes */
555 state->speed = SPEED_10000;
556 state->link = 1;
557 state->duplex = 1;
558 }
559
560 pr_debug("%s: speed is: %d %d\n", __func__, (u32)speed & 0xf, state->speed);
561 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
562 if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
563 state->pause |= MLO_PAUSE_RX;
564 if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
565 state->pause |= MLO_PAUSE_TX;
566
567 return 1;
568 }
569
570 static void rtl83xx_config_interface(int port, phy_interface_t interface)
571 {
572 u32 old, int_shift, sds_shift;
573
574 switch (port) {
575 case 24:
576 int_shift = 0;
577 sds_shift = 5;
578 break;
579 case 26:
580 int_shift = 3;
581 sds_shift = 0;
582 break;
583 default:
584 return;
585 }
586
587 old = sw_r32(RTL838X_SDS_MODE_SEL);
588 switch (interface) {
589 case PHY_INTERFACE_MODE_1000BASEX:
590 if ((old >> sds_shift & 0x1f) == 4)
591 return;
592 sw_w32_mask(0x7 << int_shift, 1 << int_shift, RTL838X_INT_MODE_CTRL);
593 sw_w32_mask(0x1f << sds_shift, 4 << sds_shift, RTL838X_SDS_MODE_SEL);
594 break;
595 case PHY_INTERFACE_MODE_SGMII:
596 if ((old >> sds_shift & 0x1f) == 2)
597 return;
598 sw_w32_mask(0x7 << int_shift, 2 << int_shift, RTL838X_INT_MODE_CTRL);
599 sw_w32_mask(0x1f << sds_shift, 2 << sds_shift, RTL838X_SDS_MODE_SEL);
600 break;
601 default:
602 return;
603 }
604 pr_debug("configured port %d for interface %s\n", port, phy_modes(interface));
605 }
606
607 static void rtl83xx_phylink_mac_config(struct dsa_switch *ds, int port,
608 unsigned int mode,
609 const struct phylink_link_state *state)
610 {
611 struct rtl838x_switch_priv *priv = ds->priv;
612 u32 reg;
613 int speed_bit = priv->family_id == RTL8380_FAMILY_ID ? 4 : 3;
614
615 pr_debug("%s port %d, mode %x\n", __func__, port, mode);
616
617 if (port == priv->cpu_port) {
618 /* Set Speed, duplex, flow control
619 * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
620 * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
621 * | MEDIA_SEL
622 */
623 if (priv->family_id == RTL8380_FAMILY_ID) {
624 sw_w32(0x6192F, priv->r->mac_force_mode_ctrl(priv->cpu_port));
625 /* allow CRC errors on CPU-port */
626 sw_w32_mask(0, 0x8, RTL838X_MAC_PORT_CTRL(priv->cpu_port));
627 } else {
628 sw_w32_mask(0, 3, priv->r->mac_force_mode_ctrl(priv->cpu_port));
629 }
630 return;
631 }
632
633 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
634 /* Auto-Negotiation does not work for MAC in RTL8390 */
635 if (priv->family_id == RTL8380_FAMILY_ID) {
636 if (mode == MLO_AN_PHY || phylink_autoneg_inband(mode)) {
637 pr_debug("PHY autonegotiates\n");
638 reg |= RTL838X_NWAY_EN;
639 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
640 rtl83xx_config_interface(port, state->interface);
641 return;
642 }
643 }
644
645 if (mode != MLO_AN_FIXED)
646 pr_debug("Fixed state.\n");
647
648 /* Clear id_mode_dis bit, and the existing port mode, let
649 * RGMII_MODE_EN bet set by mac_link_{up,down} */
650 if (priv->family_id == RTL8380_FAMILY_ID) {
651 reg &= ~(RTL838X_RX_PAUSE_EN | RTL838X_TX_PAUSE_EN);
652 if (state->pause & MLO_PAUSE_TXRX_MASK) {
653 if (state->pause & MLO_PAUSE_TX)
654 reg |= RTL838X_TX_PAUSE_EN;
655 reg |= RTL838X_RX_PAUSE_EN;
656 }
657 } else if (priv->family_id == RTL8390_FAMILY_ID) {
658 reg &= ~(RTL839X_RX_PAUSE_EN | RTL839X_TX_PAUSE_EN);
659 if (state->pause & MLO_PAUSE_TXRX_MASK) {
660 if (state->pause & MLO_PAUSE_TX)
661 reg |= RTL839X_TX_PAUSE_EN;
662 reg |= RTL839X_RX_PAUSE_EN;
663 }
664 }
665
666
667 reg &= ~(3 << speed_bit);
668 switch (state->speed) {
669 case SPEED_1000:
670 reg |= 2 << speed_bit;
671 break;
672 case SPEED_100:
673 reg |= 1 << speed_bit;
674 break;
675 default:
676 break; /* Ignore, including 10MBit which has a speed value of 0 */
677 }
678
679 if (priv->family_id == RTL8380_FAMILY_ID) {
680 reg &= ~(RTL838X_DUPLEX_MODE | RTL838X_FORCE_LINK_EN);
681 if (state->link)
682 reg |= RTL838X_FORCE_LINK_EN;
683 if (state->duplex == RTL838X_DUPLEX_MODE)
684 reg |= RTL838X_DUPLEX_MODE;
685 } else if (priv->family_id == RTL8390_FAMILY_ID) {
686 reg &= ~(RTL839X_DUPLEX_MODE | RTL839X_FORCE_LINK_EN);
687 if (state->link)
688 reg |= RTL839X_FORCE_LINK_EN;
689 if (state->duplex == RTL839X_DUPLEX_MODE)
690 reg |= RTL839X_DUPLEX_MODE;
691 }
692
693 /* LAG members must use DUPLEX and we need to enable the link */
694 if (priv->lagmembers & BIT_ULL(port)) {
695 switch(priv->family_id) {
696 case RTL8380_FAMILY_ID:
697 reg |= (RTL838X_DUPLEX_MODE | RTL838X_FORCE_LINK_EN);
698 break;
699 case RTL8390_FAMILY_ID:
700 reg |= (RTL839X_DUPLEX_MODE | RTL839X_FORCE_LINK_EN);
701 break;
702 }
703 }
704
705 /* Disable AN */
706 if (priv->family_id == RTL8380_FAMILY_ID)
707 reg &= ~RTL838X_NWAY_EN;
708 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
709 }
710
711 static void rtl931x_phylink_mac_config(struct dsa_switch *ds, int port,
712 unsigned int mode,
713 const struct phylink_link_state *state)
714 {
715 struct rtl838x_switch_priv *priv = ds->priv;
716 int sds_num;
717 u32 reg, band;
718
719 sds_num = priv->ports[port].sds_num;
720 pr_info("%s: speed %d sds_num %d\n", __func__, state->speed, sds_num);
721
722 switch (state->interface) {
723 case PHY_INTERFACE_MODE_HSGMII:
724 pr_info("%s setting mode PHY_INTERFACE_MODE_HSGMII\n", __func__);
725 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_HSGMII);
726 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_HSGMII);
727 band = rtl931x_sds_cmu_band_set(sds_num, true, 62, PHY_INTERFACE_MODE_HSGMII);
728 break;
729 case PHY_INTERFACE_MODE_1000BASEX:
730 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_1000BASEX);
731 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_1000BASEX);
732 break;
733 case PHY_INTERFACE_MODE_XGMII:
734 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_XGMII);
735 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_XGMII);
736 break;
737 case PHY_INTERFACE_MODE_10GBASER:
738 case PHY_INTERFACE_MODE_10GKR:
739 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_10GBASER);
740 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_10GBASER);
741 break;
742 case PHY_INTERFACE_MODE_USXGMII:
743 /* Translates to MII_USXGMII_10GSXGMII */
744 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_USXGMII);
745 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_USXGMII);
746 break;
747 case PHY_INTERFACE_MODE_SGMII:
748 pr_info("%s setting mode PHY_INTERFACE_MODE_SGMII\n", __func__);
749 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_SGMII);
750 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_SGMII);
751 band = rtl931x_sds_cmu_band_set(sds_num, true, 62, PHY_INTERFACE_MODE_SGMII);
752 break;
753 case PHY_INTERFACE_MODE_QSGMII:
754 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_QSGMII);
755 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_QSGMII);
756 break;
757 default:
758 pr_err("%s: unknown serdes mode: %s\n",
759 __func__, phy_modes(state->interface));
760 return;
761 }
762
763 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
764 pr_info("%s reading FORCE_MODE_CTRL: %08x\n", __func__, reg);
765
766 reg &= ~(RTL931X_DUPLEX_MODE | RTL931X_FORCE_EN | RTL931X_FORCE_LINK_EN);
767
768 reg &= ~(0xf << 12);
769 reg |= 0x2 << 12; /* Set SMI speed to 0x2 */
770
771 reg |= RTL931X_TX_PAUSE_EN | RTL931X_RX_PAUSE_EN;
772
773 if (priv->lagmembers & BIT_ULL(port))
774 reg |= RTL931X_DUPLEX_MODE;
775
776 if (state->duplex == DUPLEX_FULL)
777 reg |= RTL931X_DUPLEX_MODE;
778
779 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
780
781 }
782
783 static void rtl93xx_phylink_mac_config(struct dsa_switch *ds, int port,
784 unsigned int mode,
785 const struct phylink_link_state *state)
786 {
787 struct rtl838x_switch_priv *priv = ds->priv;
788 int sds_num, sds_mode;
789 u32 reg;
790
791 pr_info("%s port %d, mode %x, phy-mode: %s, speed %d, link %d\n", __func__,
792 port, mode, phy_modes(state->interface), state->speed, state->link);
793
794 /* Nothing to be done for the CPU-port */
795 if (port == priv->cpu_port)
796 return;
797
798 if (priv->family_id == RTL9310_FAMILY_ID)
799 return rtl931x_phylink_mac_config(ds, port, mode, state);
800
801 sds_num = priv->ports[port].sds_num;
802 pr_info("%s SDS is %d\n", __func__, sds_num);
803 if (sds_num >= 0) {
804 switch (state->interface) {
805 case PHY_INTERFACE_MODE_HSGMII:
806 sds_mode = 0x12;
807 break;
808 case PHY_INTERFACE_MODE_1000BASEX:
809 sds_mode = 0x04;
810 break;
811 case PHY_INTERFACE_MODE_XGMII:
812 sds_mode = 0x10;
813 break;
814 case PHY_INTERFACE_MODE_10GBASER:
815 case PHY_INTERFACE_MODE_10GKR:
816 sds_mode = 0x1b; /* 10G 1000X Auto */
817 break;
818 case PHY_INTERFACE_MODE_USXGMII:
819 sds_mode = 0x0d;
820 break;
821 default:
822 pr_err("%s: unknown serdes mode: %s\n",
823 __func__, phy_modes(state->interface));
824 return;
825 }
826 if (state->interface == PHY_INTERFACE_MODE_10GBASER)
827 rtl9300_serdes_setup(sds_num, state->interface);
828 }
829
830 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
831 reg &= ~(0xf << 3);
832
833 switch (state->speed) {
834 case SPEED_10000:
835 reg |= 4 << 3;
836 break;
837 case SPEED_5000:
838 reg |= 6 << 3;
839 break;
840 case SPEED_2500:
841 reg |= 5 << 3;
842 break;
843 case SPEED_1000:
844 reg |= 2 << 3;
845 break;
846 default:
847 reg |= 2 << 3;
848 break;
849 }
850
851 if (state->link)
852 reg |= RTL930X_FORCE_LINK_EN;
853
854 if (priv->lagmembers & BIT_ULL(port))
855 reg |= RTL930X_DUPLEX_MODE | RTL930X_FORCE_LINK_EN;
856
857 if (state->duplex == DUPLEX_FULL)
858 reg |= RTL930X_DUPLEX_MODE;
859
860 if (priv->ports[port].phy_is_integrated)
861 reg &= ~RTL930X_FORCE_EN; /* Clear MAC_FORCE_EN to allow SDS-MAC link */
862 else
863 reg |= RTL930X_FORCE_EN;
864
865 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
866 }
867
868 static void rtl83xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
869 unsigned int mode,
870 phy_interface_t interface)
871 {
872 struct rtl838x_switch_priv *priv = ds->priv;
873
874 /* Stop TX/RX to port */
875 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
876
877 /* No longer force link */
878 sw_w32_mask(0x3, 0, priv->r->mac_force_mode_ctrl(port));
879 }
880
881 static void rtl93xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
882 unsigned int mode,
883 phy_interface_t interface)
884 {
885 struct rtl838x_switch_priv *priv = ds->priv;
886 u32 v = 0;
887
888 /* Stop TX/RX to port */
889 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
890
891 /* No longer force link */
892 if (priv->family_id == RTL9300_FAMILY_ID)
893 v = RTL930X_FORCE_EN | RTL930X_FORCE_LINK_EN;
894 else if (priv->family_id == RTL9310_FAMILY_ID)
895 v = RTL931X_FORCE_EN | RTL931X_FORCE_LINK_EN;
896 sw_w32_mask(v, 0, priv->r->mac_force_mode_ctrl(port));
897 }
898
899 static void rtl83xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
900 unsigned int mode,
901 phy_interface_t interface,
902 struct phy_device *phydev,
903 int speed, int duplex,
904 bool tx_pause, bool rx_pause)
905 {
906 struct rtl838x_switch_priv *priv = ds->priv;
907 /* Restart TX/RX to port */
908 sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
909 /* TODO: Set speed/duplex/pauses */
910 }
911
912 static void rtl93xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
913 unsigned int mode,
914 phy_interface_t interface,
915 struct phy_device *phydev,
916 int speed, int duplex,
917 bool tx_pause, bool rx_pause)
918 {
919 struct rtl838x_switch_priv *priv = ds->priv;
920
921 /* Restart TX/RX to port */
922 sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
923 /* TODO: Set speed/duplex/pauses */
924 }
925
926 static void rtl83xx_get_strings(struct dsa_switch *ds,
927 int port, u32 stringset, u8 *data)
928 {
929 if (stringset != ETH_SS_STATS)
930 return;
931
932 for (int i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++)
933 strncpy(data + i * ETH_GSTRING_LEN, rtl83xx_mib[i].name,
934 ETH_GSTRING_LEN);
935 }
936
937 static void rtl83xx_get_ethtool_stats(struct dsa_switch *ds, int port,
938 uint64_t *data)
939 {
940 struct rtl838x_switch_priv *priv = ds->priv;
941 const struct rtl83xx_mib_desc *mib;
942 u64 h;
943
944 for (int i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++) {
945 mib = &rtl83xx_mib[i];
946
947 data[i] = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 252 - mib->offset);
948 if (mib->size == 2) {
949 h = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 248 - mib->offset);
950 data[i] |= h << 32;
951 }
952 }
953 }
954
955 static int rtl83xx_get_sset_count(struct dsa_switch *ds, int port, int sset)
956 {
957 if (sset != ETH_SS_STATS)
958 return 0;
959
960 return ARRAY_SIZE(rtl83xx_mib);
961 }
962
963 static int rtl83xx_mc_group_alloc(struct rtl838x_switch_priv *priv, int port)
964 {
965 int mc_group = find_first_zero_bit(priv->mc_group_bm, MAX_MC_GROUPS - 1);
966 u64 portmask;
967
968 if (mc_group >= MAX_MC_GROUPS - 1)
969 return -1;
970
971 if (priv->is_lagmember[port]) {
972 pr_info("%s: %d is lag slave. ignore\n", __func__, port);
973 return 0;
974 }
975
976 set_bit(mc_group, priv->mc_group_bm);
977 mc_group++; /* We cannot use group 0, as this is used for lookup miss flooding */
978 portmask = BIT_ULL(port) | BIT_ULL(priv->cpu_port);
979 priv->r->write_mcast_pmask(mc_group, portmask);
980
981 return mc_group;
982 }
983
984 static u64 rtl83xx_mc_group_add_port(struct rtl838x_switch_priv *priv, int mc_group, int port)
985 {
986 u64 portmask = priv->r->read_mcast_pmask(mc_group);
987
988 pr_debug("%s: %d\n", __func__, port);
989 if (priv->is_lagmember[port]) {
990 pr_info("%s: %d is lag slave. ignore\n", __func__, port);
991 return portmask;
992 }
993 portmask |= BIT_ULL(port);
994 priv->r->write_mcast_pmask(mc_group, portmask);
995
996 return portmask;
997 }
998
999 static u64 rtl83xx_mc_group_del_port(struct rtl838x_switch_priv *priv, int mc_group, int port)
1000 {
1001 u64 portmask = priv->r->read_mcast_pmask(mc_group);
1002
1003 pr_debug("%s: %d\n", __func__, port);
1004 if (priv->is_lagmember[port]) {
1005 pr_info("%s: %d is lag slave. ignore\n", __func__, port);
1006 return portmask;
1007 }
1008 priv->r->write_mcast_pmask(mc_group, portmask);
1009 if (portmask == BIT_ULL(priv->cpu_port)) {
1010 portmask &= ~BIT_ULL(priv->cpu_port);
1011 priv->r->write_mcast_pmask(mc_group, portmask);
1012 clear_bit(mc_group, priv->mc_group_bm);
1013 }
1014
1015 return portmask;
1016 }
1017
1018 static void store_mcgroups(struct rtl838x_switch_priv *priv, int port)
1019 {
1020 for (int mc_group = 0; mc_group < MAX_MC_GROUPS; mc_group++) {
1021 u64 portmask = priv->r->read_mcast_pmask(mc_group);
1022 if (portmask & BIT_ULL(port)) {
1023 priv->mc_group_saves[mc_group] = port;
1024 rtl83xx_mc_group_del_port(priv, mc_group, port);
1025 }
1026 }
1027 }
1028
1029 static void load_mcgroups(struct rtl838x_switch_priv *priv, int port)
1030 {
1031 for (int mc_group = 0; mc_group < MAX_MC_GROUPS; mc_group++) {
1032 if (priv->mc_group_saves[mc_group] == port) {
1033 rtl83xx_mc_group_add_port(priv, mc_group, port);
1034 priv->mc_group_saves[mc_group] = -1;
1035 }
1036 }
1037 }
1038
1039 static int rtl83xx_port_enable(struct dsa_switch *ds, int port,
1040 struct phy_device *phydev)
1041 {
1042 struct rtl838x_switch_priv *priv = ds->priv;
1043 u64 v;
1044
1045 pr_debug("%s: %x %d", __func__, (u32) priv, port);
1046 priv->ports[port].enable = true;
1047
1048 /* enable inner tagging on egress, do not keep any tags */
1049 priv->r->vlan_port_keep_tag_set(port, 0, 1);
1050
1051 if (dsa_is_cpu_port(ds, port))
1052 return 0;
1053
1054 /* add port to switch mask of CPU_PORT */
1055 priv->r->traffic_enable(priv->cpu_port, port);
1056
1057 load_mcgroups(priv, port);
1058
1059 if (priv->is_lagmember[port]) {
1060 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1061 return 0;
1062 }
1063
1064 /* add all other ports in the same bridge to switch mask of port */
1065 v = priv->r->traffic_get(port);
1066 v |= priv->ports[port].pm;
1067 priv->r->traffic_set(port, v);
1068
1069 /* TODO: Figure out if this is necessary */
1070 if (priv->family_id == RTL9300_FAMILY_ID) {
1071 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_SABLK_CTRL);
1072 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_DABLK_CTRL);
1073 }
1074
1075 if (priv->ports[port].sds_num < 0)
1076 priv->ports[port].sds_num = rtl93xx_get_sds(phydev);
1077
1078 return 0;
1079 }
1080
1081 static void rtl83xx_port_disable(struct dsa_switch *ds, int port)
1082 {
1083 struct rtl838x_switch_priv *priv = ds->priv;
1084 u64 v;
1085
1086 pr_debug("%s %x: %d", __func__, (u32)priv, port);
1087 /* you can only disable user ports */
1088 if (!dsa_is_user_port(ds, port))
1089 return;
1090
1091 /* BUG: This does not work on RTL931X */
1092 /* remove port from switch mask of CPU_PORT */
1093 priv->r->traffic_disable(priv->cpu_port, port);
1094 store_mcgroups(priv, port);
1095
1096 /* remove all other ports in the same bridge from switch mask of port */
1097 v = priv->r->traffic_get(port);
1098 v &= ~priv->ports[port].pm;
1099 priv->r->traffic_set(port, v);
1100
1101 priv->ports[port].enable = false;
1102 }
1103
1104 static int rtl83xx_set_mac_eee(struct dsa_switch *ds, int port,
1105 struct ethtool_eee *e)
1106 {
1107 struct rtl838x_switch_priv *priv = ds->priv;
1108
1109 if (e->eee_enabled && !priv->eee_enabled) {
1110 pr_info("Globally enabling EEE\n");
1111 priv->r->init_eee(priv, true);
1112 }
1113
1114 priv->r->port_eee_set(priv, port, e->eee_enabled);
1115
1116 if (e->eee_enabled)
1117 pr_info("Enabled EEE for port %d\n", port);
1118 else
1119 pr_info("Disabled EEE for port %d\n", port);
1120
1121 return 0;
1122 }
1123
1124 static int rtl83xx_get_mac_eee(struct dsa_switch *ds, int port,
1125 struct ethtool_eee *e)
1126 {
1127 struct rtl838x_switch_priv *priv = ds->priv;
1128
1129 e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full;
1130
1131 priv->r->eee_port_ability(priv, e, port);
1132
1133 e->eee_enabled = priv->ports[port].eee_enabled;
1134
1135 e->eee_active = !!(e->advertised & e->lp_advertised);
1136
1137 return 0;
1138 }
1139
1140 static int rtl93xx_get_mac_eee(struct dsa_switch *ds, int port,
1141 struct ethtool_eee *e)
1142 {
1143 struct rtl838x_switch_priv *priv = ds->priv;
1144
1145 e->supported = SUPPORTED_100baseT_Full |
1146 SUPPORTED_1000baseT_Full |
1147 SUPPORTED_2500baseX_Full;
1148
1149 priv->r->eee_port_ability(priv, e, port);
1150
1151 e->eee_enabled = priv->ports[port].eee_enabled;
1152
1153 e->eee_active = !!(e->advertised & e->lp_advertised);
1154
1155 return 0;
1156 }
1157
1158 static int rtl83xx_set_ageing_time(struct dsa_switch *ds, unsigned int msec)
1159 {
1160 struct rtl838x_switch_priv *priv = ds->priv;
1161
1162 priv->r->set_ageing_time(msec);
1163
1164 return 0;
1165 }
1166
1167 static int rtl83xx_port_bridge_join(struct dsa_switch *ds, int port,
1168 struct net_device *bridge)
1169 {
1170 struct rtl838x_switch_priv *priv = ds->priv;
1171 u64 port_bitmap = BIT_ULL(priv->cpu_port), v;
1172
1173 pr_debug("%s %x: %d %llx", __func__, (u32)priv, port, port_bitmap);
1174
1175 if (priv->is_lagmember[port]) {
1176 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1177 return 0;
1178 }
1179
1180 mutex_lock(&priv->reg_mutex);
1181 for (int i = 0; i < ds->num_ports; i++) {
1182 /* Add this port to the port matrix of the other ports in the
1183 * same bridge. If the port is disabled, port matrix is kept
1184 * and not being setup until the port becomes enabled.
1185 */
1186 if (dsa_is_user_port(ds, i) && !priv->is_lagmember[i] && i != port) {
1187 if (dsa_to_port(ds, i)->bridge_dev != bridge)
1188 continue;
1189 if (priv->ports[i].enable)
1190 priv->r->traffic_enable(i, port);
1191
1192 priv->ports[i].pm |= BIT_ULL(port);
1193 port_bitmap |= BIT_ULL(i);
1194 }
1195 }
1196 load_mcgroups(priv, port);
1197
1198 /* Add all other ports to this port matrix. */
1199 if (priv->ports[port].enable) {
1200 priv->r->traffic_enable(priv->cpu_port, port);
1201 v = priv->r->traffic_get(port);
1202 v |= port_bitmap;
1203 priv->r->traffic_set(port, v);
1204 }
1205 priv->ports[port].pm |= port_bitmap;
1206 mutex_unlock(&priv->reg_mutex);
1207
1208 return 0;
1209 }
1210
1211 static void rtl83xx_port_bridge_leave(struct dsa_switch *ds, int port,
1212 struct net_device *bridge)
1213 {
1214 struct rtl838x_switch_priv *priv = ds->priv;
1215 u64 port_bitmap = 0, v;
1216
1217 pr_debug("%s %x: %d", __func__, (u32)priv, port);
1218 mutex_lock(&priv->reg_mutex);
1219 for (int i = 0; i < ds->num_ports; i++) {
1220 /* Remove this port from the port matrix of the other ports
1221 * in the same bridge. If the port is disabled, port matrix
1222 * is kept and not being setup until the port becomes enabled.
1223 * And the other port's port matrix cannot be broken when the
1224 * other port is still a VLAN-aware port.
1225 */
1226 if (dsa_is_user_port(ds, i) && i != port) {
1227 if (dsa_to_port(ds, i)->bridge_dev != bridge)
1228 continue;
1229 if (priv->ports[i].enable)
1230 priv->r->traffic_disable(i, port);
1231
1232 priv->ports[i].pm &= ~BIT_ULL(port);
1233 port_bitmap |= BIT_ULL(i);
1234 }
1235 }
1236 store_mcgroups(priv, port);
1237
1238 /* Remove all other ports from this port matrix. */
1239 if (priv->ports[port].enable) {
1240 v = priv->r->traffic_get(port);
1241 v &= ~port_bitmap;
1242 priv->r->traffic_set(port, v);
1243 }
1244 priv->ports[port].pm &= ~port_bitmap;
1245
1246 mutex_unlock(&priv->reg_mutex);
1247 }
1248
1249 void rtl83xx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1250 {
1251 u32 msti = 0;
1252 u32 port_state[4];
1253 int index, bit;
1254 int pos = port;
1255 struct rtl838x_switch_priv *priv = ds->priv;
1256 int n = priv->port_width << 1;
1257
1258 /* Ports above or equal CPU port can never be configured */
1259 if (port >= priv->cpu_port)
1260 return;
1261
1262 mutex_lock(&priv->reg_mutex);
1263
1264 /* For the RTL839x and following, the bits are left-aligned, 838x and 930x
1265 * have 64 bit fields, 839x and 931x have 128 bit fields
1266 */
1267 if (priv->family_id == RTL8390_FAMILY_ID)
1268 pos += 12;
1269 if (priv->family_id == RTL9300_FAMILY_ID)
1270 pos += 3;
1271 if (priv->family_id == RTL9310_FAMILY_ID)
1272 pos += 8;
1273
1274 index = n - (pos >> 4) - 1;
1275 bit = (pos << 1) % 32;
1276
1277 priv->r->stp_get(priv, msti, port_state);
1278
1279 pr_debug("Current state, port %d: %d\n", port, (port_state[index] >> bit) & 3);
1280 port_state[index] &= ~(3 << bit);
1281
1282 switch (state) {
1283 case BR_STATE_DISABLED: /* 0 */
1284 port_state[index] |= (0 << bit);
1285 break;
1286 case BR_STATE_BLOCKING: /* 4 */
1287 case BR_STATE_LISTENING: /* 1 */
1288 port_state[index] |= (1 << bit);
1289 break;
1290 case BR_STATE_LEARNING: /* 2 */
1291 port_state[index] |= (2 << bit);
1292 break;
1293 case BR_STATE_FORWARDING: /* 3 */
1294 port_state[index] |= (3 << bit);
1295 default:
1296 break;
1297 }
1298
1299 priv->r->stp_set(priv, msti, port_state);
1300
1301 mutex_unlock(&priv->reg_mutex);
1302 }
1303
1304 void rtl83xx_fast_age(struct dsa_switch *ds, int port)
1305 {
1306 struct rtl838x_switch_priv *priv = ds->priv;
1307 int s = priv->family_id == RTL8390_FAMILY_ID ? 2 : 0;
1308
1309 pr_debug("FAST AGE port %d\n", port);
1310 mutex_lock(&priv->reg_mutex);
1311 /* RTL838X_L2_TBL_FLUSH_CTRL register bits, 839x has 1 bit larger
1312 * port fields:
1313 * 0-4: Replacing port
1314 * 5-9: Flushed/replaced port
1315 * 10-21: FVID
1316 * 22: Entry types: 1: dynamic, 0: also static
1317 * 23: Match flush port
1318 * 24: Match FVID
1319 * 25: Flush (0) or replace (1) L2 entries
1320 * 26: Status of action (1: Start, 0: Done)
1321 */
1322 sw_w32(1 << (26 + s) | 1 << (23 + s) | port << (5 + (s / 2)), priv->r->l2_tbl_flush_ctrl);
1323
1324 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(26 + s));
1325
1326 mutex_unlock(&priv->reg_mutex);
1327 }
1328
1329 void rtl931x_fast_age(struct dsa_switch *ds, int port)
1330 {
1331 struct rtl838x_switch_priv *priv = ds->priv;
1332
1333 pr_info("%s port %d\n", __func__, port);
1334 mutex_lock(&priv->reg_mutex);
1335 sw_w32(port << 11, RTL931X_L2_TBL_FLUSH_CTRL + 4);
1336
1337 sw_w32(BIT(24) | BIT(28), RTL931X_L2_TBL_FLUSH_CTRL);
1338
1339 do { } while (sw_r32(RTL931X_L2_TBL_FLUSH_CTRL) & BIT (28));
1340
1341 mutex_unlock(&priv->reg_mutex);
1342 }
1343
1344 void rtl930x_fast_age(struct dsa_switch *ds, int port)
1345 {
1346 struct rtl838x_switch_priv *priv = ds->priv;
1347
1348 if (priv->family_id == RTL9310_FAMILY_ID)
1349 return rtl931x_fast_age(ds, port);
1350
1351 pr_debug("FAST AGE port %d\n", port);
1352 mutex_lock(&priv->reg_mutex);
1353 sw_w32(port << 11, RTL930X_L2_TBL_FLUSH_CTRL + 4);
1354
1355 sw_w32(BIT(26) | BIT(30), RTL930X_L2_TBL_FLUSH_CTRL);
1356
1357 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(30));
1358
1359 mutex_unlock(&priv->reg_mutex);
1360 }
1361
1362 static int rtl83xx_vlan_filtering(struct dsa_switch *ds, int port,
1363 bool vlan_filtering,
1364 struct netlink_ext_ack *extack)
1365 {
1366 struct rtl838x_switch_priv *priv = ds->priv;
1367
1368 pr_debug("%s: port %d\n", __func__, port);
1369 mutex_lock(&priv->reg_mutex);
1370
1371 if (vlan_filtering) {
1372 /* Enable ingress and egress filtering
1373 * The VLAN_PORT_IGR_FILTER register uses 2 bits for each port to define
1374 * the filter action:
1375 * 0: Always Forward
1376 * 1: Drop packet
1377 * 2: Trap packet to CPU port
1378 * The Egress filter used 1 bit per state (0: DISABLED, 1: ENABLED)
1379 */
1380 if (port != priv->cpu_port)
1381 priv->r->set_vlan_igr_filter(port, IGR_DROP);
1382
1383 priv->r->set_vlan_egr_filter(port, EGR_ENABLE);
1384 } else {
1385 /* Disable ingress and egress filtering */
1386 if (port != priv->cpu_port)
1387 priv->r->set_vlan_igr_filter(port, IGR_FORWARD);
1388
1389 priv->r->set_vlan_egr_filter(port, EGR_DISABLE);
1390 }
1391
1392 /* Do we need to do something to the CPU-Port, too? */
1393 mutex_unlock(&priv->reg_mutex);
1394
1395 return 0;
1396 }
1397
1398 static int rtl83xx_vlan_prepare(struct dsa_switch *ds, int port,
1399 const struct switchdev_obj_port_vlan *vlan)
1400 {
1401 struct rtl838x_vlan_info info;
1402 struct rtl838x_switch_priv *priv = ds->priv;
1403
1404 priv->r->vlan_tables_read(0, &info);
1405
1406 pr_debug("VLAN 0: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
1407 info.tagged_ports, info.untagged_ports, info.profile_id,
1408 info.hash_mc_fid, info.hash_uc_fid, info.fid);
1409
1410 priv->r->vlan_tables_read(1, &info);
1411 pr_debug("VLAN 1: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
1412 info.tagged_ports, info.untagged_ports, info.profile_id,
1413 info.hash_mc_fid, info.hash_uc_fid, info.fid);
1414 priv->r->vlan_set_untagged(1, info.untagged_ports);
1415 pr_debug("SET: Untagged ports, VLAN %d: %llx\n", 1, info.untagged_ports);
1416
1417 priv->r->vlan_set_tagged(1, &info);
1418 pr_debug("SET: Tagged ports, VLAN %d: %llx\n", 1, info.tagged_ports);
1419
1420 return 0;
1421 }
1422
1423 static int rtl83xx_vlan_add(struct dsa_switch *ds, int port,
1424 const struct switchdev_obj_port_vlan *vlan,
1425 struct netlink_ext_ack *extack)
1426 {
1427 struct rtl838x_vlan_info info;
1428 struct rtl838x_switch_priv *priv = ds->priv;
1429 int err;
1430
1431 pr_debug("%s port %d, vid %d, flags %x\n",
1432 __func__, port, vlan->vid, vlan->flags);
1433
1434 if (vlan->vid > 4095) {
1435 dev_err(priv->dev, "VLAN out of range: %d", vlan->vid);
1436 return -ENOTSUPP;
1437 }
1438
1439 err = rtl83xx_vlan_prepare(ds, port, vlan);
1440 if (err)
1441 return err;
1442
1443 mutex_lock(&priv->reg_mutex);
1444
1445 if (vlan->flags & BRIDGE_VLAN_INFO_PVID && vlan->vid) {
1446 /* Set both inner and outer PVID of the port */
1447 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_INNER, vlan->vid);
1448 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_OUTER, vlan->vid);
1449 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_INNER,
1450 PBVLAN_MODE_UNTAG_AND_PRITAG);
1451 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_OUTER,
1452 PBVLAN_MODE_UNTAG_AND_PRITAG);
1453
1454 priv->ports[port].pvid = vlan->vid;
1455 }
1456
1457 /* Get port memberships of this vlan */
1458 priv->r->vlan_tables_read(vlan->vid, &info);
1459
1460 /* new VLAN? */
1461 if (!info.tagged_ports) {
1462 info.fid = 0;
1463 info.hash_mc_fid = false;
1464 info.hash_uc_fid = false;
1465 info.profile_id = 0;
1466 }
1467
1468 /* sanitize untagged_ports - must be a subset */
1469 if (info.untagged_ports & ~info.tagged_ports)
1470 info.untagged_ports = 0;
1471
1472 info.tagged_ports |= BIT_ULL(port);
1473 if (vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED)
1474 info.untagged_ports |= BIT_ULL(port);
1475
1476 priv->r->vlan_set_untagged(vlan->vid, info.untagged_ports);
1477 pr_debug("Untagged ports, VLAN %d: %llx\n", vlan->vid, info.untagged_ports);
1478
1479 priv->r->vlan_set_tagged(vlan->vid, &info);
1480 pr_debug("Tagged ports, VLAN %d: %llx\n", vlan->vid, info.tagged_ports);
1481
1482 mutex_unlock(&priv->reg_mutex);
1483
1484 return 0;
1485 }
1486
1487 static int rtl83xx_vlan_del(struct dsa_switch *ds, int port,
1488 const struct switchdev_obj_port_vlan *vlan)
1489 {
1490 struct rtl838x_vlan_info info;
1491 struct rtl838x_switch_priv *priv = ds->priv;
1492 u16 pvid;
1493
1494 pr_debug("%s: port %d, vid %d, flags %x\n",
1495 __func__, port, vlan->vid, vlan->flags);
1496
1497 if (vlan->vid > 4095) {
1498 dev_err(priv->dev, "VLAN out of range: %d", vlan->vid);
1499 return -ENOTSUPP;
1500 }
1501
1502 mutex_lock(&priv->reg_mutex);
1503 pvid = priv->ports[port].pvid;
1504
1505 /* Reset to default if removing the current PVID */
1506 if (vlan->vid == pvid) {
1507 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_INNER, 0);
1508 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_OUTER, 0);
1509 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_INNER,
1510 PBVLAN_MODE_UNTAG_AND_PRITAG);
1511 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_OUTER,
1512 PBVLAN_MODE_UNTAG_AND_PRITAG);
1513 }
1514 /* Get port memberships of this vlan */
1515 priv->r->vlan_tables_read(vlan->vid, &info);
1516
1517 /* remove port from both tables */
1518 info.untagged_ports &= (~BIT_ULL(port));
1519 info.tagged_ports &= (~BIT_ULL(port));
1520
1521 priv->r->vlan_set_untagged(vlan->vid, info.untagged_ports);
1522 pr_debug("Untagged ports, VLAN %d: %llx\n", vlan->vid, info.untagged_ports);
1523
1524 priv->r->vlan_set_tagged(vlan->vid, &info);
1525 pr_debug("Tagged ports, VLAN %d: %llx\n", vlan->vid, info.tagged_ports);
1526
1527 mutex_unlock(&priv->reg_mutex);
1528
1529 return 0;
1530 }
1531
1532 static void rtl83xx_setup_l2_uc_entry(struct rtl838x_l2_entry *e, int port, int vid, u64 mac)
1533 {
1534 memset(e, 0, sizeof(*e));
1535
1536 e->type = L2_UNICAST;
1537 e->valid = true;
1538
1539 e->age = 3;
1540 e->is_static = true;
1541
1542 e->port = port;
1543
1544 e->rvid = e->vid = vid;
1545 e->is_ip_mc = e->is_ipv6_mc = false;
1546 u64_to_ether_addr(mac, e->mac);
1547 }
1548
1549 static void rtl83xx_setup_l2_mc_entry(struct rtl838x_l2_entry *e, int vid, u64 mac, int mc_group)
1550 {
1551 memset(e, 0, sizeof(*e));
1552
1553 e->type = L2_MULTICAST;
1554 e->valid = true;
1555
1556 e->mc_portmask_index = mc_group;
1557
1558 e->rvid = e->vid = vid;
1559 e->is_ip_mc = e->is_ipv6_mc = false;
1560 u64_to_ether_addr(mac, e->mac);
1561 }
1562
1563 /* Uses the seed to identify a hash bucket in the L2 using the derived hash key and then loops
1564 * over the entries in the bucket until either a matching entry is found or an empty slot
1565 * Returns the filled in rtl838x_l2_entry and the index in the bucket when an entry was found
1566 * when an empty slot was found and must exist is false, the index of the slot is returned
1567 * when no slots are available returns -1
1568 */
1569 static int rtl83xx_find_l2_hash_entry(struct rtl838x_switch_priv *priv, u64 seed,
1570 bool must_exist, struct rtl838x_l2_entry *e)
1571 {
1572 int idx = -1;
1573 u32 key = priv->r->l2_hash_key(priv, seed);
1574 u64 entry;
1575
1576 pr_debug("%s: using key %x, for seed %016llx\n", __func__, key, seed);
1577 /* Loop over all entries in the hash-bucket and over the second block on 93xx SoCs */
1578 for (int i = 0; i < priv->l2_bucket_size; i++) {
1579 entry = priv->r->read_l2_entry_using_hash(key, i, e);
1580 pr_debug("valid %d, mac %016llx\n", e->valid, ether_addr_to_u64(&e->mac[0]));
1581 if (must_exist && !e->valid)
1582 continue;
1583 if (!e->valid || ((entry & 0x0fffffffffffffffULL) == seed)) {
1584 idx = i > 3 ? ((key >> 14) & 0xffff) | i >> 1 : ((key << 2) | i) & 0xffff;
1585 break;
1586 }
1587 }
1588
1589 return idx;
1590 }
1591
1592 /* Uses the seed to identify an entry in the CAM by looping over all its entries
1593 * Returns the filled in rtl838x_l2_entry and the index in the CAM when an entry was found
1594 * when an empty slot was found the index of the slot is returned
1595 * when no slots are available returns -1
1596 */
1597 static int rtl83xx_find_l2_cam_entry(struct rtl838x_switch_priv *priv, u64 seed,
1598 bool must_exist, struct rtl838x_l2_entry *e)
1599 {
1600 int idx = -1;
1601 u64 entry;
1602
1603 for (int i = 0; i < 64; i++) {
1604 entry = priv->r->read_cam(i, e);
1605 if (!must_exist && !e->valid) {
1606 if (idx < 0) /* First empty entry? */
1607 idx = i;
1608 break;
1609 } else if ((entry & 0x0fffffffffffffffULL) == seed) {
1610 pr_debug("Found entry in CAM\n");
1611 idx = i;
1612 break;
1613 }
1614 }
1615
1616 return idx;
1617 }
1618
1619 static int rtl83xx_port_fdb_add(struct dsa_switch *ds, int port,
1620 const unsigned char *addr, u16 vid)
1621 {
1622 struct rtl838x_switch_priv *priv = ds->priv;
1623 u64 mac = ether_addr_to_u64(addr);
1624 struct rtl838x_l2_entry e;
1625 int err = 0, idx;
1626 u64 seed = priv->r->l2_hash_seed(mac, vid);
1627
1628 if (priv->is_lagmember[port]) {
1629 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1630 return 0;
1631 }
1632
1633 mutex_lock(&priv->reg_mutex);
1634
1635 idx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e);
1636
1637 /* Found an existing or empty entry */
1638 if (idx >= 0) {
1639 rtl83xx_setup_l2_uc_entry(&e, port, vid, mac);
1640 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1641 goto out;
1642 }
1643
1644 /* Hash buckets full, try CAM */
1645 rtl83xx_find_l2_cam_entry(priv, seed, false, &e);
1646
1647 if (idx >= 0) {
1648 rtl83xx_setup_l2_uc_entry(&e, port, vid, mac);
1649 priv->r->write_cam(idx, &e);
1650 goto out;
1651 }
1652
1653 err = -ENOTSUPP;
1654
1655 out:
1656 mutex_unlock(&priv->reg_mutex);
1657
1658 return err;
1659 }
1660
1661 static int rtl83xx_port_fdb_del(struct dsa_switch *ds, int port,
1662 const unsigned char *addr, u16 vid)
1663 {
1664 struct rtl838x_switch_priv *priv = ds->priv;
1665 u64 mac = ether_addr_to_u64(addr);
1666 struct rtl838x_l2_entry e;
1667 int err = 0, idx;
1668 u64 seed = priv->r->l2_hash_seed(mac, vid);
1669
1670 pr_debug("In %s, mac %llx, vid: %d\n", __func__, mac, vid);
1671 mutex_lock(&priv->reg_mutex);
1672
1673 idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e);
1674
1675 if (idx >= 0) {
1676 pr_debug("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3);
1677 e.valid = false;
1678 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1679 goto out;
1680 }
1681
1682 /* Check CAM for spillover from hash buckets */
1683 rtl83xx_find_l2_cam_entry(priv, seed, true, &e);
1684
1685 if (idx >= 0) {
1686 e.valid = false;
1687 priv->r->write_cam(idx, &e);
1688 goto out;
1689 }
1690 err = -ENOENT;
1691
1692 out:
1693 mutex_unlock(&priv->reg_mutex);
1694
1695 return err;
1696 }
1697
1698 static int rtl83xx_port_fdb_dump(struct dsa_switch *ds, int port,
1699 dsa_fdb_dump_cb_t *cb, void *data)
1700 {
1701 struct rtl838x_l2_entry e;
1702 struct rtl838x_switch_priv *priv = ds->priv;
1703
1704 mutex_lock(&priv->reg_mutex);
1705
1706 for (int i = 0; i < priv->fib_entries; i++) {
1707 priv->r->read_l2_entry_using_hash(i >> 2, i & 0x3, &e);
1708
1709 if (!e.valid)
1710 continue;
1711
1712 if (e.port == port || e.port == RTL930X_PORT_IGNORE)
1713 cb(e.mac, e.vid, e.is_static, data);
1714
1715 if (!((i + 1) % 64))
1716 cond_resched();
1717 }
1718
1719 for (int i = 0; i < 64; i++) {
1720 priv->r->read_cam(i, &e);
1721
1722 if (!e.valid)
1723 continue;
1724
1725 if (e.port == port)
1726 cb(e.mac, e.vid, e.is_static, data);
1727 }
1728
1729 mutex_unlock(&priv->reg_mutex);
1730
1731 return 0;
1732 }
1733
1734 static int rtl83xx_port_mdb_add(struct dsa_switch *ds, int port,
1735 const struct switchdev_obj_port_mdb *mdb)
1736 {
1737 struct rtl838x_switch_priv *priv = ds->priv;
1738 u64 mac = ether_addr_to_u64(mdb->addr);
1739 struct rtl838x_l2_entry e;
1740 int err = 0, idx;
1741 int vid = mdb->vid;
1742 u64 seed = priv->r->l2_hash_seed(mac, vid);
1743 int mc_group;
1744
1745 if (priv->id >= 0x9300)
1746 return -EOPNOTSUPP;
1747
1748 pr_debug("In %s port %d, mac %llx, vid: %d\n", __func__, port, mac, vid);
1749
1750 if (priv->is_lagmember[port]) {
1751 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1752 return -EINVAL;
1753 }
1754
1755 mutex_lock(&priv->reg_mutex);
1756
1757 idx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e);
1758
1759 /* Found an existing or empty entry */
1760 if (idx >= 0) {
1761 if (e.valid) {
1762 pr_debug("Found an existing entry %016llx, mc_group %d\n",
1763 ether_addr_to_u64(e.mac), e.mc_portmask_index);
1764 rtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port);
1765 } else {
1766 pr_debug("New entry for seed %016llx\n", seed);
1767 mc_group = rtl83xx_mc_group_alloc(priv, port);
1768 if (mc_group < 0) {
1769 err = -ENOTSUPP;
1770 goto out;
1771 }
1772 rtl83xx_setup_l2_mc_entry(&e, vid, mac, mc_group);
1773 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1774 }
1775 goto out;
1776 }
1777
1778 /* Hash buckets full, try CAM */
1779 rtl83xx_find_l2_cam_entry(priv, seed, false, &e);
1780
1781 if (idx >= 0) {
1782 if (e.valid) {
1783 pr_debug("Found existing CAM entry %016llx, mc_group %d\n",
1784 ether_addr_to_u64(e.mac), e.mc_portmask_index);
1785 rtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port);
1786 } else {
1787 pr_debug("New entry\n");
1788 mc_group = rtl83xx_mc_group_alloc(priv, port);
1789 if (mc_group < 0) {
1790 err = -ENOTSUPP;
1791 goto out;
1792 }
1793 rtl83xx_setup_l2_mc_entry(&e, vid, mac, mc_group);
1794 priv->r->write_cam(idx, &e);
1795 }
1796 goto out;
1797 }
1798
1799 err = -ENOTSUPP;
1800
1801 out:
1802 mutex_unlock(&priv->reg_mutex);
1803 if (err)
1804 dev_err(ds->dev, "failed to add MDB entry\n");
1805
1806 return err;
1807 }
1808
1809 int rtl83xx_port_mdb_del(struct dsa_switch *ds, int port,
1810 const struct switchdev_obj_port_mdb *mdb)
1811 {
1812 struct rtl838x_switch_priv *priv = ds->priv;
1813 u64 mac = ether_addr_to_u64(mdb->addr);
1814 struct rtl838x_l2_entry e;
1815 int err = 0, idx;
1816 int vid = mdb->vid;
1817 u64 seed = priv->r->l2_hash_seed(mac, vid);
1818 u64 portmask;
1819
1820 pr_debug("In %s, port %d, mac %llx, vid: %d\n", __func__, port, mac, vid);
1821
1822 if (priv->is_lagmember[port]) {
1823 pr_info("%s: %d is lag slave. ignore\n", __func__, port);
1824 return 0;
1825 }
1826
1827 mutex_lock(&priv->reg_mutex);
1828
1829 idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e);
1830
1831 if (idx >= 0) {
1832 pr_debug("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3);
1833 portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port);
1834 if (!portmask) {
1835 e.valid = false;
1836 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1837 }
1838 goto out;
1839 }
1840
1841 /* Check CAM for spillover from hash buckets */
1842 rtl83xx_find_l2_cam_entry(priv, seed, true, &e);
1843
1844 if (idx >= 0) {
1845 portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port);
1846 if (!portmask) {
1847 e.valid = false;
1848 priv->r->write_cam(idx, &e);
1849 }
1850 goto out;
1851 }
1852 /* TODO: Re-enable with a newer kernel: err = -ENOENT; */
1853
1854 out:
1855 mutex_unlock(&priv->reg_mutex);
1856
1857 return err;
1858 }
1859
1860 static int rtl83xx_port_mirror_add(struct dsa_switch *ds, int port,
1861 struct dsa_mall_mirror_tc_entry *mirror,
1862 bool ingress)
1863 {
1864 /* We support 4 mirror groups, one destination port per group */
1865 int group;
1866 struct rtl838x_switch_priv *priv = ds->priv;
1867 int ctrl_reg, dpm_reg, spm_reg;
1868
1869 pr_debug("In %s\n", __func__);
1870
1871 for (group = 0; group < 4; group++) {
1872 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1873 break;
1874 }
1875 if (group >= 4) {
1876 for (group = 0; group < 4; group++) {
1877 if (priv->mirror_group_ports[group] < 0)
1878 break;
1879 }
1880 }
1881
1882 if (group >= 4)
1883 return -ENOSPC;
1884
1885 ctrl_reg = priv->r->mir_ctrl + group * 4;
1886 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1887 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1888
1889 pr_debug("Using group %d\n", group);
1890 mutex_lock(&priv->reg_mutex);
1891
1892 if (priv->family_id == RTL8380_FAMILY_ID) {
1893 /* Enable mirroring to port across VLANs (bit 11) */
1894 sw_w32(1 << 11 | (mirror->to_local_port << 4) | 1, ctrl_reg);
1895 } else {
1896 /* Enable mirroring to destination port */
1897 sw_w32((mirror->to_local_port << 4) | 1, ctrl_reg);
1898 }
1899
1900 if (ingress && (priv->r->get_port_reg_be(spm_reg) & (1ULL << port))) {
1901 mutex_unlock(&priv->reg_mutex);
1902 return -EEXIST;
1903 }
1904 if ((!ingress) && (priv->r->get_port_reg_be(dpm_reg) & (1ULL << port))) {
1905 mutex_unlock(&priv->reg_mutex);
1906 return -EEXIST;
1907 }
1908
1909 if (ingress)
1910 priv->r->mask_port_reg_be(0, 1ULL << port, spm_reg);
1911 else
1912 priv->r->mask_port_reg_be(0, 1ULL << port, dpm_reg);
1913
1914 priv->mirror_group_ports[group] = mirror->to_local_port;
1915 mutex_unlock(&priv->reg_mutex);
1916
1917 return 0;
1918 }
1919
1920 static void rtl83xx_port_mirror_del(struct dsa_switch *ds, int port,
1921 struct dsa_mall_mirror_tc_entry *mirror)
1922 {
1923 int group = 0;
1924 struct rtl838x_switch_priv *priv = ds->priv;
1925 int ctrl_reg, dpm_reg, spm_reg;
1926
1927 pr_debug("In %s\n", __func__);
1928 for (group = 0; group < 4; group++) {
1929 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1930 break;
1931 }
1932 if (group >= 4)
1933 return;
1934
1935 ctrl_reg = priv->r->mir_ctrl + group * 4;
1936 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1937 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1938
1939 mutex_lock(&priv->reg_mutex);
1940 if (mirror->ingress) {
1941 /* Ingress, clear source port matrix */
1942 priv->r->mask_port_reg_be(1ULL << port, 0, spm_reg);
1943 } else {
1944 /* Egress, clear destination port matrix */
1945 priv->r->mask_port_reg_be(1ULL << port, 0, dpm_reg);
1946 }
1947
1948 if (!(sw_r32(spm_reg) || sw_r32(dpm_reg))) {
1949 priv->mirror_group_ports[group] = -1;
1950 sw_w32(0, ctrl_reg);
1951 }
1952
1953 mutex_unlock(&priv->reg_mutex);
1954 }
1955
1956 static int rtl83xx_port_pre_bridge_flags(struct dsa_switch *ds, int port, struct switchdev_brport_flags flags, struct netlink_ext_ack *extack)
1957 {
1958 struct rtl838x_switch_priv *priv = ds->priv;
1959 unsigned long features = 0;
1960 pr_debug("%s: %d %lX\n", __func__, port, flags.val);
1961 if (priv->r->enable_learning)
1962 features |= BR_LEARNING;
1963 if (priv->r->enable_flood)
1964 features |= BR_FLOOD;
1965 if (priv->r->enable_mcast_flood)
1966 features |= BR_MCAST_FLOOD;
1967 if (priv->r->enable_bcast_flood)
1968 features |= BR_BCAST_FLOOD;
1969 if (flags.mask & ~(features))
1970 return -EINVAL;
1971
1972 return 0;
1973 }
1974
1975 static int rtl83xx_port_bridge_flags(struct dsa_switch *ds, int port, struct switchdev_brport_flags flags, struct netlink_ext_ack *extack)
1976 {
1977 struct rtl838x_switch_priv *priv = ds->priv;
1978
1979 pr_debug("%s: %d %lX\n", __func__, port, flags.val);
1980 if (priv->r->enable_learning && (flags.mask & BR_LEARNING))
1981 priv->r->enable_learning(port, !!(flags.val & BR_LEARNING));
1982
1983 if (priv->r->enable_flood && (flags.mask & BR_FLOOD))
1984 priv->r->enable_flood(port, !!(flags.val & BR_FLOOD));
1985
1986 if (priv->r->enable_mcast_flood && (flags.mask & BR_MCAST_FLOOD))
1987 priv->r->enable_mcast_flood(port, !!(flags.val & BR_MCAST_FLOOD));
1988
1989 if (priv->r->enable_bcast_flood && (flags.mask & BR_BCAST_FLOOD))
1990 priv->r->enable_bcast_flood(port, !!(flags.val & BR_BCAST_FLOOD));
1991
1992 return 0;
1993 }
1994
1995 static bool rtl83xx_lag_can_offload(struct dsa_switch *ds,
1996 struct net_device *lag,
1997 struct netdev_lag_upper_info *info)
1998 {
1999 int id;
2000
2001 id = dsa_lag_id(ds->dst, lag);
2002 if (id < 0 || id >= ds->num_lag_ids)
2003 return false;
2004
2005 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
2006 return false;
2007 }
2008 if (info->hash_type != NETDEV_LAG_HASH_L2 && info->hash_type != NETDEV_LAG_HASH_L23)
2009 return false;
2010
2011 return true;
2012 }
2013
2014 static int rtl83xx_port_lag_change(struct dsa_switch *ds, int port)
2015 {
2016 struct rtl838x_switch_priv *priv = ds->priv;
2017
2018 pr_debug("%s: %d\n", __func__, port);
2019 /* Nothing to be done... */
2020
2021 return 0;
2022 }
2023
2024 static int rtl83xx_port_lag_join(struct dsa_switch *ds, int port,
2025 struct net_device *lag,
2026 struct netdev_lag_upper_info *info)
2027 {
2028 struct rtl838x_switch_priv *priv = ds->priv;
2029 int i, err = 0;
2030
2031 if (!rtl83xx_lag_can_offload(ds, lag, info))
2032 return -EOPNOTSUPP;
2033
2034 mutex_lock(&priv->reg_mutex);
2035
2036 for (i = 0; i < priv->n_lags; i++) {
2037 if ((!priv->lag_devs[i]) || (priv->lag_devs[i] == lag))
2038 break;
2039 }
2040 if (port >= priv->cpu_port) {
2041 err = -EINVAL;
2042 goto out;
2043 }
2044 pr_info("port_lag_join: group %d, port %d\n",i, port);
2045 if (!priv->lag_devs[i])
2046 priv->lag_devs[i] = lag;
2047
2048 if (priv->lag_primary[i] == -1) {
2049 priv->lag_primary[i] = port;
2050 } else
2051 priv->is_lagmember[port] = 1;
2052
2053 priv->lagmembers |= (1ULL << port);
2054
2055 pr_debug("lag_members = %llX\n", priv->lagmembers);
2056 err = rtl83xx_lag_add(priv->ds, i, port, info);
2057 if (err) {
2058 err = -EINVAL;
2059 goto out;
2060 }
2061
2062 out:
2063 mutex_unlock(&priv->reg_mutex);
2064
2065 return err;
2066 }
2067
2068 static int rtl83xx_port_lag_leave(struct dsa_switch *ds, int port,
2069 struct net_device *lag)
2070 {
2071 int i, group = -1, err;
2072 struct rtl838x_switch_priv *priv = ds->priv;
2073
2074 mutex_lock(&priv->reg_mutex);
2075 for (i = 0; i < priv->n_lags; i++) {
2076 if (priv->lags_port_members[i] & BIT_ULL(port)) {
2077 group = i;
2078 break;
2079 }
2080 }
2081
2082 if (group == -1) {
2083 pr_info("port_lag_leave: port %d is not a member\n", port);
2084 err = -EINVAL;
2085 goto out;
2086 }
2087
2088 if (port >= priv->cpu_port) {
2089 err = -EINVAL;
2090 goto out;
2091 }
2092 pr_info("port_lag_del: group %d, port %d\n",group, port);
2093 priv->lagmembers &=~ (1ULL << port);
2094 priv->lag_primary[i] = -1;
2095 priv->is_lagmember[port] = 0;
2096 pr_debug("lag_members = %llX\n", priv->lagmembers);
2097 err = rtl83xx_lag_del(priv->ds, group, port);
2098 if (err) {
2099 err = -EINVAL;
2100 goto out;
2101 }
2102 if (!priv->lags_port_members[i])
2103 priv->lag_devs[i] = NULL;
2104
2105 out:
2106 mutex_unlock(&priv->reg_mutex);
2107 return 0;
2108 }
2109
2110 int dsa_phy_read(struct dsa_switch *ds, int phy_addr, int phy_reg)
2111 {
2112 u32 val;
2113 u32 offset = 0;
2114 struct rtl838x_switch_priv *priv = ds->priv;
2115
2116 if ((phy_addr >= 24) &&
2117 (phy_addr <= 27) &&
2118 (priv->ports[24].phy == PHY_RTL838X_SDS)) {
2119 if (phy_addr == 26)
2120 offset = 0x100;
2121 val = sw_r32(RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2)) & 0xffff;
2122 return val;
2123 }
2124
2125 read_phy(phy_addr, 0, phy_reg, &val);
2126 return val;
2127 }
2128
2129 int dsa_phy_write(struct dsa_switch *ds, int phy_addr, int phy_reg, u16 val)
2130 {
2131 u32 offset = 0;
2132 struct rtl838x_switch_priv *priv = ds->priv;
2133
2134 if ((phy_addr >= 24) &&
2135 (phy_addr <= 27) &&
2136 (priv->ports[24].phy == PHY_RTL838X_SDS)) {
2137 if (phy_addr == 26)
2138 offset = 0x100;
2139 sw_w32(val, RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2));
2140 return 0;
2141 }
2142 return write_phy(phy_addr, 0, phy_reg, val);
2143 }
2144
2145 const struct dsa_switch_ops rtl83xx_switch_ops = {
2146 .get_tag_protocol = rtl83xx_get_tag_protocol,
2147 .setup = rtl83xx_setup,
2148
2149 .phy_read = dsa_phy_read,
2150 .phy_write = dsa_phy_write,
2151
2152 .phylink_validate = rtl83xx_phylink_validate,
2153 .phylink_mac_link_state = rtl83xx_phylink_mac_link_state,
2154 .phylink_mac_config = rtl83xx_phylink_mac_config,
2155 .phylink_mac_link_down = rtl83xx_phylink_mac_link_down,
2156 .phylink_mac_link_up = rtl83xx_phylink_mac_link_up,
2157
2158 .get_strings = rtl83xx_get_strings,
2159 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
2160 .get_sset_count = rtl83xx_get_sset_count,
2161
2162 .port_enable = rtl83xx_port_enable,
2163 .port_disable = rtl83xx_port_disable,
2164
2165 .get_mac_eee = rtl83xx_get_mac_eee,
2166 .set_mac_eee = rtl83xx_set_mac_eee,
2167
2168 .set_ageing_time = rtl83xx_set_ageing_time,
2169 .port_bridge_join = rtl83xx_port_bridge_join,
2170 .port_bridge_leave = rtl83xx_port_bridge_leave,
2171 .port_stp_state_set = rtl83xx_port_stp_state_set,
2172 .port_fast_age = rtl83xx_fast_age,
2173
2174 .port_vlan_filtering = rtl83xx_vlan_filtering,
2175 .port_vlan_add = rtl83xx_vlan_add,
2176 .port_vlan_del = rtl83xx_vlan_del,
2177
2178 .port_fdb_add = rtl83xx_port_fdb_add,
2179 .port_fdb_del = rtl83xx_port_fdb_del,
2180 .port_fdb_dump = rtl83xx_port_fdb_dump,
2181
2182 .port_mdb_add = rtl83xx_port_mdb_add,
2183 .port_mdb_del = rtl83xx_port_mdb_del,
2184
2185 .port_mirror_add = rtl83xx_port_mirror_add,
2186 .port_mirror_del = rtl83xx_port_mirror_del,
2187
2188 .port_lag_change = rtl83xx_port_lag_change,
2189 .port_lag_join = rtl83xx_port_lag_join,
2190 .port_lag_leave = rtl83xx_port_lag_leave,
2191
2192 .port_pre_bridge_flags = rtl83xx_port_pre_bridge_flags,
2193 .port_bridge_flags = rtl83xx_port_bridge_flags,
2194 };
2195
2196 const struct dsa_switch_ops rtl930x_switch_ops = {
2197 .get_tag_protocol = rtl83xx_get_tag_protocol,
2198 .setup = rtl93xx_setup,
2199
2200 .phy_read = dsa_phy_read,
2201 .phy_write = dsa_phy_write,
2202
2203 .phylink_validate = rtl93xx_phylink_validate,
2204 .phylink_mac_link_state = rtl93xx_phylink_mac_link_state,
2205 .phylink_mac_config = rtl93xx_phylink_mac_config,
2206 .phylink_mac_link_down = rtl93xx_phylink_mac_link_down,
2207 .phylink_mac_link_up = rtl93xx_phylink_mac_link_up,
2208
2209 .get_strings = rtl83xx_get_strings,
2210 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
2211 .get_sset_count = rtl83xx_get_sset_count,
2212
2213 .port_enable = rtl83xx_port_enable,
2214 .port_disable = rtl83xx_port_disable,
2215
2216 .get_mac_eee = rtl93xx_get_mac_eee,
2217 .set_mac_eee = rtl83xx_set_mac_eee,
2218
2219 .set_ageing_time = rtl83xx_set_ageing_time,
2220 .port_bridge_join = rtl83xx_port_bridge_join,
2221 .port_bridge_leave = rtl83xx_port_bridge_leave,
2222 .port_stp_state_set = rtl83xx_port_stp_state_set,
2223 .port_fast_age = rtl930x_fast_age,
2224
2225 .port_vlan_filtering = rtl83xx_vlan_filtering,
2226 .port_vlan_add = rtl83xx_vlan_add,
2227 .port_vlan_del = rtl83xx_vlan_del,
2228
2229 .port_fdb_add = rtl83xx_port_fdb_add,
2230 .port_fdb_del = rtl83xx_port_fdb_del,
2231 .port_fdb_dump = rtl83xx_port_fdb_dump,
2232
2233 .port_mdb_add = rtl83xx_port_mdb_add,
2234 .port_mdb_del = rtl83xx_port_mdb_del,
2235
2236 .port_lag_change = rtl83xx_port_lag_change,
2237 .port_lag_join = rtl83xx_port_lag_join,
2238 .port_lag_leave = rtl83xx_port_lag_leave,
2239
2240 .port_pre_bridge_flags = rtl83xx_port_pre_bridge_flags,
2241 .port_bridge_flags = rtl83xx_port_bridge_flags,
2242 };
Staging tree of Jo-Philipp Wich