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realtek: initialize port masks to match the default state
[openwrt/staging/jow.git] / target / linux / realtek / files-5.15 / drivers / net / dsa / rtl83xx / dsa.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <net/dsa.h>
4 #include <linux/if_bridge.h>
5 #include <asm/mach-rtl838x/mach-rtl83xx.h>
6
7 #include "rtl83xx.h"
8
9 extern struct rtl83xx_soc_info soc_info;
10
11 static void rtl83xx_init_stats(struct rtl838x_switch_priv *priv)
12 {
13 mutex_lock(&priv->reg_mutex);
14
15 /* Enable statistics module: all counters plus debug.
16 * On RTL839x all counters are enabled by default
17 */
18 if (priv->family_id == RTL8380_FAMILY_ID)
19 sw_w32_mask(0, 3, RTL838X_STAT_CTRL);
20
21 /* Reset statistics counters */
22 sw_w32_mask(0, 1, priv->r->stat_rst);
23
24 mutex_unlock(&priv->reg_mutex);
25 }
26
27 static void rtl83xx_enable_phy_polling(struct rtl838x_switch_priv *priv)
28 {
29 u64 v = 0;
30
31 msleep(1000);
32 /* Enable all ports with a PHY, including the SFP-ports */
33 for (int i = 0; i < priv->cpu_port; i++) {
34 if (priv->ports[i].phy)
35 v |= BIT_ULL(i);
36 }
37
38 pr_info("%s: %16llx\n", __func__, v);
39 priv->r->set_port_reg_le(v, priv->r->smi_poll_ctrl);
40
41 /* PHY update complete, there is no global PHY polling enable bit on the 9300 */
42 if (priv->family_id == RTL8390_FAMILY_ID)
43 sw_w32_mask(0, BIT(7), RTL839X_SMI_GLB_CTRL);
44 else if(priv->family_id == RTL9300_FAMILY_ID)
45 sw_w32_mask(0, 0x8000, RTL838X_SMI_GLB_CTRL);
46 }
47
48 const struct rtl83xx_mib_desc rtl83xx_mib[] = {
49 MIB_DESC(2, 0xf8, "ifInOctets"),
50 MIB_DESC(2, 0xf0, "ifOutOctets"),
51 MIB_DESC(1, 0xec, "dot1dTpPortInDiscards"),
52 MIB_DESC(1, 0xe8, "ifInUcastPkts"),
53 MIB_DESC(1, 0xe4, "ifInMulticastPkts"),
54 MIB_DESC(1, 0xe0, "ifInBroadcastPkts"),
55 MIB_DESC(1, 0xdc, "ifOutUcastPkts"),
56 MIB_DESC(1, 0xd8, "ifOutMulticastPkts"),
57 MIB_DESC(1, 0xd4, "ifOutBroadcastPkts"),
58 MIB_DESC(1, 0xd0, "ifOutDiscards"),
59 MIB_DESC(1, 0xcc, ".3SingleCollisionFrames"),
60 MIB_DESC(1, 0xc8, ".3MultipleCollisionFrames"),
61 MIB_DESC(1, 0xc4, ".3DeferredTransmissions"),
62 MIB_DESC(1, 0xc0, ".3LateCollisions"),
63 MIB_DESC(1, 0xbc, ".3ExcessiveCollisions"),
64 MIB_DESC(1, 0xb8, ".3SymbolErrors"),
65 MIB_DESC(1, 0xb4, ".3ControlInUnknownOpcodes"),
66 MIB_DESC(1, 0xb0, ".3InPauseFrames"),
67 MIB_DESC(1, 0xac, ".3OutPauseFrames"),
68 MIB_DESC(1, 0xa8, "DropEvents"),
69 MIB_DESC(1, 0xa4, "tx_BroadcastPkts"),
70 MIB_DESC(1, 0xa0, "tx_MulticastPkts"),
71 MIB_DESC(1, 0x9c, "CRCAlignErrors"),
72 MIB_DESC(1, 0x98, "tx_UndersizePkts"),
73 MIB_DESC(1, 0x94, "rx_UndersizePkts"),
74 MIB_DESC(1, 0x90, "rx_UndersizedropPkts"),
75 MIB_DESC(1, 0x8c, "tx_OversizePkts"),
76 MIB_DESC(1, 0x88, "rx_OversizePkts"),
77 MIB_DESC(1, 0x84, "Fragments"),
78 MIB_DESC(1, 0x80, "Jabbers"),
79 MIB_DESC(1, 0x7c, "Collisions"),
80 MIB_DESC(1, 0x78, "tx_Pkts64Octets"),
81 MIB_DESC(1, 0x74, "rx_Pkts64Octets"),
82 MIB_DESC(1, 0x70, "tx_Pkts65to127Octets"),
83 MIB_DESC(1, 0x6c, "rx_Pkts65to127Octets"),
84 MIB_DESC(1, 0x68, "tx_Pkts128to255Octets"),
85 MIB_DESC(1, 0x64, "rx_Pkts128to255Octets"),
86 MIB_DESC(1, 0x60, "tx_Pkts256to511Octets"),
87 MIB_DESC(1, 0x5c, "rx_Pkts256to511Octets"),
88 MIB_DESC(1, 0x58, "tx_Pkts512to1023Octets"),
89 MIB_DESC(1, 0x54, "rx_Pkts512to1023Octets"),
90 MIB_DESC(1, 0x50, "tx_Pkts1024to1518Octets"),
91 MIB_DESC(1, 0x4c, "rx_StatsPkts1024to1518Octets"),
92 MIB_DESC(1, 0x48, "tx_Pkts1519toMaxOctets"),
93 MIB_DESC(1, 0x44, "rx_Pkts1519toMaxOctets"),
94 MIB_DESC(1, 0x40, "rxMacDiscards")
95 };
96
97
98 /* DSA callbacks */
99
100
101 static enum dsa_tag_protocol rtl83xx_get_tag_protocol(struct dsa_switch *ds,
102 int port,
103 enum dsa_tag_protocol mprot)
104 {
105 /* The switch does not tag the frames, instead internally the header
106 * structure for each packet is tagged accordingly.
107 */
108 return DSA_TAG_PROTO_TRAILER;
109 }
110
111 /* Initialize all VLANS */
112 static void rtl83xx_vlan_setup(struct rtl838x_switch_priv *priv)
113 {
114 struct rtl838x_vlan_info info;
115
116 pr_info("In %s\n", __func__);
117
118 priv->r->vlan_profile_setup(0);
119 priv->r->vlan_profile_setup(1);
120 pr_info("UNKNOWN_MC_PMASK: %016llx\n", priv->r->read_mcast_pmask(UNKNOWN_MC_PMASK));
121 priv->r->vlan_profile_dump(0);
122
123 info.fid = 0; /* Default Forwarding ID / MSTI */
124 info.hash_uc_fid = false; /* Do not build the L2 lookup hash with FID, but VID */
125 info.hash_mc_fid = false; /* Do the same for Multicast packets */
126 info.profile_id = 0; /* Use default Vlan Profile 0 */
127 info.tagged_ports = 0; /* Initially no port members */
128 if (priv->family_id == RTL9310_FAMILY_ID) {
129 info.if_id = 0;
130 info.multicast_grp_mask = 0;
131 info.l2_tunnel_list_id = -1;
132 }
133
134 /* Initialize all vlans 0-4095 */
135 for (int i = 0; i < MAX_VLANS; i ++)
136 priv->r->vlan_set_tagged(i, &info);
137
138 /* reset PVIDs; defaults to 1 on reset */
139 for (int i = 0; i <= priv->ds->num_ports; i++) {
140 priv->r->vlan_port_pvid_set(i, PBVLAN_TYPE_INNER, 0);
141 priv->r->vlan_port_pvid_set(i, PBVLAN_TYPE_OUTER, 0);
142 priv->r->vlan_port_pvidmode_set(i, PBVLAN_TYPE_INNER, PBVLAN_MODE_UNTAG_AND_PRITAG);
143 priv->r->vlan_port_pvidmode_set(i, PBVLAN_TYPE_OUTER, PBVLAN_MODE_UNTAG_AND_PRITAG);
144 }
145
146 /* Set forwarding action based on inner VLAN tag */
147 for (int i = 0; i < priv->cpu_port; i++)
148 priv->r->vlan_fwd_on_inner(i, true);
149 }
150
151 static void rtl83xx_setup_bpdu_traps(struct rtl838x_switch_priv *priv)
152 {
153 for (int i = 0; i < priv->cpu_port; i++)
154 priv->r->set_receive_management_action(i, BPDU, COPY2CPU);
155 }
156
157 static void rtl83xx_port_set_salrn(struct rtl838x_switch_priv *priv,
158 int port, bool enable)
159 {
160 int shift = SALRN_PORT_SHIFT(port);
161 int val = enable ? SALRN_MODE_HARDWARE : SALRN_MODE_DISABLED;
162
163 sw_w32_mask(SALRN_MODE_MASK << shift, val << shift,
164 priv->r->l2_port_new_salrn(port));
165 }
166
167 static int rtl83xx_setup(struct dsa_switch *ds)
168 {
169 struct rtl838x_switch_priv *priv = ds->priv;
170
171 pr_debug("%s called\n", __func__);
172
173 /* Disable MAC polling the PHY so that we can start configuration */
174 priv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl);
175
176 for (int i = 0; i < ds->num_ports; i++)
177 priv->ports[i].enable = false;
178 priv->ports[priv->cpu_port].enable = true;
179
180 /* Configure ports so they are disabled by default, but once enabled
181 * they will work in isolated mode (only traffic between port and CPU).
182 */
183 for (int i = 0; i < priv->cpu_port; i++) {
184 if (priv->ports[i].phy) {
185 priv->ports[i].pm = BIT_ULL(priv->cpu_port);
186 priv->r->traffic_set(i, BIT_ULL(i));
187 }
188 }
189 priv->r->traffic_set(priv->cpu_port, BIT_ULL(priv->cpu_port));
190
191 if (priv->family_id == RTL8380_FAMILY_ID)
192 rtl838x_print_matrix();
193 else
194 rtl839x_print_matrix();
195
196 rtl83xx_init_stats(priv);
197
198 rtl83xx_vlan_setup(priv);
199
200 rtl83xx_setup_bpdu_traps(priv);
201
202 ds->configure_vlan_while_not_filtering = true;
203
204 priv->r->l2_learning_setup();
205
206 rtl83xx_port_set_salrn(priv, priv->cpu_port, false);
207 ds->assisted_learning_on_cpu_port = true;
208
209 /* Make sure all frames sent to the switch's MAC are trapped to the CPU-port
210 * 0: FWD, 1: DROP, 2: TRAP2CPU
211 */
212 if (priv->family_id == RTL8380_FAMILY_ID)
213 sw_w32(0x2, RTL838X_SPCL_TRAP_SWITCH_MAC_CTRL);
214 else
215 sw_w32(0x2, RTL839X_SPCL_TRAP_SWITCH_MAC_CTRL);
216
217 /* Enable MAC Polling PHY again */
218 rtl83xx_enable_phy_polling(priv);
219 pr_debug("Please wait until PHY is settled\n");
220 msleep(1000);
221 priv->r->pie_init(priv);
222
223 return 0;
224 }
225
226 static int rtl93xx_setup(struct dsa_switch *ds)
227 {
228 struct rtl838x_switch_priv *priv = ds->priv;
229
230 pr_info("%s called\n", __func__);
231
232 /* Disable MAC polling the PHY so that we can start configuration */
233 if (priv->family_id == RTL9300_FAMILY_ID)
234 sw_w32(0, RTL930X_SMI_POLL_CTRL);
235
236 if (priv->family_id == RTL9310_FAMILY_ID) {
237 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL);
238 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL + 4);
239 }
240
241 /* Disable all ports except CPU port */
242 for (int i = 0; i < ds->num_ports; i++)
243 priv->ports[i].enable = false;
244 priv->ports[priv->cpu_port].enable = true;
245
246 /* Configure ports so they are disabled by default, but once enabled
247 * they will work in isolated mode (only traffic between port and CPU).
248 */
249 for (int i = 0; i < priv->cpu_port; i++) {
250 if (priv->ports[i].phy) {
251 priv->ports[i].pm = BIT_ULL(priv->cpu_port);
252 priv->r->traffic_set(i, BIT_ULL(i));
253 }
254 }
255 priv->r->traffic_set(priv->cpu_port, BIT_ULL(priv->cpu_port));
256
257 rtl930x_print_matrix();
258
259 /* TODO: Initialize statistics */
260
261 rtl83xx_vlan_setup(priv);
262
263 ds->configure_vlan_while_not_filtering = true;
264
265 priv->r->l2_learning_setup();
266
267 rtl83xx_port_set_salrn(priv, priv->cpu_port, false);
268 ds->assisted_learning_on_cpu_port = true;
269
270 rtl83xx_enable_phy_polling(priv);
271
272 priv->r->pie_init(priv);
273
274 priv->r->led_init(priv);
275
276 return 0;
277 }
278
279 static int rtl93xx_get_sds(struct phy_device *phydev)
280 {
281 struct device *dev = &phydev->mdio.dev;
282 struct device_node *dn;
283 u32 sds_num;
284
285 if (!dev)
286 return -1;
287 if (dev->of_node) {
288 dn = dev->of_node;
289 if (of_property_read_u32(dn, "sds", &sds_num))
290 sds_num = -1;
291 } else {
292 dev_err(dev, "No DT node.\n");
293 return -1;
294 }
295
296 return sds_num;
297 }
298
299 static void rtl83xx_phylink_validate(struct dsa_switch *ds, int port,
300 unsigned long *supported,
301 struct phylink_link_state *state)
302 {
303 struct rtl838x_switch_priv *priv = ds->priv;
304 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
305
306 pr_debug("In %s port %d, state is %d", __func__, port, state->interface);
307
308 if (!phy_interface_mode_is_rgmii(state->interface) &&
309 state->interface != PHY_INTERFACE_MODE_NA &&
310 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
311 state->interface != PHY_INTERFACE_MODE_MII &&
312 state->interface != PHY_INTERFACE_MODE_REVMII &&
313 state->interface != PHY_INTERFACE_MODE_GMII &&
314 state->interface != PHY_INTERFACE_MODE_QSGMII &&
315 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
316 state->interface != PHY_INTERFACE_MODE_SGMII) {
317 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
318 dev_err(ds->dev,
319 "Unsupported interface: %d for port %d\n",
320 state->interface, port);
321 return;
322 }
323
324 /* Allow all the expected bits */
325 phylink_set(mask, Autoneg);
326 phylink_set_port_modes(mask);
327 phylink_set(mask, Pause);
328 phylink_set(mask, Asym_Pause);
329
330 /* With the exclusion of MII and Reverse MII, we support Gigabit,
331 * including Half duplex
332 */
333 if (state->interface != PHY_INTERFACE_MODE_MII &&
334 state->interface != PHY_INTERFACE_MODE_REVMII) {
335 phylink_set(mask, 1000baseT_Full);
336 phylink_set(mask, 1000baseT_Half);
337 }
338
339 /* On both the 8380 and 8382, ports 24-27 are SFP ports */
340 if (port >= 24 && port <= 27 && priv->family_id == RTL8380_FAMILY_ID)
341 phylink_set(mask, 1000baseX_Full);
342
343 /* On the RTL839x family of SoCs, ports 48 to 51 are SFP ports */
344 if (port >= 48 && port <= 51 && priv->family_id == RTL8390_FAMILY_ID)
345 phylink_set(mask, 1000baseX_Full);
346
347 phylink_set(mask, 10baseT_Half);
348 phylink_set(mask, 10baseT_Full);
349 phylink_set(mask, 100baseT_Half);
350 phylink_set(mask, 100baseT_Full);
351
352 bitmap_and(supported, supported, mask,
353 __ETHTOOL_LINK_MODE_MASK_NBITS);
354 bitmap_and(state->advertising, state->advertising, mask,
355 __ETHTOOL_LINK_MODE_MASK_NBITS);
356 }
357
358 static void rtl93xx_phylink_validate(struct dsa_switch *ds, int port,
359 unsigned long *supported,
360 struct phylink_link_state *state)
361 {
362 struct rtl838x_switch_priv *priv = ds->priv;
363 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
364
365 pr_debug("In %s port %d, state is %d (%s)", __func__, port, state->interface,
366 phy_modes(state->interface));
367
368 if (!phy_interface_mode_is_rgmii(state->interface) &&
369 state->interface != PHY_INTERFACE_MODE_NA &&
370 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
371 state->interface != PHY_INTERFACE_MODE_MII &&
372 state->interface != PHY_INTERFACE_MODE_REVMII &&
373 state->interface != PHY_INTERFACE_MODE_GMII &&
374 state->interface != PHY_INTERFACE_MODE_QSGMII &&
375 state->interface != PHY_INTERFACE_MODE_XGMII &&
376 state->interface != PHY_INTERFACE_MODE_HSGMII &&
377 state->interface != PHY_INTERFACE_MODE_10GBASER &&
378 state->interface != PHY_INTERFACE_MODE_10GKR &&
379 state->interface != PHY_INTERFACE_MODE_USXGMII &&
380 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
381 state->interface != PHY_INTERFACE_MODE_SGMII) {
382 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
383 dev_err(ds->dev,
384 "Unsupported interface: %d for port %d\n",
385 state->interface, port);
386 return;
387 }
388
389 /* Allow all the expected bits */
390 phylink_set(mask, Autoneg);
391 phylink_set_port_modes(mask);
392 phylink_set(mask, Pause);
393 phylink_set(mask, Asym_Pause);
394
395 /* With the exclusion of MII and Reverse MII, we support Gigabit,
396 * including Half duplex
397 */
398 if (state->interface != PHY_INTERFACE_MODE_MII &&
399 state->interface != PHY_INTERFACE_MODE_REVMII) {
400 phylink_set(mask, 1000baseT_Full);
401 phylink_set(mask, 1000baseT_Half);
402 }
403
404 /* Internal phys of the RTL93xx family provide 10G */
405 if (priv->ports[port].phy_is_integrated &&
406 state->interface == PHY_INTERFACE_MODE_1000BASEX) {
407 phylink_set(mask, 1000baseX_Full);
408 } else if (priv->ports[port].phy_is_integrated) {
409 phylink_set(mask, 1000baseX_Full);
410 phylink_set(mask, 10000baseKR_Full);
411 phylink_set(mask, 10000baseSR_Full);
412 phylink_set(mask, 10000baseCR_Full);
413 }
414 if (state->interface == PHY_INTERFACE_MODE_INTERNAL) {
415 phylink_set(mask, 1000baseX_Full);
416 phylink_set(mask, 1000baseT_Full);
417 phylink_set(mask, 10000baseKR_Full);
418 phylink_set(mask, 10000baseT_Full);
419 phylink_set(mask, 10000baseSR_Full);
420 phylink_set(mask, 10000baseCR_Full);
421 }
422
423 if (state->interface == PHY_INTERFACE_MODE_USXGMII)
424 phylink_set(mask, 10000baseT_Full);
425
426 phylink_set(mask, 10baseT_Half);
427 phylink_set(mask, 10baseT_Full);
428 phylink_set(mask, 100baseT_Half);
429 phylink_set(mask, 100baseT_Full);
430
431 bitmap_and(supported, supported, mask,
432 __ETHTOOL_LINK_MODE_MASK_NBITS);
433 bitmap_and(state->advertising, state->advertising, mask,
434 __ETHTOOL_LINK_MODE_MASK_NBITS);
435 pr_debug("%s leaving supported: %*pb", __func__, __ETHTOOL_LINK_MODE_MASK_NBITS, supported);
436 }
437
438 static int rtl83xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
439 struct phylink_link_state *state)
440 {
441 struct rtl838x_switch_priv *priv = ds->priv;
442 u64 speed;
443 u64 link;
444
445 if (port < 0 || port > priv->cpu_port)
446 return -EINVAL;
447
448 state->link = 0;
449 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
450 if (link & BIT_ULL(port))
451 state->link = 1;
452 pr_debug("%s: link state port %d: %llx\n", __func__, port, link & BIT_ULL(port));
453
454 state->duplex = 0;
455 if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
456 state->duplex = 1;
457
458 speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
459 speed >>= (port % 16) << 1;
460 switch (speed & 0x3) {
461 case 0:
462 state->speed = SPEED_10;
463 break;
464 case 1:
465 state->speed = SPEED_100;
466 break;
467 case 2:
468 state->speed = SPEED_1000;
469 break;
470 case 3:
471 if (priv->family_id == RTL9300_FAMILY_ID
472 && (port == 24 || port == 26)) /* Internal serdes */
473 state->speed = SPEED_2500;
474 else
475 state->speed = SPEED_100; /* Is in fact 500Mbit */
476 }
477
478 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
479 if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
480 state->pause |= MLO_PAUSE_RX;
481 if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
482 state->pause |= MLO_PAUSE_TX;
483
484 return 1;
485 }
486
487 static int rtl93xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
488 struct phylink_link_state *state)
489 {
490 struct rtl838x_switch_priv *priv = ds->priv;
491 u64 speed;
492 u64 link;
493 u64 media;
494
495 if (port < 0 || port > priv->cpu_port)
496 return -EINVAL;
497
498 /* On the RTL9300 for at least the RTL8226B PHY, the MAC-side link
499 * state needs to be read twice in order to read a correct result.
500 * This would not be necessary for ports connected e.g. to RTL8218D
501 * PHYs.
502 */
503 state->link = 0;
504 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
505 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
506 if (link & BIT_ULL(port))
507 state->link = 1;
508
509 if (priv->family_id == RTL9310_FAMILY_ID)
510 media = priv->r->get_port_reg_le(RTL931X_MAC_LINK_MEDIA_STS);
511
512 if (priv->family_id == RTL9300_FAMILY_ID)
513 media = sw_r32(RTL930X_MAC_LINK_MEDIA_STS);
514
515 if (media & BIT_ULL(port))
516 state->link = 1;
517
518 pr_debug("%s: link state port %d: %llx, media %llx\n", __func__, port,
519 link & BIT_ULL(port), media);
520
521 state->duplex = 0;
522 if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
523 state->duplex = 1;
524
525 speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
526 speed >>= (port % 8) << 2;
527 switch (speed & 0xf) {
528 case 0:
529 state->speed = SPEED_10;
530 break;
531 case 1:
532 state->speed = SPEED_100;
533 break;
534 case 2:
535 case 7:
536 state->speed = SPEED_1000;
537 break;
538 case 4:
539 state->speed = SPEED_10000;
540 break;
541 case 5:
542 case 8:
543 state->speed = SPEED_2500;
544 break;
545 case 6:
546 state->speed = SPEED_5000;
547 break;
548 default:
549 pr_err("%s: unknown speed: %d\n", __func__, (u32)speed & 0xf);
550 }
551
552 if (priv->family_id == RTL9310_FAMILY_ID
553 && (port >= 52 || port <= 55)) { /* Internal serdes */
554 state->speed = SPEED_10000;
555 state->link = 1;
556 state->duplex = 1;
557 }
558
559 pr_debug("%s: speed is: %d %d\n", __func__, (u32)speed & 0xf, state->speed);
560 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
561 if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
562 state->pause |= MLO_PAUSE_RX;
563 if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
564 state->pause |= MLO_PAUSE_TX;
565
566 return 1;
567 }
568
569 static void rtl83xx_config_interface(int port, phy_interface_t interface)
570 {
571 u32 old, int_shift, sds_shift;
572
573 switch (port) {
574 case 24:
575 int_shift = 0;
576 sds_shift = 5;
577 break;
578 case 26:
579 int_shift = 3;
580 sds_shift = 0;
581 break;
582 default:
583 return;
584 }
585
586 old = sw_r32(RTL838X_SDS_MODE_SEL);
587 switch (interface) {
588 case PHY_INTERFACE_MODE_1000BASEX:
589 if ((old >> sds_shift & 0x1f) == 4)
590 return;
591 sw_w32_mask(0x7 << int_shift, 1 << int_shift, RTL838X_INT_MODE_CTRL);
592 sw_w32_mask(0x1f << sds_shift, 4 << sds_shift, RTL838X_SDS_MODE_SEL);
593 break;
594 case PHY_INTERFACE_MODE_SGMII:
595 if ((old >> sds_shift & 0x1f) == 2)
596 return;
597 sw_w32_mask(0x7 << int_shift, 2 << int_shift, RTL838X_INT_MODE_CTRL);
598 sw_w32_mask(0x1f << sds_shift, 2 << sds_shift, RTL838X_SDS_MODE_SEL);
599 break;
600 default:
601 return;
602 }
603 pr_debug("configured port %d for interface %s\n", port, phy_modes(interface));
604 }
605
606 static void rtl83xx_phylink_mac_config(struct dsa_switch *ds, int port,
607 unsigned int mode,
608 const struct phylink_link_state *state)
609 {
610 struct rtl838x_switch_priv *priv = ds->priv;
611 u32 reg;
612 int speed_bit = priv->family_id == RTL8380_FAMILY_ID ? 4 : 3;
613
614 pr_debug("%s port %d, mode %x\n", __func__, port, mode);
615
616 if (port == priv->cpu_port) {
617 /* Set Speed, duplex, flow control
618 * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
619 * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
620 * | MEDIA_SEL
621 */
622 if (priv->family_id == RTL8380_FAMILY_ID) {
623 sw_w32(0x6192F, priv->r->mac_force_mode_ctrl(priv->cpu_port));
624 /* allow CRC errors on CPU-port */
625 sw_w32_mask(0, 0x8, RTL838X_MAC_PORT_CTRL(priv->cpu_port));
626 } else {
627 sw_w32_mask(0, 3, priv->r->mac_force_mode_ctrl(priv->cpu_port));
628 }
629 return;
630 }
631
632 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
633 /* Auto-Negotiation does not work for MAC in RTL8390 */
634 if (priv->family_id == RTL8380_FAMILY_ID) {
635 if (mode == MLO_AN_PHY || phylink_autoneg_inband(mode)) {
636 pr_debug("PHY autonegotiates\n");
637 reg |= RTL838X_NWAY_EN;
638 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
639 rtl83xx_config_interface(port, state->interface);
640 return;
641 }
642 }
643
644 if (mode != MLO_AN_FIXED)
645 pr_debug("Fixed state.\n");
646
647 /* Clear id_mode_dis bit, and the existing port mode, let
648 * RGMII_MODE_EN bet set by mac_link_{up,down} */
649 if (priv->family_id == RTL8380_FAMILY_ID) {
650 reg &= ~(RTL838X_RX_PAUSE_EN | RTL838X_TX_PAUSE_EN);
651 if (state->pause & MLO_PAUSE_TXRX_MASK) {
652 if (state->pause & MLO_PAUSE_TX)
653 reg |= RTL838X_TX_PAUSE_EN;
654 reg |= RTL838X_RX_PAUSE_EN;
655 }
656 } else if (priv->family_id == RTL8390_FAMILY_ID) {
657 reg &= ~(RTL839X_RX_PAUSE_EN | RTL839X_TX_PAUSE_EN);
658 if (state->pause & MLO_PAUSE_TXRX_MASK) {
659 if (state->pause & MLO_PAUSE_TX)
660 reg |= RTL839X_TX_PAUSE_EN;
661 reg |= RTL839X_RX_PAUSE_EN;
662 }
663 }
664
665
666 reg &= ~(3 << speed_bit);
667 switch (state->speed) {
668 case SPEED_1000:
669 reg |= 2 << speed_bit;
670 break;
671 case SPEED_100:
672 reg |= 1 << speed_bit;
673 break;
674 default:
675 break; /* Ignore, including 10MBit which has a speed value of 0 */
676 }
677
678 if (priv->family_id == RTL8380_FAMILY_ID) {
679 reg &= ~(RTL838X_DUPLEX_MODE | RTL838X_FORCE_LINK_EN);
680 if (state->link)
681 reg |= RTL838X_FORCE_LINK_EN;
682 if (state->duplex == RTL838X_DUPLEX_MODE)
683 reg |= RTL838X_DUPLEX_MODE;
684 } else if (priv->family_id == RTL8390_FAMILY_ID) {
685 reg &= ~(RTL839X_DUPLEX_MODE | RTL839X_FORCE_LINK_EN);
686 if (state->link)
687 reg |= RTL839X_FORCE_LINK_EN;
688 if (state->duplex == RTL839X_DUPLEX_MODE)
689 reg |= RTL839X_DUPLEX_MODE;
690 }
691
692 /* LAG members must use DUPLEX and we need to enable the link */
693 if (priv->lagmembers & BIT_ULL(port)) {
694 switch(priv->family_id) {
695 case RTL8380_FAMILY_ID:
696 reg |= (RTL838X_DUPLEX_MODE | RTL838X_FORCE_LINK_EN);
697 break;
698 case RTL8390_FAMILY_ID:
699 reg |= (RTL839X_DUPLEX_MODE | RTL839X_FORCE_LINK_EN);
700 break;
701 }
702 }
703
704 /* Disable AN */
705 if (priv->family_id == RTL8380_FAMILY_ID)
706 reg &= ~RTL838X_NWAY_EN;
707 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
708 }
709
710 static void rtl931x_phylink_mac_config(struct dsa_switch *ds, int port,
711 unsigned int mode,
712 const struct phylink_link_state *state)
713 {
714 struct rtl838x_switch_priv *priv = ds->priv;
715 int sds_num;
716 u32 reg, band;
717
718 sds_num = priv->ports[port].sds_num;
719 pr_info("%s: speed %d sds_num %d\n", __func__, state->speed, sds_num);
720
721 switch (state->interface) {
722 case PHY_INTERFACE_MODE_HSGMII:
723 pr_info("%s setting mode PHY_INTERFACE_MODE_HSGMII\n", __func__);
724 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_HSGMII);
725 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_HSGMII);
726 band = rtl931x_sds_cmu_band_set(sds_num, true, 62, PHY_INTERFACE_MODE_HSGMII);
727 break;
728 case PHY_INTERFACE_MODE_1000BASEX:
729 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_1000BASEX);
730 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_1000BASEX);
731 break;
732 case PHY_INTERFACE_MODE_XGMII:
733 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_XGMII);
734 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_XGMII);
735 break;
736 case PHY_INTERFACE_MODE_10GBASER:
737 case PHY_INTERFACE_MODE_10GKR:
738 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_10GBASER);
739 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_10GBASER);
740 break;
741 case PHY_INTERFACE_MODE_USXGMII:
742 /* Translates to MII_USXGMII_10GSXGMII */
743 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_USXGMII);
744 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_USXGMII);
745 break;
746 case PHY_INTERFACE_MODE_SGMII:
747 pr_info("%s setting mode PHY_INTERFACE_MODE_SGMII\n", __func__);
748 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_SGMII);
749 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_SGMII);
750 band = rtl931x_sds_cmu_band_set(sds_num, true, 62, PHY_INTERFACE_MODE_SGMII);
751 break;
752 case PHY_INTERFACE_MODE_QSGMII:
753 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_QSGMII);
754 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_QSGMII);
755 break;
756 default:
757 pr_err("%s: unknown serdes mode: %s\n",
758 __func__, phy_modes(state->interface));
759 return;
760 }
761
762 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
763 pr_info("%s reading FORCE_MODE_CTRL: %08x\n", __func__, reg);
764
765 reg &= ~(RTL931X_DUPLEX_MODE | RTL931X_FORCE_EN | RTL931X_FORCE_LINK_EN);
766
767 reg &= ~(0xf << 12);
768 reg |= 0x2 << 12; /* Set SMI speed to 0x2 */
769
770 reg |= RTL931X_TX_PAUSE_EN | RTL931X_RX_PAUSE_EN;
771
772 if (priv->lagmembers & BIT_ULL(port))
773 reg |= RTL931X_DUPLEX_MODE;
774
775 if (state->duplex == DUPLEX_FULL)
776 reg |= RTL931X_DUPLEX_MODE;
777
778 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
779
780 }
781
782 static void rtl93xx_phylink_mac_config(struct dsa_switch *ds, int port,
783 unsigned int mode,
784 const struct phylink_link_state *state)
785 {
786 struct rtl838x_switch_priv *priv = ds->priv;
787 int sds_num, sds_mode;
788 u32 reg;
789
790 pr_info("%s port %d, mode %x, phy-mode: %s, speed %d, link %d\n", __func__,
791 port, mode, phy_modes(state->interface), state->speed, state->link);
792
793 /* Nothing to be done for the CPU-port */
794 if (port == priv->cpu_port)
795 return;
796
797 if (priv->family_id == RTL9310_FAMILY_ID)
798 return rtl931x_phylink_mac_config(ds, port, mode, state);
799
800 sds_num = priv->ports[port].sds_num;
801 pr_info("%s SDS is %d\n", __func__, sds_num);
802 if (sds_num >= 0) {
803 switch (state->interface) {
804 case PHY_INTERFACE_MODE_HSGMII:
805 sds_mode = 0x12;
806 break;
807 case PHY_INTERFACE_MODE_1000BASEX:
808 sds_mode = 0x04;
809 break;
810 case PHY_INTERFACE_MODE_XGMII:
811 sds_mode = 0x10;
812 break;
813 case PHY_INTERFACE_MODE_10GBASER:
814 case PHY_INTERFACE_MODE_10GKR:
815 sds_mode = 0x1b; /* 10G 1000X Auto */
816 break;
817 case PHY_INTERFACE_MODE_USXGMII:
818 sds_mode = 0x0d;
819 break;
820 default:
821 pr_err("%s: unknown serdes mode: %s\n",
822 __func__, phy_modes(state->interface));
823 return;
824 }
825 if (state->interface == PHY_INTERFACE_MODE_10GBASER)
826 rtl9300_serdes_setup(sds_num, state->interface);
827 }
828
829 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
830 reg &= ~(0xf << 3);
831
832 switch (state->speed) {
833 case SPEED_10000:
834 reg |= 4 << 3;
835 break;
836 case SPEED_5000:
837 reg |= 6 << 3;
838 break;
839 case SPEED_2500:
840 reg |= 5 << 3;
841 break;
842 case SPEED_1000:
843 reg |= 2 << 3;
844 break;
845 default:
846 reg |= 2 << 3;
847 break;
848 }
849
850 if (state->link)
851 reg |= RTL930X_FORCE_LINK_EN;
852
853 if (priv->lagmembers & BIT_ULL(port))
854 reg |= RTL930X_DUPLEX_MODE | RTL930X_FORCE_LINK_EN;
855
856 if (state->duplex == DUPLEX_FULL)
857 reg |= RTL930X_DUPLEX_MODE;
858
859 if (priv->ports[port].phy_is_integrated)
860 reg &= ~RTL930X_FORCE_EN; /* Clear MAC_FORCE_EN to allow SDS-MAC link */
861 else
862 reg |= RTL930X_FORCE_EN;
863
864 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
865 }
866
867 static void rtl83xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
868 unsigned int mode,
869 phy_interface_t interface)
870 {
871 struct rtl838x_switch_priv *priv = ds->priv;
872
873 /* Stop TX/RX to port */
874 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
875
876 /* No longer force link */
877 sw_w32_mask(0x3, 0, priv->r->mac_force_mode_ctrl(port));
878 }
879
880 static void rtl93xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
881 unsigned int mode,
882 phy_interface_t interface)
883 {
884 struct rtl838x_switch_priv *priv = ds->priv;
885 u32 v = 0;
886
887 /* Stop TX/RX to port */
888 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
889
890 /* No longer force link */
891 if (priv->family_id == RTL9300_FAMILY_ID)
892 v = RTL930X_FORCE_EN | RTL930X_FORCE_LINK_EN;
893 else if (priv->family_id == RTL9310_FAMILY_ID)
894 v = RTL931X_FORCE_EN | RTL931X_FORCE_LINK_EN;
895 sw_w32_mask(v, 0, priv->r->mac_force_mode_ctrl(port));
896 }
897
898 static void rtl83xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
899 unsigned int mode,
900 phy_interface_t interface,
901 struct phy_device *phydev,
902 int speed, int duplex,
903 bool tx_pause, bool rx_pause)
904 {
905 struct rtl838x_switch_priv *priv = ds->priv;
906 /* Restart TX/RX to port */
907 sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
908 /* TODO: Set speed/duplex/pauses */
909 }
910
911 static void rtl93xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
912 unsigned int mode,
913 phy_interface_t interface,
914 struct phy_device *phydev,
915 int speed, int duplex,
916 bool tx_pause, bool rx_pause)
917 {
918 struct rtl838x_switch_priv *priv = ds->priv;
919
920 /* Restart TX/RX to port */
921 sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
922 /* TODO: Set speed/duplex/pauses */
923 }
924
925 static void rtl83xx_get_strings(struct dsa_switch *ds,
926 int port, u32 stringset, u8 *data)
927 {
928 if (stringset != ETH_SS_STATS)
929 return;
930
931 for (int i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++)
932 strncpy(data + i * ETH_GSTRING_LEN, rtl83xx_mib[i].name,
933 ETH_GSTRING_LEN);
934 }
935
936 static void rtl83xx_get_ethtool_stats(struct dsa_switch *ds, int port,
937 uint64_t *data)
938 {
939 struct rtl838x_switch_priv *priv = ds->priv;
940 const struct rtl83xx_mib_desc *mib;
941 u64 h;
942
943 for (int i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++) {
944 mib = &rtl83xx_mib[i];
945
946 data[i] = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 252 - mib->offset);
947 if (mib->size == 2) {
948 h = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 248 - mib->offset);
949 data[i] |= h << 32;
950 }
951 }
952 }
953
954 static int rtl83xx_get_sset_count(struct dsa_switch *ds, int port, int sset)
955 {
956 if (sset != ETH_SS_STATS)
957 return 0;
958
959 return ARRAY_SIZE(rtl83xx_mib);
960 }
961
962 static int rtl83xx_mc_group_alloc(struct rtl838x_switch_priv *priv, int port)
963 {
964 int mc_group = find_first_zero_bit(priv->mc_group_bm, MAX_MC_GROUPS - 1);
965 u64 portmask;
966
967 if (mc_group >= MAX_MC_GROUPS - 1)
968 return -1;
969
970 if (priv->is_lagmember[port]) {
971 pr_info("%s: %d is lag slave. ignore\n", __func__, port);
972 return 0;
973 }
974
975 set_bit(mc_group, priv->mc_group_bm);
976 mc_group++; /* We cannot use group 0, as this is used for lookup miss flooding */
977 portmask = BIT_ULL(port) | BIT_ULL(priv->cpu_port);
978 priv->r->write_mcast_pmask(mc_group, portmask);
979
980 return mc_group;
981 }
982
983 static u64 rtl83xx_mc_group_add_port(struct rtl838x_switch_priv *priv, int mc_group, int port)
984 {
985 u64 portmask = priv->r->read_mcast_pmask(mc_group);
986
987 pr_debug("%s: %d\n", __func__, port);
988 if (priv->is_lagmember[port]) {
989 pr_info("%s: %d is lag slave. ignore\n", __func__, port);
990 return portmask;
991 }
992 portmask |= BIT_ULL(port);
993 priv->r->write_mcast_pmask(mc_group, portmask);
994
995 return portmask;
996 }
997
998 static u64 rtl83xx_mc_group_del_port(struct rtl838x_switch_priv *priv, int mc_group, int port)
999 {
1000 u64 portmask = priv->r->read_mcast_pmask(mc_group);
1001
1002 pr_debug("%s: %d\n", __func__, port);
1003 if (priv->is_lagmember[port]) {
1004 pr_info("%s: %d is lag slave. ignore\n", __func__, port);
1005 return portmask;
1006 }
1007 priv->r->write_mcast_pmask(mc_group, portmask);
1008 if (portmask == BIT_ULL(priv->cpu_port)) {
1009 portmask &= ~BIT_ULL(priv->cpu_port);
1010 priv->r->write_mcast_pmask(mc_group, portmask);
1011 clear_bit(mc_group, priv->mc_group_bm);
1012 }
1013
1014 return portmask;
1015 }
1016
1017 static void store_mcgroups(struct rtl838x_switch_priv *priv, int port)
1018 {
1019 for (int mc_group = 0; mc_group < MAX_MC_GROUPS; mc_group++) {
1020 u64 portmask = priv->r->read_mcast_pmask(mc_group);
1021 if (portmask & BIT_ULL(port)) {
1022 priv->mc_group_saves[mc_group] = port;
1023 rtl83xx_mc_group_del_port(priv, mc_group, port);
1024 }
1025 }
1026 }
1027
1028 static void load_mcgroups(struct rtl838x_switch_priv *priv, int port)
1029 {
1030 for (int mc_group = 0; mc_group < MAX_MC_GROUPS; mc_group++) {
1031 if (priv->mc_group_saves[mc_group] == port) {
1032 rtl83xx_mc_group_add_port(priv, mc_group, port);
1033 priv->mc_group_saves[mc_group] = -1;
1034 }
1035 }
1036 }
1037
1038 static int rtl83xx_port_enable(struct dsa_switch *ds, int port,
1039 struct phy_device *phydev)
1040 {
1041 struct rtl838x_switch_priv *priv = ds->priv;
1042 u64 v;
1043
1044 pr_debug("%s: %x %d", __func__, (u32) priv, port);
1045 priv->ports[port].enable = true;
1046
1047 /* enable inner tagging on egress, do not keep any tags */
1048 priv->r->vlan_port_keep_tag_set(port, 0, 1);
1049
1050 if (dsa_is_cpu_port(ds, port))
1051 return 0;
1052
1053 /* add port to switch mask of CPU_PORT */
1054 priv->r->traffic_enable(priv->cpu_port, port);
1055
1056 load_mcgroups(priv, port);
1057
1058 if (priv->is_lagmember[port]) {
1059 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1060 return 0;
1061 }
1062
1063 /* add all other ports in the same bridge to switch mask of port */
1064 v = priv->r->traffic_get(port);
1065 v |= priv->ports[port].pm;
1066 priv->r->traffic_set(port, v);
1067
1068 /* TODO: Figure out if this is necessary */
1069 if (priv->family_id == RTL9300_FAMILY_ID) {
1070 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_SABLK_CTRL);
1071 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_DABLK_CTRL);
1072 }
1073
1074 if (priv->ports[port].sds_num < 0)
1075 priv->ports[port].sds_num = rtl93xx_get_sds(phydev);
1076
1077 return 0;
1078 }
1079
1080 static void rtl83xx_port_disable(struct dsa_switch *ds, int port)
1081 {
1082 struct rtl838x_switch_priv *priv = ds->priv;
1083 u64 v;
1084
1085 pr_debug("%s %x: %d", __func__, (u32)priv, port);
1086 /* you can only disable user ports */
1087 if (!dsa_is_user_port(ds, port))
1088 return;
1089
1090 /* BUG: This does not work on RTL931X */
1091 /* remove port from switch mask of CPU_PORT */
1092 priv->r->traffic_disable(priv->cpu_port, port);
1093 store_mcgroups(priv, port);
1094
1095 /* remove all other ports in the same bridge from switch mask of port */
1096 v = priv->r->traffic_get(port);
1097 v &= ~priv->ports[port].pm;
1098 priv->r->traffic_set(port, v);
1099
1100 priv->ports[port].enable = false;
1101 }
1102
1103 static int rtl83xx_set_mac_eee(struct dsa_switch *ds, int port,
1104 struct ethtool_eee *e)
1105 {
1106 struct rtl838x_switch_priv *priv = ds->priv;
1107
1108 if (e->eee_enabled && !priv->eee_enabled) {
1109 pr_info("Globally enabling EEE\n");
1110 priv->r->init_eee(priv, true);
1111 }
1112
1113 priv->r->port_eee_set(priv, port, e->eee_enabled);
1114
1115 if (e->eee_enabled)
1116 pr_info("Enabled EEE for port %d\n", port);
1117 else
1118 pr_info("Disabled EEE for port %d\n", port);
1119
1120 return 0;
1121 }
1122
1123 static int rtl83xx_get_mac_eee(struct dsa_switch *ds, int port,
1124 struct ethtool_eee *e)
1125 {
1126 struct rtl838x_switch_priv *priv = ds->priv;
1127
1128 e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full;
1129
1130 priv->r->eee_port_ability(priv, e, port);
1131
1132 e->eee_enabled = priv->ports[port].eee_enabled;
1133
1134 e->eee_active = !!(e->advertised & e->lp_advertised);
1135
1136 return 0;
1137 }
1138
1139 static int rtl93xx_get_mac_eee(struct dsa_switch *ds, int port,
1140 struct ethtool_eee *e)
1141 {
1142 struct rtl838x_switch_priv *priv = ds->priv;
1143
1144 e->supported = SUPPORTED_100baseT_Full |
1145 SUPPORTED_1000baseT_Full |
1146 SUPPORTED_2500baseX_Full;
1147
1148 priv->r->eee_port_ability(priv, e, port);
1149
1150 e->eee_enabled = priv->ports[port].eee_enabled;
1151
1152 e->eee_active = !!(e->advertised & e->lp_advertised);
1153
1154 return 0;
1155 }
1156
1157 static int rtl83xx_set_ageing_time(struct dsa_switch *ds, unsigned int msec)
1158 {
1159 struct rtl838x_switch_priv *priv = ds->priv;
1160
1161 priv->r->set_ageing_time(msec);
1162
1163 return 0;
1164 }
1165
1166 static int rtl83xx_port_bridge_join(struct dsa_switch *ds, int port,
1167 struct net_device *bridge)
1168 {
1169 struct rtl838x_switch_priv *priv = ds->priv;
1170 u64 port_bitmap = BIT_ULL(priv->cpu_port), v;
1171
1172 pr_debug("%s %x: %d %llx", __func__, (u32)priv, port, port_bitmap);
1173
1174 if (priv->is_lagmember[port]) {
1175 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1176 return 0;
1177 }
1178
1179 mutex_lock(&priv->reg_mutex);
1180 for (int i = 0; i < ds->num_ports; i++) {
1181 /* Add this port to the port matrix of the other ports in the
1182 * same bridge. If the port is disabled, port matrix is kept
1183 * and not being setup until the port becomes enabled.
1184 */
1185 if (dsa_is_user_port(ds, i) && !priv->is_lagmember[i] && i != port) {
1186 if (dsa_to_port(ds, i)->bridge_dev != bridge)
1187 continue;
1188 if (priv->ports[i].enable)
1189 priv->r->traffic_enable(i, port);
1190
1191 priv->ports[i].pm |= BIT_ULL(port);
1192 port_bitmap |= BIT_ULL(i);
1193 }
1194 }
1195 load_mcgroups(priv, port);
1196
1197 /* Add all other ports to this port matrix. */
1198 if (priv->ports[port].enable) {
1199 priv->r->traffic_enable(priv->cpu_port, port);
1200 v = priv->r->traffic_get(port);
1201 v |= port_bitmap;
1202 priv->r->traffic_set(port, v);
1203 }
1204 priv->ports[port].pm |= port_bitmap;
1205 mutex_unlock(&priv->reg_mutex);
1206
1207 return 0;
1208 }
1209
1210 static void rtl83xx_port_bridge_leave(struct dsa_switch *ds, int port,
1211 struct net_device *bridge)
1212 {
1213 struct rtl838x_switch_priv *priv = ds->priv;
1214 u64 port_bitmap = 0, v;
1215
1216 pr_debug("%s %x: %d", __func__, (u32)priv, port);
1217 mutex_lock(&priv->reg_mutex);
1218 for (int i = 0; i < ds->num_ports; i++) {
1219 /* Remove this port from the port matrix of the other ports
1220 * in the same bridge. If the port is disabled, port matrix
1221 * is kept and not being setup until the port becomes enabled.
1222 * And the other port's port matrix cannot be broken when the
1223 * other port is still a VLAN-aware port.
1224 */
1225 if (dsa_is_user_port(ds, i) && i != port) {
1226 if (dsa_to_port(ds, i)->bridge_dev != bridge)
1227 continue;
1228 if (priv->ports[i].enable)
1229 priv->r->traffic_disable(i, port);
1230
1231 priv->ports[i].pm &= ~BIT_ULL(port);
1232 port_bitmap |= BIT_ULL(i);
1233 }
1234 }
1235 store_mcgroups(priv, port);
1236
1237 /* Remove all other ports from this port matrix. */
1238 if (priv->ports[port].enable) {
1239 v = priv->r->traffic_get(port);
1240 v &= ~port_bitmap;
1241 priv->r->traffic_set(port, v);
1242 }
1243 priv->ports[port].pm &= ~port_bitmap;
1244
1245 mutex_unlock(&priv->reg_mutex);
1246 }
1247
1248 void rtl83xx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1249 {
1250 u32 msti = 0;
1251 u32 port_state[4];
1252 int index, bit;
1253 int pos = port;
1254 struct rtl838x_switch_priv *priv = ds->priv;
1255 int n = priv->port_width << 1;
1256
1257 /* Ports above or equal CPU port can never be configured */
1258 if (port >= priv->cpu_port)
1259 return;
1260
1261 mutex_lock(&priv->reg_mutex);
1262
1263 /* For the RTL839x and following, the bits are left-aligned, 838x and 930x
1264 * have 64 bit fields, 839x and 931x have 128 bit fields
1265 */
1266 if (priv->family_id == RTL8390_FAMILY_ID)
1267 pos += 12;
1268 if (priv->family_id == RTL9300_FAMILY_ID)
1269 pos += 3;
1270 if (priv->family_id == RTL9310_FAMILY_ID)
1271 pos += 8;
1272
1273 index = n - (pos >> 4) - 1;
1274 bit = (pos << 1) % 32;
1275
1276 priv->r->stp_get(priv, msti, port_state);
1277
1278 pr_debug("Current state, port %d: %d\n", port, (port_state[index] >> bit) & 3);
1279 port_state[index] &= ~(3 << bit);
1280
1281 switch (state) {
1282 case BR_STATE_DISABLED: /* 0 */
1283 port_state[index] |= (0 << bit);
1284 break;
1285 case BR_STATE_BLOCKING: /* 4 */
1286 case BR_STATE_LISTENING: /* 1 */
1287 port_state[index] |= (1 << bit);
1288 break;
1289 case BR_STATE_LEARNING: /* 2 */
1290 port_state[index] |= (2 << bit);
1291 break;
1292 case BR_STATE_FORWARDING: /* 3 */
1293 port_state[index] |= (3 << bit);
1294 default:
1295 break;
1296 }
1297
1298 priv->r->stp_set(priv, msti, port_state);
1299
1300 mutex_unlock(&priv->reg_mutex);
1301 }
1302
1303 void rtl83xx_fast_age(struct dsa_switch *ds, int port)
1304 {
1305 struct rtl838x_switch_priv *priv = ds->priv;
1306 int s = priv->family_id == RTL8390_FAMILY_ID ? 2 : 0;
1307
1308 pr_debug("FAST AGE port %d\n", port);
1309 mutex_lock(&priv->reg_mutex);
1310 /* RTL838X_L2_TBL_FLUSH_CTRL register bits, 839x has 1 bit larger
1311 * port fields:
1312 * 0-4: Replacing port
1313 * 5-9: Flushed/replaced port
1314 * 10-21: FVID
1315 * 22: Entry types: 1: dynamic, 0: also static
1316 * 23: Match flush port
1317 * 24: Match FVID
1318 * 25: Flush (0) or replace (1) L2 entries
1319 * 26: Status of action (1: Start, 0: Done)
1320 */
1321 sw_w32(1 << (26 + s) | 1 << (23 + s) | port << (5 + (s / 2)), priv->r->l2_tbl_flush_ctrl);
1322
1323 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(26 + s));
1324
1325 mutex_unlock(&priv->reg_mutex);
1326 }
1327
1328 void rtl931x_fast_age(struct dsa_switch *ds, int port)
1329 {
1330 struct rtl838x_switch_priv *priv = ds->priv;
1331
1332 pr_info("%s port %d\n", __func__, port);
1333 mutex_lock(&priv->reg_mutex);
1334 sw_w32(port << 11, RTL931X_L2_TBL_FLUSH_CTRL + 4);
1335
1336 sw_w32(BIT(24) | BIT(28), RTL931X_L2_TBL_FLUSH_CTRL);
1337
1338 do { } while (sw_r32(RTL931X_L2_TBL_FLUSH_CTRL) & BIT (28));
1339
1340 mutex_unlock(&priv->reg_mutex);
1341 }
1342
1343 void rtl930x_fast_age(struct dsa_switch *ds, int port)
1344 {
1345 struct rtl838x_switch_priv *priv = ds->priv;
1346
1347 if (priv->family_id == RTL9310_FAMILY_ID)
1348 return rtl931x_fast_age(ds, port);
1349
1350 pr_debug("FAST AGE port %d\n", port);
1351 mutex_lock(&priv->reg_mutex);
1352 sw_w32(port << 11, RTL930X_L2_TBL_FLUSH_CTRL + 4);
1353
1354 sw_w32(BIT(26) | BIT(30), RTL930X_L2_TBL_FLUSH_CTRL);
1355
1356 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(30));
1357
1358 mutex_unlock(&priv->reg_mutex);
1359 }
1360
1361 static int rtl83xx_vlan_filtering(struct dsa_switch *ds, int port,
1362 bool vlan_filtering,
1363 struct netlink_ext_ack *extack)
1364 {
1365 struct rtl838x_switch_priv *priv = ds->priv;
1366
1367 pr_debug("%s: port %d\n", __func__, port);
1368 mutex_lock(&priv->reg_mutex);
1369
1370 if (vlan_filtering) {
1371 /* Enable ingress and egress filtering
1372 * The VLAN_PORT_IGR_FILTER register uses 2 bits for each port to define
1373 * the filter action:
1374 * 0: Always Forward
1375 * 1: Drop packet
1376 * 2: Trap packet to CPU port
1377 * The Egress filter used 1 bit per state (0: DISABLED, 1: ENABLED)
1378 */
1379 if (port != priv->cpu_port)
1380 priv->r->set_vlan_igr_filter(port, IGR_DROP);
1381
1382 priv->r->set_vlan_egr_filter(port, EGR_ENABLE);
1383 } else {
1384 /* Disable ingress and egress filtering */
1385 if (port != priv->cpu_port)
1386 priv->r->set_vlan_igr_filter(port, IGR_FORWARD);
1387
1388 priv->r->set_vlan_egr_filter(port, EGR_DISABLE);
1389 }
1390
1391 /* Do we need to do something to the CPU-Port, too? */
1392 mutex_unlock(&priv->reg_mutex);
1393
1394 return 0;
1395 }
1396
1397 static int rtl83xx_vlan_prepare(struct dsa_switch *ds, int port,
1398 const struct switchdev_obj_port_vlan *vlan)
1399 {
1400 struct rtl838x_vlan_info info;
1401 struct rtl838x_switch_priv *priv = ds->priv;
1402
1403 priv->r->vlan_tables_read(0, &info);
1404
1405 pr_debug("VLAN 0: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
1406 info.tagged_ports, info.untagged_ports, info.profile_id,
1407 info.hash_mc_fid, info.hash_uc_fid, info.fid);
1408
1409 priv->r->vlan_tables_read(1, &info);
1410 pr_debug("VLAN 1: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
1411 info.tagged_ports, info.untagged_ports, info.profile_id,
1412 info.hash_mc_fid, info.hash_uc_fid, info.fid);
1413 priv->r->vlan_set_untagged(1, info.untagged_ports);
1414 pr_debug("SET: Untagged ports, VLAN %d: %llx\n", 1, info.untagged_ports);
1415
1416 priv->r->vlan_set_tagged(1, &info);
1417 pr_debug("SET: Tagged ports, VLAN %d: %llx\n", 1, info.tagged_ports);
1418
1419 return 0;
1420 }
1421
1422 static int rtl83xx_vlan_add(struct dsa_switch *ds, int port,
1423 const struct switchdev_obj_port_vlan *vlan,
1424 struct netlink_ext_ack *extack)
1425 {
1426 struct rtl838x_vlan_info info;
1427 struct rtl838x_switch_priv *priv = ds->priv;
1428 int err;
1429
1430 pr_debug("%s port %d, vid %d, flags %x\n",
1431 __func__, port, vlan->vid, vlan->flags);
1432
1433 if (vlan->vid > 4095) {
1434 dev_err(priv->dev, "VLAN out of range: %d", vlan->vid);
1435 return -ENOTSUPP;
1436 }
1437
1438 err = rtl83xx_vlan_prepare(ds, port, vlan);
1439 if (err)
1440 return err;
1441
1442 mutex_lock(&priv->reg_mutex);
1443
1444 if (vlan->flags & BRIDGE_VLAN_INFO_PVID && vlan->vid) {
1445 /* Set both inner and outer PVID of the port */
1446 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_INNER, vlan->vid);
1447 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_OUTER, vlan->vid);
1448 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_INNER,
1449 PBVLAN_MODE_UNTAG_AND_PRITAG);
1450 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_OUTER,
1451 PBVLAN_MODE_UNTAG_AND_PRITAG);
1452
1453 priv->ports[port].pvid = vlan->vid;
1454 }
1455
1456 /* Get port memberships of this vlan */
1457 priv->r->vlan_tables_read(vlan->vid, &info);
1458
1459 /* new VLAN? */
1460 if (!info.tagged_ports) {
1461 info.fid = 0;
1462 info.hash_mc_fid = false;
1463 info.hash_uc_fid = false;
1464 info.profile_id = 0;
1465 }
1466
1467 /* sanitize untagged_ports - must be a subset */
1468 if (info.untagged_ports & ~info.tagged_ports)
1469 info.untagged_ports = 0;
1470
1471 info.tagged_ports |= BIT_ULL(port);
1472 if (vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED)
1473 info.untagged_ports |= BIT_ULL(port);
1474
1475 priv->r->vlan_set_untagged(vlan->vid, info.untagged_ports);
1476 pr_debug("Untagged ports, VLAN %d: %llx\n", vlan->vid, info.untagged_ports);
1477
1478 priv->r->vlan_set_tagged(vlan->vid, &info);
1479 pr_debug("Tagged ports, VLAN %d: %llx\n", vlan->vid, info.tagged_ports);
1480
1481 mutex_unlock(&priv->reg_mutex);
1482
1483 return 0;
1484 }
1485
1486 static int rtl83xx_vlan_del(struct dsa_switch *ds, int port,
1487 const struct switchdev_obj_port_vlan *vlan)
1488 {
1489 struct rtl838x_vlan_info info;
1490 struct rtl838x_switch_priv *priv = ds->priv;
1491 u16 pvid;
1492
1493 pr_debug("%s: port %d, vid %d, flags %x\n",
1494 __func__, port, vlan->vid, vlan->flags);
1495
1496 if (vlan->vid > 4095) {
1497 dev_err(priv->dev, "VLAN out of range: %d", vlan->vid);
1498 return -ENOTSUPP;
1499 }
1500
1501 mutex_lock(&priv->reg_mutex);
1502 pvid = priv->ports[port].pvid;
1503
1504 /* Reset to default if removing the current PVID */
1505 if (vlan->vid == pvid) {
1506 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_INNER, 0);
1507 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_OUTER, 0);
1508 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_INNER,
1509 PBVLAN_MODE_UNTAG_AND_PRITAG);
1510 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_OUTER,
1511 PBVLAN_MODE_UNTAG_AND_PRITAG);
1512 }
1513 /* Get port memberships of this vlan */
1514 priv->r->vlan_tables_read(vlan->vid, &info);
1515
1516 /* remove port from both tables */
1517 info.untagged_ports &= (~BIT_ULL(port));
1518 info.tagged_ports &= (~BIT_ULL(port));
1519
1520 priv->r->vlan_set_untagged(vlan->vid, info.untagged_ports);
1521 pr_debug("Untagged ports, VLAN %d: %llx\n", vlan->vid, info.untagged_ports);
1522
1523 priv->r->vlan_set_tagged(vlan->vid, &info);
1524 pr_debug("Tagged ports, VLAN %d: %llx\n", vlan->vid, info.tagged_ports);
1525
1526 mutex_unlock(&priv->reg_mutex);
1527
1528 return 0;
1529 }
1530
1531 static void rtl83xx_setup_l2_uc_entry(struct rtl838x_l2_entry *e, int port, int vid, u64 mac)
1532 {
1533 memset(e, 0, sizeof(*e));
1534
1535 e->type = L2_UNICAST;
1536 e->valid = true;
1537
1538 e->age = 3;
1539 e->is_static = true;
1540
1541 e->port = port;
1542
1543 e->rvid = e->vid = vid;
1544 e->is_ip_mc = e->is_ipv6_mc = false;
1545 u64_to_ether_addr(mac, e->mac);
1546 }
1547
1548 static void rtl83xx_setup_l2_mc_entry(struct rtl838x_l2_entry *e, int vid, u64 mac, int mc_group)
1549 {
1550 memset(e, 0, sizeof(*e));
1551
1552 e->type = L2_MULTICAST;
1553 e->valid = true;
1554
1555 e->mc_portmask_index = mc_group;
1556
1557 e->rvid = e->vid = vid;
1558 e->is_ip_mc = e->is_ipv6_mc = false;
1559 u64_to_ether_addr(mac, e->mac);
1560 }
1561
1562 /* Uses the seed to identify a hash bucket in the L2 using the derived hash key and then loops
1563 * over the entries in the bucket until either a matching entry is found or an empty slot
1564 * Returns the filled in rtl838x_l2_entry and the index in the bucket when an entry was found
1565 * when an empty slot was found and must exist is false, the index of the slot is returned
1566 * when no slots are available returns -1
1567 */
1568 static int rtl83xx_find_l2_hash_entry(struct rtl838x_switch_priv *priv, u64 seed,
1569 bool must_exist, struct rtl838x_l2_entry *e)
1570 {
1571 int idx = -1;
1572 u32 key = priv->r->l2_hash_key(priv, seed);
1573 u64 entry;
1574
1575 pr_debug("%s: using key %x, for seed %016llx\n", __func__, key, seed);
1576 /* Loop over all entries in the hash-bucket and over the second block on 93xx SoCs */
1577 for (int i = 0; i < priv->l2_bucket_size; i++) {
1578 entry = priv->r->read_l2_entry_using_hash(key, i, e);
1579 pr_debug("valid %d, mac %016llx\n", e->valid, ether_addr_to_u64(&e->mac[0]));
1580 if (must_exist && !e->valid)
1581 continue;
1582 if (!e->valid || ((entry & 0x0fffffffffffffffULL) == seed)) {
1583 idx = i > 3 ? ((key >> 14) & 0xffff) | i >> 1 : ((key << 2) | i) & 0xffff;
1584 break;
1585 }
1586 }
1587
1588 return idx;
1589 }
1590
1591 /* Uses the seed to identify an entry in the CAM by looping over all its entries
1592 * Returns the filled in rtl838x_l2_entry and the index in the CAM when an entry was found
1593 * when an empty slot was found the index of the slot is returned
1594 * when no slots are available returns -1
1595 */
1596 static int rtl83xx_find_l2_cam_entry(struct rtl838x_switch_priv *priv, u64 seed,
1597 bool must_exist, struct rtl838x_l2_entry *e)
1598 {
1599 int idx = -1;
1600 u64 entry;
1601
1602 for (int i = 0; i < 64; i++) {
1603 entry = priv->r->read_cam(i, e);
1604 if (!must_exist && !e->valid) {
1605 if (idx < 0) /* First empty entry? */
1606 idx = i;
1607 break;
1608 } else if ((entry & 0x0fffffffffffffffULL) == seed) {
1609 pr_debug("Found entry in CAM\n");
1610 idx = i;
1611 break;
1612 }
1613 }
1614
1615 return idx;
1616 }
1617
1618 static int rtl83xx_port_fdb_add(struct dsa_switch *ds, int port,
1619 const unsigned char *addr, u16 vid)
1620 {
1621 struct rtl838x_switch_priv *priv = ds->priv;
1622 u64 mac = ether_addr_to_u64(addr);
1623 struct rtl838x_l2_entry e;
1624 int err = 0, idx;
1625 u64 seed = priv->r->l2_hash_seed(mac, vid);
1626
1627 if (priv->is_lagmember[port]) {
1628 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1629 return 0;
1630 }
1631
1632 mutex_lock(&priv->reg_mutex);
1633
1634 idx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e);
1635
1636 /* Found an existing or empty entry */
1637 if (idx >= 0) {
1638 rtl83xx_setup_l2_uc_entry(&e, port, vid, mac);
1639 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1640 goto out;
1641 }
1642
1643 /* Hash buckets full, try CAM */
1644 rtl83xx_find_l2_cam_entry(priv, seed, false, &e);
1645
1646 if (idx >= 0) {
1647 rtl83xx_setup_l2_uc_entry(&e, port, vid, mac);
1648 priv->r->write_cam(idx, &e);
1649 goto out;
1650 }
1651
1652 err = -ENOTSUPP;
1653
1654 out:
1655 mutex_unlock(&priv->reg_mutex);
1656
1657 return err;
1658 }
1659
1660 static int rtl83xx_port_fdb_del(struct dsa_switch *ds, int port,
1661 const unsigned char *addr, u16 vid)
1662 {
1663 struct rtl838x_switch_priv *priv = ds->priv;
1664 u64 mac = ether_addr_to_u64(addr);
1665 struct rtl838x_l2_entry e;
1666 int err = 0, idx;
1667 u64 seed = priv->r->l2_hash_seed(mac, vid);
1668
1669 pr_debug("In %s, mac %llx, vid: %d\n", __func__, mac, vid);
1670 mutex_lock(&priv->reg_mutex);
1671
1672 idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e);
1673
1674 if (idx >= 0) {
1675 pr_debug("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3);
1676 e.valid = false;
1677 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1678 goto out;
1679 }
1680
1681 /* Check CAM for spillover from hash buckets */
1682 rtl83xx_find_l2_cam_entry(priv, seed, true, &e);
1683
1684 if (idx >= 0) {
1685 e.valid = false;
1686 priv->r->write_cam(idx, &e);
1687 goto out;
1688 }
1689 err = -ENOENT;
1690
1691 out:
1692 mutex_unlock(&priv->reg_mutex);
1693
1694 return err;
1695 }
1696
1697 static int rtl83xx_port_fdb_dump(struct dsa_switch *ds, int port,
1698 dsa_fdb_dump_cb_t *cb, void *data)
1699 {
1700 struct rtl838x_l2_entry e;
1701 struct rtl838x_switch_priv *priv = ds->priv;
1702
1703 mutex_lock(&priv->reg_mutex);
1704
1705 for (int i = 0; i < priv->fib_entries; i++) {
1706 priv->r->read_l2_entry_using_hash(i >> 2, i & 0x3, &e);
1707
1708 if (!e.valid)
1709 continue;
1710
1711 if (e.port == port || e.port == RTL930X_PORT_IGNORE)
1712 cb(e.mac, e.vid, e.is_static, data);
1713
1714 if (!((i + 1) % 64))
1715 cond_resched();
1716 }
1717
1718 for (int i = 0; i < 64; i++) {
1719 priv->r->read_cam(i, &e);
1720
1721 if (!e.valid)
1722 continue;
1723
1724 if (e.port == port)
1725 cb(e.mac, e.vid, e.is_static, data);
1726 }
1727
1728 mutex_unlock(&priv->reg_mutex);
1729
1730 return 0;
1731 }
1732
1733 static int rtl83xx_port_mdb_add(struct dsa_switch *ds, int port,
1734 const struct switchdev_obj_port_mdb *mdb)
1735 {
1736 struct rtl838x_switch_priv *priv = ds->priv;
1737 u64 mac = ether_addr_to_u64(mdb->addr);
1738 struct rtl838x_l2_entry e;
1739 int err = 0, idx;
1740 int vid = mdb->vid;
1741 u64 seed = priv->r->l2_hash_seed(mac, vid);
1742 int mc_group;
1743
1744 if (priv->id >= 0x9300)
1745 return -EOPNOTSUPP;
1746
1747 pr_debug("In %s port %d, mac %llx, vid: %d\n", __func__, port, mac, vid);
1748
1749 if (priv->is_lagmember[port]) {
1750 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1751 return -EINVAL;
1752 }
1753
1754 mutex_lock(&priv->reg_mutex);
1755
1756 idx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e);
1757
1758 /* Found an existing or empty entry */
1759 if (idx >= 0) {
1760 if (e.valid) {
1761 pr_debug("Found an existing entry %016llx, mc_group %d\n",
1762 ether_addr_to_u64(e.mac), e.mc_portmask_index);
1763 rtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port);
1764 } else {
1765 pr_debug("New entry for seed %016llx\n", seed);
1766 mc_group = rtl83xx_mc_group_alloc(priv, port);
1767 if (mc_group < 0) {
1768 err = -ENOTSUPP;
1769 goto out;
1770 }
1771 rtl83xx_setup_l2_mc_entry(&e, vid, mac, mc_group);
1772 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1773 }
1774 goto out;
1775 }
1776
1777 /* Hash buckets full, try CAM */
1778 rtl83xx_find_l2_cam_entry(priv, seed, false, &e);
1779
1780 if (idx >= 0) {
1781 if (e.valid) {
1782 pr_debug("Found existing CAM entry %016llx, mc_group %d\n",
1783 ether_addr_to_u64(e.mac), e.mc_portmask_index);
1784 rtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port);
1785 } else {
1786 pr_debug("New entry\n");
1787 mc_group = rtl83xx_mc_group_alloc(priv, port);
1788 if (mc_group < 0) {
1789 err = -ENOTSUPP;
1790 goto out;
1791 }
1792 rtl83xx_setup_l2_mc_entry(&e, vid, mac, mc_group);
1793 priv->r->write_cam(idx, &e);
1794 }
1795 goto out;
1796 }
1797
1798 err = -ENOTSUPP;
1799
1800 out:
1801 mutex_unlock(&priv->reg_mutex);
1802 if (err)
1803 dev_err(ds->dev, "failed to add MDB entry\n");
1804
1805 return err;
1806 }
1807
1808 int rtl83xx_port_mdb_del(struct dsa_switch *ds, int port,
1809 const struct switchdev_obj_port_mdb *mdb)
1810 {
1811 struct rtl838x_switch_priv *priv = ds->priv;
1812 u64 mac = ether_addr_to_u64(mdb->addr);
1813 struct rtl838x_l2_entry e;
1814 int err = 0, idx;
1815 int vid = mdb->vid;
1816 u64 seed = priv->r->l2_hash_seed(mac, vid);
1817 u64 portmask;
1818
1819 pr_debug("In %s, port %d, mac %llx, vid: %d\n", __func__, port, mac, vid);
1820
1821 if (priv->is_lagmember[port]) {
1822 pr_info("%s: %d is lag slave. ignore\n", __func__, port);
1823 return 0;
1824 }
1825
1826 mutex_lock(&priv->reg_mutex);
1827
1828 idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e);
1829
1830 if (idx >= 0) {
1831 pr_debug("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3);
1832 portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port);
1833 if (!portmask) {
1834 e.valid = false;
1835 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1836 }
1837 goto out;
1838 }
1839
1840 /* Check CAM for spillover from hash buckets */
1841 rtl83xx_find_l2_cam_entry(priv, seed, true, &e);
1842
1843 if (idx >= 0) {
1844 portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port);
1845 if (!portmask) {
1846 e.valid = false;
1847 priv->r->write_cam(idx, &e);
1848 }
1849 goto out;
1850 }
1851 /* TODO: Re-enable with a newer kernel: err = -ENOENT; */
1852
1853 out:
1854 mutex_unlock(&priv->reg_mutex);
1855
1856 return err;
1857 }
1858
1859 static int rtl83xx_port_mirror_add(struct dsa_switch *ds, int port,
1860 struct dsa_mall_mirror_tc_entry *mirror,
1861 bool ingress)
1862 {
1863 /* We support 4 mirror groups, one destination port per group */
1864 int group;
1865 struct rtl838x_switch_priv *priv = ds->priv;
1866 int ctrl_reg, dpm_reg, spm_reg;
1867
1868 pr_debug("In %s\n", __func__);
1869
1870 for (group = 0; group < 4; group++) {
1871 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1872 break;
1873 }
1874 if (group >= 4) {
1875 for (group = 0; group < 4; group++) {
1876 if (priv->mirror_group_ports[group] < 0)
1877 break;
1878 }
1879 }
1880
1881 if (group >= 4)
1882 return -ENOSPC;
1883
1884 ctrl_reg = priv->r->mir_ctrl + group * 4;
1885 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1886 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1887
1888 pr_debug("Using group %d\n", group);
1889 mutex_lock(&priv->reg_mutex);
1890
1891 if (priv->family_id == RTL8380_FAMILY_ID) {
1892 /* Enable mirroring to port across VLANs (bit 11) */
1893 sw_w32(1 << 11 | (mirror->to_local_port << 4) | 1, ctrl_reg);
1894 } else {
1895 /* Enable mirroring to destination port */
1896 sw_w32((mirror->to_local_port << 4) | 1, ctrl_reg);
1897 }
1898
1899 if (ingress && (priv->r->get_port_reg_be(spm_reg) & (1ULL << port))) {
1900 mutex_unlock(&priv->reg_mutex);
1901 return -EEXIST;
1902 }
1903 if ((!ingress) && (priv->r->get_port_reg_be(dpm_reg) & (1ULL << port))) {
1904 mutex_unlock(&priv->reg_mutex);
1905 return -EEXIST;
1906 }
1907
1908 if (ingress)
1909 priv->r->mask_port_reg_be(0, 1ULL << port, spm_reg);
1910 else
1911 priv->r->mask_port_reg_be(0, 1ULL << port, dpm_reg);
1912
1913 priv->mirror_group_ports[group] = mirror->to_local_port;
1914 mutex_unlock(&priv->reg_mutex);
1915
1916 return 0;
1917 }
1918
1919 static void rtl83xx_port_mirror_del(struct dsa_switch *ds, int port,
1920 struct dsa_mall_mirror_tc_entry *mirror)
1921 {
1922 int group = 0;
1923 struct rtl838x_switch_priv *priv = ds->priv;
1924 int ctrl_reg, dpm_reg, spm_reg;
1925
1926 pr_debug("In %s\n", __func__);
1927 for (group = 0; group < 4; group++) {
1928 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1929 break;
1930 }
1931 if (group >= 4)
1932 return;
1933
1934 ctrl_reg = priv->r->mir_ctrl + group * 4;
1935 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1936 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1937
1938 mutex_lock(&priv->reg_mutex);
1939 if (mirror->ingress) {
1940 /* Ingress, clear source port matrix */
1941 priv->r->mask_port_reg_be(1ULL << port, 0, spm_reg);
1942 } else {
1943 /* Egress, clear destination port matrix */
1944 priv->r->mask_port_reg_be(1ULL << port, 0, dpm_reg);
1945 }
1946
1947 if (!(sw_r32(spm_reg) || sw_r32(dpm_reg))) {
1948 priv->mirror_group_ports[group] = -1;
1949 sw_w32(0, ctrl_reg);
1950 }
1951
1952 mutex_unlock(&priv->reg_mutex);
1953 }
1954
1955 static int rtl83xx_port_pre_bridge_flags(struct dsa_switch *ds, int port, struct switchdev_brport_flags flags, struct netlink_ext_ack *extack)
1956 {
1957 struct rtl838x_switch_priv *priv = ds->priv;
1958 unsigned long features = 0;
1959 pr_debug("%s: %d %lX\n", __func__, port, flags.val);
1960 if (priv->r->enable_learning)
1961 features |= BR_LEARNING;
1962 if (priv->r->enable_flood)
1963 features |= BR_FLOOD;
1964 if (priv->r->enable_mcast_flood)
1965 features |= BR_MCAST_FLOOD;
1966 if (priv->r->enable_bcast_flood)
1967 features |= BR_BCAST_FLOOD;
1968 if (flags.mask & ~(features))
1969 return -EINVAL;
1970
1971 return 0;
1972 }
1973
1974 static int rtl83xx_port_bridge_flags(struct dsa_switch *ds, int port, struct switchdev_brport_flags flags, struct netlink_ext_ack *extack)
1975 {
1976 struct rtl838x_switch_priv *priv = ds->priv;
1977
1978 pr_debug("%s: %d %lX\n", __func__, port, flags.val);
1979 if (priv->r->enable_learning && (flags.mask & BR_LEARNING))
1980 priv->r->enable_learning(port, !!(flags.val & BR_LEARNING));
1981
1982 if (priv->r->enable_flood && (flags.mask & BR_FLOOD))
1983 priv->r->enable_flood(port, !!(flags.val & BR_FLOOD));
1984
1985 if (priv->r->enable_mcast_flood && (flags.mask & BR_MCAST_FLOOD))
1986 priv->r->enable_mcast_flood(port, !!(flags.val & BR_MCAST_FLOOD));
1987
1988 if (priv->r->enable_bcast_flood && (flags.mask & BR_BCAST_FLOOD))
1989 priv->r->enable_bcast_flood(port, !!(flags.val & BR_BCAST_FLOOD));
1990
1991 return 0;
1992 }
1993
1994 static bool rtl83xx_lag_can_offload(struct dsa_switch *ds,
1995 struct net_device *lag,
1996 struct netdev_lag_upper_info *info)
1997 {
1998 int id;
1999
2000 id = dsa_lag_id(ds->dst, lag);
2001 if (id < 0 || id >= ds->num_lag_ids)
2002 return false;
2003
2004 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
2005 return false;
2006 }
2007 if (info->hash_type != NETDEV_LAG_HASH_L2 && info->hash_type != NETDEV_LAG_HASH_L23)
2008 return false;
2009
2010 return true;
2011 }
2012
2013 static int rtl83xx_port_lag_change(struct dsa_switch *ds, int port)
2014 {
2015 struct rtl838x_switch_priv *priv = ds->priv;
2016
2017 pr_debug("%s: %d\n", __func__, port);
2018 /* Nothing to be done... */
2019
2020 return 0;
2021 }
2022
2023 static int rtl83xx_port_lag_join(struct dsa_switch *ds, int port,
2024 struct net_device *lag,
2025 struct netdev_lag_upper_info *info)
2026 {
2027 struct rtl838x_switch_priv *priv = ds->priv;
2028 int i, err = 0;
2029
2030 if (!rtl83xx_lag_can_offload(ds, lag, info))
2031 return -EOPNOTSUPP;
2032
2033 mutex_lock(&priv->reg_mutex);
2034
2035 for (i = 0; i < priv->n_lags; i++) {
2036 if ((!priv->lag_devs[i]) || (priv->lag_devs[i] == lag))
2037 break;
2038 }
2039 if (port >= priv->cpu_port) {
2040 err = -EINVAL;
2041 goto out;
2042 }
2043 pr_info("port_lag_join: group %d, port %d\n",i, port);
2044 if (!priv->lag_devs[i])
2045 priv->lag_devs[i] = lag;
2046
2047 if (priv->lag_primary[i] == -1) {
2048 priv->lag_primary[i] = port;
2049 } else
2050 priv->is_lagmember[port] = 1;
2051
2052 priv->lagmembers |= (1ULL << port);
2053
2054 pr_debug("lag_members = %llX\n", priv->lagmembers);
2055 err = rtl83xx_lag_add(priv->ds, i, port, info);
2056 if (err) {
2057 err = -EINVAL;
2058 goto out;
2059 }
2060
2061 out:
2062 mutex_unlock(&priv->reg_mutex);
2063
2064 return err;
2065 }
2066
2067 static int rtl83xx_port_lag_leave(struct dsa_switch *ds, int port,
2068 struct net_device *lag)
2069 {
2070 int i, group = -1, err;
2071 struct rtl838x_switch_priv *priv = ds->priv;
2072
2073 mutex_lock(&priv->reg_mutex);
2074 for (i = 0; i < priv->n_lags; i++) {
2075 if (priv->lags_port_members[i] & BIT_ULL(port)) {
2076 group = i;
2077 break;
2078 }
2079 }
2080
2081 if (group == -1) {
2082 pr_info("port_lag_leave: port %d is not a member\n", port);
2083 err = -EINVAL;
2084 goto out;
2085 }
2086
2087 if (port >= priv->cpu_port) {
2088 err = -EINVAL;
2089 goto out;
2090 }
2091 pr_info("port_lag_del: group %d, port %d\n",group, port);
2092 priv->lagmembers &=~ (1ULL << port);
2093 priv->lag_primary[i] = -1;
2094 priv->is_lagmember[port] = 0;
2095 pr_debug("lag_members = %llX\n", priv->lagmembers);
2096 err = rtl83xx_lag_del(priv->ds, group, port);
2097 if (err) {
2098 err = -EINVAL;
2099 goto out;
2100 }
2101 if (!priv->lags_port_members[i])
2102 priv->lag_devs[i] = NULL;
2103
2104 out:
2105 mutex_unlock(&priv->reg_mutex);
2106 return 0;
2107 }
2108
2109 int dsa_phy_read(struct dsa_switch *ds, int phy_addr, int phy_reg)
2110 {
2111 u32 val;
2112 u32 offset = 0;
2113 struct rtl838x_switch_priv *priv = ds->priv;
2114
2115 if ((phy_addr >= 24) &&
2116 (phy_addr <= 27) &&
2117 (priv->ports[24].phy == PHY_RTL838X_SDS)) {
2118 if (phy_addr == 26)
2119 offset = 0x100;
2120 val = sw_r32(RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2)) & 0xffff;
2121 return val;
2122 }
2123
2124 read_phy(phy_addr, 0, phy_reg, &val);
2125 return val;
2126 }
2127
2128 int dsa_phy_write(struct dsa_switch *ds, int phy_addr, int phy_reg, u16 val)
2129 {
2130 u32 offset = 0;
2131 struct rtl838x_switch_priv *priv = ds->priv;
2132
2133 if ((phy_addr >= 24) &&
2134 (phy_addr <= 27) &&
2135 (priv->ports[24].phy == PHY_RTL838X_SDS)) {
2136 if (phy_addr == 26)
2137 offset = 0x100;
2138 sw_w32(val, RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2));
2139 return 0;
2140 }
2141 return write_phy(phy_addr, 0, phy_reg, val);
2142 }
2143
2144 const struct dsa_switch_ops rtl83xx_switch_ops = {
2145 .get_tag_protocol = rtl83xx_get_tag_protocol,
2146 .setup = rtl83xx_setup,
2147
2148 .phy_read = dsa_phy_read,
2149 .phy_write = dsa_phy_write,
2150
2151 .phylink_validate = rtl83xx_phylink_validate,
2152 .phylink_mac_link_state = rtl83xx_phylink_mac_link_state,
2153 .phylink_mac_config = rtl83xx_phylink_mac_config,
2154 .phylink_mac_link_down = rtl83xx_phylink_mac_link_down,
2155 .phylink_mac_link_up = rtl83xx_phylink_mac_link_up,
2156
2157 .get_strings = rtl83xx_get_strings,
2158 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
2159 .get_sset_count = rtl83xx_get_sset_count,
2160
2161 .port_enable = rtl83xx_port_enable,
2162 .port_disable = rtl83xx_port_disable,
2163
2164 .get_mac_eee = rtl83xx_get_mac_eee,
2165 .set_mac_eee = rtl83xx_set_mac_eee,
2166
2167 .set_ageing_time = rtl83xx_set_ageing_time,
2168 .port_bridge_join = rtl83xx_port_bridge_join,
2169 .port_bridge_leave = rtl83xx_port_bridge_leave,
2170 .port_stp_state_set = rtl83xx_port_stp_state_set,
2171 .port_fast_age = rtl83xx_fast_age,
2172
2173 .port_vlan_filtering = rtl83xx_vlan_filtering,
2174 .port_vlan_add = rtl83xx_vlan_add,
2175 .port_vlan_del = rtl83xx_vlan_del,
2176
2177 .port_fdb_add = rtl83xx_port_fdb_add,
2178 .port_fdb_del = rtl83xx_port_fdb_del,
2179 .port_fdb_dump = rtl83xx_port_fdb_dump,
2180
2181 .port_mdb_add = rtl83xx_port_mdb_add,
2182 .port_mdb_del = rtl83xx_port_mdb_del,
2183
2184 .port_mirror_add = rtl83xx_port_mirror_add,
2185 .port_mirror_del = rtl83xx_port_mirror_del,
2186
2187 .port_lag_change = rtl83xx_port_lag_change,
2188 .port_lag_join = rtl83xx_port_lag_join,
2189 .port_lag_leave = rtl83xx_port_lag_leave,
2190
2191 .port_pre_bridge_flags = rtl83xx_port_pre_bridge_flags,
2192 .port_bridge_flags = rtl83xx_port_bridge_flags,
2193 };
2194
2195 const struct dsa_switch_ops rtl930x_switch_ops = {
2196 .get_tag_protocol = rtl83xx_get_tag_protocol,
2197 .setup = rtl93xx_setup,
2198
2199 .phy_read = dsa_phy_read,
2200 .phy_write = dsa_phy_write,
2201
2202 .phylink_validate = rtl93xx_phylink_validate,
2203 .phylink_mac_link_state = rtl93xx_phylink_mac_link_state,
2204 .phylink_mac_config = rtl93xx_phylink_mac_config,
2205 .phylink_mac_link_down = rtl93xx_phylink_mac_link_down,
2206 .phylink_mac_link_up = rtl93xx_phylink_mac_link_up,
2207
2208 .get_strings = rtl83xx_get_strings,
2209 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
2210 .get_sset_count = rtl83xx_get_sset_count,
2211
2212 .port_enable = rtl83xx_port_enable,
2213 .port_disable = rtl83xx_port_disable,
2214
2215 .get_mac_eee = rtl93xx_get_mac_eee,
2216 .set_mac_eee = rtl83xx_set_mac_eee,
2217
2218 .set_ageing_time = rtl83xx_set_ageing_time,
2219 .port_bridge_join = rtl83xx_port_bridge_join,
2220 .port_bridge_leave = rtl83xx_port_bridge_leave,
2221 .port_stp_state_set = rtl83xx_port_stp_state_set,
2222 .port_fast_age = rtl930x_fast_age,
2223
2224 .port_vlan_filtering = rtl83xx_vlan_filtering,
2225 .port_vlan_add = rtl83xx_vlan_add,
2226 .port_vlan_del = rtl83xx_vlan_del,
2227
2228 .port_fdb_add = rtl83xx_port_fdb_add,
2229 .port_fdb_del = rtl83xx_port_fdb_del,
2230 .port_fdb_dump = rtl83xx_port_fdb_dump,
2231
2232 .port_mdb_add = rtl83xx_port_mdb_add,
2233 .port_mdb_del = rtl83xx_port_mdb_del,
2234
2235 .port_lag_change = rtl83xx_port_lag_change,
2236 .port_lag_join = rtl83xx_port_lag_join,
2237 .port_lag_leave = rtl83xx_port_lag_leave,
2238
2239 .port_pre_bridge_flags = rtl83xx_port_pre_bridge_flags,
2240 .port_bridge_flags = rtl83xx_port_bridge_flags,
2241 };
Staging tree of Jo-Philipp Wich