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[openwrt/staging/jow.git] / target / linux / realtek / files-5.15 / drivers / net / dsa / rtl83xx / common.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <linux/of_mdio.h>
4 #include <linux/of_platform.h>
5 #include <net/arp.h>
6 #include <net/nexthop.h>
7 #include <net/neighbour.h>
8 #include <net/netevent.h>
9 #include <linux/inetdevice.h>
10 #include <linux/rhashtable.h>
11 #include <linux/of_net.h>
12
13 #include <asm/mach-rtl838x/mach-rtl83xx.h>
14 #include "rtl83xx.h"
15
16 extern struct rtl83xx_soc_info soc_info;
17
18 extern const struct rtl838x_reg rtl838x_reg;
19 extern const struct rtl838x_reg rtl839x_reg;
20 extern const struct rtl838x_reg rtl930x_reg;
21 extern const struct rtl838x_reg rtl931x_reg;
22
23 extern const struct dsa_switch_ops rtl83xx_switch_ops;
24 extern const struct dsa_switch_ops rtl930x_switch_ops;
25
26 DEFINE_MUTEX(smi_lock);
27
28 int rtl83xx_port_get_stp_state(struct rtl838x_switch_priv *priv, int port)
29 {
30 u32 msti = 0;
31 u32 port_state[4];
32 int index, bit;
33 int pos = port;
34 int n = priv->port_width << 1;
35
36 /* Ports above or equal CPU port can never be configured */
37 if (port >= priv->cpu_port)
38 return -1;
39
40 mutex_lock(&priv->reg_mutex);
41
42 /* For the RTL839x and following, the bits are left-aligned in the 64/128 bit field */
43 if (priv->family_id == RTL8390_FAMILY_ID)
44 pos += 12;
45 if (priv->family_id == RTL9300_FAMILY_ID)
46 pos += 3;
47 if (priv->family_id == RTL9310_FAMILY_ID)
48 pos += 8;
49
50 index = n - (pos >> 4) - 1;
51 bit = (pos << 1) % 32;
52
53 priv->r->stp_get(priv, msti, port_state);
54
55 mutex_unlock(&priv->reg_mutex);
56
57 return (port_state[index] >> bit) & 3;
58 }
59
60 static struct table_reg rtl838x_tbl_regs[] = {
61 TBL_DESC(0x6900, 0x6908, 3, 15, 13, 1), // RTL8380_TBL_L2
62 TBL_DESC(0x6914, 0x6918, 18, 14, 12, 1), // RTL8380_TBL_0
63 TBL_DESC(0xA4C8, 0xA4CC, 6, 14, 12, 1), // RTL8380_TBL_1
64
65 TBL_DESC(0x1180, 0x1184, 3, 16, 14, 0), // RTL8390_TBL_L2
66 TBL_DESC(0x1190, 0x1194, 17, 15, 12, 0), // RTL8390_TBL_0
67 TBL_DESC(0x6B80, 0x6B84, 4, 14, 12, 0), // RTL8390_TBL_1
68 TBL_DESC(0x611C, 0x6120, 9, 8, 6, 0), // RTL8390_TBL_2
69
70 TBL_DESC(0xB320, 0xB334, 3, 18, 16, 0), // RTL9300_TBL_L2
71 TBL_DESC(0xB340, 0xB344, 19, 16, 12, 0), // RTL9300_TBL_0
72 TBL_DESC(0xB3A0, 0xB3A4, 20, 16, 13, 0), // RTL9300_TBL_1
73 TBL_DESC(0xCE04, 0xCE08, 6, 14, 12, 0), // RTL9300_TBL_2
74 TBL_DESC(0xD600, 0xD604, 30, 7, 6, 0), // RTL9300_TBL_HSB
75 TBL_DESC(0x7880, 0x7884, 22, 9, 8, 0), // RTL9300_TBL_HSA
76
77 TBL_DESC(0x8500, 0x8508, 8, 19, 15, 0), // RTL9310_TBL_0
78 TBL_DESC(0x40C0, 0x40C4, 22, 16, 14, 0), // RTL9310_TBL_1
79 TBL_DESC(0x8528, 0x852C, 6, 18, 14, 0), // RTL9310_TBL_2
80 TBL_DESC(0x0200, 0x0204, 9, 15, 12, 0), // RTL9310_TBL_3
81 TBL_DESC(0x20dc, 0x20e0, 29, 7, 6, 0), // RTL9310_TBL_4
82 TBL_DESC(0x7e1c, 0x7e20, 53, 8, 6, 0), // RTL9310_TBL_5
83 };
84
85 void rtl_table_init(void)
86 {
87 int i;
88
89 for (i = 0; i < RTL_TBL_END; i++)
90 mutex_init(&rtl838x_tbl_regs[i].lock);
91 }
92
93 /*
94 * Request access to table t in table access register r
95 * Returns a handle to a lock for that table
96 */
97 struct table_reg *rtl_table_get(rtl838x_tbl_reg_t r, int t)
98 {
99 if (r >= RTL_TBL_END)
100 return NULL;
101
102 if (t >= BIT(rtl838x_tbl_regs[r].c_bit-rtl838x_tbl_regs[r].t_bit))
103 return NULL;
104
105 mutex_lock(&rtl838x_tbl_regs[r].lock);
106 rtl838x_tbl_regs[r].tbl = t;
107
108 return &rtl838x_tbl_regs[r];
109 }
110
111 /*
112 * Release a table r, unlock the corresponding lock
113 */
114 void rtl_table_release(struct table_reg *r)
115 {
116 if (!r)
117 return;
118
119 // pr_info("Unlocking %08x\n", (u32)r);
120 mutex_unlock(&r->lock);
121 // pr_info("Unlock done\n");
122 }
123
124 static int rtl_table_exec(struct table_reg *r, bool is_write, int idx)
125 {
126 int ret = 0;
127 u32 cmd, val;
128
129 /* Read/write bit has inverted meaning on RTL838x */
130 if (r->rmode)
131 cmd = is_write ? 0 : BIT(r->c_bit);
132 else
133 cmd = is_write ? BIT(r->c_bit) : 0;
134
135 cmd |= BIT(r->c_bit + 1); /* Execute bit */
136 cmd |= r->tbl << r->t_bit; /* Table type */
137 cmd |= idx & (BIT(r->t_bit) - 1); /* Index */
138
139 sw_w32(cmd, r->addr);
140
141 ret = readx_poll_timeout(sw_r32, r->addr, val,
142 !(val & BIT(r->c_bit + 1)), 20, 10000);
143 if (ret)
144 pr_err("%s: timeout\n", __func__);
145
146 return ret;
147 }
148
149 /*
150 * Reads table index idx into the data registers of the table
151 */
152 int rtl_table_read(struct table_reg *r, int idx)
153 {
154 return rtl_table_exec(r, false, idx);
155 }
156
157 /*
158 * Writes the content of the table data registers into the table at index idx
159 */
160 int rtl_table_write(struct table_reg *r, int idx)
161 {
162 return rtl_table_exec(r, true, idx);
163 }
164
165 /*
166 * Returns the address of the ith data register of table register r
167 * the address is relative to the beginning of the Switch-IO block at 0xbb000000
168 */
169 inline u16 rtl_table_data(struct table_reg *r, int i)
170 {
171 if (i >= r->max_data)
172 i = r->max_data - 1;
173 return r->data + i * 4;
174 }
175
176 inline u32 rtl_table_data_r(struct table_reg *r, int i)
177 {
178 return sw_r32(rtl_table_data(r, i));
179 }
180
181 inline void rtl_table_data_w(struct table_reg *r, u32 v, int i)
182 {
183 sw_w32(v, rtl_table_data(r, i));
184 }
185
186 /* Port register accessor functions for the RTL838x and RTL930X SoCs */
187 void rtl838x_mask_port_reg(u64 clear, u64 set, int reg)
188 {
189 sw_w32_mask((u32)clear, (u32)set, reg);
190 }
191
192 void rtl838x_set_port_reg(u64 set, int reg)
193 {
194 sw_w32((u32)set, reg);
195 }
196
197 u64 rtl838x_get_port_reg(int reg)
198 {
199 return ((u64) sw_r32(reg));
200 }
201
202 /* Port register accessor functions for the RTL839x and RTL931X SoCs */
203 void rtl839x_mask_port_reg_be(u64 clear, u64 set, int reg)
204 {
205 sw_w32_mask((u32)(clear >> 32), (u32)(set >> 32), reg);
206 sw_w32_mask((u32)(clear & 0xffffffff), (u32)(set & 0xffffffff), reg + 4);
207 }
208
209 u64 rtl839x_get_port_reg_be(int reg)
210 {
211 u64 v = sw_r32(reg);
212
213 v <<= 32;
214 v |= sw_r32(reg + 4);
215 return v;
216 }
217
218 void rtl839x_set_port_reg_be(u64 set, int reg)
219 {
220 sw_w32(set >> 32, reg);
221 sw_w32(set & 0xffffffff, reg + 4);
222 }
223
224 void rtl839x_mask_port_reg_le(u64 clear, u64 set, int reg)
225 {
226 sw_w32_mask((u32)clear, (u32)set, reg);
227 sw_w32_mask((u32)(clear >> 32), (u32)(set >> 32), reg + 4);
228 }
229
230 void rtl839x_set_port_reg_le(u64 set, int reg)
231 {
232 sw_w32(set, reg);
233 sw_w32(set >> 32, reg + 4);
234 }
235
236 u64 rtl839x_get_port_reg_le(int reg)
237 {
238 u64 v = sw_r32(reg + 4);
239
240 v <<= 32;
241 v |= sw_r32(reg);
242 return v;
243 }
244
245 int read_phy(u32 port, u32 page, u32 reg, u32 *val)
246 {
247 switch (soc_info.family) {
248 case RTL8380_FAMILY_ID:
249 return rtl838x_read_phy(port, page, reg, val);
250 case RTL8390_FAMILY_ID:
251 return rtl839x_read_phy(port, page, reg, val);
252 case RTL9300_FAMILY_ID:
253 return rtl930x_read_phy(port, page, reg, val);
254 case RTL9310_FAMILY_ID:
255 return rtl931x_read_phy(port, page, reg, val);
256 }
257 return -1;
258 }
259
260 int write_phy(u32 port, u32 page, u32 reg, u32 val)
261 {
262 switch (soc_info.family) {
263 case RTL8380_FAMILY_ID:
264 return rtl838x_write_phy(port, page, reg, val);
265 case RTL8390_FAMILY_ID:
266 return rtl839x_write_phy(port, page, reg, val);
267 case RTL9300_FAMILY_ID:
268 return rtl930x_write_phy(port, page, reg, val);
269 case RTL9310_FAMILY_ID:
270 return rtl931x_write_phy(port, page, reg, val);
271 }
272 return -1;
273 }
274
275 static int __init rtl83xx_mdio_probe(struct rtl838x_switch_priv *priv)
276 {
277 struct device *dev = priv->dev;
278 struct device_node *dn, *phy_node, *mii_np = dev->of_node;
279 struct mii_bus *bus;
280 int ret;
281 u32 pn;
282
283 pr_debug("In %s\n", __func__);
284 mii_np = of_find_compatible_node(NULL, NULL, "realtek,rtl838x-mdio");
285 if (mii_np) {
286 pr_debug("Found compatible MDIO node!\n");
287 } else {
288 dev_err(priv->dev, "no %s child node found", "mdio-bus");
289 return -ENODEV;
290 }
291
292 priv->mii_bus = of_mdio_find_bus(mii_np);
293 if (!priv->mii_bus) {
294 pr_debug("Deferring probe of mdio bus\n");
295 return -EPROBE_DEFER;
296 }
297 if (!of_device_is_available(mii_np))
298 ret = -ENODEV;
299
300 bus = devm_mdiobus_alloc(priv->ds->dev);
301 if (!bus)
302 return -ENOMEM;
303
304 bus->name = "rtl838x slave mii";
305
306 /*
307 * Since the NIC driver is loaded first, we can use the mdio rw functions
308 * assigned there.
309 */
310 bus->read = priv->mii_bus->read;
311 bus->write = priv->mii_bus->write;
312 bus->read_paged = priv->mii_bus->read_paged;
313 bus->write_paged = priv->mii_bus->write_paged;
314 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d", bus->name, dev->id);
315
316 bus->parent = dev;
317 priv->ds->slave_mii_bus = bus;
318 priv->ds->slave_mii_bus->priv = priv->mii_bus->priv;
319 priv->ds->slave_mii_bus->access_capabilities = priv->mii_bus->access_capabilities;
320
321 ret = mdiobus_register(priv->ds->slave_mii_bus);
322 if (ret && mii_np) {
323 of_node_put(dn);
324 return ret;
325 }
326
327 dn = of_find_compatible_node(NULL, NULL, "realtek,rtl83xx-switch");
328 if (!dn) {
329 dev_err(priv->dev, "No RTL switch node in DTS\n");
330 return -ENODEV;
331 }
332
333 for_each_node_by_name(dn, "port") {
334 phy_interface_t interface;
335 u32 led_set;
336
337 if (!of_device_is_available(dn))
338 continue;
339
340 if (of_property_read_u32(dn, "reg", &pn))
341 continue;
342
343 phy_node = of_parse_phandle(dn, "phy-handle", 0);
344 if (!phy_node) {
345 if (pn != priv->cpu_port)
346 dev_err(priv->dev, "Port node %d misses phy-handle\n", pn);
347 continue;
348 }
349
350 if (of_property_read_u32(phy_node, "sds", &priv->ports[pn].sds_num))
351 priv->ports[pn].sds_num = -1;
352 pr_debug("%s port %d has SDS %d\n", __func__, pn, priv->ports[pn].sds_num);
353
354 if (of_get_phy_mode(dn, &interface))
355 interface = PHY_INTERFACE_MODE_NA;
356 if (interface == PHY_INTERFACE_MODE_HSGMII)
357 priv->ports[pn].is2G5 = true;
358 if (interface == PHY_INTERFACE_MODE_USXGMII)
359 priv->ports[pn].is2G5 = priv->ports[pn].is10G = true;
360 if (interface == PHY_INTERFACE_MODE_10GBASER)
361 priv->ports[pn].is10G = true;
362
363 if (of_property_read_u32(dn, "led-set", &led_set))
364 led_set = 0;
365 priv->ports[pn].led_set = led_set;
366
367 // Check for the integrated SerDes of the RTL8380M first
368 if (of_property_read_bool(phy_node, "phy-is-integrated")
369 && priv->id == 0x8380 && pn >= 24) {
370 pr_debug("----> FÓUND A SERDES\n");
371 priv->ports[pn].phy = PHY_RTL838X_SDS;
372 continue;
373 }
374
375 if (priv->id >= 0x9300) {
376 priv->ports[pn].phy_is_integrated = false;
377 if (of_property_read_bool(phy_node, "phy-is-integrated")) {
378 priv->ports[pn].phy_is_integrated = true;
379 priv->ports[pn].phy = PHY_RTL930X_SDS;
380 }
381 } else {
382 if (of_property_read_bool(phy_node, "phy-is-integrated")
383 && !of_property_read_bool(phy_node, "sfp")) {
384 priv->ports[pn].phy = PHY_RTL8218B_INT;
385 continue;
386 }
387 }
388
389 if (!of_property_read_bool(phy_node, "phy-is-integrated")
390 && of_property_read_bool(phy_node, "sfp")) {
391 priv->ports[pn].phy = PHY_RTL8214FC;
392 continue;
393 }
394
395 if (!of_property_read_bool(phy_node, "phy-is-integrated")
396 && !of_property_read_bool(phy_node, "sfp")) {
397 priv->ports[pn].phy = PHY_RTL8218B_EXT;
398 continue;
399 }
400 }
401
402 /* Disable MAC polling the PHY so that we can start configuration */
403 priv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl);
404
405 /* Enable PHY control via SoC */
406 if (priv->family_id == RTL8380_FAMILY_ID) {
407 /* Enable SerDes NWAY and PHY control via SoC */
408 sw_w32_mask(BIT(7), BIT(15), RTL838X_SMI_GLB_CTRL);
409 } else if (priv->family_id == RTL8390_FAMILY_ID) {
410 /* Disable PHY polling via SoC */
411 sw_w32_mask(BIT(7), 0, RTL839X_SMI_GLB_CTRL);
412 }
413
414 /* Power on fibre ports and reset them if necessary */
415 if (priv->ports[24].phy == PHY_RTL838X_SDS) {
416 pr_debug("Powering on fibre ports & reset\n");
417 rtl8380_sds_power(24, 1);
418 rtl8380_sds_power(26, 1);
419 }
420
421 pr_debug("%s done\n", __func__);
422 return 0;
423 }
424
425 static int __init rtl83xx_get_l2aging(struct rtl838x_switch_priv *priv)
426 {
427 int t = sw_r32(priv->r->l2_ctrl_1);
428
429 t &= priv->family_id == RTL8380_FAMILY_ID ? 0x7fffff : 0x1FFFFF;
430
431 if (priv->family_id == RTL8380_FAMILY_ID)
432 t = t * 128 / 625; /* Aging time in seconds. 0: L2 aging disabled */
433 else
434 t = (t * 3) / 5;
435
436 pr_debug("L2 AGING time: %d sec\n", t);
437 pr_debug("Dynamic aging for ports: %x\n", sw_r32(priv->r->l2_port_aging_out));
438 return t;
439 }
440
441 /* Caller must hold priv->reg_mutex */
442 int rtl83xx_lag_add(struct dsa_switch *ds, int group, int port, struct netdev_lag_upper_info *info)
443 {
444 struct rtl838x_switch_priv *priv = ds->priv;
445 int i;
446 u32 algomsk = 0;
447 u32 algoidx = 0;
448
449 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
450 pr_err("%s: Only mode LACP 802.3ad (4) allowed.\n", __func__);
451 return -EINVAL;
452 }
453
454 if (group >= priv->n_lags) {
455 pr_err("%s: LAG %d invalid.\n", __func__, group);
456 return -EINVAL;
457 }
458
459 if (port >= priv->cpu_port) {
460 pr_err("%s: Port %d invalid.\n", __func__, port);
461 return -EINVAL;
462 }
463
464 for (i = 0; i < priv->n_lags; i++) {
465 if (priv->lags_port_members[i] & BIT_ULL(port))
466 break;
467 }
468 if (i != priv->n_lags) {
469 pr_err("%s: Port %d already member of LAG %d.\n", __func__, port, i);
470 return -ENOSPC;
471 }
472 switch(info->hash_type) {
473 case NETDEV_LAG_HASH_L2:
474 algomsk |= TRUNK_DISTRIBUTION_ALGO_DMAC_BIT;
475 algomsk |= TRUNK_DISTRIBUTION_ALGO_SMAC_BIT;
476 break;
477 case NETDEV_LAG_HASH_L23:
478 algomsk |= TRUNK_DISTRIBUTION_ALGO_DMAC_BIT;
479 algomsk |= TRUNK_DISTRIBUTION_ALGO_SMAC_BIT;
480 algomsk |= TRUNK_DISTRIBUTION_ALGO_SIP_BIT; //source ip
481 algomsk |= TRUNK_DISTRIBUTION_ALGO_DIP_BIT; //dest ip
482 algoidx = 1;
483 break;
484 case NETDEV_LAG_HASH_L34:
485 algomsk |= TRUNK_DISTRIBUTION_ALGO_SRC_L4PORT_BIT; //sport
486 algomsk |= TRUNK_DISTRIBUTION_ALGO_DST_L4PORT_BIT; //dport
487 algomsk |= TRUNK_DISTRIBUTION_ALGO_SIP_BIT; //source ip
488 algomsk |= TRUNK_DISTRIBUTION_ALGO_DIP_BIT; //dest ip
489 algoidx = 2;
490 break;
491 default:
492 algomsk |= 0x7f;
493 }
494 priv->r->set_distribution_algorithm(group, algoidx, algomsk);
495 priv->r->mask_port_reg_be(0, BIT_ULL(port), priv->r->trk_mbr_ctr(group));
496 priv->lags_port_members[group] |= BIT_ULL(port);
497
498 pr_info("%s: Added port %d to LAG %d. Members now %016llx.\n",
499 __func__, port, group, priv->lags_port_members[group]);
500 return 0;
501 }
502
503 /* Caller must hold priv->reg_mutex */
504 int rtl83xx_lag_del(struct dsa_switch *ds, int group, int port)
505 {
506 struct rtl838x_switch_priv *priv = ds->priv;
507
508 if (group >= priv->n_lags) {
509 pr_err("%s: LAG %d invalid.\n", __func__, group);
510 return -EINVAL;
511 }
512
513 if (port >= priv->cpu_port) {
514 pr_err("%s: Port %d invalid.\n", __func__, port);
515 return -EINVAL;
516 }
517
518 if (!(priv->lags_port_members[group] & BIT_ULL(port))) {
519 pr_err("%s: Port %d not member of LAG %d.\n", __func__, port, group);
520 return -ENOSPC;
521 }
522
523 // 0x7f algo mask all
524 priv->r->mask_port_reg_be(BIT_ULL(port), 0, priv->r->trk_mbr_ctr(group));
525 priv->lags_port_members[group] &= ~BIT_ULL(port);
526
527 pr_info("%s: Removed port %d from LAG %d. Members now %016llx.\n",
528 __func__, port, group, priv->lags_port_members[group]);
529 return 0;
530 }
531
532 /*
533 * Allocate a 64 bit octet counter located in the LOG HW table
534 */
535 static int rtl83xx_octet_cntr_alloc(struct rtl838x_switch_priv *priv)
536 {
537 int idx;
538
539 mutex_lock(&priv->reg_mutex);
540
541 idx = find_first_zero_bit(priv->octet_cntr_use_bm, MAX_COUNTERS);
542 if (idx >= priv->n_counters) {
543 mutex_unlock(&priv->reg_mutex);
544 return -1;
545 }
546
547 set_bit(idx, priv->octet_cntr_use_bm);
548 mutex_unlock(&priv->reg_mutex);
549
550 return idx;
551 }
552
553 /*
554 * Allocate a 32-bit packet counter
555 * 2 32-bit packet counters share the location of a 64-bit octet counter
556 * Initially there are no free packet counters and 2 new ones need to be freed
557 * by allocating the corresponding octet counter
558 */
559 int rtl83xx_packet_cntr_alloc(struct rtl838x_switch_priv *priv)
560 {
561 int idx, j;
562
563 mutex_lock(&priv->reg_mutex);
564
565 /* Because initially no packet counters are free, the logic is reversed:
566 * a 0-bit means the counter is already allocated (for octets)
567 */
568 idx = find_first_bit(priv->packet_cntr_use_bm, MAX_COUNTERS * 2);
569 if (idx >= priv->n_counters * 2) {
570 j = find_first_zero_bit(priv->octet_cntr_use_bm, MAX_COUNTERS);
571 if (j >= priv->n_counters) {
572 mutex_unlock(&priv->reg_mutex);
573 return -1;
574 }
575 set_bit(j, priv->octet_cntr_use_bm);
576 idx = j * 2;
577 set_bit(j * 2 + 1, priv->packet_cntr_use_bm);
578
579 } else {
580 clear_bit(idx, priv->packet_cntr_use_bm);
581 }
582
583 mutex_unlock(&priv->reg_mutex);
584
585 return idx;
586 }
587
588 /*
589 * Add an L2 nexthop entry for the L3 routing system / PIE forwarding in the SoC
590 * Use VID and MAC in rtl838x_l2_entry to identify either a free slot in the L2 hash table
591 * or mark an existing entry as a nexthop by setting it's nexthop bit
592 * Called from the L3 layer
593 * The index in the L2 hash table is filled into nh->l2_id;
594 */
595 int rtl83xx_l2_nexthop_add(struct rtl838x_switch_priv *priv, struct rtl83xx_nexthop *nh)
596 {
597 struct rtl838x_l2_entry e;
598 u64 seed = priv->r->l2_hash_seed(nh->mac, nh->rvid);
599 u32 key = priv->r->l2_hash_key(priv, seed);
600 int i, idx = -1;
601 u64 entry;
602
603 pr_debug("%s searching for %08llx vid %d with key %d, seed: %016llx\n",
604 __func__, nh->mac, nh->rvid, key, seed);
605
606 e.type = L2_UNICAST;
607 u64_to_ether_addr(nh->mac, &e.mac[0]);
608 e.port = nh->port;
609
610 // Loop over all entries in the hash-bucket and over the second block on 93xx SoCs
611 for (i = 0; i < priv->l2_bucket_size; i++) {
612 entry = priv->r->read_l2_entry_using_hash(key, i, &e);
613
614 if (!e.valid || ((entry & 0x0fffffffffffffffULL) == seed)) {
615 idx = i > 3 ? ((key >> 14) & 0xffff) | i >> 1
616 : ((key << 2) | i) & 0xffff;
617 break;
618 }
619 }
620
621 if (idx < 0) {
622 pr_err("%s: No more L2 forwarding entries available\n", __func__);
623 return -1;
624 }
625
626 // Found an existing (e->valid is true) or empty entry, make it a nexthop entry
627 nh->l2_id = idx;
628 if (e.valid) {
629 nh->port = e.port;
630 nh->vid = e.vid; // Save VID
631 nh->rvid = e.rvid;
632 nh->dev_id = e.stack_dev;
633 // If the entry is already a valid next hop entry, don't change it
634 if (e.next_hop)
635 return 0;
636 } else {
637 e.valid = true;
638 e.is_static = true;
639 e.rvid = nh->rvid;
640 e.is_ip_mc = false;
641 e.is_ipv6_mc = false;
642 e.block_da = false;
643 e.block_sa = false;
644 e.suspended = false;
645 e.age = 0; // With port-ignore
646 e.port = priv->port_ignore;
647 u64_to_ether_addr(nh->mac, &e.mac[0]);
648 }
649 e.next_hop = true;
650 e.nh_route_id = nh->id; // NH route ID takes place of VID
651 e.nh_vlan_target = false;
652
653 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
654
655 return 0;
656 }
657
658 /*
659 * Removes a Layer 2 next hop entry in the forwarding database
660 * If it was static, the entire entry is removed, otherwise the nexthop bit is cleared
661 * and we wait until the entry ages out
662 */
663 int rtl83xx_l2_nexthop_rm(struct rtl838x_switch_priv *priv, struct rtl83xx_nexthop *nh)
664 {
665 struct rtl838x_l2_entry e;
666 u32 key = nh->l2_id >> 2;
667 int i = nh->l2_id & 0x3;
668 u64 entry = entry = priv->r->read_l2_entry_using_hash(key, i, &e);
669
670 pr_debug("%s: id %d, key %d, index %d\n", __func__, nh->l2_id, key, i);
671 if (!e.valid) {
672 dev_err(priv->dev, "unknown nexthop, id %x\n", nh->l2_id);
673 return -1;
674 }
675
676 if (e.is_static)
677 e.valid = false;
678 e.next_hop = false;
679 e.vid = nh->vid; // Restore VID
680 e.rvid = nh->rvid;
681
682 priv->r->write_l2_entry_using_hash(key, i, &e);
683
684 return 0;
685 }
686
687 static int rtl83xx_handle_changeupper(struct rtl838x_switch_priv *priv,
688 struct net_device *ndev,
689 struct netdev_notifier_changeupper_info *info)
690 {
691 struct net_device *upper = info->upper_dev;
692 struct netdev_lag_upper_info *lag_upper_info = NULL;
693 int i, j, err;
694
695 if (!netif_is_lag_master(upper))
696 return 0;
697
698 mutex_lock(&priv->reg_mutex);
699
700 for (i = 0; i < priv->n_lags; i++) {
701 if ((!priv->lag_devs[i]) || (priv->lag_devs[i] == upper))
702 break;
703 }
704 for (j = 0; j < priv->cpu_port; j++) {
705 if (priv->ports[j].dp->slave == ndev)
706 break;
707 }
708 if (j >= priv->cpu_port) {
709 err = -EINVAL;
710 goto out;
711 }
712
713 if (info->linking) {
714 lag_upper_info = info->upper_info;
715 if (!priv->lag_devs[i])
716 priv->lag_devs[i] = upper;
717 err = rtl83xx_lag_add(priv->ds, i, priv->ports[j].dp->index, lag_upper_info);
718 if (err) {
719 err = -EINVAL;
720 goto out;
721 }
722 } else {
723 if (!priv->lag_devs[i])
724 err = -EINVAL;
725 err = rtl83xx_lag_del(priv->ds, i, priv->ports[j].dp->index);
726 if (err) {
727 err = -EINVAL;
728 goto out;
729 }
730 if (!priv->lags_port_members[i])
731 priv->lag_devs[i] = NULL;
732 }
733
734 out:
735 mutex_unlock(&priv->reg_mutex);
736 return 0;
737 }
738
739 /*
740 * Is the lower network device a DSA slave network device of our RTL930X-switch?
741 * Unfortunately we cannot just follow dev->dsa_prt as this is only set for the
742 * DSA master device.
743 */
744 int rtl83xx_port_is_under(const struct net_device * dev, struct rtl838x_switch_priv *priv)
745 {
746 int i;
747
748 // TODO: On 5.12:
749 // if(!dsa_slave_dev_check(dev)) {
750 // netdev_info(dev, "%s: not a DSA device.\n", __func__);
751 // return -EINVAL;
752 // }
753
754 for (i = 0; i < priv->cpu_port; i++) {
755 if (!priv->ports[i].dp)
756 continue;
757 if (priv->ports[i].dp->slave == dev)
758 return i;
759 }
760 return -EINVAL;
761 }
762
763 static int rtl83xx_netdevice_event(struct notifier_block *this,
764 unsigned long event, void *ptr)
765 {
766 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
767 struct rtl838x_switch_priv *priv;
768 int err;
769
770 pr_debug("In: %s, event: %lu\n", __func__, event);
771
772 if ((event != NETDEV_CHANGEUPPER) && (event != NETDEV_CHANGELOWERSTATE))
773 return NOTIFY_DONE;
774
775 priv = container_of(this, struct rtl838x_switch_priv, nb);
776 switch (event) {
777 case NETDEV_CHANGEUPPER:
778 err = rtl83xx_handle_changeupper(priv, ndev, ptr);
779 break;
780 }
781
782 if (err)
783 return err;
784
785 return NOTIFY_DONE;
786 }
787
788 const static struct rhashtable_params route_ht_params = {
789 .key_len = sizeof(u32),
790 .key_offset = offsetof(struct rtl83xx_route, gw_ip),
791 .head_offset = offsetof(struct rtl83xx_route, linkage),
792 };
793
794 /*
795 * Updates an L3 next hop entry in the ROUTING table
796 */
797 static int rtl83xx_l3_nexthop_update(struct rtl838x_switch_priv *priv, __be32 ip_addr, u64 mac)
798 {
799 struct rtl83xx_route *r;
800 struct rhlist_head *tmp, *list;
801
802 rcu_read_lock();
803 list = rhltable_lookup(&priv->routes, &ip_addr, route_ht_params);
804 if (!list) {
805 rcu_read_unlock();
806 return -ENOENT;
807 }
808
809 rhl_for_each_entry_rcu(r, tmp, list, linkage) {
810 pr_info("%s: Setting up fwding: ip %pI4, GW mac %016llx\n",
811 __func__, &ip_addr, mac);
812
813 // Reads the ROUTING table entry associated with the route
814 priv->r->route_read(r->id, r);
815 pr_info("Route with id %d to %pI4 / %d\n", r->id, &r->dst_ip, r->prefix_len);
816
817 r->nh.mac = r->nh.gw = mac;
818 r->nh.port = priv->port_ignore;
819 r->nh.id = r->id;
820
821 // Do we need to explicitly add a DMAC entry with the route's nh index?
822 if (priv->r->set_l3_egress_mac)
823 priv->r->set_l3_egress_mac(r->id, mac);
824
825 // Update ROUTING table: map gateway-mac and switch-mac id to route id
826 rtl83xx_l2_nexthop_add(priv, &r->nh);
827
828 r->attr.valid = true;
829 r->attr.action = ROUTE_ACT_FORWARD;
830 r->attr.type = 0;
831 r->attr.hit = false; // Reset route-used indicator
832
833 // Add PIE entry with dst_ip and prefix_len
834 r->pr.dip = r->dst_ip;
835 r->pr.dip_m = inet_make_mask(r->prefix_len);
836
837 if (r->is_host_route) {
838 int slot = priv->r->find_l3_slot(r, false);
839
840 pr_info("%s: Got slot for route: %d\n", __func__, slot);
841 priv->r->host_route_write(slot, r);
842 } else {
843 priv->r->route_write(r->id, r);
844 r->pr.fwd_sel = true;
845 r->pr.fwd_data = r->nh.l2_id;
846 r->pr.fwd_act = PIE_ACT_ROUTE_UC;
847 }
848
849 if (priv->r->set_l3_nexthop)
850 priv->r->set_l3_nexthop(r->nh.id, r->nh.l2_id, r->nh.if_id);
851
852 if (r->pr.id < 0) {
853 r->pr.packet_cntr = rtl83xx_packet_cntr_alloc(priv);
854 if (r->pr.packet_cntr >= 0) {
855 pr_info("Using packet counter %d\n", r->pr.packet_cntr);
856 r->pr.log_sel = true;
857 r->pr.log_data = r->pr.packet_cntr;
858 }
859 priv->r->pie_rule_add(priv, &r->pr);
860 } else {
861 int pkts = priv->r->packet_cntr_read(r->pr.packet_cntr);
862 pr_info("%s: total packets: %d\n", __func__, pkts);
863
864 priv->r->pie_rule_write(priv, r->pr.id, &r->pr);
865 }
866 }
867 rcu_read_unlock();
868 return 0;
869 }
870
871 static int rtl83xx_port_ipv4_resolve(struct rtl838x_switch_priv *priv,
872 struct net_device *dev, __be32 ip_addr)
873 {
874 struct neighbour *n = neigh_lookup(&arp_tbl, &ip_addr, dev);
875 int err = 0;
876 u64 mac;
877
878 if (!n) {
879 n = neigh_create(&arp_tbl, &ip_addr, dev);
880 if (IS_ERR(n))
881 return PTR_ERR(n);
882 }
883
884 /* If the neigh is already resolved, then go ahead and
885 * install the entry, otherwise start the ARP process to
886 * resolve the neigh.
887 */
888 if (n->nud_state & NUD_VALID) {
889 mac = ether_addr_to_u64(n->ha);
890 pr_info("%s: resolved mac: %016llx\n", __func__, mac);
891 rtl83xx_l3_nexthop_update(priv, ip_addr, mac);
892 } else {
893 pr_info("%s: need to wait\n", __func__);
894 neigh_event_send(n, NULL);
895 }
896
897 neigh_release(n);
898 return err;
899 }
900
901 struct rtl83xx_walk_data {
902 struct rtl838x_switch_priv *priv;
903 int port;
904 };
905
906 static int rtl83xx_port_lower_walk(struct net_device *lower, struct netdev_nested_priv *_priv)
907 {
908 struct rtl83xx_walk_data *data = (struct rtl83xx_walk_data *)_priv->data;
909 struct rtl838x_switch_priv *priv = data->priv;
910 int ret = 0;
911 int index;
912
913 index = rtl83xx_port_is_under(lower, priv);
914 data->port = index;
915 if (index >= 0) {
916 pr_debug("Found DSA-port, index %d\n", index);
917 ret = 1;
918 }
919
920 return ret;
921 }
922
923 int rtl83xx_port_dev_lower_find(struct net_device *dev, struct rtl838x_switch_priv *priv)
924 {
925 struct rtl83xx_walk_data data;
926 struct netdev_nested_priv _priv;
927
928 data.priv = priv;
929 data.port = 0;
930 _priv.data = (void *)&data;
931
932 netdev_walk_all_lower_dev(dev, rtl83xx_port_lower_walk, &_priv);
933
934 return data.port;
935 }
936
937 static struct rtl83xx_route *rtl83xx_route_alloc(struct rtl838x_switch_priv *priv, u32 ip)
938 {
939 struct rtl83xx_route *r;
940 int idx = 0, err;
941
942 mutex_lock(&priv->reg_mutex);
943
944 idx = find_first_zero_bit(priv->route_use_bm, MAX_ROUTES);
945 pr_debug("%s id: %d, ip %pI4\n", __func__, idx, &ip);
946
947 r = kzalloc(sizeof(*r), GFP_KERNEL);
948 if (!r) {
949 mutex_unlock(&priv->reg_mutex);
950 return r;
951 }
952
953 r->id = idx;
954 r->gw_ip = ip;
955 r->pr.id = -1; // We still need to allocate a rule in HW
956 r->is_host_route = false;
957
958 err = rhltable_insert(&priv->routes, &r->linkage, route_ht_params);
959 if (err) {
960 pr_err("Could not insert new rule\n");
961 mutex_unlock(&priv->reg_mutex);
962 goto out_free;
963 }
964
965 set_bit(idx, priv->route_use_bm);
966
967 mutex_unlock(&priv->reg_mutex);
968
969 return r;
970
971 out_free:
972 kfree(r);
973 return NULL;
974 }
975
976
977 static struct rtl83xx_route *rtl83xx_host_route_alloc(struct rtl838x_switch_priv *priv, u32 ip)
978 {
979 struct rtl83xx_route *r;
980 int idx = 0, err;
981
982 mutex_lock(&priv->reg_mutex);
983
984 idx = find_first_zero_bit(priv->host_route_use_bm, MAX_HOST_ROUTES);
985 pr_debug("%s id: %d, ip %pI4\n", __func__, idx, &ip);
986
987 r = kzalloc(sizeof(*r), GFP_KERNEL);
988 if (!r) {
989 mutex_unlock(&priv->reg_mutex);
990 return r;
991 }
992
993 /* We require a unique route ID irrespective of whether it is a prefix or host
994 * route (on RTL93xx) as we use this ID to associate a DMAC and next-hop entry */
995 r->id = idx + MAX_ROUTES;
996
997 r->gw_ip = ip;
998 r->pr.id = -1; // We still need to allocate a rule in HW
999 r->is_host_route = true;
1000
1001 err = rhltable_insert(&priv->routes, &r->linkage, route_ht_params);
1002 if (err) {
1003 pr_err("Could not insert new rule\n");
1004 mutex_unlock(&priv->reg_mutex);
1005 goto out_free;
1006 }
1007
1008 set_bit(idx, priv->host_route_use_bm);
1009
1010 mutex_unlock(&priv->reg_mutex);
1011
1012 return r;
1013
1014 out_free:
1015 kfree(r);
1016 return NULL;
1017 }
1018
1019
1020
1021 static void rtl83xx_route_rm(struct rtl838x_switch_priv *priv, struct rtl83xx_route *r)
1022 {
1023 int id;
1024
1025 if (rhltable_remove(&priv->routes, &r->linkage, route_ht_params))
1026 dev_warn(priv->dev, "Could not remove route\n");
1027
1028 if (r->is_host_route) {
1029 id = priv->r->find_l3_slot(r, false);
1030 pr_debug("%s: Got id for host route: %d\n", __func__, id);
1031 r->attr.valid = false;
1032 priv->r->host_route_write(id, r);
1033 clear_bit(r->id - MAX_ROUTES, priv->host_route_use_bm);
1034 } else {
1035 // If there is a HW representation of the route, delete it
1036 if (priv->r->route_lookup_hw) {
1037 id = priv->r->route_lookup_hw(r);
1038 pr_info("%s: Got id for prefix route: %d\n", __func__, id);
1039 r->attr.valid = false;
1040 priv->r->route_write(id, r);
1041 }
1042 clear_bit(r->id, priv->route_use_bm);
1043 }
1044
1045 kfree(r);
1046 }
1047
1048 static int rtl83xx_fib4_del(struct rtl838x_switch_priv *priv,
1049 struct fib_entry_notifier_info *info)
1050 {
1051 struct fib_nh *nh = fib_info_nh(info->fi, 0);
1052 struct rtl83xx_route *r;
1053 struct rhlist_head *tmp, *list;
1054
1055 pr_debug("In %s, ip %pI4, len %d\n", __func__, &info->dst, info->dst_len);
1056 rcu_read_lock();
1057 list = rhltable_lookup(&priv->routes, &nh->fib_nh_gw4, route_ht_params);
1058 if (!list) {
1059 rcu_read_unlock();
1060 pr_err("%s: no such gateway: %pI4\n", __func__, &nh->fib_nh_gw4);
1061 return -ENOENT;
1062 }
1063 rhl_for_each_entry_rcu(r, tmp, list, linkage) {
1064 if (r->dst_ip == info->dst && r->prefix_len == info->dst_len) {
1065 pr_info("%s: found a route with id %d, nh-id %d\n",
1066 __func__, r->id, r->nh.id);
1067 break;
1068 }
1069 }
1070 rcu_read_unlock();
1071
1072 rtl83xx_l2_nexthop_rm(priv, &r->nh);
1073
1074 pr_debug("%s: Releasing packet counter %d\n", __func__, r->pr.packet_cntr);
1075 set_bit(r->pr.packet_cntr, priv->packet_cntr_use_bm);
1076 priv->r->pie_rule_rm(priv, &r->pr);
1077
1078 rtl83xx_route_rm(priv, r);
1079
1080 nh->fib_nh_flags &= ~RTNH_F_OFFLOAD;
1081
1082 return 0;
1083 }
1084
1085 /*
1086 * On the RTL93xx, an L3 termination endpoint MAC address on which the router waits
1087 * for packets to be routed needs to be allocated.
1088 */
1089 static int rtl83xx_alloc_router_mac(struct rtl838x_switch_priv *priv, u64 mac)
1090 {
1091 int i, free_mac = -1;
1092 struct rtl93xx_rt_mac m;
1093
1094 mutex_lock(&priv->reg_mutex);
1095 for (i = 0; i < MAX_ROUTER_MACS; i++) {
1096 priv->r->get_l3_router_mac(i, &m);
1097 if (free_mac < 0 && !m.valid) {
1098 free_mac = i;
1099 continue;
1100 }
1101 if (m.valid && m.mac == mac) {
1102 free_mac = i;
1103 break;
1104 }
1105 }
1106
1107 if (free_mac < 0) {
1108 pr_err("No free router MACs, cannot offload\n");
1109 mutex_unlock(&priv->reg_mutex);
1110 return -1;
1111 }
1112
1113 m.valid = true;
1114 m.mac = mac;
1115 m.p_type = 0; // An individual port, not a trunk port
1116 m.p_id = 0x3f; // Listen on any port
1117 m.p_id_mask = 0;
1118 m.vid = 0; // Listen on any VLAN...
1119 m.vid_mask = 0; // ... so mask needs to be 0
1120 m.mac_mask = 0xffffffffffffULL; // We want an exact match of the interface MAC
1121 m.action = L3_FORWARD; // Route the packet
1122 priv->r->set_l3_router_mac(free_mac, &m);
1123
1124 mutex_unlock(&priv->reg_mutex);
1125
1126 return 0;
1127 }
1128
1129 static int rtl83xx_alloc_egress_intf(struct rtl838x_switch_priv *priv, u64 mac, int vlan)
1130 {
1131 int i, free_mac = -1;
1132 struct rtl838x_l3_intf intf;
1133 u64 m;
1134
1135 mutex_lock(&priv->reg_mutex);
1136 for (i = 0; i < MAX_SMACS; i++) {
1137 m = priv->r->get_l3_egress_mac(L3_EGRESS_DMACS + i);
1138 if (free_mac < 0 && !m) {
1139 free_mac = i;
1140 continue;
1141 }
1142 if (m == mac) {
1143 mutex_unlock(&priv->reg_mutex);
1144 return i;
1145 }
1146 }
1147
1148 if (free_mac < 0) {
1149 pr_err("No free egress interface, cannot offload\n");
1150 return -1;
1151 }
1152
1153 // Set up default egress interface 1
1154 intf.vid = vlan;
1155 intf.smac_idx = free_mac;
1156 intf.ip4_mtu_id = 1;
1157 intf.ip6_mtu_id = 1;
1158 intf.ttl_scope = 1; // TTL
1159 intf.hl_scope = 1; // Hop Limit
1160 intf.ip4_icmp_redirect = intf.ip6_icmp_redirect = 2; // FORWARD
1161 intf.ip4_pbr_icmp_redirect = intf.ip6_pbr_icmp_redirect = 2; // FORWARD;
1162 priv->r->set_l3_egress_intf(free_mac, &intf);
1163
1164 priv->r->set_l3_egress_mac(L3_EGRESS_DMACS + free_mac, mac);
1165
1166 mutex_unlock(&priv->reg_mutex);
1167
1168 return free_mac;
1169 }
1170
1171 static int rtl83xx_fib4_add(struct rtl838x_switch_priv *priv,
1172 struct fib_entry_notifier_info *info)
1173 {
1174 struct fib_nh *nh = fib_info_nh(info->fi, 0);
1175 struct net_device *dev = fib_info_nh(info->fi, 0)->fib_nh_dev;
1176 int port;
1177 struct rtl83xx_route *r;
1178 bool to_localhost;
1179 int vlan = is_vlan_dev(dev) ? vlan_dev_vlan_id(dev) : 0;
1180
1181 pr_debug("In %s, ip %pI4, len %d\n", __func__, &info->dst, info->dst_len);
1182 if (!info->dst) {
1183 pr_info("Not offloading default route for now\n");
1184 return 0;
1185 }
1186
1187 pr_debug("GW: %pI4, interface name %s, mac %016llx, vlan %d\n", &nh->fib_nh_gw4, dev->name,
1188 ether_addr_to_u64(dev->dev_addr), vlan
1189 );
1190
1191 port = rtl83xx_port_dev_lower_find(dev, priv);
1192 if (port < 0)
1193 return -1;
1194
1195 // For now we only work with routes that have a gateway and are not ourself
1196 // if ((!nh->fib_nh_gw4) && (info->dst_len != 32))
1197 // return 0;
1198
1199 if ((info->dst & 0xff) == 0xff)
1200 return 0;
1201
1202 // Do not offload routes to 192.168.100.x
1203 if ((info->dst & 0xffffff00) == 0xc0a86400)
1204 return 0;
1205
1206 // Do not offload routes to 127.x.x.x
1207 if ((info->dst & 0xff000000) == 0x7f000000)
1208 return 0;
1209
1210 // Allocate route or host-route (entry if hardware supports this)
1211 if (info->dst_len == 32 && priv->r->host_route_write)
1212 r = rtl83xx_host_route_alloc(priv, nh->fib_nh_gw4);
1213 else
1214 r = rtl83xx_route_alloc(priv, nh->fib_nh_gw4);
1215
1216 if (!r) {
1217 pr_err("%s: No more free route entries\n", __func__);
1218 return -1;
1219 }
1220
1221 r->dst_ip = info->dst;
1222 r->prefix_len = info->dst_len;
1223 r->nh.rvid = vlan;
1224 to_localhost = !nh->fib_nh_gw4;
1225
1226 if (priv->r->set_l3_router_mac) {
1227 u64 mac = ether_addr_to_u64(dev->dev_addr);
1228
1229 pr_debug("Local route and router mac %016llx\n", mac);
1230
1231 if (rtl83xx_alloc_router_mac(priv, mac))
1232 goto out_free_rt;
1233
1234 // vid = 0: Do not care about VID
1235 r->nh.if_id = rtl83xx_alloc_egress_intf(priv, mac, vlan);
1236 if (r->nh.if_id < 0)
1237 goto out_free_rmac;
1238
1239 if (to_localhost) {
1240 int slot;
1241
1242 r->nh.mac = mac;
1243 r->nh.port = priv->port_ignore;
1244 r->attr.valid = true;
1245 r->attr.action = ROUTE_ACT_TRAP2CPU;
1246 r->attr.type = 0;
1247
1248 slot = priv->r->find_l3_slot(r, false);
1249 pr_debug("%s: Got slot for route: %d\n", __func__, slot);
1250 priv->r->host_route_write(slot, r);
1251 }
1252 }
1253
1254 // We need to resolve the mac address of the GW
1255 if (!to_localhost)
1256 rtl83xx_port_ipv4_resolve(priv, dev, nh->fib_nh_gw4);
1257
1258 nh->fib_nh_flags |= RTNH_F_OFFLOAD;
1259
1260 return 0;
1261
1262 out_free_rmac:
1263 out_free_rt:
1264 return 0;
1265 }
1266
1267 static int rtl83xx_fib6_add(struct rtl838x_switch_priv *priv,
1268 struct fib6_entry_notifier_info *info)
1269 {
1270 pr_debug("In %s\n", __func__);
1271 // nh->fib_nh_flags |= RTNH_F_OFFLOAD;
1272 return 0;
1273 }
1274
1275 struct net_event_work {
1276 struct work_struct work;
1277 struct rtl838x_switch_priv *priv;
1278 u64 mac;
1279 u32 gw_addr;
1280 };
1281
1282 static void rtl83xx_net_event_work_do(struct work_struct *work)
1283 {
1284 struct net_event_work *net_work =
1285 container_of(work, struct net_event_work, work);
1286 struct rtl838x_switch_priv *priv = net_work->priv;
1287
1288 rtl83xx_l3_nexthop_update(priv, net_work->gw_addr, net_work->mac);
1289 }
1290
1291 static int rtl83xx_netevent_event(struct notifier_block *this,
1292 unsigned long event, void *ptr)
1293 {
1294 struct rtl838x_switch_priv *priv;
1295 struct net_device *dev;
1296 struct neighbour *n = ptr;
1297 int err, port;
1298 struct net_event_work *net_work;
1299
1300 priv = container_of(this, struct rtl838x_switch_priv, ne_nb);
1301
1302 net_work = kzalloc(sizeof(*net_work), GFP_ATOMIC);
1303 if (!net_work)
1304 return NOTIFY_BAD;
1305
1306 INIT_WORK(&net_work->work, rtl83xx_net_event_work_do);
1307 net_work->priv = priv;
1308
1309 switch (event) {
1310 case NETEVENT_NEIGH_UPDATE:
1311 if (n->tbl != &arp_tbl)
1312 return NOTIFY_DONE;
1313 dev = n->dev;
1314 port = rtl83xx_port_dev_lower_find(dev, priv);
1315 if (port < 0 || !(n->nud_state & NUD_VALID)) {
1316 pr_debug("%s: Neigbour invalid, not updating\n", __func__);
1317 kfree(net_work);
1318 return NOTIFY_DONE;
1319 }
1320
1321 net_work->mac = ether_addr_to_u64(n->ha);
1322 net_work->gw_addr = *(__be32 *) n->primary_key;
1323
1324 pr_debug("%s: updating neighbour on port %d, mac %016llx\n",
1325 __func__, port, net_work->mac);
1326 schedule_work(&net_work->work);
1327 if (err)
1328 netdev_warn(dev, "failed to handle neigh update (err %d)\n", err);
1329 break;
1330 }
1331
1332 return NOTIFY_DONE;
1333 }
1334
1335 struct rtl83xx_fib_event_work {
1336 struct work_struct work;
1337 union {
1338 struct fib_entry_notifier_info fen_info;
1339 struct fib6_entry_notifier_info fen6_info;
1340 struct fib_rule_notifier_info fr_info;
1341 };
1342 struct rtl838x_switch_priv *priv;
1343 bool is_fib6;
1344 unsigned long event;
1345 };
1346
1347 static void rtl83xx_fib_event_work_do(struct work_struct *work)
1348 {
1349 struct rtl83xx_fib_event_work *fib_work =
1350 container_of(work, struct rtl83xx_fib_event_work, work);
1351 struct rtl838x_switch_priv *priv = fib_work->priv;
1352 struct fib_rule *rule;
1353 int err;
1354
1355 /* Protect internal structures from changes */
1356 rtnl_lock();
1357 pr_debug("%s: doing work, event %ld\n", __func__, fib_work->event);
1358 switch (fib_work->event) {
1359 case FIB_EVENT_ENTRY_ADD:
1360 case FIB_EVENT_ENTRY_REPLACE:
1361 case FIB_EVENT_ENTRY_APPEND:
1362 if (fib_work->is_fib6) {
1363 err = rtl83xx_fib6_add(priv, &fib_work->fen6_info);
1364 } else {
1365 err = rtl83xx_fib4_add(priv, &fib_work->fen_info);
1366 fib_info_put(fib_work->fen_info.fi);
1367 }
1368 if (err)
1369 pr_err("%s: FIB4 failed\n", __func__);
1370 break;
1371 case FIB_EVENT_ENTRY_DEL:
1372 rtl83xx_fib4_del(priv, &fib_work->fen_info);
1373 fib_info_put(fib_work->fen_info.fi);
1374 break;
1375 case FIB_EVENT_RULE_ADD:
1376 case FIB_EVENT_RULE_DEL:
1377 rule = fib_work->fr_info.rule;
1378 if (!fib4_rule_default(rule))
1379 pr_err("%s: FIB4 default rule failed\n", __func__);
1380 fib_rule_put(rule);
1381 break;
1382 }
1383 rtnl_unlock();
1384 kfree(fib_work);
1385 }
1386
1387 /* Called with rcu_read_lock() */
1388 static int rtl83xx_fib_event(struct notifier_block *this, unsigned long event, void *ptr)
1389 {
1390 struct fib_notifier_info *info = ptr;
1391 struct rtl838x_switch_priv *priv;
1392 struct rtl83xx_fib_event_work *fib_work;
1393
1394 if ((info->family != AF_INET && info->family != AF_INET6 &&
1395 info->family != RTNL_FAMILY_IPMR &&
1396 info->family != RTNL_FAMILY_IP6MR))
1397 return NOTIFY_DONE;
1398
1399 priv = container_of(this, struct rtl838x_switch_priv, fib_nb);
1400
1401 fib_work = kzalloc(sizeof(*fib_work), GFP_ATOMIC);
1402 if (!fib_work)
1403 return NOTIFY_BAD;
1404
1405 INIT_WORK(&fib_work->work, rtl83xx_fib_event_work_do);
1406 fib_work->priv = priv;
1407 fib_work->event = event;
1408 fib_work->is_fib6 = false;
1409
1410 switch (event) {
1411 case FIB_EVENT_ENTRY_ADD:
1412 case FIB_EVENT_ENTRY_REPLACE:
1413 case FIB_EVENT_ENTRY_APPEND:
1414 case FIB_EVENT_ENTRY_DEL:
1415 pr_debug("%s: FIB_ENTRY ADD/DEL, event %ld\n", __func__, event);
1416 if (info->family == AF_INET) {
1417 struct fib_entry_notifier_info *fen_info = ptr;
1418
1419 if (fen_info->fi->fib_nh_is_v6) {
1420 NL_SET_ERR_MSG_MOD(info->extack,
1421 "IPv6 gateway with IPv4 route is not supported");
1422 kfree(fib_work);
1423 return notifier_from_errno(-EINVAL);
1424 }
1425
1426 memcpy(&fib_work->fen_info, ptr, sizeof(fib_work->fen_info));
1427 /* Take referece on fib_info to prevent it from being
1428 * freed while work is queued. Release it afterwards.
1429 */
1430 fib_info_hold(fib_work->fen_info.fi);
1431
1432 } else if (info->family == AF_INET6) {
1433 struct fib6_entry_notifier_info *fen6_info = ptr;
1434 pr_warn("%s: FIB_RULE ADD/DEL for IPv6 not supported\n", __func__);
1435 kfree(fib_work);
1436 return NOTIFY_DONE;
1437 }
1438 break;
1439
1440 case FIB_EVENT_RULE_ADD:
1441 case FIB_EVENT_RULE_DEL:
1442 pr_debug("%s: FIB_RULE ADD/DEL, event: %ld\n", __func__, event);
1443 memcpy(&fib_work->fr_info, ptr, sizeof(fib_work->fr_info));
1444 fib_rule_get(fib_work->fr_info.rule);
1445 break;
1446 }
1447
1448 schedule_work(&fib_work->work);
1449
1450 return NOTIFY_DONE;
1451 }
1452
1453 static int __init rtl83xx_sw_probe(struct platform_device *pdev)
1454 {
1455 int err = 0, i;
1456 struct rtl838x_switch_priv *priv;
1457 struct device *dev = &pdev->dev;
1458 u64 bpdu_mask;
1459
1460 pr_debug("Probing RTL838X switch device\n");
1461 if (!pdev->dev.of_node) {
1462 dev_err(dev, "No DT found\n");
1463 return -EINVAL;
1464 }
1465
1466 // Initialize access to RTL switch tables
1467 rtl_table_init();
1468
1469 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1470 if (!priv)
1471 return -ENOMEM;
1472
1473 priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL);
1474
1475 if (!priv->ds)
1476 return -ENOMEM;
1477 priv->ds->dev = dev;
1478 priv->ds->priv = priv;
1479 priv->ds->ops = &rtl83xx_switch_ops;
1480 priv->ds->needs_standalone_vlan_filtering = true;
1481 priv->dev = dev;
1482
1483 mutex_init(&priv->reg_mutex);
1484
1485 priv->family_id = soc_info.family;
1486 priv->id = soc_info.id;
1487 switch(soc_info.family) {
1488 case RTL8380_FAMILY_ID:
1489 priv->ds->ops = &rtl83xx_switch_ops;
1490 priv->cpu_port = RTL838X_CPU_PORT;
1491 priv->port_mask = 0x1f;
1492 priv->port_width = 1;
1493 priv->irq_mask = 0x0FFFFFFF;
1494 priv->r = &rtl838x_reg;
1495 priv->ds->num_ports = 29;
1496 priv->fib_entries = 8192;
1497 rtl8380_get_version(priv);
1498 priv->n_lags = 8;
1499 priv->l2_bucket_size = 4;
1500 priv->n_pie_blocks = 12;
1501 priv->port_ignore = 0x1f;
1502 priv->n_counters = 128;
1503 break;
1504 case RTL8390_FAMILY_ID:
1505 priv->ds->ops = &rtl83xx_switch_ops;
1506 priv->cpu_port = RTL839X_CPU_PORT;
1507 priv->port_mask = 0x3f;
1508 priv->port_width = 2;
1509 priv->irq_mask = 0xFFFFFFFFFFFFFULL;
1510 priv->r = &rtl839x_reg;
1511 priv->ds->num_ports = 53;
1512 priv->fib_entries = 16384;
1513 rtl8390_get_version(priv);
1514 priv->n_lags = 16;
1515 priv->l2_bucket_size = 4;
1516 priv->n_pie_blocks = 18;
1517 priv->port_ignore = 0x3f;
1518 priv->n_counters = 1024;
1519 break;
1520 case RTL9300_FAMILY_ID:
1521 priv->ds->ops = &rtl930x_switch_ops;
1522 priv->cpu_port = RTL930X_CPU_PORT;
1523 priv->port_mask = 0x1f;
1524 priv->port_width = 1;
1525 priv->irq_mask = 0x0FFFFFFF;
1526 priv->r = &rtl930x_reg;
1527 priv->ds->num_ports = 29;
1528 priv->fib_entries = 16384;
1529 priv->version = RTL8390_VERSION_A;
1530 priv->n_lags = 16;
1531 sw_w32(1, RTL930X_ST_CTRL);
1532 priv->l2_bucket_size = 8;
1533 priv->n_pie_blocks = 16;
1534 priv->port_ignore = 0x3f;
1535 priv->n_counters = 2048;
1536 break;
1537 case RTL9310_FAMILY_ID:
1538 priv->ds->ops = &rtl930x_switch_ops;
1539 priv->cpu_port = RTL931X_CPU_PORT;
1540 priv->port_mask = 0x3f;
1541 priv->port_width = 2;
1542 priv->irq_mask = 0xFFFFFFFFFFFFFULL;
1543 priv->r = &rtl931x_reg;
1544 priv->ds->num_ports = 57;
1545 priv->fib_entries = 16384;
1546 priv->version = RTL8390_VERSION_A;
1547 priv->n_lags = 16;
1548 priv->l2_bucket_size = 8;
1549 break;
1550 }
1551 pr_debug("Chip version %c\n", priv->version);
1552
1553 err = rtl83xx_mdio_probe(priv);
1554 if (err) {
1555 /* Probing fails the 1st time because of missing ethernet driver
1556 * initialization. Use this to disable traffic in case the bootloader left if on
1557 */
1558 return err;
1559 }
1560 err = dsa_register_switch(priv->ds);
1561 if (err) {
1562 dev_err(dev, "Error registering switch: %d\n", err);
1563 return err;
1564 }
1565
1566 /*
1567 * dsa_to_port returns dsa_port from the port list in
1568 * dsa_switch_tree, the tree is built when the switch
1569 * is registered by dsa_register_switch
1570 */
1571 for (i = 0; i <= priv->cpu_port; i++)
1572 priv->ports[i].dp = dsa_to_port(priv->ds, i);
1573
1574 /* Enable link and media change interrupts. Are the SERDES masks needed? */
1575 sw_w32_mask(0, 3, priv->r->isr_glb_src);
1576
1577 priv->r->set_port_reg_le(priv->irq_mask, priv->r->isr_port_link_sts_chg);
1578 priv->r->set_port_reg_le(priv->irq_mask, priv->r->imr_port_link_sts_chg);
1579
1580 priv->link_state_irq = platform_get_irq(pdev, 0);
1581 pr_info("LINK state irq: %d\n", priv->link_state_irq);
1582 switch (priv->family_id) {
1583 case RTL8380_FAMILY_ID:
1584 err = request_irq(priv->link_state_irq, rtl838x_switch_irq,
1585 IRQF_SHARED, "rtl838x-link-state", priv->ds);
1586 break;
1587 case RTL8390_FAMILY_ID:
1588 err = request_irq(priv->link_state_irq, rtl839x_switch_irq,
1589 IRQF_SHARED, "rtl839x-link-state", priv->ds);
1590 break;
1591 case RTL9300_FAMILY_ID:
1592 err = request_irq(priv->link_state_irq, rtl930x_switch_irq,
1593 IRQF_SHARED, "rtl930x-link-state", priv->ds);
1594 break;
1595 case RTL9310_FAMILY_ID:
1596 err = request_irq(priv->link_state_irq, rtl931x_switch_irq,
1597 IRQF_SHARED, "rtl931x-link-state", priv->ds);
1598 break;
1599 }
1600 if (err) {
1601 dev_err(dev, "Error setting up switch interrupt.\n");
1602 /* Need to free allocated switch here */
1603 }
1604
1605 /* Enable interrupts for switch, on RTL931x, the IRQ is always on globally */
1606 if (soc_info.family != RTL9310_FAMILY_ID)
1607 sw_w32(0x1, priv->r->imr_glb);
1608
1609 rtl83xx_get_l2aging(priv);
1610
1611 rtl83xx_setup_qos(priv);
1612
1613 priv->r->l3_setup(priv);
1614
1615 /* Clear all destination ports for mirror groups */
1616 for (i = 0; i < 4; i++)
1617 priv->mirror_group_ports[i] = -1;
1618
1619 /*
1620 * Register netdevice event callback to catch changes in link aggregation groups
1621 */
1622 priv->nb.notifier_call = rtl83xx_netdevice_event;
1623 if (register_netdevice_notifier(&priv->nb)) {
1624 priv->nb.notifier_call = NULL;
1625 dev_err(dev, "Failed to register LAG netdev notifier\n");
1626 goto err_register_nb;
1627 }
1628
1629 // Initialize hash table for L3 routing
1630 rhltable_init(&priv->routes, &route_ht_params);
1631
1632 /*
1633 * Register netevent notifier callback to catch notifications about neighboring
1634 * changes to update nexthop entries for L3 routing.
1635 */
1636 priv->ne_nb.notifier_call = rtl83xx_netevent_event;
1637 if (register_netevent_notifier(&priv->ne_nb)) {
1638 priv->ne_nb.notifier_call = NULL;
1639 dev_err(dev, "Failed to register netevent notifier\n");
1640 goto err_register_ne_nb;
1641 }
1642
1643 priv->fib_nb.notifier_call = rtl83xx_fib_event;
1644
1645 /*
1646 * Register Forwarding Information Base notifier to offload routes where
1647 * where possible
1648 * Only FIBs pointing to our own netdevs are programmed into
1649 * the device, so no need to pass a callback.
1650 */
1651 err = register_fib_notifier(&init_net, &priv->fib_nb, NULL, NULL);
1652 if (err)
1653 goto err_register_fib_nb;
1654
1655 // TODO: put this into l2_setup()
1656 // Flood BPDUs to all ports including cpu-port
1657 if (soc_info.family != RTL9300_FAMILY_ID) {
1658 bpdu_mask = soc_info.family == RTL8380_FAMILY_ID ? 0x1FFFFFFF : 0x1FFFFFFFFFFFFF;
1659 priv->r->set_port_reg_be(bpdu_mask, priv->r->rma_bpdu_fld_pmask);
1660
1661 // TRAP 802.1X frames (EAPOL) to the CPU-Port, bypass STP and VLANs
1662 sw_w32(7, priv->r->spcl_trap_eapol_ctrl);
1663
1664 rtl838x_dbgfs_init(priv);
1665 } else {
1666 rtl930x_dbgfs_init(priv);
1667 }
1668
1669 return 0;
1670
1671 err_register_fib_nb:
1672 unregister_netevent_notifier(&priv->ne_nb);
1673 err_register_ne_nb:
1674 unregister_netdevice_notifier(&priv->nb);
1675 err_register_nb:
1676 return err;
1677 }
1678
1679 static int rtl83xx_sw_remove(struct platform_device *pdev)
1680 {
1681 // TODO:
1682 pr_debug("Removing platform driver for rtl83xx-sw\n");
1683 return 0;
1684 }
1685
1686 static const struct of_device_id rtl83xx_switch_of_ids[] = {
1687 { .compatible = "realtek,rtl83xx-switch"},
1688 { /* sentinel */ }
1689 };
1690
1691
1692 MODULE_DEVICE_TABLE(of, rtl83xx_switch_of_ids);
1693
1694 static struct platform_driver rtl83xx_switch_driver = {
1695 .probe = rtl83xx_sw_probe,
1696 .remove = rtl83xx_sw_remove,
1697 .driver = {
1698 .name = "rtl83xx-switch",
1699 .pm = NULL,
1700 .of_match_table = rtl83xx_switch_of_ids,
1701 },
1702 };
1703
1704 module_platform_driver(rtl83xx_switch_driver);
1705
1706 MODULE_AUTHOR("B. Koblitz");
1707 MODULE_DESCRIPTION("RTL83XX SoC Switch Driver");
1708 MODULE_LICENSE("GPL");
Staging tree of Jo-Philipp Wich