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70b57924b9b30446985c830b133db6a14cf809aa
[openwrt/staging/jow.git] / target / linux / realtek / files-5.10 / drivers / net / phy / rtl83xx-phy.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Realtek RTL838X Ethernet MDIO interface driver
3 *
4 * Copyright (C) 2020 B. Koblitz
5 */
6
7 #include <linux/module.h>
8 #include <linux/delay.h>
9 #include <linux/phy.h>
10 #include <linux/netdevice.h>
11 #include <linux/firmware.h>
12 #include <linux/crc32.h>
13
14 #include <asm/mach-rtl838x/mach-rtl83xx.h>
15 #include "rtl83xx-phy.h"
16
17 extern struct rtl83xx_soc_info soc_info;
18 extern struct mutex smi_lock;
19
20 #define PHY_CTRL_REG 0
21 #define PHY_POWER_BIT 11
22
23 #define PHY_PAGE_2 2
24 #define PHY_PAGE_4 4
25
26 /* all Clause-22 RealTek MDIO PHYs use register 0x1f for page select */
27 #define RTL8XXX_PAGE_SELECT 0x1f
28
29 #define RTL8XXX_PAGE_MAIN 0x0000
30 #define RTL821X_PAGE_PORT 0x0266
31 #define RTL821X_PAGE_POWER 0x0a40
32 #define RTL821X_PAGE_GPHY 0x0a42
33 #define RTL821X_PAGE_MAC 0x0a43
34 #define RTL821X_PAGE_STATE 0x0b80
35 #define RTL821X_PAGE_PATCH 0x0b82
36
37 /*
38 * Using the special page 0xfff with the MDIO controller found in
39 * RealTek SoCs allows to access the PHY in RAW mode, ie. bypassing
40 * the cache and paging engine of the MDIO controller.
41 */
42 #define RTL83XX_PAGE_RAW 0x0fff
43
44 /* internal RTL821X PHY uses register 0x1d to select media page */
45 #define RTL821XINT_MEDIA_PAGE_SELECT 0x1d
46 /* external RTL821X PHY uses register 0x1e to select media page */
47 #define RTL821XEXT_MEDIA_PAGE_SELECT 0x1e
48
49 #define RTL821X_MEDIA_PAGE_AUTO 0
50 #define RTL821X_MEDIA_PAGE_COPPER 1
51 #define RTL821X_MEDIA_PAGE_FIBRE 3
52 #define RTL821X_MEDIA_PAGE_INTERNAL 8
53
54 #define RTL9300_PHY_ID_MASK 0xf0ffffff
55
56 /*
57 * This lock protects the state of the SoC automatically polling the PHYs over the SMI
58 * bus to detect e.g. link and media changes. For operations on the PHYs such as
59 * patching or other configuration changes such as EEE, polling needs to be disabled
60 * since otherwise these operations may fails or lead to unpredictable results.
61 */
62 DEFINE_MUTEX(poll_lock);
63
64 static const struct firmware rtl838x_8380_fw;
65 static const struct firmware rtl838x_8214fc_fw;
66 static const struct firmware rtl838x_8218b_fw;
67
68 static u64 disable_polling(int port)
69 {
70 u64 saved_state;
71
72 mutex_lock(&poll_lock);
73
74 switch (soc_info.family) {
75 case RTL8380_FAMILY_ID:
76 saved_state = sw_r32(RTL838X_SMI_POLL_CTRL);
77 sw_w32_mask(BIT(port), 0, RTL838X_SMI_POLL_CTRL);
78 break;
79 case RTL8390_FAMILY_ID:
80 saved_state = sw_r32(RTL839X_SMI_PORT_POLLING_CTRL + 4);
81 saved_state <<= 32;
82 saved_state |= sw_r32(RTL839X_SMI_PORT_POLLING_CTRL);
83 sw_w32_mask(BIT(port % 32), 0,
84 RTL839X_SMI_PORT_POLLING_CTRL + ((port >> 5) << 2));
85 break;
86 case RTL9300_FAMILY_ID:
87 saved_state = sw_r32(RTL930X_SMI_POLL_CTRL);
88 sw_w32_mask(BIT(port), 0, RTL930X_SMI_POLL_CTRL);
89 break;
90 case RTL9310_FAMILY_ID:
91 pr_warn("%s not implemented for RTL931X\n", __func__);
92 break;
93 }
94
95 mutex_unlock(&poll_lock);
96
97 return saved_state;
98 }
99
100 static int resume_polling(u64 saved_state)
101 {
102 mutex_lock(&poll_lock);
103
104 switch (soc_info.family) {
105 case RTL8380_FAMILY_ID:
106 sw_w32(saved_state, RTL838X_SMI_POLL_CTRL);
107 break;
108 case RTL8390_FAMILY_ID:
109 sw_w32(saved_state >> 32, RTL839X_SMI_PORT_POLLING_CTRL + 4);
110 sw_w32(saved_state, RTL839X_SMI_PORT_POLLING_CTRL);
111 break;
112 case RTL9300_FAMILY_ID:
113 sw_w32(saved_state, RTL930X_SMI_POLL_CTRL);
114 break;
115 case RTL9310_FAMILY_ID:
116 pr_warn("%s not implemented for RTL931X\n", __func__);
117 break;
118 }
119
120 mutex_unlock(&poll_lock);
121
122 return 0;
123 }
124
125 static void rtl8380_int_phy_on_off(struct phy_device *phydev, bool on)
126 {
127 phy_modify(phydev, 0, BIT(11), on?0:BIT(11));
128 }
129
130 static void rtl8380_rtl8214fc_on_off(struct phy_device *phydev, bool on)
131 {
132 /* fiber ports */
133 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_FIBRE);
134 phy_modify(phydev, 0x10, BIT(11), on?0:BIT(11));
135
136 /* copper ports */
137 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
138 phy_modify_paged(phydev, RTL821X_PAGE_POWER, 0x10, BIT(11), on?0:BIT(11));
139 }
140
141 static void rtl8380_phy_reset(struct phy_device *phydev)
142 {
143 phy_modify(phydev, 0, BIT(15), BIT(15));
144 }
145
146 // The access registers for SDS_MODE_SEL and the LSB for each SDS within
147 u16 rtl9300_sds_regs[] = { 0x0194, 0x0194, 0x0194, 0x0194, 0x02a0, 0x02a0, 0x02a0, 0x02a0,
148 0x02A4, 0x02A4, 0x0198, 0x0198 };
149 u8 rtl9300_sds_lsb[] = { 0, 6, 12, 18, 0, 6, 12, 18, 0, 6, 0, 6};
150
151 /*
152 * Reset the SerDes by powering it off and set a new operations mode
153 * of the SerDes. 0x1f is off. Other modes are
154 * 0x02: SGMII 0x04: 1000BX_FIBER 0x05: FIBER100
155 * 0x06: QSGMII 0x09: RSGMII 0x0d: USXGMII
156 * 0x10: XSGMII 0x12: HISGMII 0x16: 2500Base_X
157 * 0x17: RXAUI_LITE 0x19: RXAUI_PLUS 0x1a: 10G Base-R
158 * 0x1b: 10GR1000BX_AUTO 0x1f: OFF
159 */
160 void rtl9300_sds_rst(int sds_num, u32 mode)
161 {
162 pr_info("%s %d\n", __func__, mode);
163 if (sds_num < 0 || sds_num > 11) {
164 pr_err("Wrong SerDes number: %d\n", sds_num);
165 return;
166 }
167
168 sw_w32_mask(0x1f << rtl9300_sds_lsb[sds_num], 0x1f << rtl9300_sds_lsb[sds_num],
169 rtl9300_sds_regs[sds_num]);
170 mdelay(10);
171
172 sw_w32_mask(0x1f << rtl9300_sds_lsb[sds_num], mode << rtl9300_sds_lsb[sds_num],
173 rtl9300_sds_regs[sds_num]);
174 mdelay(10);
175
176 pr_debug("%s: 194:%08x 198:%08x 2a0:%08x 2a4:%08x\n", __func__,
177 sw_r32(0x194), sw_r32(0x198), sw_r32(0x2a0), sw_r32(0x2a4));
178 }
179
180 void rtl9300_sds_set(int sds_num, u32 mode)
181 {
182 pr_info("%s %d\n", __func__, mode);
183 if (sds_num < 0 || sds_num > 11) {
184 pr_err("Wrong SerDes number: %d\n", sds_num);
185 return;
186 }
187
188 sw_w32_mask(0x1f << rtl9300_sds_lsb[sds_num], mode << rtl9300_sds_lsb[sds_num],
189 rtl9300_sds_regs[sds_num]);
190 mdelay(10);
191
192 pr_debug("%s: 194:%08x 198:%08x 2a0:%08x 2a4:%08x\n", __func__,
193 sw_r32(0x194), sw_r32(0x198), sw_r32(0x2a0), sw_r32(0x2a4));
194 }
195
196 u32 rtl9300_sds_mode_get(int sds_num)
197 {
198 u32 v;
199
200 if (sds_num < 0 || sds_num > 11) {
201 pr_err("Wrong SerDes number: %d\n", sds_num);
202 return 0;
203 }
204
205 v = sw_r32(rtl9300_sds_regs[sds_num]);
206 v >>= rtl9300_sds_lsb[sds_num];
207
208 return v & 0x1f;
209 }
210
211 /*
212 * On the RTL839x family of SoCs with inbuilt SerDes, these SerDes are accessed through
213 * a 2048 bit register that holds the contents of the PHY being simulated by the SoC.
214 */
215 int rtl839x_read_sds_phy(int phy_addr, int phy_reg)
216 {
217 int offset = 0;
218 int reg;
219 u32 val;
220
221 if (phy_addr == 49)
222 offset = 0x100;
223
224 /*
225 * For the RTL8393 internal SerDes, we simulate a PHY ID in registers 2/3
226 * which would otherwise read as 0.
227 */
228 if (soc_info.id == 0x8393) {
229 if (phy_reg == 2)
230 return 0x1c;
231 if (phy_reg == 3)
232 return 0x8393;
233 }
234
235 /*
236 * Register RTL839X_SDS12_13_XSG0 is 2048 bit broad, the MSB (bit 15) of the
237 * 0th PHY register is bit 1023 (in byte 0x80). Because PHY-registers are 16
238 * bit broad, we offset by reg << 1. In the SoC 2 registers are stored in
239 * one 32 bit register.
240 */
241 reg = (phy_reg << 1) & 0xfc;
242 val = sw_r32(RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);
243
244 if (phy_reg & 1)
245 val = (val >> 16) & 0xffff;
246 else
247 val &= 0xffff;
248 return val;
249 }
250
251 /*
252 * On the RTL930x family of SoCs, the internal SerDes are accessed through an IO
253 * register which simulates commands to an internal MDIO bus.
254 */
255 int rtl930x_read_sds_phy(int phy_addr, int page, int phy_reg)
256 {
257 int i;
258 u32 cmd = phy_addr << 2 | page << 7 | phy_reg << 13 | 1;
259
260 sw_w32(cmd, RTL930X_SDS_INDACS_CMD);
261
262 for (i = 0; i < 100; i++) {
263 if (!(sw_r32(RTL930X_SDS_INDACS_CMD) & 0x1))
264 break;
265 mdelay(1);
266 }
267
268 if (i >= 100)
269 return -EIO;
270
271 return sw_r32(RTL930X_SDS_INDACS_DATA) & 0xffff;
272 }
273
274 int rtl930x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v)
275 {
276 int i;
277 u32 cmd;
278
279 sw_w32(v, RTL930X_SDS_INDACS_DATA);
280 cmd = phy_addr << 2 | page << 7 | phy_reg << 13 | 0x3;
281
282 for (i = 0; i < 100; i++) {
283 if (!(sw_r32(RTL930X_SDS_INDACS_CMD) & 0x1))
284 break;
285 mdelay(1);
286 }
287
288
289 if (i >= 100) {
290 pr_info("%s ERROR !!!!!!!!!!!!!!!!!!!!\n", __func__);
291 return -EIO;
292 }
293
294 return 0;
295 }
296
297 int rtl931x_read_sds_phy(int phy_addr, int page, int phy_reg)
298 {
299 int i;
300 u32 cmd = phy_addr << 2 | page << 7 | phy_reg << 13 | 1;
301
302 pr_debug("%s: phy_addr(SDS-ID) %d, phy_reg: %d\n", __func__, phy_addr, phy_reg);
303 sw_w32(cmd, RTL931X_SERDES_INDRT_ACCESS_CTRL);
304
305 for (i = 0; i < 100; i++) {
306 if (!(sw_r32(RTL931X_SERDES_INDRT_ACCESS_CTRL) & 0x1))
307 break;
308 mdelay(1);
309 }
310
311 if (i >= 100)
312 return -EIO;
313
314 pr_debug("%s: returning %04x\n", __func__, sw_r32(RTL931X_SERDES_INDRT_DATA_CTRL) & 0xffff);
315 return sw_r32(RTL931X_SERDES_INDRT_DATA_CTRL) & 0xffff;
316 }
317
318 int rtl931x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v)
319 {
320 int i;
321 u32 cmd;
322
323 cmd = phy_addr << 2 | page << 7 | phy_reg << 13;
324 sw_w32(cmd, RTL931X_SERDES_INDRT_ACCESS_CTRL);
325
326 sw_w32(v, RTL931X_SERDES_INDRT_DATA_CTRL);
327
328 cmd = sw_r32(RTL931X_SERDES_INDRT_ACCESS_CTRL) | 0x3;
329 sw_w32(cmd, RTL931X_SERDES_INDRT_ACCESS_CTRL);
330
331 for (i = 0; i < 100; i++) {
332 if (!(sw_r32(RTL931X_SERDES_INDRT_ACCESS_CTRL) & 0x1))
333 break;
334 mdelay(1);
335 }
336
337 if (i >= 100)
338 return -EIO;
339
340 return 0;
341 }
342
343 /*
344 * On the RTL838x SoCs, the internal SerDes is accessed through direct access to
345 * standard PHY registers, where a 32 bit register holds a 16 bit word as found
346 * in a standard page 0 of a PHY
347 */
348 int rtl838x_read_sds_phy(int phy_addr, int phy_reg)
349 {
350 int offset = 0;
351 u32 val;
352
353 if (phy_addr == 26)
354 offset = 0x100;
355 val = sw_r32(RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2)) & 0xffff;
356
357 return val;
358 }
359
360 int rtl839x_write_sds_phy(int phy_addr, int phy_reg, u16 v)
361 {
362 int offset = 0;
363 int reg;
364 u32 val;
365
366 if (phy_addr == 49)
367 offset = 0x100;
368
369 reg = (phy_reg << 1) & 0xfc;
370 val = v;
371 if (phy_reg & 1) {
372 val = val << 16;
373 sw_w32_mask(0xffff0000, val,
374 RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);
375 } else {
376 sw_w32_mask(0xffff, val,
377 RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);
378 }
379
380 return 0;
381 }
382
383 /* Read the link and speed status of the 2 internal SGMII/1000Base-X
384 * ports of the RTL838x SoCs
385 */
386 static int rtl8380_read_status(struct phy_device *phydev)
387 {
388 int err;
389
390 err = genphy_read_status(phydev);
391
392 if (phydev->link) {
393 phydev->speed = SPEED_1000;
394 phydev->duplex = DUPLEX_FULL;
395 }
396
397 return err;
398 }
399
400 /* Read the link and speed status of the 2 internal SGMII/1000Base-X
401 * ports of the RTL8393 SoC
402 */
403 static int rtl8393_read_status(struct phy_device *phydev)
404 {
405 int offset = 0;
406 int err;
407 int phy_addr = phydev->mdio.addr;
408 u32 v;
409
410 err = genphy_read_status(phydev);
411 if (phy_addr == 49)
412 offset = 0x100;
413
414 if (phydev->link) {
415 phydev->speed = SPEED_100;
416 /* Read SPD_RD_00 (bit 13) and SPD_RD_01 (bit 6) out of the internal
417 * PHY registers
418 */
419 v = sw_r32(RTL839X_SDS12_13_XSG0 + offset + 0x80);
420 if (!(v & (1 << 13)) && (v & (1 << 6)))
421 phydev->speed = SPEED_1000;
422 phydev->duplex = DUPLEX_FULL;
423 }
424
425 return err;
426 }
427
428 static int rtl8226_read_page(struct phy_device *phydev)
429 {
430 return __phy_read(phydev, RTL8XXX_PAGE_SELECT);
431 }
432
433 static int rtl8226_write_page(struct phy_device *phydev, int page)
434 {
435 return __phy_write(phydev, RTL8XXX_PAGE_SELECT, page);
436 }
437
438 static int rtl8226_read_status(struct phy_device *phydev)
439 {
440 int ret = 0, i;
441 u32 val;
442
443 // TODO: ret = genphy_read_status(phydev);
444 // if (ret < 0) {
445 // pr_info("%s: genphy_read_status failed\n", __func__);
446 // return ret;
447 // }
448
449 // Link status must be read twice
450 for (i = 0; i < 2; i++) {
451 val = phy_read_mmd(phydev, MMD_VEND2, 0xA402);
452 }
453 phydev->link = val & BIT(2) ? 1 : 0;
454 if (!phydev->link)
455 goto out;
456
457 // Read duplex status
458 val = phy_read_mmd(phydev, MMD_VEND2, 0xA434);
459 if (val < 0)
460 goto out;
461 phydev->duplex = !!(val & BIT(3));
462
463 // Read speed
464 val = phy_read_mmd(phydev, MMD_VEND2, 0xA434);
465 switch (val & 0x0630) {
466 case 0x0000:
467 phydev->speed = SPEED_10;
468 break;
469 case 0x0010:
470 phydev->speed = SPEED_100;
471 break;
472 case 0x0020:
473 phydev->speed = SPEED_1000;
474 break;
475 case 0x0200:
476 phydev->speed = SPEED_10000;
477 break;
478 case 0x0210:
479 phydev->speed = SPEED_2500;
480 break;
481 case 0x0220:
482 phydev->speed = SPEED_5000;
483 break;
484 default:
485 break;
486 }
487 out:
488 return ret;
489 }
490
491 static int rtl8226_advertise_aneg(struct phy_device *phydev)
492 {
493 int ret = 0;
494 u32 v;
495
496 pr_info("In %s\n", __func__);
497
498 v = phy_read_mmd(phydev, MMD_AN, 16);
499 if (v < 0)
500 goto out;
501
502 v |= BIT(5); // HD 10M
503 v |= BIT(6); // FD 10M
504 v |= BIT(7); // HD 100M
505 v |= BIT(8); // FD 100M
506
507 ret = phy_write_mmd(phydev, MMD_AN, 16, v);
508
509 // Allow 1GBit
510 v = phy_read_mmd(phydev, MMD_VEND2, 0xA412);
511 if (v < 0)
512 goto out;
513 v |= BIT(9); // FD 1000M
514
515 ret = phy_write_mmd(phydev, MMD_VEND2, 0xA412, v);
516 if (ret < 0)
517 goto out;
518
519 // Allow 2.5G
520 v = phy_read_mmd(phydev, MMD_AN, 32);
521 if (v < 0)
522 goto out;
523
524 v |= BIT(7);
525 ret = phy_write_mmd(phydev, MMD_AN, 32, v);
526
527 out:
528 return ret;
529 }
530
531 static int rtl8226_config_aneg(struct phy_device *phydev)
532 {
533 int ret = 0;
534 u32 v;
535
536 pr_debug("In %s\n", __func__);
537 if (phydev->autoneg == AUTONEG_ENABLE) {
538 ret = rtl8226_advertise_aneg(phydev);
539 if (ret)
540 goto out;
541 // AutoNegotiationEnable
542 v = phy_read_mmd(phydev, MMD_AN, 0);
543 if (v < 0)
544 goto out;
545
546 v |= BIT(12); // Enable AN
547 ret = phy_write_mmd(phydev, MMD_AN, 0, v);
548 if (ret < 0)
549 goto out;
550
551 // RestartAutoNegotiation
552 v = phy_read_mmd(phydev, MMD_VEND2, 0xA400);
553 if (v < 0)
554 goto out;
555 v |= BIT(9);
556
557 ret = phy_write_mmd(phydev, MMD_VEND2, 0xA400, v);
558 }
559
560 // TODO: ret = __genphy_config_aneg(phydev, ret);
561
562 out:
563 return ret;
564 }
565
566 static int rtl8226_get_eee(struct phy_device *phydev,
567 struct ethtool_eee *e)
568 {
569 u32 val;
570 int addr = phydev->mdio.addr;
571
572 pr_debug("In %s, port %d, was enabled: %d\n", __func__, addr, e->eee_enabled);
573
574 val = phy_read_mmd(phydev, MMD_AN, 60);
575 if (e->eee_enabled) {
576 e->eee_enabled = !!(val & BIT(1));
577 if (!e->eee_enabled) {
578 val = phy_read_mmd(phydev, MMD_AN, 62);
579 e->eee_enabled = !!(val & BIT(0));
580 }
581 }
582 pr_debug("%s: enabled: %d\n", __func__, e->eee_enabled);
583
584 return 0;
585 }
586
587 static int rtl8226_set_eee(struct phy_device *phydev, struct ethtool_eee *e)
588 {
589 int port = phydev->mdio.addr;
590 u64 poll_state;
591 bool an_enabled;
592 u32 val;
593
594 pr_info("In %s, port %d, enabled %d\n", __func__, port, e->eee_enabled);
595
596 poll_state = disable_polling(port);
597
598 // Remember aneg state
599 val = phy_read_mmd(phydev, MMD_AN, 0);
600 an_enabled = !!(val & BIT(12));
601
602 // Setup 100/1000MBit
603 val = phy_read_mmd(phydev, MMD_AN, 60);
604 if (e->eee_enabled)
605 val |= 0x6;
606 else
607 val &= 0x6;
608 phy_write_mmd(phydev, MMD_AN, 60, val);
609
610 // Setup 2.5GBit
611 val = phy_read_mmd(phydev, MMD_AN, 62);
612 if (e->eee_enabled)
613 val |= 0x1;
614 else
615 val &= 0x1;
616 phy_write_mmd(phydev, MMD_AN, 62, val);
617
618 // RestartAutoNegotiation
619 val = phy_read_mmd(phydev, MMD_VEND2, 0xA400);
620 val |= BIT(9);
621 phy_write_mmd(phydev, MMD_VEND2, 0xA400, val);
622
623 resume_polling(poll_state);
624
625 return 0;
626 }
627
628 static struct fw_header *rtl838x_request_fw(struct phy_device *phydev,
629 const struct firmware *fw,
630 const char *name)
631 {
632 struct device *dev = &phydev->mdio.dev;
633 int err;
634 struct fw_header *h;
635 uint32_t checksum, my_checksum;
636
637 err = request_firmware(&fw, name, dev);
638 if (err < 0)
639 goto out;
640
641 if (fw->size < sizeof(struct fw_header)) {
642 pr_err("Firmware size too small.\n");
643 err = -EINVAL;
644 goto out;
645 }
646
647 h = (struct fw_header *) fw->data;
648 pr_info("Firmware loaded. Size %d, magic: %08x\n", fw->size, h->magic);
649
650 if (h->magic != 0x83808380) {
651 pr_err("Wrong firmware file: MAGIC mismatch.\n");
652 goto out;
653 }
654
655 checksum = h->checksum;
656 h->checksum = 0;
657 my_checksum = ~crc32(0xFFFFFFFFU, fw->data, fw->size);
658 if (checksum != my_checksum) {
659 pr_err("Firmware checksum mismatch.\n");
660 err = -EINVAL;
661 goto out;
662 }
663 h->checksum = checksum;
664
665 return h;
666 out:
667 dev_err(dev, "Unable to load firmware %s (%d)\n", name, err);
668 return NULL;
669 }
670
671 static void rtl821x_phy_setup_package_broadcast(struct phy_device *phydev, bool enable)
672 {
673 int mac = phydev->mdio.addr;
674
675 /* select main page 0 */
676 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
677 /* write to 0x8 to register 0x1d on main page 0 */
678 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL);
679 /* select page 0x266 */
680 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL821X_PAGE_PORT);
681 /* set phy id and target broadcast bitmap in register 0x16 on page 0x266 */
682 phy_write_paged(phydev, RTL83XX_PAGE_RAW, 0x16, (enable?0xff00:0x00) | mac);
683 /* return to main page 0 */
684 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
685 /* write to 0x0 to register 0x1d on main page 0 */
686 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
687 mdelay(1);
688 }
689
690 static int rtl8390_configure_generic(struct phy_device *phydev)
691 {
692 int mac = phydev->mdio.addr;
693 u32 val, phy_id;
694
695 val = phy_read(phydev, 2);
696 phy_id = val << 16;
697 val = phy_read(phydev, 3);
698 phy_id |= val;
699 pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
700
701 /* Read internal PHY ID */
702 phy_write_paged(phydev, 31, 27, 0x0002);
703 val = phy_read_paged(phydev, 31, 28);
704
705 /* Internal RTL8218B, version 2 */
706 phydev_info(phydev, "Detected unknown %x\n", val);
707 return 0;
708 }
709
710 static int rtl8380_configure_int_rtl8218b(struct phy_device *phydev)
711 {
712 u32 val, phy_id;
713 int i, p, ipd_flag;
714 int mac = phydev->mdio.addr;
715 struct fw_header *h;
716 u32 *rtl838x_6275B_intPhy_perport;
717 u32 *rtl8218b_6276B_hwEsd_perport;
718
719 val = phy_read(phydev, 2);
720 phy_id = val << 16;
721 val = phy_read(phydev, 3);
722 phy_id |= val;
723 pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
724
725 /* Read internal PHY ID */
726 phy_write_paged(phydev, 31, 27, 0x0002);
727 val = phy_read_paged(phydev, 31, 28);
728 if (val != 0x6275) {
729 phydev_err(phydev, "Expected internal RTL8218B, found PHY-ID %x\n", val);
730 return -1;
731 }
732
733 /* Internal RTL8218B, version 2 */
734 phydev_info(phydev, "Detected internal RTL8218B\n");
735
736 h = rtl838x_request_fw(phydev, &rtl838x_8380_fw, FIRMWARE_838X_8380_1);
737 if (!h)
738 return -1;
739
740 if (h->phy != 0x83800000) {
741 phydev_err(phydev, "Wrong firmware file: PHY mismatch.\n");
742 return -1;
743 }
744
745 rtl838x_6275B_intPhy_perport = (void *)h + sizeof(struct fw_header)
746 + h->parts[8].start;
747
748 rtl8218b_6276B_hwEsd_perport = (void *)h + sizeof(struct fw_header)
749 + h->parts[9].start;
750
751 if (sw_r32(RTL838X_DMY_REG31) == 0x1)
752 ipd_flag = 1;
753
754 val = phy_read(phydev, 0);
755 if (val & BIT(11))
756 rtl8380_int_phy_on_off(phydev, true);
757 else
758 rtl8380_phy_reset(phydev);
759 msleep(100);
760
761 /* Ready PHY for patch */
762 for (p = 0; p < 8; p++) {
763 phy_package_port_write_paged(phydev, p, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL821X_PAGE_PATCH);
764 phy_package_port_write_paged(phydev, p, RTL83XX_PAGE_RAW, 0x10, 0x0010);
765 }
766 msleep(500);
767 for (p = 0; p < 8; p++) {
768 for (i = 0; i < 100 ; i++) {
769 val = phy_package_port_read_paged(phydev, p, RTL821X_PAGE_STATE, 0x10);
770 if (val & 0x40)
771 break;
772 }
773 if (i >= 100) {
774 phydev_err(phydev,
775 "ERROR: Port %d not ready for patch.\n",
776 mac + p);
777 return -1;
778 }
779 }
780 for (p = 0; p < 8; p++) {
781 i = 0;
782 while (rtl838x_6275B_intPhy_perport[i * 2]) {
783 phy_package_port_write_paged(phydev, p, RTL83XX_PAGE_RAW,
784 rtl838x_6275B_intPhy_perport[i * 2],
785 rtl838x_6275B_intPhy_perport[i * 2 + 1]);
786 i++;
787 }
788 i = 0;
789 while (rtl8218b_6276B_hwEsd_perport[i * 2]) {
790 phy_package_port_write_paged(phydev, p, RTL83XX_PAGE_RAW,
791 rtl8218b_6276B_hwEsd_perport[i * 2],
792 rtl8218b_6276B_hwEsd_perport[i * 2 + 1]);
793 i++;
794 }
795 }
796 return 0;
797 }
798
799 static int rtl8380_configure_ext_rtl8218b(struct phy_device *phydev)
800 {
801 u32 val, ipd, phy_id;
802 int i, l;
803 int mac = phydev->mdio.addr;
804 struct fw_header *h;
805 u32 *rtl8380_rtl8218b_perchip;
806 u32 *rtl8218B_6276B_rtl8380_perport;
807 u32 *rtl8380_rtl8218b_perport;
808
809 if (soc_info.family == RTL8380_FAMILY_ID && mac != 0 && mac != 16) {
810 phydev_err(phydev, "External RTL8218B must have PHY-IDs 0 or 16!\n");
811 return -1;
812 }
813 val = phy_read(phydev, 2);
814 phy_id = val << 16;
815 val = phy_read(phydev, 3);
816 phy_id |= val;
817 pr_info("Phy on MAC %d: %x\n", mac, phy_id);
818
819 /* Read internal PHY ID */
820 phy_write_paged(phydev, 31, 27, 0x0002);
821 val = phy_read_paged(phydev, 31, 28);
822 if (val != 0x6276) {
823 phydev_err(phydev, "Expected external RTL8218B, found PHY-ID %x\n", val);
824 return -1;
825 }
826 phydev_info(phydev, "Detected external RTL8218B\n");
827
828 h = rtl838x_request_fw(phydev, &rtl838x_8218b_fw, FIRMWARE_838X_8218b_1);
829 if (!h)
830 return -1;
831
832 if (h->phy != 0x8218b000) {
833 phydev_err(phydev, "Wrong firmware file: PHY mismatch.\n");
834 return -1;
835 }
836
837 rtl8380_rtl8218b_perchip = (void *)h + sizeof(struct fw_header)
838 + h->parts[0].start;
839
840 rtl8218B_6276B_rtl8380_perport = (void *)h + sizeof(struct fw_header)
841 + h->parts[1].start;
842
843 rtl8380_rtl8218b_perport = (void *)h + sizeof(struct fw_header)
844 + h->parts[2].start;
845
846 val = phy_read(phydev, 0);
847 if (val & (1 << 11))
848 rtl8380_int_phy_on_off(phydev, true);
849 else
850 rtl8380_phy_reset(phydev);
851
852 msleep(100);
853
854 /* Get Chip revision */
855 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
856 phy_write_paged(phydev, RTL83XX_PAGE_RAW, 0x1b, 0x4);
857 val = phy_read_paged(phydev, RTL83XX_PAGE_RAW, 0x1c);
858
859 phydev_info(phydev, "Detected chip revision %04x\n", val);
860
861 i = 0;
862 while (rtl8380_rtl8218b_perchip[i * 3]
863 && rtl8380_rtl8218b_perchip[i * 3 + 1]) {
864 phy_package_port_write_paged(phydev, rtl8380_rtl8218b_perchip[i * 3],
865 RTL83XX_PAGE_RAW, rtl8380_rtl8218b_perchip[i * 3 + 1],
866 rtl8380_rtl8218b_perchip[i * 3 + 2]);
867 i++;
868 }
869
870 /* Enable PHY */
871 for (i = 0; i < 8; i++) {
872 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
873 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, 0x00, 0x1140);
874 }
875 mdelay(100);
876
877 /* Request patch */
878 for (i = 0; i < 8; i++) {
879 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL821X_PAGE_PATCH);
880 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, 0x10, 0x0010);
881 }
882
883 mdelay(300);
884
885 /* Verify patch readiness */
886 for (i = 0; i < 8; i++) {
887 for (l = 0; l < 100; l++) {
888 val = phy_package_port_read_paged(phydev, i, RTL821X_PAGE_STATE, 0x10);
889 if (val & 0x40)
890 break;
891 }
892 if (l >= 100) {
893 phydev_err(phydev, "Could not patch PHY\n");
894 return -1;
895 }
896 }
897
898 /* Use Broadcast ID method for patching */
899 rtl821x_phy_setup_package_broadcast(phydev, true);
900
901 phy_write_paged(phydev, RTL83XX_PAGE_RAW, 30, 8);
902 phy_write_paged(phydev, 0x26e, 17, 0xb);
903 phy_write_paged(phydev, 0x26e, 16, 0x2);
904 mdelay(1);
905 ipd = phy_read_paged(phydev, 0x26e, 19);
906 phy_write_paged(phydev, 0, 30, 0);
907 ipd = (ipd >> 4) & 0xf; /* unused ? */
908
909 i = 0;
910 while (rtl8218B_6276B_rtl8380_perport[i * 2]) {
911 phy_write_paged(phydev, RTL83XX_PAGE_RAW, rtl8218B_6276B_rtl8380_perport[i * 2],
912 rtl8218B_6276B_rtl8380_perport[i * 2 + 1]);
913 i++;
914 }
915
916 /*Disable broadcast ID*/
917 rtl821x_phy_setup_package_broadcast(phydev, false);
918
919 return 0;
920 }
921
922 static int rtl8218b_ext_match_phy_device(struct phy_device *phydev)
923 {
924 int addr = phydev->mdio.addr;
925
926 /* Both the RTL8214FC and the external RTL8218B have the same
927 * PHY ID. On the RTL838x, the RTL8218B can only be attached_dev
928 * at PHY IDs 0-7, while the RTL8214FC must be attached via
929 * the pair of SGMII/1000Base-X with higher PHY-IDs
930 */
931 if (soc_info.family == RTL8380_FAMILY_ID)
932 return phydev->phy_id == PHY_ID_RTL8218B_E && addr < 8;
933 else
934 return phydev->phy_id == PHY_ID_RTL8218B_E;
935 }
936
937 static bool rtl8214fc_media_is_fibre(struct phy_device *phydev)
938 {
939 int mac = phydev->mdio.addr;
940
941 static int reg[] = {16, 19, 20, 21};
942 u32 val;
943
944 phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL);
945 val = phy_package_read_paged(phydev, RTL821X_PAGE_PORT, reg[mac % 4]);
946 phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
947
948 if (val & BIT(11))
949 return false;
950
951 return true;
952 }
953
954 static void rtl8214fc_power_set(struct phy_device *phydev, int port, bool on)
955 {
956 char *state = on ? "on" : "off";
957
958 if (port == PORT_FIBRE) {
959 pr_info("%s: Powering %s FIBRE (port %d)\n", __func__, state, phydev->mdio.addr);
960 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_FIBRE);
961 } else {
962 pr_info("%s: Powering %s COPPER (port %d)\n", __func__, state, phydev->mdio.addr);
963 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
964 }
965
966 if (on) {
967 phy_modify_paged(phydev, RTL821X_PAGE_POWER, 0x10, BIT(11), 0);
968 } else {
969 phy_modify_paged(phydev, RTL821X_PAGE_POWER, 0x10, 0, BIT(11));
970 }
971
972 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
973 }
974
975 static int rtl8214fc_suspend(struct phy_device *phydev)
976 {
977 rtl8214fc_power_set(phydev, PORT_MII, false);
978 rtl8214fc_power_set(phydev, PORT_FIBRE, false);
979
980 return 0;
981 }
982
983 static int rtl8214fc_resume(struct phy_device *phydev)
984 {
985 if (rtl8214fc_media_is_fibre(phydev)) {
986 rtl8214fc_power_set(phydev, PORT_MII, false);
987 rtl8214fc_power_set(phydev, PORT_FIBRE, true);
988 } else {
989 rtl8214fc_power_set(phydev, PORT_FIBRE, false);
990 rtl8214fc_power_set(phydev, PORT_MII, true);
991 }
992
993 return 0;
994 }
995
996 static void rtl8214fc_media_set(struct phy_device *phydev, bool set_fibre)
997 {
998 int mac = phydev->mdio.addr;
999
1000 static int reg[] = {16, 19, 20, 21};
1001 int val;
1002
1003 pr_info("%s: port %d, set_fibre: %d\n", __func__, mac, set_fibre);
1004 phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL);
1005 val = phy_package_read_paged(phydev, RTL821X_PAGE_PORT, reg[mac % 4]);
1006
1007 val |= BIT(10);
1008 if (set_fibre) {
1009 val &= ~BIT(11);
1010 } else {
1011 val |= BIT(11);
1012 }
1013
1014 phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL);
1015 phy_package_write_paged(phydev, RTL821X_PAGE_PORT, reg[mac % 4], val);
1016 phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1017
1018 if (!phydev->suspended) {
1019 if (set_fibre) {
1020 rtl8214fc_power_set(phydev, PORT_MII, false);
1021 rtl8214fc_power_set(phydev, PORT_FIBRE, true);
1022 } else {
1023 rtl8214fc_power_set(phydev, PORT_FIBRE, false);
1024 rtl8214fc_power_set(phydev, PORT_MII, true);
1025 }
1026 }
1027 }
1028
1029 static int rtl8214fc_set_port(struct phy_device *phydev, int port)
1030 {
1031 bool is_fibre = (port == PORT_FIBRE ? true : false);
1032 int addr = phydev->mdio.addr;
1033
1034 pr_debug("%s port %d to %d\n", __func__, addr, port);
1035
1036 rtl8214fc_media_set(phydev, is_fibre);
1037 return 0;
1038 }
1039
1040 static int rtl8214fc_get_port(struct phy_device *phydev)
1041 {
1042 int addr = phydev->mdio.addr;
1043
1044 pr_debug("%s: port %d\n", __func__, addr);
1045 if (rtl8214fc_media_is_fibre(phydev))
1046 return PORT_FIBRE;
1047 return PORT_MII;
1048 }
1049
1050 /*
1051 * Enable EEE on the RTL8218B PHYs
1052 * The method used is not the preferred way (which would be based on the MAC-EEE state,
1053 * but the only way that works since the kernel first enables EEE in the MAC
1054 * and then sets up the PHY. The MAC-based approach would require the oppsite.
1055 */
1056 void rtl8218d_eee_set(struct phy_device *phydev, bool enable)
1057 {
1058 u32 val;
1059 bool an_enabled;
1060
1061 pr_debug("In %s %d, enable %d\n", __func__, phydev->mdio.addr, enable);
1062 /* Set GPHY page to copper */
1063 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1064
1065 val = phy_read(phydev, 0);
1066 an_enabled = val & BIT(12);
1067
1068 /* Enable 100M (bit 1) / 1000M (bit 2) EEE */
1069 val = phy_read_mmd(phydev, 7, 60);
1070 val |= BIT(2) | BIT(1);
1071 phy_write_mmd(phydev, 7, 60, enable ? 0x6 : 0);
1072
1073 /* 500M EEE ability */
1074 val = phy_read_paged(phydev, RTL821X_PAGE_GPHY, 20);
1075 if (enable)
1076 val |= BIT(7);
1077 else
1078 val &= ~BIT(7);
1079 phy_write_paged(phydev, RTL821X_PAGE_GPHY, 20, val);
1080
1081 /* Restart AN if enabled */
1082 if (an_enabled) {
1083 val = phy_read(phydev, 0);
1084 val |= BIT(9);
1085 phy_write(phydev, 0, val);
1086 }
1087
1088 /* GPHY page back to auto*/
1089 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1090 }
1091
1092 static int rtl8218b_get_eee(struct phy_device *phydev,
1093 struct ethtool_eee *e)
1094 {
1095 u32 val;
1096 int addr = phydev->mdio.addr;
1097
1098 pr_debug("In %s, port %d, was enabled: %d\n", __func__, addr, e->eee_enabled);
1099
1100 /* Set GPHY page to copper */
1101 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1102
1103 val = phy_read_paged(phydev, 7, 60);
1104 if (e->eee_enabled) {
1105 // Verify vs MAC-based EEE
1106 e->eee_enabled = !!(val & BIT(7));
1107 if (!e->eee_enabled) {
1108 val = phy_read_paged(phydev, RTL821X_PAGE_MAC, 25);
1109 e->eee_enabled = !!(val & BIT(4));
1110 }
1111 }
1112 pr_debug("%s: enabled: %d\n", __func__, e->eee_enabled);
1113
1114 /* GPHY page to auto */
1115 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1116
1117 return 0;
1118 }
1119
1120 static int rtl8218d_get_eee(struct phy_device *phydev,
1121 struct ethtool_eee *e)
1122 {
1123 u32 val;
1124 int addr = phydev->mdio.addr;
1125
1126 pr_debug("In %s, port %d, was enabled: %d\n", __func__, addr, e->eee_enabled);
1127
1128 /* Set GPHY page to copper */
1129 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1130
1131 val = phy_read_paged(phydev, 7, 60);
1132 if (e->eee_enabled)
1133 e->eee_enabled = !!(val & BIT(7));
1134 pr_debug("%s: enabled: %d\n", __func__, e->eee_enabled);
1135
1136 /* GPHY page to auto */
1137 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1138
1139 return 0;
1140 }
1141
1142 static int rtl8214fc_set_eee(struct phy_device *phydev,
1143 struct ethtool_eee *e)
1144 {
1145 u32 poll_state;
1146 int port = phydev->mdio.addr;
1147 bool an_enabled;
1148 u32 val;
1149
1150 pr_debug("In %s port %d, enabled %d\n", __func__, port, e->eee_enabled);
1151
1152 if (rtl8214fc_media_is_fibre(phydev)) {
1153 netdev_err(phydev->attached_dev, "Port %d configured for FIBRE", port);
1154 return -ENOTSUPP;
1155 }
1156
1157 poll_state = disable_polling(port);
1158
1159 /* Set GPHY page to copper */
1160 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1161
1162 // Get auto-negotiation status
1163 val = phy_read(phydev, 0);
1164 an_enabled = val & BIT(12);
1165
1166 pr_info("%s: aneg: %d\n", __func__, an_enabled);
1167 val = phy_read_paged(phydev, RTL821X_PAGE_MAC, 25);
1168 val &= ~BIT(5); // Use MAC-based EEE
1169 phy_write_paged(phydev, RTL821X_PAGE_MAC, 25, val);
1170
1171 /* Enable 100M (bit 1) / 1000M (bit 2) EEE */
1172 phy_write_paged(phydev, 7, 60, e->eee_enabled ? 0x6 : 0);
1173
1174 /* 500M EEE ability */
1175 val = phy_read_paged(phydev, RTL821X_PAGE_GPHY, 20);
1176 if (e->eee_enabled)
1177 val |= BIT(7);
1178 else
1179 val &= ~BIT(7);
1180
1181 phy_write_paged(phydev, RTL821X_PAGE_GPHY, 20, val);
1182
1183 /* Restart AN if enabled */
1184 if (an_enabled) {
1185 pr_info("%s: doing aneg\n", __func__);
1186 val = phy_read(phydev, 0);
1187 val |= BIT(9);
1188 phy_write(phydev, 0, val);
1189 }
1190
1191 /* GPHY page back to auto*/
1192 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1193
1194 resume_polling(poll_state);
1195
1196 return 0;
1197 }
1198
1199 static int rtl8214fc_get_eee(struct phy_device *phydev,
1200 struct ethtool_eee *e)
1201 {
1202 int addr = phydev->mdio.addr;
1203
1204 pr_debug("In %s port %d, enabled %d\n", __func__, addr, e->eee_enabled);
1205 if (rtl8214fc_media_is_fibre(phydev)) {
1206 netdev_err(phydev->attached_dev, "Port %d configured for FIBRE", addr);
1207 return -ENOTSUPP;
1208 }
1209
1210 return rtl8218b_get_eee(phydev, e);
1211 }
1212
1213 static int rtl8218b_set_eee(struct phy_device *phydev, struct ethtool_eee *e)
1214 {
1215 int port = phydev->mdio.addr;
1216 u64 poll_state;
1217 u32 val;
1218 bool an_enabled;
1219
1220 pr_info("In %s, port %d, enabled %d\n", __func__, port, e->eee_enabled);
1221
1222 poll_state = disable_polling(port);
1223
1224 /* Set GPHY page to copper */
1225 phy_write(phydev, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1226 val = phy_read(phydev, 0);
1227 an_enabled = val & BIT(12);
1228
1229 if (e->eee_enabled) {
1230 /* 100/1000M EEE Capability */
1231 phy_write(phydev, 13, 0x0007);
1232 phy_write(phydev, 14, 0x003C);
1233 phy_write(phydev, 13, 0x4007);
1234 phy_write(phydev, 14, 0x0006);
1235
1236 val = phy_read_paged(phydev, RTL821X_PAGE_MAC, 25);
1237 val |= BIT(4);
1238 phy_write_paged(phydev, RTL821X_PAGE_MAC, 25, val);
1239 } else {
1240 /* 100/1000M EEE Capability */
1241 phy_write(phydev, 13, 0x0007);
1242 phy_write(phydev, 14, 0x003C);
1243 phy_write(phydev, 13, 0x0007);
1244 phy_write(phydev, 14, 0x0000);
1245
1246 val = phy_read_paged(phydev, RTL821X_PAGE_MAC, 25);
1247 val &= ~BIT(4);
1248 phy_write_paged(phydev, RTL821X_PAGE_MAC, 25, val);
1249 }
1250
1251 /* Restart AN if enabled */
1252 if (an_enabled) {
1253 val = phy_read(phydev, 0);
1254 val |= BIT(9);
1255 phy_write(phydev, 0, val);
1256 }
1257
1258 /* GPHY page back to auto*/
1259 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1260
1261 pr_info("%s done\n", __func__);
1262 resume_polling(poll_state);
1263
1264 return 0;
1265 }
1266
1267 static int rtl8218d_set_eee(struct phy_device *phydev, struct ethtool_eee *e)
1268 {
1269 int addr = phydev->mdio.addr;
1270 u64 poll_state;
1271
1272 pr_info("In %s, port %d, enabled %d\n", __func__, addr, e->eee_enabled);
1273
1274 poll_state = disable_polling(addr);
1275
1276 rtl8218d_eee_set(phydev, (bool) e->eee_enabled);
1277
1278 resume_polling(poll_state);
1279
1280 return 0;
1281 }
1282
1283 static int rtl8214c_match_phy_device(struct phy_device *phydev)
1284 {
1285 return phydev->phy_id == PHY_ID_RTL8214C;
1286 }
1287
1288 static int rtl8380_configure_rtl8214c(struct phy_device *phydev)
1289 {
1290 u32 phy_id, val;
1291 int mac = phydev->mdio.addr;
1292
1293 val = phy_read(phydev, 2);
1294 phy_id = val << 16;
1295 val = phy_read(phydev, 3);
1296 phy_id |= val;
1297 pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
1298
1299 phydev_info(phydev, "Detected external RTL8214C\n");
1300
1301 /* GPHY auto conf */
1302 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1303 return 0;
1304 }
1305
1306 static int rtl8380_configure_rtl8214fc(struct phy_device *phydev)
1307 {
1308 u32 phy_id, val, page = 0;
1309 int i, l;
1310 int mac = phydev->mdio.addr;
1311 struct fw_header *h;
1312 u32 *rtl8380_rtl8214fc_perchip;
1313 u32 *rtl8380_rtl8214fc_perport;
1314
1315 val = phy_read(phydev, 2);
1316 phy_id = val << 16;
1317 val = phy_read(phydev, 3);
1318 phy_id |= val;
1319 pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
1320
1321 /* Read internal PHY id */
1322 phy_write_paged(phydev, 0, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1323 phy_write_paged(phydev, 0x1f, 0x1b, 0x0002);
1324 val = phy_read_paged(phydev, 0x1f, 0x1c);
1325 if (val != 0x6276) {
1326 phydev_err(phydev, "Expected external RTL8214FC, found PHY-ID %x\n", val);
1327 return -1;
1328 }
1329 phydev_info(phydev, "Detected external RTL8214FC\n");
1330
1331 h = rtl838x_request_fw(phydev, &rtl838x_8214fc_fw, FIRMWARE_838X_8214FC_1);
1332 if (!h)
1333 return -1;
1334
1335 if (h->phy != 0x8214fc00) {
1336 phydev_err(phydev, "Wrong firmware file: PHY mismatch.\n");
1337 return -1;
1338 }
1339
1340 rtl8380_rtl8214fc_perchip = (void *)h + sizeof(struct fw_header)
1341 + h->parts[0].start;
1342
1343 rtl8380_rtl8214fc_perport = (void *)h + sizeof(struct fw_header)
1344 + h->parts[1].start;
1345
1346 /* detect phy version */
1347 phy_write_paged(phydev, RTL83XX_PAGE_RAW, 27, 0x0004);
1348 val = phy_read_paged(phydev, RTL83XX_PAGE_RAW, 28);
1349
1350 val = phy_read(phydev, 16);
1351 if (val & (1 << 11))
1352 rtl8380_rtl8214fc_on_off(phydev, true);
1353 else
1354 rtl8380_phy_reset(phydev);
1355
1356 msleep(100);
1357 phy_write_paged(phydev, 0, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1358
1359 i = 0;
1360 while (rtl8380_rtl8214fc_perchip[i * 3]
1361 && rtl8380_rtl8214fc_perchip[i * 3 + 1]) {
1362 if (rtl8380_rtl8214fc_perchip[i * 3 + 1] == 0x1f)
1363 page = rtl8380_rtl8214fc_perchip[i * 3 + 2];
1364 if (rtl8380_rtl8214fc_perchip[i * 3 + 1] == 0x13 && page == 0x260) {
1365 val = phy_read_paged(phydev, 0x260, 13);
1366 val = (val & 0x1f00) | (rtl8380_rtl8214fc_perchip[i * 3 + 2]
1367 & 0xe0ff);
1368 phy_write_paged(phydev, RTL83XX_PAGE_RAW,
1369 rtl8380_rtl8214fc_perchip[i * 3 + 1], val);
1370 } else {
1371 phy_write_paged(phydev, RTL83XX_PAGE_RAW,
1372 rtl8380_rtl8214fc_perchip[i * 3 + 1],
1373 rtl8380_rtl8214fc_perchip[i * 3 + 2]);
1374 }
1375 i++;
1376 }
1377
1378 /* Force copper medium */
1379 for (i = 0; i < 4; i++) {
1380 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
1381 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1382 }
1383
1384 /* Enable PHY */
1385 for (i = 0; i < 4; i++) {
1386 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
1387 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, 0x00, 0x1140);
1388 }
1389 mdelay(100);
1390
1391 /* Disable Autosensing */
1392 for (i = 0; i < 4; i++) {
1393 for (l = 0; l < 100; l++) {
1394 val = phy_package_port_read_paged(phydev, i, RTL821X_PAGE_GPHY, 0x10);
1395 if ((val & 0x7) >= 3)
1396 break;
1397 }
1398 if (l >= 100) {
1399 phydev_err(phydev, "Could not disable autosensing\n");
1400 return -1;
1401 }
1402 }
1403
1404 /* Request patch */
1405 for (i = 0; i < 4; i++) {
1406 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL821X_PAGE_PATCH);
1407 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, 0x10, 0x0010);
1408 }
1409 mdelay(300);
1410
1411 /* Verify patch readiness */
1412 for (i = 0; i < 4; i++) {
1413 for (l = 0; l < 100; l++) {
1414 val = phy_package_port_read_paged(phydev, i, RTL821X_PAGE_STATE, 0x10);
1415 if (val & 0x40)
1416 break;
1417 }
1418 if (l >= 100) {
1419 phydev_err(phydev, "Could not patch PHY\n");
1420 return -1;
1421 }
1422 }
1423 /* Use Broadcast ID method for patching */
1424 rtl821x_phy_setup_package_broadcast(phydev, true);
1425
1426 i = 0;
1427 while (rtl8380_rtl8214fc_perport[i * 2]) {
1428 phy_write_paged(phydev, RTL83XX_PAGE_RAW, rtl8380_rtl8214fc_perport[i * 2],
1429 rtl8380_rtl8214fc_perport[i * 2 + 1]);
1430 i++;
1431 }
1432
1433 /*Disable broadcast ID*/
1434 rtl821x_phy_setup_package_broadcast(phydev, false);
1435
1436 /* Auto medium selection */
1437 for (i = 0; i < 4; i++) {
1438 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
1439 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1440 }
1441
1442 return 0;
1443 }
1444
1445 static int rtl8214fc_match_phy_device(struct phy_device *phydev)
1446 {
1447 int addr = phydev->mdio.addr;
1448
1449 return phydev->phy_id == PHY_ID_RTL8214FC && addr >= 24;
1450 }
1451
1452 static int rtl8380_configure_serdes(struct phy_device *phydev)
1453 {
1454 u32 v;
1455 u32 sds_conf_value;
1456 int i;
1457 struct fw_header *h;
1458 u32 *rtl8380_sds_take_reset;
1459 u32 *rtl8380_sds_common;
1460 u32 *rtl8380_sds01_qsgmii_6275b;
1461 u32 *rtl8380_sds23_qsgmii_6275b;
1462 u32 *rtl8380_sds4_fiber_6275b;
1463 u32 *rtl8380_sds5_fiber_6275b;
1464 u32 *rtl8380_sds_reset;
1465 u32 *rtl8380_sds_release_reset;
1466
1467 phydev_info(phydev, "Detected internal RTL8380 SERDES\n");
1468
1469 h = rtl838x_request_fw(phydev, &rtl838x_8218b_fw, FIRMWARE_838X_8380_1);
1470 if (!h)
1471 return -1;
1472
1473 if (h->magic != 0x83808380) {
1474 phydev_err(phydev, "Wrong firmware file: magic number mismatch.\n");
1475 return -1;
1476 }
1477
1478 rtl8380_sds_take_reset = (void *)h + sizeof(struct fw_header)
1479 + h->parts[0].start;
1480
1481 rtl8380_sds_common = (void *)h + sizeof(struct fw_header)
1482 + h->parts[1].start;
1483
1484 rtl8380_sds01_qsgmii_6275b = (void *)h + sizeof(struct fw_header)
1485 + h->parts[2].start;
1486
1487 rtl8380_sds23_qsgmii_6275b = (void *)h + sizeof(struct fw_header)
1488 + h->parts[3].start;
1489
1490 rtl8380_sds4_fiber_6275b = (void *)h + sizeof(struct fw_header)
1491 + h->parts[4].start;
1492
1493 rtl8380_sds5_fiber_6275b = (void *)h + sizeof(struct fw_header)
1494 + h->parts[5].start;
1495
1496 rtl8380_sds_reset = (void *)h + sizeof(struct fw_header)
1497 + h->parts[6].start;
1498
1499 rtl8380_sds_release_reset = (void *)h + sizeof(struct fw_header)
1500 + h->parts[7].start;
1501
1502 /* Back up serdes power off value */
1503 sds_conf_value = sw_r32(RTL838X_SDS_CFG_REG);
1504 pr_info("SDS power down value: %x\n", sds_conf_value);
1505
1506 /* take serdes into reset */
1507 i = 0;
1508 while (rtl8380_sds_take_reset[2 * i]) {
1509 sw_w32(rtl8380_sds_take_reset[2 * i + 1], rtl8380_sds_take_reset[2 * i]);
1510 i++;
1511 udelay(1000);
1512 }
1513
1514 /* apply common serdes patch */
1515 i = 0;
1516 while (rtl8380_sds_common[2 * i]) {
1517 sw_w32(rtl8380_sds_common[2 * i + 1], rtl8380_sds_common[2 * i]);
1518 i++;
1519 udelay(1000);
1520 }
1521
1522 /* internal R/W enable */
1523 sw_w32(3, RTL838X_INT_RW_CTRL);
1524
1525 /* SerDes ports 4 and 5 are FIBRE ports */
1526 sw_w32_mask(0x7 | 0x38, 1 | (1 << 3), RTL838X_INT_MODE_CTRL);
1527
1528 /* SerDes module settings, SerDes 0-3 are QSGMII */
1529 v = 0x6 << 25 | 0x6 << 20 | 0x6 << 15 | 0x6 << 10;
1530 /* SerDes 4 and 5 are 1000BX FIBRE */
1531 v |= 0x4 << 5 | 0x4;
1532 sw_w32(v, RTL838X_SDS_MODE_SEL);
1533
1534 pr_info("PLL control register: %x\n", sw_r32(RTL838X_PLL_CML_CTRL));
1535 sw_w32_mask(0xfffffff0, 0xaaaaaaaf & 0xf, RTL838X_PLL_CML_CTRL);
1536 i = 0;
1537 while (rtl8380_sds01_qsgmii_6275b[2 * i]) {
1538 sw_w32(rtl8380_sds01_qsgmii_6275b[2 * i + 1],
1539 rtl8380_sds01_qsgmii_6275b[2 * i]);
1540 i++;
1541 }
1542
1543 i = 0;
1544 while (rtl8380_sds23_qsgmii_6275b[2 * i]) {
1545 sw_w32(rtl8380_sds23_qsgmii_6275b[2 * i + 1], rtl8380_sds23_qsgmii_6275b[2 * i]);
1546 i++;
1547 }
1548
1549 i = 0;
1550 while (rtl8380_sds4_fiber_6275b[2 * i]) {
1551 sw_w32(rtl8380_sds4_fiber_6275b[2 * i + 1], rtl8380_sds4_fiber_6275b[2 * i]);
1552 i++;
1553 }
1554
1555 i = 0;
1556 while (rtl8380_sds5_fiber_6275b[2 * i]) {
1557 sw_w32(rtl8380_sds5_fiber_6275b[2 * i + 1], rtl8380_sds5_fiber_6275b[2 * i]);
1558 i++;
1559 }
1560
1561 i = 0;
1562 while (rtl8380_sds_reset[2 * i]) {
1563 sw_w32(rtl8380_sds_reset[2 * i + 1], rtl8380_sds_reset[2 * i]);
1564 i++;
1565 }
1566
1567 i = 0;
1568 while (rtl8380_sds_release_reset[2 * i]) {
1569 sw_w32(rtl8380_sds_release_reset[2 * i + 1], rtl8380_sds_release_reset[2 * i]);
1570 i++;
1571 }
1572
1573 pr_info("SDS power down value now: %x\n", sw_r32(RTL838X_SDS_CFG_REG));
1574 sw_w32(sds_conf_value, RTL838X_SDS_CFG_REG);
1575
1576 pr_info("Configuration of SERDES done\n");
1577 return 0;
1578 }
1579
1580 static int rtl8390_configure_serdes(struct phy_device *phydev)
1581 {
1582 phydev_info(phydev, "Detected internal RTL8390 SERDES\n");
1583
1584 /* In autoneg state, force link, set SR4_CFG_EN_LINK_FIB1G */
1585 sw_w32_mask(0, 1 << 18, RTL839X_SDS12_13_XSG0 + 0x0a);
1586
1587 /* Disable EEE: Clear FRE16_EEE_RSG_FIB1G, FRE16_EEE_STD_FIB1G,
1588 * FRE16_C1_PWRSAV_EN_FIB1G, FRE16_C2_PWRSAV_EN_FIB1G
1589 * and FRE16_EEE_QUIET_FIB1G
1590 */
1591 sw_w32_mask(0x1f << 10, 0, RTL839X_SDS12_13_XSG0 + 0xe0);
1592
1593 return 0;
1594 }
1595
1596 void rtl9300_sds_field_w(int sds, u32 page, u32 reg, int end_bit, int start_bit, u32 v)
1597 {
1598 int l = end_bit - start_bit + 1;
1599 u32 data = v;
1600
1601 if (l < 32) {
1602 u32 mask = BIT(l) - 1;
1603
1604 data = rtl930x_read_sds_phy(sds, page, reg);
1605 data &= ~(mask << start_bit);
1606 data |= (v & mask) << start_bit;
1607 }
1608
1609 rtl930x_write_sds_phy(sds, page, reg, data);
1610 }
1611
1612 u32 rtl9300_sds_field_r(int sds, u32 page, u32 reg, int end_bit, int start_bit)
1613 {
1614 int l = end_bit - start_bit + 1;
1615 u32 v = rtl930x_read_sds_phy(sds, page, reg);
1616
1617 if (l >= 32)
1618 return v;
1619
1620 return (v >> start_bit) & (BIT(l) - 1);
1621 }
1622
1623 /* Read the link and speed status of the internal SerDes of the RTL9300
1624 */
1625 static int rtl9300_read_status(struct phy_device *phydev)
1626 {
1627 struct device *dev = &phydev->mdio.dev;
1628 int phy_addr = phydev->mdio.addr;
1629 struct device_node *dn;
1630 u32 sds_num = 0, status, latch_status, mode;
1631
1632 if (dev->of_node) {
1633 dn = dev->of_node;
1634
1635 if (of_property_read_u32(dn, "sds", &sds_num))
1636 sds_num = -1;
1637 pr_info("%s: Port %d, SerDes is %d\n", __func__, phy_addr, sds_num);
1638 } else {
1639 dev_err(dev, "No DT node.\n");
1640 return -EINVAL;
1641 }
1642
1643 if (sds_num < 0)
1644 return 0;
1645
1646 mode = rtl9300_sds_mode_get(sds_num);
1647 pr_info("%s got SDS mode %02x\n", __func__, mode);
1648 if (mode == 0x1a) { // 10GR mode
1649 status = rtl9300_sds_field_r(sds_num, 0x5, 0, 12, 12);
1650 latch_status = rtl9300_sds_field_r(sds_num, 0x4, 1, 2, 2);
1651 status |= rtl9300_sds_field_r(sds_num, 0x5, 0, 12, 12);
1652 latch_status |= rtl9300_sds_field_r(sds_num, 0x4, 1, 2, 2);
1653 } else {
1654 status = rtl9300_sds_field_r(sds_num, 0x1, 29, 8, 0);
1655 latch_status = rtl9300_sds_field_r(sds_num, 0x1, 30, 8, 0);
1656 status |= rtl9300_sds_field_r(sds_num, 0x1, 29, 8, 0);
1657 latch_status |= rtl9300_sds_field_r(sds_num, 0x1, 30, 8, 0);
1658 }
1659
1660 pr_info("%s link status: status: %d, latch %d\n", __func__, status, latch_status);
1661
1662 if (latch_status) {
1663 phydev->link = true;
1664 if (mode == 0x1a)
1665 phydev->speed = SPEED_10000;
1666 else
1667 phydev->speed = SPEED_1000;
1668
1669 phydev->duplex = DUPLEX_FULL;
1670 }
1671
1672 return 0;
1673 }
1674
1675 void rtl930x_sds_rx_rst(int sds_num, phy_interface_t phy_if)
1676 {
1677 int page = 0x2e; // 10GR and USXGMII
1678
1679 if (phy_if == PHY_INTERFACE_MODE_1000BASEX)
1680 page = 0x24;
1681
1682 rtl9300_sds_field_w(sds_num, page, 0x15, 4, 4, 0x1);
1683 mdelay(5);
1684 rtl9300_sds_field_w(sds_num, page, 0x15, 4, 4, 0x0);
1685 }
1686
1687 /*
1688 * Force PHY modes on 10GBit Serdes
1689 */
1690 void rtl9300_force_sds_mode(int sds, phy_interface_t phy_if)
1691 {
1692 int sds_mode;
1693 bool lc_on;
1694 int i, lc_value;
1695 int lane_0 = (sds % 2) ? sds - 1 : sds;
1696 u32 v, cr_0, cr_1, cr_2;
1697 u32 m_bit, l_bit;
1698
1699 pr_info("%s --------------------- serdes %d forcing to %x ...\n", __func__, sds, sds_mode);
1700 pr_info("%s: SDS: %d, mode %d\n", __func__, sds, phy_if);
1701 switch (phy_if) {
1702 case PHY_INTERFACE_MODE_SGMII:
1703 sds_mode = 0x2;
1704 lc_on = false;
1705 lc_value = 0x1;
1706 break;
1707
1708 case PHY_INTERFACE_MODE_HSGMII:
1709 sds_mode = 0x12;
1710 lc_value = 0x3;
1711 // Configure LC
1712 break;
1713
1714 case PHY_INTERFACE_MODE_1000BASEX:
1715 sds_mode = 0x04;
1716 lc_on = false;
1717 break;
1718
1719 case PHY_INTERFACE_MODE_2500BASEX:
1720 sds_mode = 0x16;
1721 lc_value = 0x3;
1722 // Configure LC
1723 break;
1724
1725 case PHY_INTERFACE_MODE_10GBASER:
1726 sds_mode = 0x1a;
1727 lc_on = true;
1728 lc_value = 0x5;
1729 break;
1730
1731 case PHY_INTERFACE_MODE_NA:
1732 // This will disable SerDes
1733 sds_mode = 0x1f;
1734 break;
1735
1736 default:
1737 pr_err("%s: unknown serdes mode: %s\n",
1738 __func__, phy_modes(phy_if));
1739 return;
1740 }
1741
1742 pr_info("%s: SDS mode %x\n", __func__, sds_mode);
1743 // Power down SerDes
1744 rtl9300_sds_field_w(sds, 0x20, 0, 7, 6, 0x3);
1745 if (sds == 5) pr_info("%s after %x\n", __func__, rtl930x_read_sds_phy(sds, 0x20, 0));
1746
1747 if (sds == 5) pr_info("%s a %x\n", __func__, rtl930x_read_sds_phy(sds, 0x1f, 9));
1748 // Force mode enable
1749 rtl9300_sds_field_w(sds, 0x1f, 9, 6, 6, 0x1);
1750 if (sds == 5) pr_info("%s b %x\n", __func__, rtl930x_read_sds_phy(sds, 0x1f, 9));
1751
1752 /* SerDes off */
1753 rtl9300_sds_field_w(sds, 0x1f, 9, 11, 7, 0x1f);
1754
1755 if (phy_if == PHY_INTERFACE_MODE_NA)
1756 return;
1757
1758 if (sds == 5) pr_info("%s c %x\n", __func__, rtl930x_read_sds_phy(sds, 0x20, 18));
1759 // Enable LC and ring
1760 rtl9300_sds_field_w(lane_0, 0x20, 18, 3, 0, 0xf);
1761
1762 if (sds == lane_0)
1763 rtl9300_sds_field_w(lane_0, 0x20, 18, 5, 4, 0x1);
1764 else
1765 rtl9300_sds_field_w(lane_0, 0x20, 18, 7, 6, 0x1);
1766
1767 rtl9300_sds_field_w(sds, 0x20, 0, 5, 4, 0x3);
1768
1769 if (lc_on)
1770 rtl9300_sds_field_w(lane_0, 0x20, 18, 11, 8, lc_value);
1771 else
1772 rtl9300_sds_field_w(lane_0, 0x20, 18, 15, 12, lc_value);
1773
1774 // Force analog LC & ring on
1775 rtl9300_sds_field_w(lane_0, 0x21, 11, 3, 0, 0xf);
1776
1777 v = lc_on ? 0x3 : 0x1;
1778
1779 if (sds == lane_0)
1780 rtl9300_sds_field_w(lane_0, 0x20, 18, 5, 4, v);
1781 else
1782 rtl9300_sds_field_w(lane_0, 0x20, 18, 7, 6, v);
1783
1784 // Force SerDes mode
1785 rtl9300_sds_field_w(sds, 0x1f, 9, 6, 6, 1);
1786 rtl9300_sds_field_w(sds, 0x1f, 9, 11, 7, sds_mode);
1787
1788 // Toggle LC or Ring
1789 for (i = 0; i < 20; i++) {
1790 mdelay(200);
1791
1792 rtl930x_write_sds_phy(lane_0, 0x1f, 2, 53);
1793
1794 m_bit = (lane_0 == sds) ? (4) : (5);
1795 l_bit = (lane_0 == sds) ? (4) : (5);
1796
1797 cr_0 = rtl9300_sds_field_r(lane_0, 0x1f, 20, m_bit, l_bit);
1798 mdelay(10);
1799 cr_1 = rtl9300_sds_field_r(lane_0, 0x1f, 20, m_bit, l_bit);
1800 mdelay(10);
1801 cr_2 = rtl9300_sds_field_r(lane_0, 0x1f, 20, m_bit, l_bit);
1802
1803 if (cr_0 && cr_1 && cr_2) {
1804 u32 t;
1805 if (phy_if != PHY_INTERFACE_MODE_10GBASER)
1806 break;
1807
1808 t = rtl9300_sds_field_r(sds, 0x6, 0x1, 2, 2);
1809 rtl9300_sds_field_w(sds, 0x6, 0x1, 2, 2, 0x1);
1810
1811 // Reset FSM
1812 rtl9300_sds_field_w(sds, 0x6, 0x2, 12, 12, 0x1);
1813 mdelay(10);
1814 rtl9300_sds_field_w(sds, 0x6, 0x2, 12, 12, 0x0);
1815 mdelay(10);
1816
1817 // Need to read this twice
1818 v = rtl9300_sds_field_r(sds, 0x5, 0, 12, 12);
1819 v = rtl9300_sds_field_r(sds, 0x5, 0, 12, 12);
1820
1821 rtl9300_sds_field_w(sds, 0x6, 0x1, 2, 2, t);
1822
1823 // Reset FSM again
1824 rtl9300_sds_field_w(sds, 0x6, 0x2, 12, 12, 0x1);
1825 mdelay(10);
1826 rtl9300_sds_field_w(sds, 0x6, 0x2, 12, 12, 0x0);
1827 mdelay(10);
1828
1829 if (v == 1)
1830 break;
1831 }
1832
1833 m_bit = (phy_if == PHY_INTERFACE_MODE_10GBASER) ? 3 : 1;
1834 l_bit = (phy_if == PHY_INTERFACE_MODE_10GBASER) ? 2 : 0;
1835
1836 rtl9300_sds_field_w(lane_0, 0x21, 11, m_bit, l_bit, 0x2);
1837 mdelay(10);
1838 rtl9300_sds_field_w(lane_0, 0x21, 11, m_bit, l_bit, 0x3);
1839 }
1840
1841 rtl930x_sds_rx_rst(sds, phy_if);
1842
1843 // Re-enable power
1844 rtl9300_sds_field_w(sds, 0x20, 0, 7, 6, 0);
1845
1846 pr_info("%s --------------------- serdes %d forced to %x DONE\n", __func__, sds, sds_mode);
1847 }
1848
1849 void rtl9300_sds_tx_config(int sds, phy_interface_t phy_if)
1850 {
1851 // parameters: rtl9303_80G_txParam_s2
1852 int impedance = 0x8;
1853 int pre_amp = 0x2;
1854 int main_amp = 0x9;
1855 int post_amp = 0x2;
1856 int pre_en = 0x1;
1857 int post_en = 0x1;
1858 int page;
1859
1860 switch(phy_if) {
1861 case PHY_INTERFACE_MODE_1000BASEX:
1862 page = 0x25;
1863 break;
1864 case PHY_INTERFACE_MODE_HSGMII:
1865 case PHY_INTERFACE_MODE_2500BASEX:
1866 page = 0x29;
1867 break;
1868 case PHY_INTERFACE_MODE_10GBASER:
1869 page = 0x2f;
1870 break;
1871 default:
1872 pr_err("%s: unsupported PHY mode\n", __func__);
1873 return;
1874 }
1875
1876 rtl9300_sds_field_w(sds, page, 0x1, 15, 11, pre_amp);
1877 rtl9300_sds_field_w(sds, page, 0x7, 0, 0, pre_en);
1878 rtl9300_sds_field_w(sds, page, 0x7, 8, 4, main_amp);
1879 rtl9300_sds_field_w(sds, page, 0x6, 4, 0, post_amp);
1880 rtl9300_sds_field_w(sds, page, 0x7, 3, 3, post_en);
1881 rtl9300_sds_field_w(sds, page, 0x18, 15, 12, impedance);
1882 }
1883
1884 /*
1885 * Wait for clock ready, this assumes the SerDes is in XGMII mode
1886 * timeout is in ms
1887 */
1888 int rtl9300_sds_clock_wait(int timeout)
1889 {
1890 u32 v;
1891 unsigned long start = jiffies;
1892
1893 do {
1894 rtl9300_sds_field_w(2, 0x1f, 0x2, 15, 0, 53);
1895 v = rtl9300_sds_field_r(2, 0x1f, 20, 5, 4);
1896 if (v == 3)
1897 return 0;
1898 } while (jiffies < start + (HZ / 1000) * timeout);
1899
1900 return 1;
1901 }
1902
1903 void rtl9300_serdes_mac_link_config(int sds, bool tx_normal, bool rx_normal)
1904 {
1905 u32 v10, v1;
1906
1907 v10 = rtl930x_read_sds_phy(sds, 6, 2); // 10GBit, page 6, reg 2
1908 v1 = rtl930x_read_sds_phy(sds, 0, 0); // 1GBit, page 0, reg 0
1909 pr_info("%s: registers before %08x %08x\n", __func__, v10, v1);
1910
1911 v10 &= ~(BIT(13) | BIT(14));
1912 v1 &= ~(BIT(8) | BIT(9));
1913
1914 v10 |= rx_normal ? 0 : BIT(13);
1915 v1 |= rx_normal ? 0 : BIT(9);
1916
1917 v10 |= tx_normal ? 0 : BIT(14);
1918 v1 |= tx_normal ? 0 : BIT(8);
1919
1920 rtl930x_write_sds_phy(sds, 6, 2, v10);
1921 rtl930x_write_sds_phy(sds, 0, 0, v1);
1922
1923 v10 = rtl930x_read_sds_phy(sds, 6, 2);
1924 v1 = rtl930x_read_sds_phy(sds, 0, 0);
1925 pr_info("%s: registers after %08x %08x\n", __func__, v10, v1);
1926 }
1927
1928 void rtl9300_sds_rxcal_dcvs_manual(u32 sds_num, u32 dcvs_id, bool manual, u32 dvcs_list[])
1929 {
1930 if (manual) {
1931 switch(dcvs_id) {
1932 case 0:
1933 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 14, 14, 0x1);
1934 rtl9300_sds_field_w(sds_num, 0x2f, 0x03, 5, 5, dvcs_list[0]);
1935 rtl9300_sds_field_w(sds_num, 0x2f, 0x03, 4, 0, dvcs_list[1]);
1936 break;
1937 case 1:
1938 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 13, 13, 0x1);
1939 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 15, 15, dvcs_list[0]);
1940 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 14, 11, dvcs_list[1]);
1941 break;
1942 case 2:
1943 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 12, 12, 0x1);
1944 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 10, 10, dvcs_list[0]);
1945 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 9, 6, dvcs_list[1]);
1946 break;
1947 case 3:
1948 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 11, 11, 0x1);
1949 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 5, 5, dvcs_list[0]);
1950 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 4, 1, dvcs_list[1]);
1951 break;
1952 case 4:
1953 rtl9300_sds_field_w(sds_num, 0x2e, 0x01, 15, 15, 0x1);
1954 rtl9300_sds_field_w(sds_num, 0x2e, 0x11, 10, 10, dvcs_list[0]);
1955 rtl9300_sds_field_w(sds_num, 0x2e, 0x11, 9, 6, dvcs_list[1]);
1956 break;
1957 case 5:
1958 rtl9300_sds_field_w(sds_num, 0x2e, 0x02, 11, 11, 0x1);
1959 rtl9300_sds_field_w(sds_num, 0x2e, 0x11, 4, 4, dvcs_list[0]);
1960 rtl9300_sds_field_w(sds_num, 0x2e, 0x11, 3, 0, dvcs_list[1]);
1961 break;
1962 default:
1963 break;
1964 }
1965 } else {
1966 switch(dcvs_id) {
1967 case 0:
1968 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 14, 14, 0x0);
1969 break;
1970 case 1:
1971 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 13, 13, 0x0);
1972 break;
1973 case 2:
1974 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 12, 12, 0x0);
1975 break;
1976 case 3:
1977 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 11, 11, 0x0);
1978 break;
1979 case 4:
1980 rtl9300_sds_field_w(sds_num, 0x2e, 0x01, 15, 15, 0x0);
1981 break;
1982 case 5:
1983 rtl9300_sds_field_w(sds_num, 0x2e, 0x02, 11, 11, 0x0);
1984 break;
1985 default:
1986 break;
1987 }
1988 mdelay(1);
1989 }
1990 }
1991
1992 void rtl9300_sds_rxcal_dcvs_get(u32 sds_num, u32 dcvs_id, u32 dcvs_list[])
1993 {
1994 u32 dcvs_sign_out = 0, dcvs_coef_bin = 0;
1995 bool dcvs_manual;
1996
1997 if (!(sds_num % 2))
1998 rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
1999 else
2000 rtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31);
2001
2002 // ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1]
2003 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
2004
2005 // ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x]
2006 rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x20);
2007
2008 switch(dcvs_id) {
2009 case 0:
2010 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x22);
2011 mdelay(1);
2012
2013 // ##DCVS0 Read Out
2014 dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2015 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2016 dcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 14, 14);
2017 break;
2018
2019 case 1:
2020 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x23);
2021 mdelay(1);
2022
2023 // ##DCVS0 Read Out
2024 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2025 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2026 dcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 13, 13);
2027 break;
2028
2029 case 2:
2030 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x24);
2031 mdelay(1);
2032
2033 // ##DCVS0 Read Out
2034 dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2035 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2036 dcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 12, 12);
2037 break;
2038 case 3:
2039 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x25);
2040 mdelay(1);
2041
2042 // ##DCVS0 Read Out
2043 dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2044 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2045 dcvs_manual = rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 11, 11);
2046 break;
2047
2048 case 4:
2049 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x2c);
2050 mdelay(1);
2051
2052 // ##DCVS0 Read Out
2053 dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2054 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2055 dcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x01, 15, 15);
2056 break;
2057
2058 case 5:
2059 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x2d);
2060 mdelay(1);
2061
2062 // ##DCVS0 Read Out
2063 dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2064 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2065 dcvs_manual = rtl9300_sds_field_r(sds_num, 0x2e, 0x02, 11, 11);
2066 break;
2067
2068 default:
2069 break;
2070 }
2071
2072 if (dcvs_sign_out)
2073 pr_info("%s DCVS %u Sign: -", __func__, dcvs_id);
2074 else
2075 pr_info("%s DCVS %u Sign: +", __func__, dcvs_id);
2076
2077 pr_info("DCVS %u even coefficient = %u", dcvs_id, dcvs_coef_bin);
2078 pr_info("DCVS %u manual = %u", dcvs_id, dcvs_manual);
2079
2080 dcvs_list[0] = dcvs_sign_out;
2081 dcvs_list[1] = dcvs_coef_bin;
2082 }
2083
2084 void rtl9300_sds_rxcal_leq_manual(u32 sds_num, bool manual, u32 leq_gray)
2085 {
2086 if (manual) {
2087 rtl9300_sds_field_w(sds_num, 0x2e, 0x18, 15, 15, 0x1);
2088 rtl9300_sds_field_w(sds_num, 0x2e, 0x16, 14, 10, leq_gray);
2089 } else {
2090 rtl9300_sds_field_w(sds_num, 0x2e, 0x18, 15, 15, 0x0);
2091 mdelay(100);
2092 }
2093 }
2094
2095 void rtl9300_sds_rxcal_leq_offset_manual(u32 sds_num, bool manual, u32 offset)
2096 {
2097 if (manual) {
2098 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 6, 2, offset);
2099 } else {
2100 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 6, 2, offset);
2101 mdelay(1);
2102 }
2103 }
2104
2105 #define GRAY_BITS 5
2106 u32 rtl9300_sds_rxcal_gray_to_binary(u32 gray_code)
2107 {
2108 int i, j, m;
2109 u32 g[GRAY_BITS];
2110 u32 c[GRAY_BITS];
2111 u32 leq_binary = 0;
2112
2113 for(i = 0; i < GRAY_BITS; i++)
2114 g[i] = (gray_code & BIT(i)) >> i;
2115
2116 m = GRAY_BITS - 1;
2117
2118 c[m] = g[m];
2119
2120 for(i = 0; i < m; i++) {
2121 c[i] = g[i];
2122 for(j = i + 1; j < GRAY_BITS; j++)
2123 c[i] = c[i] ^ g[j];
2124 }
2125
2126 for(i = 0; i < GRAY_BITS; i++)
2127 leq_binary += c[i] << i;
2128
2129 return leq_binary;
2130 }
2131
2132 u32 rtl9300_sds_rxcal_leq_read(int sds_num)
2133 {
2134 u32 leq_gray, leq_bin;
2135 bool leq_manual;
2136
2137 if (!(sds_num % 2))
2138 rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
2139 else
2140 rtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31);
2141
2142 // ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1]
2143 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
2144
2145 // ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[0 1 x x x x]
2146 rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x10);
2147 mdelay(1);
2148
2149 // ##LEQ Read Out
2150 leq_gray = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 7, 3);
2151 leq_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x18, 15, 15);
2152 leq_bin = rtl9300_sds_rxcal_gray_to_binary(leq_gray);
2153
2154 pr_info("LEQ_gray: %u, LEQ_bin: %u", leq_gray, leq_bin);
2155 pr_info("LEQ manual: %u", leq_manual);
2156
2157 return leq_bin;
2158 }
2159
2160 void rtl9300_sds_rxcal_vth_manual(u32 sds_num, bool manual, u32 vth_list[])
2161 {
2162 if (manual) {
2163 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, 13, 13, 0x1);
2164 rtl9300_sds_field_w(sds_num, 0x2e, 0x13, 5, 3, vth_list[0]);
2165 rtl9300_sds_field_w(sds_num, 0x2e, 0x13, 2, 0, vth_list[1]);
2166 } else {
2167 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, 13, 13, 0x0);
2168 mdelay(10);
2169 }
2170 }
2171
2172 void rtl9300_sds_rxcal_vth_get(u32 sds_num, u32 vth_list[])
2173 {
2174 u32 vth_manual;
2175
2176 //##Page0x1F, Reg0x02[15 0], REG_DBGO_SEL=[0x002F]; //Lane0
2177 //##Page0x1F, Reg0x02[15 0], REG_DBGO_SEL=[0x0031]; //Lane1
2178 if (!(sds_num % 2))
2179 rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
2180 else
2181 rtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31);
2182
2183 //##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1]
2184 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
2185 //##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x]
2186 rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x20);
2187 //##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 1 1 0 0]
2188 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0xc);
2189
2190 mdelay(1);
2191
2192 //##VthP & VthN Read Out
2193 vth_list[0] = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 2, 0); // v_thp set bin
2194 vth_list[1] = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 3); // v_thn set bin
2195
2196 pr_info("vth_set_bin = %d", vth_list[0]);
2197 pr_info("vth_set_bin = %d", vth_list[1]);
2198
2199 vth_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x0f, 13, 13);
2200 pr_info("Vth Maunal = %d", vth_manual);
2201 }
2202
2203 void rtl9300_sds_rxcal_tap_manual(u32 sds_num, int tap_id, bool manual, u32 tap_list[])
2204 {
2205 if (manual) {
2206 switch(tap_id) {
2207 case 0:
2208 //##REG0_LOAD_IN_INIT[0]=1; REG0_TAP0_INIT[5:0]=Tap0_Value
2209 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);
2210 rtl9300_sds_field_w(sds_num, 0x2f, 0x03, 5, 5, tap_list[0]);
2211 rtl9300_sds_field_w(sds_num, 0x2f, 0x03, 4, 0, tap_list[1]);
2212 break;
2213 case 1:
2214 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);
2215 rtl9300_sds_field_w(sds_num, 0x21, 0x07, 6, 6, tap_list[0]);
2216 rtl9300_sds_field_w(sds_num, 0x2e, 0x09, 11, 6, tap_list[1]);
2217 rtl9300_sds_field_w(sds_num, 0x21, 0x07, 5, 5, tap_list[2]);
2218 rtl9300_sds_field_w(sds_num, 0x2f, 0x12, 5, 0, tap_list[3]);
2219 break;
2220 case 2:
2221 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);
2222 rtl9300_sds_field_w(sds_num, 0x2e, 0x09, 5, 5, tap_list[0]);
2223 rtl9300_sds_field_w(sds_num, 0x2e, 0x09, 4, 0, tap_list[1]);
2224 rtl9300_sds_field_w(sds_num, 0x2e, 0x0a, 11, 11, tap_list[2]);
2225 rtl9300_sds_field_w(sds_num, 0x2e, 0x0a, 10, 6, tap_list[3]);
2226 break;
2227 case 3:
2228 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);
2229 rtl9300_sds_field_w(sds_num, 0x2e, 0x0a, 5, 5, tap_list[0]);
2230 rtl9300_sds_field_w(sds_num, 0x2e, 0x0a, 4, 0, tap_list[1]);
2231 rtl9300_sds_field_w(sds_num, 0x2e, 0x06, 5, 5, tap_list[2]);
2232 rtl9300_sds_field_w(sds_num, 0x2e, 0x06, 4, 0, tap_list[3]);
2233 break;
2234 case 4:
2235 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);
2236 rtl9300_sds_field_w(sds_num, 0x2f, 0x01, 5, 5, tap_list[0]);
2237 rtl9300_sds_field_w(sds_num, 0x2f, 0x01, 4, 0, tap_list[1]);
2238 rtl9300_sds_field_w(sds_num, 0x2e, 0x06, 11, 11, tap_list[2]);
2239 rtl9300_sds_field_w(sds_num, 0x2e, 0x06, 10, 6, tap_list[3]);
2240 break;
2241 default:
2242 break;
2243 }
2244 } else {
2245 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x0);
2246 mdelay(10);
2247 }
2248 }
2249
2250 void rtl9300_sds_rxcal_tap_get(u32 sds_num, u32 tap_id, u32 tap_list[])
2251 {
2252 u32 tap0_sign_out;
2253 u32 tap0_coef_bin;
2254 u32 tap_sign_out_even;
2255 u32 tap_coef_bin_even;
2256 u32 tap_sign_out_odd;
2257 u32 tap_coef_bin_odd;
2258 bool tap_manual;
2259
2260 if (!(sds_num % 2))
2261 rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
2262 else
2263 rtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31);
2264
2265 //##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1]
2266 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
2267 //##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x]
2268 rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x20);
2269
2270 if (!tap_id) {
2271 //##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 0 0 0 1]
2272 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0);
2273 //##Tap1 Even Read Out
2274 mdelay(1);
2275 tap0_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 5);
2276 tap0_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 0);
2277
2278 if (tap0_sign_out == 1)
2279 pr_info("Tap0 Sign : -");
2280 else
2281 pr_info("Tap0 Sign : +");
2282
2283 pr_info("tap0_coef_bin = %d", tap0_coef_bin);
2284
2285 tap_list[0] = tap0_sign_out;
2286 tap_list[1] = tap0_coef_bin;
2287
2288 tap_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x0f, 7, 7);
2289 pr_info("tap0 manual = %u",tap_manual);
2290 } else {
2291 //##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 0 0 0 1]
2292 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, tap_id);
2293 mdelay(1);
2294 //##Tap1 Even Read Out
2295 tap_sign_out_even = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 5);
2296 tap_coef_bin_even = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 0);
2297
2298 //##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 0 1 1 0]
2299 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, (tap_id + 5));
2300 //##Tap1 Odd Read Out
2301 tap_sign_out_odd = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 5);
2302 tap_coef_bin_odd = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 0);
2303
2304 if (tap_sign_out_even == 1)
2305 pr_info("Tap %u even sign: -", tap_id);
2306 else
2307 pr_info("Tap %u even sign: +", tap_id);
2308
2309 pr_info("Tap %u even coefficient = %u", tap_id, tap_coef_bin_even);
2310
2311 if (tap_sign_out_odd == 1)
2312 pr_info("Tap %u odd sign: -", tap_id);
2313 else
2314 pr_info("Tap %u odd sign: +", tap_id);
2315
2316 pr_info("Tap %u odd coefficient = %u", tap_id,tap_coef_bin_odd);
2317
2318 tap_list[0] = tap_sign_out_even;
2319 tap_list[1] = tap_coef_bin_even;
2320 tap_list[2] = tap_sign_out_odd;
2321 tap_list[3] = tap_coef_bin_odd;
2322
2323 tap_manual = rtl9300_sds_field_r(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7);
2324 pr_info("tap %u manual = %d",tap_id, tap_manual);
2325 }
2326 }
2327
2328 void rtl9300_do_rx_calibration_1(int sds, phy_interface_t phy_mode)
2329 {
2330 // From both rtl9300_rxCaliConf_serdes_myParam and rtl9300_rxCaliConf_phy_myParam
2331 int tap0_init_val = 0x1f; // Initial Decision Fed Equalizer 0 tap
2332 int vth_min = 0x0;
2333
2334 pr_info("start_1.1.1 initial value for sds %d\n", sds);
2335 rtl930x_write_sds_phy(sds, 6, 0, 0);
2336
2337 // FGCAL
2338 rtl9300_sds_field_w(sds, 0x2e, 0x01, 14, 14, 0x0);
2339 rtl9300_sds_field_w(sds, 0x2e, 0x1c, 10, 5, 0x20);
2340 rtl9300_sds_field_w(sds, 0x2f, 0x02, 0, 0, 0x1);
2341
2342 // DCVS
2343 rtl9300_sds_field_w(sds, 0x2e, 0x1e, 14, 11, 0x0);
2344 rtl9300_sds_field_w(sds, 0x2e, 0x01, 15, 15, 0x0);
2345 rtl9300_sds_field_w(sds, 0x2e, 0x02, 11, 11, 0x0);
2346 rtl9300_sds_field_w(sds, 0x2e, 0x1c, 4, 0, 0x0);
2347 rtl9300_sds_field_w(sds, 0x2e, 0x1d, 15, 11, 0x0);
2348 rtl9300_sds_field_w(sds, 0x2e, 0x1d, 10, 6, 0x0);
2349 rtl9300_sds_field_w(sds, 0x2e, 0x1d, 5, 1, 0x0);
2350 rtl9300_sds_field_w(sds, 0x2e, 0x02, 10, 6, 0x0);
2351 rtl9300_sds_field_w(sds, 0x2e, 0x11, 4, 0, 0x0);
2352 rtl9300_sds_field_w(sds, 0x2f, 0x00, 3, 0, 0xf);
2353 rtl9300_sds_field_w(sds, 0x2e, 0x04, 6, 6, 0x1);
2354 rtl9300_sds_field_w(sds, 0x2e, 0x04, 7, 7, 0x1);
2355
2356 // LEQ (Long Term Equivalent signal level)
2357 rtl9300_sds_field_w(sds, 0x2e, 0x16, 14, 8, 0x0);
2358
2359 // DFE (Decision Fed Equalizer)
2360 rtl9300_sds_field_w(sds, 0x2f, 0x03, 5, 0, tap0_init_val);
2361 rtl9300_sds_field_w(sds, 0x2e, 0x09, 11, 6, 0x0);
2362 rtl9300_sds_field_w(sds, 0x2e, 0x09, 5, 0, 0x0);
2363 rtl9300_sds_field_w(sds, 0x2e, 0x0a, 5, 0, 0x0);
2364 rtl9300_sds_field_w(sds, 0x2f, 0x01, 5, 0, 0x0);
2365 rtl9300_sds_field_w(sds, 0x2f, 0x12, 5, 0, 0x0);
2366 rtl9300_sds_field_w(sds, 0x2e, 0x0a, 11, 6, 0x0);
2367 rtl9300_sds_field_w(sds, 0x2e, 0x06, 5, 0, 0x0);
2368 rtl9300_sds_field_w(sds, 0x2f, 0x01, 5, 0, 0x0);
2369
2370 // Vth
2371 rtl9300_sds_field_w(sds, 0x2e, 0x13, 5, 3, 0x7);
2372 rtl9300_sds_field_w(sds, 0x2e, 0x13, 2, 0, 0x7);
2373 rtl9300_sds_field_w(sds, 0x2f, 0x0b, 5, 3, vth_min);
2374
2375 pr_info("end_1.1.1 --\n");
2376
2377 pr_info("start_1.1.2 Load DFE init. value\n");
2378
2379 rtl9300_sds_field_w(sds, 0x2e, 0x0f, 13, 7, 0x7f);
2380
2381 pr_info("end_1.1.2\n");
2382
2383 pr_info("start_1.1.3 disable LEQ training,enable DFE clock\n");
2384
2385 rtl9300_sds_field_w(sds, 0x2e, 0x17, 7, 7, 0x0);
2386 rtl9300_sds_field_w(sds, 0x2e, 0x17, 6, 2, 0x0);
2387 rtl9300_sds_field_w(sds, 0x2e, 0x0c, 8, 8, 0x0);
2388 rtl9300_sds_field_w(sds, 0x2e, 0x0b, 4, 4, 0x1);
2389 rtl9300_sds_field_w(sds, 0x2e, 0x12, 14, 14, 0x0);
2390 rtl9300_sds_field_w(sds, 0x2f, 0x02, 15, 15, 0x0);
2391
2392 pr_info("end_1.1.3 --\n");
2393
2394 pr_info("start_1.1.4 offset cali setting\n");
2395
2396 rtl9300_sds_field_w(sds, 0x2e, 0x0f, 15, 14, 0x3);
2397
2398 pr_info("end_1.1.4\n");
2399
2400 pr_info("start_1.1.5 LEQ and DFE setting\n");
2401
2402 // TODO: make this work for DAC cables of different lengths
2403 // For a 10GBit serdes wit Fibre, SDS 8 or 9
2404 if (phy_mode == PHY_INTERFACE_MODE_10GBASER || PHY_INTERFACE_MODE_1000BASEX)
2405 rtl9300_sds_field_w(sds, 0x2e, 0x16, 3, 2, 0x2);
2406 else
2407 pr_err("%s not PHY-based or SerDes, implement DAC!\n", __func__);
2408
2409 // No serdes, check for Aquantia PHYs
2410 rtl9300_sds_field_w(sds, 0x2e, 0x16, 3, 2, 0x2);
2411
2412 rtl9300_sds_field_w(sds, 0x2e, 0x0f, 6, 0, 0x5f);
2413 rtl9300_sds_field_w(sds, 0x2f, 0x05, 7, 2, 0x1f);
2414 rtl9300_sds_field_w(sds, 0x2e, 0x19, 9, 5, 0x1f);
2415 rtl9300_sds_field_w(sds, 0x2f, 0x0b, 15, 9, 0x3c);
2416 rtl9300_sds_field_w(sds, 0x2e, 0x0b, 1, 0, 0x3);
2417
2418 pr_info("end_1.1.5\n");
2419 }
2420
2421 void rtl9300_do_rx_calibration_2_1(u32 sds_num)
2422 {
2423 pr_info("start_1.2.1 ForegroundOffsetCal_Manual\n");
2424
2425 // Gray config endis to 1
2426 rtl9300_sds_field_w(sds_num, 0x2f, 0x02, 2, 2, 0x1);
2427
2428 // ForegroundOffsetCal_Manual(auto mode)
2429 rtl9300_sds_field_w(sds_num, 0x2e, 0x01, 14, 14, 0x0);
2430
2431 pr_info("end_1.2.1");
2432 }
2433
2434 void rtl9300_do_rx_calibration_2_2(int sds_num)
2435 {
2436 //Force Rx-Run = 0
2437 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 8, 8, 0x0);
2438
2439 rtl930x_sds_rx_rst(sds_num, PHY_INTERFACE_MODE_10GBASER);
2440 }
2441
2442 void rtl9300_do_rx_calibration_2_3(int sds_num)
2443 {
2444 u32 fgcal_binary, fgcal_gray;
2445 u32 offset_range;
2446
2447 pr_info("start_1.2.3 Foreground Calibration\n");
2448
2449 while(1) {
2450 if (!(sds_num % 2))
2451 rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
2452 else
2453 rtl930x_write_sds_phy(sds_num -1 , 0x1f, 0x2, 0x31);
2454
2455 // ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1]
2456 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
2457 // ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x]
2458 rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x20);
2459 // ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 1 1 1 1]
2460 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0xf);
2461 // ##FGCAL read gray
2462 fgcal_gray = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 0);
2463 // ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 1 1 1 0]
2464 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0xe);
2465 // ##FGCAL read binary
2466 fgcal_binary = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 0);
2467
2468 pr_info("%s: fgcal_gray: %d, fgcal_binary %d\n",
2469 __func__, fgcal_gray, fgcal_binary);
2470
2471 offset_range = rtl9300_sds_field_r(sds_num, 0x2e, 0x15, 15, 14);
2472
2473 if (fgcal_binary > 60 || fgcal_binary < 3) {
2474 if (offset_range == 3) {
2475 pr_info("%s: Foreground Calibration result marginal!", __func__);
2476 break;
2477 } else {
2478 offset_range++;
2479 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 15, 14, offset_range);
2480 rtl9300_do_rx_calibration_2_2(sds_num);
2481 }
2482 } else {
2483 break;
2484 }
2485 }
2486 pr_info("%s: end_1.2.3\n", __func__);
2487 }
2488
2489 void rtl9300_do_rx_calibration_2(int sds)
2490 {
2491 rtl930x_sds_rx_rst(sds, PHY_INTERFACE_MODE_10GBASER);
2492 rtl9300_do_rx_calibration_2_1(sds);
2493 rtl9300_do_rx_calibration_2_2(sds);
2494 rtl9300_do_rx_calibration_2_3(sds);
2495 }
2496
2497 void rtl9300_sds_rxcal_3_1(int sds_num, phy_interface_t phy_mode)
2498 {
2499 pr_info("start_1.3.1");
2500
2501 // ##1.3.1
2502 if (phy_mode != PHY_INTERFACE_MODE_10GBASER && phy_mode != PHY_INTERFACE_MODE_1000BASEX)
2503 rtl9300_sds_field_w(sds_num, 0x2e, 0xc, 8, 8, 0);
2504
2505 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 7, 7, 0x0);
2506 rtl9300_sds_rxcal_leq_manual(sds_num, false, 0);
2507
2508 pr_info("end_1.3.1");
2509 }
2510
2511 void rtl9300_sds_rxcal_3_2(int sds_num, phy_interface_t phy_mode)
2512 {
2513 u32 sum10 = 0, avg10, int10;
2514 int dac_long_cable_offset;
2515 bool eq_hold_enabled;
2516 int i;
2517
2518 if (phy_mode == PHY_INTERFACE_MODE_10GBASER || phy_mode == PHY_INTERFACE_MODE_1000BASEX) {
2519 // rtl9300_rxCaliConf_serdes_myParam
2520 dac_long_cable_offset = 3;
2521 eq_hold_enabled = true;
2522 } else {
2523 // rtl9300_rxCaliConf_phy_myParam
2524 dac_long_cable_offset = 0;
2525 eq_hold_enabled = false;
2526 }
2527
2528 if (phy_mode == PHY_INTERFACE_MODE_1000BASEX)
2529 pr_warn("%s: LEQ only valid for 10GR!\n", __func__);
2530
2531 pr_info("start_1.3.2");
2532
2533 for(i = 0; i < 10; i++) {
2534 sum10 += rtl9300_sds_rxcal_leq_read(sds_num);
2535 mdelay(10);
2536 }
2537
2538 avg10 = (sum10 / 10) + (((sum10 % 10) >= 5) ? 1 : 0);
2539 int10 = sum10 / 10;
2540
2541 pr_info("sum10:%u, avg10:%u, int10:%u", sum10, avg10, int10);
2542
2543 if (phy_mode == PHY_INTERFACE_MODE_10GBASER || phy_mode == PHY_INTERFACE_MODE_1000BASEX) {
2544 if (dac_long_cable_offset) {
2545 rtl9300_sds_rxcal_leq_offset_manual(sds_num, 1, dac_long_cable_offset);
2546 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 7, 7, eq_hold_enabled);
2547 if (phy_mode == PHY_INTERFACE_MODE_10GBASER)
2548 rtl9300_sds_rxcal_leq_manual(sds_num, true, avg10);
2549 } else {
2550 if (sum10 >= 5) {
2551 rtl9300_sds_rxcal_leq_offset_manual(sds_num, 1, 3);
2552 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 7, 7, 0x1);
2553 if (phy_mode == PHY_INTERFACE_MODE_10GBASER)
2554 rtl9300_sds_rxcal_leq_manual(sds_num, true, avg10);
2555 } else {
2556 rtl9300_sds_rxcal_leq_offset_manual(sds_num, 1, 0);
2557 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 7, 7, 0x1);
2558 if (phy_mode == PHY_INTERFACE_MODE_10GBASER)
2559 rtl9300_sds_rxcal_leq_manual(sds_num, true, avg10);
2560 }
2561 }
2562 }
2563
2564 pr_info("Sds:%u LEQ = %u",sds_num, rtl9300_sds_rxcal_leq_read(sds_num));
2565
2566 pr_info("end_1.3.2");
2567 }
2568
2569 void rtl9300_do_rx_calibration_3(int sds_num, phy_interface_t phy_mode)
2570 {
2571 rtl9300_sds_rxcal_3_1(sds_num, phy_mode);
2572
2573 if (phy_mode == PHY_INTERFACE_MODE_10GBASER || phy_mode == PHY_INTERFACE_MODE_1000BASEX)
2574 rtl9300_sds_rxcal_3_2(sds_num, phy_mode);
2575 }
2576
2577 void rtl9300_do_rx_calibration_4_1(int sds_num)
2578 {
2579 u32 vth_list[2] = {0, 0};
2580 u32 tap0_list[4] = {0, 0, 0, 0};
2581
2582 pr_info("start_1.4.1");
2583
2584 // ##1.4.1
2585 rtl9300_sds_rxcal_vth_manual(sds_num, false, vth_list);
2586 rtl9300_sds_rxcal_tap_manual(sds_num, 0, false, tap0_list);
2587 mdelay(200);
2588
2589 pr_info("end_1.4.1");
2590 }
2591
2592 void rtl9300_do_rx_calibration_4_2(u32 sds_num)
2593 {
2594 u32 vth_list[2];
2595 u32 tap_list[4];
2596
2597 pr_info("start_1.4.2");
2598
2599 rtl9300_sds_rxcal_vth_get(sds_num, vth_list);
2600 rtl9300_sds_rxcal_vth_manual(sds_num, true, vth_list);
2601
2602 mdelay(100);
2603
2604 rtl9300_sds_rxcal_tap_get(sds_num, 0, tap_list);
2605 rtl9300_sds_rxcal_tap_manual(sds_num, 0, true, tap_list);
2606
2607 pr_info("end_1.4.2");
2608 }
2609
2610 void rtl9300_do_rx_calibration_4(u32 sds_num)
2611 {
2612 rtl9300_do_rx_calibration_4_1(sds_num);
2613 rtl9300_do_rx_calibration_4_2(sds_num);
2614 }
2615
2616 void rtl9300_do_rx_calibration_5_2(u32 sds_num)
2617 {
2618 u32 tap1_list[4] = {0};
2619 u32 tap2_list[4] = {0};
2620 u32 tap3_list[4] = {0};
2621 u32 tap4_list[4] = {0};
2622
2623 pr_info("start_1.5.2");
2624
2625 rtl9300_sds_rxcal_tap_manual(sds_num, 1, false, tap1_list);
2626 rtl9300_sds_rxcal_tap_manual(sds_num, 2, false, tap2_list);
2627 rtl9300_sds_rxcal_tap_manual(sds_num, 3, false, tap3_list);
2628 rtl9300_sds_rxcal_tap_manual(sds_num, 4, false, tap4_list);
2629
2630 mdelay(30);
2631
2632 pr_info("end_1.5.2");
2633 }
2634
2635 void rtl9300_do_rx_calibration_5(u32 sds_num, phy_interface_t phy_mode)
2636 {
2637 if (phy_mode == PHY_INTERFACE_MODE_10GBASER) // dfeTap1_4Enable true
2638 rtl9300_do_rx_calibration_5_2(sds_num);
2639 }
2640
2641
2642 void rtl9300_do_rx_calibration_dfe_disable(u32 sds_num)
2643 {
2644 u32 tap1_list[4] = {0};
2645 u32 tap2_list[4] = {0};
2646 u32 tap3_list[4] = {0};
2647 u32 tap4_list[4] = {0};
2648
2649 rtl9300_sds_rxcal_tap_manual(sds_num, 1, true, tap1_list);
2650 rtl9300_sds_rxcal_tap_manual(sds_num, 2, true, tap2_list);
2651 rtl9300_sds_rxcal_tap_manual(sds_num, 3, true, tap3_list);
2652 rtl9300_sds_rxcal_tap_manual(sds_num, 4, true, tap4_list);
2653
2654 mdelay(10);
2655 }
2656
2657 void rtl9300_do_rx_calibration(int sds, phy_interface_t phy_mode)
2658 {
2659 u32 latch_sts;
2660
2661 rtl9300_do_rx_calibration_1(sds, phy_mode);
2662 rtl9300_do_rx_calibration_2(sds);
2663 rtl9300_do_rx_calibration_4(sds);
2664 rtl9300_do_rx_calibration_5(sds, phy_mode);
2665 mdelay(20);
2666
2667 // Do this only for 10GR mode, SDS active in mode 0x1a
2668 if (rtl9300_sds_field_r(sds, 0x1f, 9, 11, 7) == 0x1a) {
2669 pr_info("%s: SDS enabled\n", __func__);
2670 latch_sts = rtl9300_sds_field_r(sds, 0x4, 1, 2, 2);
2671 mdelay(1);
2672 latch_sts = rtl9300_sds_field_r(sds, 0x4, 1, 2, 2);
2673 if (latch_sts) {
2674 rtl9300_do_rx_calibration_dfe_disable(sds);
2675 rtl9300_do_rx_calibration_4(sds);
2676 rtl9300_do_rx_calibration_5(sds, phy_mode);
2677 }
2678 }
2679 }
2680
2681 int rtl9300_sds_sym_err_reset(int sds_num, phy_interface_t phy_mode)
2682 {
2683 switch (phy_mode) {
2684 case PHY_INTERFACE_MODE_XGMII:
2685 break;
2686
2687 case PHY_INTERFACE_MODE_10GBASER:
2688 // Read twice to clear
2689 rtl930x_read_sds_phy(sds_num, 5, 1);
2690 rtl930x_read_sds_phy(sds_num, 5, 1);
2691 break;
2692
2693 case PHY_INTERFACE_MODE_1000BASEX:
2694 rtl9300_sds_field_w(sds_num, 0x1, 24, 2, 0, 0);
2695 rtl9300_sds_field_w(sds_num, 0x1, 3, 15, 8, 0);
2696 rtl9300_sds_field_w(sds_num, 0x1, 2, 15, 0, 0);
2697 break;
2698
2699 default:
2700 pr_info("%s unsupported phy mode\n", __func__);
2701 return -1;
2702 }
2703
2704 return 0;
2705 }
2706
2707 u32 rtl9300_sds_sym_err_get(int sds_num, phy_interface_t phy_mode)
2708 {
2709 u32 v = 0;
2710
2711 switch (phy_mode) {
2712 case PHY_INTERFACE_MODE_XGMII:
2713 break;
2714
2715 case PHY_INTERFACE_MODE_10GBASER:
2716 v = rtl930x_read_sds_phy(sds_num, 5, 1);
2717 return v & 0xff;
2718
2719 default:
2720 pr_info("%s unsupported PHY-mode\n", __func__);
2721 }
2722
2723 return v;
2724 }
2725
2726 int rtl9300_sds_check_calibration(int sds_num, phy_interface_t phy_mode)
2727 {
2728 u32 errors1, errors2;
2729
2730 rtl9300_sds_sym_err_reset(sds_num, phy_mode);
2731 rtl9300_sds_sym_err_reset(sds_num, phy_mode);
2732
2733 // Count errors during 1ms
2734 errors1 = rtl9300_sds_sym_err_get(sds_num, phy_mode);
2735 mdelay(1);
2736 errors2 = rtl9300_sds_sym_err_get(sds_num, phy_mode);
2737
2738 switch (phy_mode) {
2739 case PHY_INTERFACE_MODE_XGMII:
2740
2741 if ((errors2 - errors1 > 100)
2742 || (errors1 >= 0xffff00) || (errors2 >= 0xffff00)) {
2743 pr_info("%s XSGMII error rate too high\n", __func__);
2744 return 1;
2745 }
2746 break;
2747 case PHY_INTERFACE_MODE_10GBASER:
2748 if (errors2 > 0) {
2749 pr_info("%s 10GBASER error rate too high\n", __func__);
2750 return 1;
2751 }
2752 break;
2753 default:
2754 return 1;
2755 }
2756 return 0;
2757 }
2758
2759 void rtl9300_phy_enable_10g_1g(int sds_num)
2760 {
2761 u32 v;
2762
2763 // Enable 1GBit PHY
2764 v = rtl930x_read_sds_phy(sds_num, PHY_PAGE_2, PHY_CTRL_REG);
2765 pr_info("%s 1gbit phy: %08x\n", __func__, v);
2766 v &= ~BIT(PHY_POWER_BIT);
2767 rtl930x_write_sds_phy(sds_num, PHY_PAGE_2, PHY_CTRL_REG, v);
2768 pr_info("%s 1gbit phy enabled: %08x\n", __func__, v);
2769
2770 // Enable 10GBit PHY
2771 v = rtl930x_read_sds_phy(sds_num, PHY_PAGE_4, PHY_CTRL_REG);
2772 pr_info("%s 10gbit phy: %08x\n", __func__, v);
2773 v &= ~BIT(PHY_POWER_BIT);
2774 rtl930x_write_sds_phy(sds_num, PHY_PAGE_4, PHY_CTRL_REG, v);
2775 pr_info("%s 10gbit phy after: %08x\n", __func__, v);
2776
2777 // dal_longan_construct_mac_default_10gmedia_fiber
2778 v = rtl930x_read_sds_phy(sds_num, 0x1f, 11);
2779 pr_info("%s set medium: %08x\n", __func__, v);
2780 v |= BIT(1);
2781 rtl930x_write_sds_phy(sds_num, 0x1f, 11, v);
2782 pr_info("%s set medium after: %08x\n", __func__, v);
2783 }
2784
2785 #define RTL930X_MAC_FORCE_MODE_CTRL (0xCA1C)
2786 // phy_mode = PHY_INTERFACE_MODE_10GBASER, sds_mode = 0x1a
2787 int rtl9300_serdes_setup(int sds_num, phy_interface_t phy_mode)
2788 {
2789 int sds_mode;
2790 int calib_tries = 0;
2791
2792 switch (phy_mode) {
2793 case PHY_INTERFACE_MODE_HSGMII:
2794 sds_mode = 0x12;
2795 break;
2796 case PHY_INTERFACE_MODE_1000BASEX:
2797 sds_mode = 0x04;
2798 break;
2799 case PHY_INTERFACE_MODE_XGMII:
2800 sds_mode = 0x10;
2801 break;
2802 case PHY_INTERFACE_MODE_10GBASER:
2803 sds_mode = 0x1a;
2804 break;
2805 case PHY_INTERFACE_MODE_USXGMII:
2806 sds_mode = 0x0d;
2807 break;
2808 default:
2809 pr_err("%s: unknown serdes mode: %s\n", __func__, phy_modes(phy_mode));
2810 return -EINVAL;
2811 }
2812
2813 // Maybe use dal_longan_sds_init
2814
2815 // dal_longan_construct_serdesConfig_init // Serdes Construct
2816 rtl9300_phy_enable_10g_1g(sds_num);
2817
2818 // Set Serdes Mode
2819 rtl9300_sds_set(sds_num, 0x1a); // 0x1b: RTK_MII_10GR1000BX_AUTO
2820
2821 // Do RX calibration
2822 do {
2823 rtl9300_do_rx_calibration(sds_num, phy_mode);
2824 calib_tries++;
2825 mdelay(50);
2826 } while (rtl9300_sds_check_calibration(sds_num, phy_mode) && calib_tries < 3);
2827
2828
2829 return 0;
2830 }
2831
2832 typedef struct {
2833 u8 page;
2834 u8 reg;
2835 u16 data;
2836 } sds_config;
2837
2838 sds_config rtl9300_a_sds_10gr_lane0[] =
2839 {
2840 /*1G*/
2841 {0x00, 0x0E, 0x3053}, {0x01, 0x14, 0x0100}, {0x21, 0x03, 0x8206},
2842 {0x21, 0x05, 0x40B0}, {0x21, 0x06, 0x0010}, {0x21, 0x07, 0xF09F},
2843 {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009}, {0x21, 0x0E, 0x0000},
2844 {0x21, 0x0F, 0x0008}, {0x24, 0x00, 0x0668}, {0x24, 0x02, 0xD020},
2845 {0x24, 0x06, 0xC000}, {0x24, 0x0B, 0x1892}, {0x24, 0x0F, 0xFFDF},
2846 {0x24, 0x12, 0x03C4}, {0x24, 0x13, 0x027F}, {0x24, 0x14, 0x1311},
2847 {0x24, 0x16, 0x00C9}, {0x24, 0x17, 0xA100}, {0x24, 0x1A, 0x0001},
2848 {0x24, 0x1C, 0x0400}, {0x25, 0x01, 0x0300}, {0x25, 0x02, 0x1017},
2849 {0x25, 0x03, 0xFFDF}, {0x25, 0x05, 0x7F7C}, {0x25, 0x07, 0x8100},
2850 {0x25, 0x08, 0x0001}, {0x25, 0x09, 0xFFD4}, {0x25, 0x0A, 0x7C2F},
2851 {0x25, 0x0E, 0x003F}, {0x25, 0x0F, 0x0121}, {0x25, 0x10, 0x0020},
2852 {0x25, 0x11, 0x8840}, {0x2B, 0x13, 0x0050}, {0x2B, 0x18, 0x8E88},
2853 {0x2B, 0x19, 0x4902}, {0x2B, 0x1D, 0x2501}, {0x2D, 0x13, 0x0050},
2854 {0x2D, 0x18, 0x8E88}, {0x2D, 0x19, 0x4902}, {0x2D, 0x1D, 0x2641},
2855 {0x2F, 0x13, 0x0050}, {0x2F, 0x18, 0x8E88}, {0x2F, 0x19, 0x4902},
2856 {0x2F, 0x1D, 0x66E1},
2857 /*3.125G*/
2858 {0x28, 0x00, 0x0668}, {0x28, 0x02, 0xD020}, {0x28, 0x06, 0xC000},
2859 {0x28, 0x0B, 0x1892}, {0x28, 0x0F, 0xFFDF}, {0x28, 0x12, 0x01C4},
2860 {0x28, 0x13, 0x027F}, {0x28, 0x14, 0x1311}, {0x28, 0x16, 0x00C9},
2861 {0x28, 0x17, 0xA100}, {0x28, 0x1A, 0x0001}, {0x28, 0x1C, 0x0400},
2862 {0x29, 0x01, 0x0300}, {0x29, 0x02, 0x1017}, {0x29, 0x03, 0xFFDF},
2863 {0x29, 0x05, 0x7F7C}, {0x29, 0x07, 0x8100}, {0x29, 0x08, 0x0001},
2864 {0x29, 0x09, 0xFFD4}, {0x29, 0x0A, 0x7C2F}, {0x29, 0x0E, 0x003F},
2865 {0x29, 0x0F, 0x0121}, {0x29, 0x10, 0x0020}, {0x29, 0x11, 0x8840},
2866 /*10G*/
2867 {0x06, 0x0D, 0x0F00}, {0x06, 0x00, 0x0000}, {0x06, 0x01, 0xC800},
2868 {0x21, 0x03, 0x8206}, {0x21, 0x05, 0x40B0}, {0x21, 0x06, 0x0010},
2869 {0x21, 0x07, 0xF09F}, {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009},
2870 {0x21, 0x0E, 0x0000}, {0x21, 0x0F, 0x0008}, {0x2E, 0x00, 0xA668},
2871 {0x2E, 0x02, 0xD020}, {0x2E, 0x06, 0xC000}, {0x2E, 0x0B, 0x1892},
2872 {0x2E, 0x0F, 0xFFDF}, {0x2E, 0x11, 0x8280}, {0x2E, 0x12, 0x0044},
2873 {0x2E, 0x13, 0x027F}, {0x2E, 0x14, 0x1311}, {0x2E, 0x17, 0xA100},
2874 {0x2E, 0x1A, 0x0001}, {0x2E, 0x1C, 0x0400}, {0x2F, 0x01, 0x0300},
2875 {0x2F, 0x02, 0x1217}, {0x2F, 0x03, 0xFFDF}, {0x2F, 0x05, 0x7F7C},
2876 {0x2F, 0x07, 0x80C4}, {0x2F, 0x08, 0x0001}, {0x2F, 0x09, 0xFFD4},
2877 {0x2F, 0x0A, 0x7C2F}, {0x2F, 0x0E, 0x003F}, {0x2F, 0x0F, 0x0121},
2878 {0x2F, 0x10, 0x0020}, {0x2F, 0x11, 0x8840}, {0x2F, 0x14, 0xE008},
2879 {0x2B, 0x13, 0x0050}, {0x2B, 0x18, 0x8E88}, {0x2B, 0x19, 0x4902},
2880 {0x2B, 0x1D, 0x2501}, {0x2D, 0x13, 0x0050}, {0x2D, 0x17, 0x4109},
2881 {0x2D, 0x18, 0x8E88}, {0x2D, 0x19, 0x4902}, {0x2D, 0x1C, 0x1109},
2882 {0x2D, 0x1D, 0x2641}, {0x2F, 0x13, 0x0050}, {0x2F, 0x18, 0x8E88},
2883 {0x2F, 0x19, 0x4902}, {0x2F, 0x1D, 0x76E1},
2884 };
2885
2886 sds_config rtl9300_a_sds_10gr_lane1[] =
2887 {
2888 /*1G*/
2889 {0x00, 0x0E, 0x3053}, {0x01, 0x14, 0x0100}, {0x21, 0x03, 0x8206},
2890 {0x21, 0x06, 0x0010}, {0x21, 0x07, 0xF09F}, {0x21, 0x0A, 0x0003},
2891 {0x21, 0x0B, 0x0005}, {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009},
2892 {0x21, 0x0E, 0x0000}, {0x21, 0x0F, 0x0008}, {0x24, 0x00, 0x0668},
2893 {0x24, 0x02, 0xD020}, {0x24, 0x06, 0xC000}, {0x24, 0x0B, 0x1892},
2894 {0x24, 0x0F, 0xFFDF}, {0x24, 0x12, 0x03C4}, {0x24, 0x13, 0x027F},
2895 {0x24, 0x14, 0x1311}, {0x24, 0x16, 0x00C9}, {0x24, 0x17, 0xA100},
2896 {0x24, 0x1A, 0x0001}, {0x24, 0x1C, 0x0400}, {0x25, 0x00, 0x820F},
2897 {0x25, 0x01, 0x0300}, {0x25, 0x02, 0x1017}, {0x25, 0x03, 0xFFDF},
2898 {0x25, 0x05, 0x7F7C}, {0x25, 0x07, 0x8100}, {0x25, 0x08, 0x0001},
2899 {0x25, 0x09, 0xFFD4}, {0x25, 0x0A, 0x7C2F}, {0x25, 0x0E, 0x003F},
2900 {0x25, 0x0F, 0x0121}, {0x25, 0x10, 0x0020}, {0x25, 0x11, 0x8840},
2901 {0x2B, 0x13, 0x3D87}, {0x2B, 0x14, 0x3108}, {0x2D, 0x13, 0x3C87},
2902 {0x2D, 0x14, 0x1808},
2903 /*3.125G*/
2904 {0x28, 0x00, 0x0668}, {0x28, 0x02, 0xD020}, {0x28, 0x06, 0xC000},
2905 {0x28, 0x0B, 0x1892}, {0x28, 0x0F, 0xFFDF}, {0x28, 0x12, 0x01C4},
2906 {0x28, 0x13, 0x027F}, {0x28, 0x14, 0x1311}, {0x28, 0x16, 0x00C9},
2907 {0x28, 0x17, 0xA100}, {0x28, 0x1A, 0x0001}, {0x28, 0x1C, 0x0400},
2908 {0x29, 0x00, 0x820F}, {0x29, 0x01, 0x0300}, {0x29, 0x02, 0x1017},
2909 {0x29, 0x03, 0xFFDF}, {0x29, 0x05, 0x7F7C}, {0x29, 0x07, 0x8100},
2910 {0x29, 0x08, 0x0001}, {0x29, 0x0A, 0x7C2F}, {0x29, 0x0E, 0x003F},
2911 {0x29, 0x0F, 0x0121}, {0x29, 0x10, 0x0020}, {0x29, 0x11, 0x8840},
2912 /*10G*/
2913 {0x06, 0x0D, 0x0F00}, {0x06, 0x00, 0x0000}, {0x06, 0x01, 0xC800},
2914 {0x21, 0x03, 0x8206}, {0x21, 0x05, 0x40B0}, {0x21, 0x06, 0x0010},
2915 {0x21, 0x07, 0xF09F}, {0x21, 0x0A, 0x0003}, {0x21, 0x0B, 0x0005},
2916 {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009}, {0x21, 0x0E, 0x0000},
2917 {0x21, 0x0F, 0x0008}, {0x2E, 0x00, 0xA668}, {0x2E, 0x02, 0xD020},
2918 {0x2E, 0x06, 0xC000}, {0x2E, 0x0B, 0x1892}, {0x2E, 0x0F, 0xFFDF},
2919 {0x2E, 0x11, 0x8280}, {0x2E, 0x12, 0x0044}, {0x2E, 0x13, 0x027F},
2920 {0x2E, 0x14, 0x1311}, {0x2E, 0x17, 0xA100}, {0x2E, 0x1A, 0x0001},
2921 {0x2E, 0x1C, 0x0400}, {0x2F, 0x00, 0x820F}, {0x2F, 0x01, 0x0300},
2922 {0x2F, 0x02, 0x1217}, {0x2F, 0x03, 0xFFDF}, {0x2F, 0x05, 0x7F7C},
2923 {0x2F, 0x07, 0x80C4}, {0x2F, 0x08, 0x0001}, {0x2F, 0x09, 0xFFD4},
2924 {0x2F, 0x0A, 0x7C2F}, {0x2F, 0x0E, 0x003F}, {0x2F, 0x0F, 0x0121},
2925 {0x2F, 0x10, 0x0020}, {0x2F, 0x11, 0x8840}, {0x2B, 0x13, 0x3D87},
2926 {0x2B, 0x14, 0x3108}, {0x2D, 0x13, 0x3C87}, {0x2D, 0x14, 0x1808},
2927 };
2928
2929 int rtl9300_sds_cmu_band_get(int sds)
2930 {
2931 u32 page;
2932 u32 en;
2933 u32 cmu_band;
2934
2935 // page = rtl9300_sds_cmu_page_get(sds);
2936 page = 0x25; // 10GR and 1000BX
2937 sds = (sds % 2) ? (sds - 1) : (sds);
2938
2939 rtl9300_sds_field_w(sds, page, 0x1c, 15, 15, 1);
2940 rtl9300_sds_field_w(sds + 1, page, 0x1c, 15, 15, 1);
2941
2942 en = rtl9300_sds_field_r(sds, page, 27, 1, 1);
2943 if(!en) { // Auto mode
2944 rtl930x_write_sds_phy(sds, 0x1f, 0x02, 31);
2945
2946 cmu_band = rtl9300_sds_field_r(sds, 0x1f, 0x15, 5, 1);
2947 } else {
2948 cmu_band = rtl9300_sds_field_r(sds, page, 30, 4, 0);
2949 }
2950
2951 return cmu_band;
2952 }
2953
2954 int rtl9300_configure_serdes(struct phy_device *phydev)
2955 {
2956 struct device *dev = &phydev->mdio.dev;
2957 int phy_addr = phydev->mdio.addr;
2958 struct device_node *dn;
2959 u32 sds_num = 0;
2960 int sds_mode, calib_tries = 0, phy_mode = PHY_INTERFACE_MODE_10GBASER, i;
2961
2962 if (dev->of_node) {
2963 dn = dev->of_node;
2964
2965 if (of_property_read_u32(dn, "sds", &sds_num))
2966 sds_num = -1;
2967 pr_info("%s: Port %d, SerDes is %d\n", __func__, phy_addr, sds_num);
2968 } else {
2969 dev_err(dev, "No DT node.\n");
2970 return -EINVAL;
2971 }
2972
2973 if (sds_num < 0)
2974 return 0;
2975
2976 if (phy_mode != PHY_INTERFACE_MODE_10GBASER) // TODO: for now we only patch 10GR SerDes
2977 return 0;
2978
2979 switch (phy_mode) {
2980 case PHY_INTERFACE_MODE_HSGMII:
2981 sds_mode = 0x12;
2982 break;
2983 case PHY_INTERFACE_MODE_1000BASEX:
2984 sds_mode = 0x04;
2985 break;
2986 case PHY_INTERFACE_MODE_XGMII:
2987 sds_mode = 0x10;
2988 break;
2989 case PHY_INTERFACE_MODE_10GBASER:
2990 sds_mode = 0x1a;
2991 break;
2992 case PHY_INTERFACE_MODE_USXGMII:
2993 sds_mode = 0x0d;
2994 break;
2995 default:
2996 pr_err("%s: unknown serdes mode: %s\n", __func__, phy_modes(phy_mode));
2997 return -EINVAL;
2998 }
2999
3000 pr_info("%s CMU BAND is %d\n", __func__, rtl9300_sds_cmu_band_get(sds_num));
3001
3002 // Turn Off Serdes
3003 rtl9300_sds_rst(sds_num, 0x1f);
3004
3005 pr_info("%s PATCHING SerDes %d\n", __func__, sds_num);
3006 if (sds_num % 2) {
3007 for (i = 0; i < sizeof(rtl9300_a_sds_10gr_lane1) / sizeof(sds_config); ++i) {
3008 rtl930x_write_sds_phy(sds_num, rtl9300_a_sds_10gr_lane1[i].page,
3009 rtl9300_a_sds_10gr_lane1[i].reg,
3010 rtl9300_a_sds_10gr_lane1[i].data);
3011 }
3012 } else {
3013 for (i = 0; i < sizeof(rtl9300_a_sds_10gr_lane0) / sizeof(sds_config); ++i) {
3014 rtl930x_write_sds_phy(sds_num, rtl9300_a_sds_10gr_lane0[i].page,
3015 rtl9300_a_sds_10gr_lane0[i].reg,
3016 rtl9300_a_sds_10gr_lane0[i].data);
3017 }
3018 }
3019
3020 rtl9300_phy_enable_10g_1g(sds_num);
3021
3022 // Disable MAC
3023 sw_w32_mask(0, 1, RTL930X_MAC_FORCE_MODE_CTRL);
3024 mdelay(20);
3025
3026 // ----> dal_longan_sds_mode_set
3027 pr_info("%s: Configuring RTL9300 SERDES %d, mode %02x\n", __func__, sds_num, sds_mode);
3028
3029 // Configure link to MAC
3030 rtl9300_serdes_mac_link_config(sds_num, true, true); // MAC Construct
3031
3032 // Disable MAC
3033 sw_w32_mask(0, 1, RTL930X_MAC_FORCE_MODE_CTRL);
3034 mdelay(20);
3035
3036 rtl9300_force_sds_mode(sds_num, PHY_INTERFACE_MODE_NA);
3037
3038 // Re-Enable MAC
3039 sw_w32_mask(1, 0, RTL930X_MAC_FORCE_MODE_CTRL);
3040
3041 rtl9300_force_sds_mode(sds_num, phy_mode);
3042
3043 // Do RX calibration
3044 do {
3045 rtl9300_do_rx_calibration(sds_num, phy_mode);
3046 calib_tries++;
3047 mdelay(50);
3048 } while (rtl9300_sds_check_calibration(sds_num, phy_mode) && calib_tries < 3);
3049
3050 if (calib_tries >= 3)
3051 pr_err("%s CALIBTRATION FAILED\n", __func__);
3052
3053 rtl9300_sds_tx_config(sds_num, phy_mode);
3054
3055 // The clock needs only to be configured on the FPGA implementation
3056
3057 return 0;
3058 }
3059
3060 void rtl9310_sds_field_w(int sds, u32 page, u32 reg, int end_bit, int start_bit, u32 v)
3061 {
3062 int l = end_bit - start_bit + 1;
3063 u32 data = v;
3064
3065 if (l < 32) {
3066 u32 mask = BIT(l) - 1;
3067
3068 data = rtl930x_read_sds_phy(sds, page, reg);
3069 data &= ~(mask << start_bit);
3070 data |= (v & mask) << start_bit;
3071 }
3072
3073 rtl931x_write_sds_phy(sds, page, reg, data);
3074 }
3075
3076
3077 u32 rtl9310_sds_field_r(int sds, u32 page, u32 reg, int end_bit, int start_bit)
3078 {
3079 int l = end_bit - start_bit + 1;
3080 u32 v = rtl931x_read_sds_phy(sds, page, reg);
3081
3082 if (l >= 32)
3083 return v;
3084
3085 return (v >> start_bit) & (BIT(l) - 1);
3086 }
3087
3088 static void rtl931x_sds_rst(u32 sds)
3089 {
3090 u32 o, v, o_mode;
3091 int shift = ((sds & 0x3) << 3);
3092
3093 // TODO: We need to lock this!
3094
3095 o = sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3096 v = o | BIT(sds);
3097 sw_w32(v, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3098
3099 o_mode = sw_r32(RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3100 v = BIT(7) | 0x1F;
3101 sw_w32_mask(0xff << shift, v << shift, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3102 sw_w32(o_mode, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3103
3104 sw_w32(o, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3105 }
3106
3107 static void rtl931x_symerr_clear(u32 sds, phy_interface_t mode)
3108 {
3109 u32 i;
3110 u32 xsg_sdsid_0, xsg_sdsid_1;
3111
3112 switch (mode) {
3113 case PHY_INTERFACE_MODE_NA:
3114 break;
3115 case PHY_INTERFACE_MODE_XGMII:
3116 if (sds < 2)
3117 xsg_sdsid_0 = sds;
3118 else
3119 xsg_sdsid_0 = (sds - 1) * 2;
3120 xsg_sdsid_1 = xsg_sdsid_0 + 1;
3121
3122 for (i = 0; i < 4; ++i) {
3123 rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 24, 2, 0, i);
3124 rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 3, 15, 8, 0x0);
3125 rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 2, 15, 0, 0x0);
3126 }
3127
3128 for (i = 0; i < 4; ++i) {
3129 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 24, 2, 0, i);
3130 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 3, 15, 8, 0x0);
3131 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 2, 15, 0, 0x0);
3132 }
3133
3134 rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 0, 15, 0, 0x0);
3135 rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 1, 15, 8, 0x0);
3136 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 0, 15, 0, 0x0);
3137 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 1, 15, 8, 0x0);
3138 break;
3139 default:
3140 break;
3141 }
3142
3143 return;
3144 }
3145
3146 static u32 rtl931x_get_analog_sds(u32 sds)
3147 {
3148 u32 sds_map[] = { 0, 1, 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23 };
3149
3150 if (sds < 14)
3151 return sds_map[sds];
3152 return sds;
3153 }
3154
3155 void rtl931x_sds_fiber_disable(u32 sds)
3156 {
3157 u32 v = 0x3F;
3158 u32 asds = rtl931x_get_analog_sds(sds);
3159
3160 rtl9310_sds_field_w(asds, 0x1F, 0x9, 11, 6, v);
3161 }
3162
3163 static void rtl931x_sds_fiber_mode_set(u32 sds, phy_interface_t mode)
3164 {
3165 u32 val, asds = rtl931x_get_analog_sds(sds);
3166
3167 /* clear symbol error count before changing mode */
3168 rtl931x_symerr_clear(sds, mode);
3169
3170 val = 0x9F;
3171 sw_w32(val, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3172
3173 switch (mode) {
3174 case PHY_INTERFACE_MODE_SGMII:
3175 val = 0x5;
3176 break;
3177
3178 case PHY_INTERFACE_MODE_1000BASEX:
3179 /* serdes mode FIBER1G */
3180 val = 0x9;
3181 break;
3182
3183 case PHY_INTERFACE_MODE_10GBASER:
3184 case PHY_INTERFACE_MODE_10GKR:
3185 val = 0x35;
3186 break;
3187 /* case MII_10GR1000BX_AUTO:
3188 val = 0x39;
3189 break; */
3190
3191
3192 case PHY_INTERFACE_MODE_USXGMII:
3193 val = 0x1B;
3194 break;
3195 default:
3196 val = 0x25;
3197 }
3198
3199 pr_info("%s writing analog SerDes Mode value %02x\n", __func__, val);
3200 rtl9310_sds_field_w(asds, 0x1F, 0x9, 11, 6, val);
3201
3202 return;
3203 }
3204
3205 static int rtl931x_sds_cmu_page_get(phy_interface_t mode)
3206 {
3207 switch (mode) {
3208 case PHY_INTERFACE_MODE_SGMII:
3209 case PHY_INTERFACE_MODE_1000BASEX: // MII_1000BX_FIBER / 100BX_FIBER / 1000BX100BX_AUTO
3210 return 0x24;
3211 case PHY_INTERFACE_MODE_HSGMII:
3212 case PHY_INTERFACE_MODE_2500BASEX: // MII_2500Base_X:
3213 return 0x28;
3214 // case MII_HISGMII_5G:
3215 // return 0x2a;
3216 case PHY_INTERFACE_MODE_QSGMII:
3217 return 0x2a; // Code also has 0x34
3218 case PHY_INTERFACE_MODE_XAUI: // MII_RXAUI_LITE:
3219 return 0x2c;
3220 case PHY_INTERFACE_MODE_XGMII: // MII_XSGMII
3221 case PHY_INTERFACE_MODE_10GKR:
3222 case PHY_INTERFACE_MODE_10GBASER: // MII_10GR
3223 return 0x2e;
3224 default:
3225 return -1;
3226 }
3227 return -1;
3228 }
3229
3230 static void rtl931x_cmu_type_set(u32 asds, phy_interface_t mode, int chiptype)
3231 {
3232 int cmu_type = 0; // Clock Management Unit
3233 u32 cmu_page = 0;
3234 u32 frc_cmu_spd;
3235 u32 evenSds;
3236 u32 lane, frc_lc_mode_bitnum, frc_lc_mode_val_bitnum;
3237
3238 switch (mode) {
3239 case PHY_INTERFACE_MODE_NA:
3240 case PHY_INTERFACE_MODE_10GKR:
3241 case PHY_INTERFACE_MODE_XGMII:
3242 case PHY_INTERFACE_MODE_10GBASER:
3243 case PHY_INTERFACE_MODE_USXGMII:
3244 return;
3245
3246 /* case MII_10GR1000BX_AUTO:
3247 if (chiptype)
3248 rtl9310_sds_field_w(asds, 0x24, 0xd, 14, 14, 0);
3249 return; */
3250
3251 case PHY_INTERFACE_MODE_QSGMII:
3252 cmu_type = 1;
3253 frc_cmu_spd = 0;
3254 break;
3255
3256 case PHY_INTERFACE_MODE_HSGMII:
3257 cmu_type = 1;
3258 frc_cmu_spd = 1;
3259 break;
3260
3261 case PHY_INTERFACE_MODE_1000BASEX:
3262 cmu_type = 1;
3263 frc_cmu_spd = 0;
3264 break;
3265
3266 /* case MII_1000BX100BX_AUTO:
3267 cmu_type = 1;
3268 frc_cmu_spd = 0;
3269 break; */
3270
3271 case PHY_INTERFACE_MODE_SGMII:
3272 cmu_type = 1;
3273 frc_cmu_spd = 0;
3274 break;
3275
3276 case PHY_INTERFACE_MODE_2500BASEX:
3277 cmu_type = 1;
3278 frc_cmu_spd = 1;
3279 break;
3280
3281 default:
3282 pr_info("SerDes %d mode is invalid\n", asds);
3283 return;
3284 }
3285
3286 if (cmu_type == 1)
3287 cmu_page = rtl931x_sds_cmu_page_get(mode);
3288
3289 lane = asds % 2;
3290
3291 if (!lane) {
3292 frc_lc_mode_bitnum = 4;
3293 frc_lc_mode_val_bitnum = 5;
3294 } else {
3295 frc_lc_mode_bitnum = 6;
3296 frc_lc_mode_val_bitnum = 7;
3297 }
3298
3299 evenSds = asds - lane;
3300
3301 pr_info("%s: cmu_type %0d cmu_page %x frc_cmu_spd %d lane %d asds %d\n",
3302 __func__, cmu_type, cmu_page, frc_cmu_spd, lane, asds);
3303
3304 if (cmu_type == 1) {
3305 pr_info("%s A CMU page 0x28 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x28, 0x7));
3306 rtl9310_sds_field_w(asds, cmu_page, 0x7, 15, 15, 0);
3307 pr_info("%s B CMU page 0x28 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x28, 0x7));
3308 if (chiptype) {
3309 rtl9310_sds_field_w(asds, cmu_page, 0xd, 14, 14, 0);
3310 }
3311
3312 rtl9310_sds_field_w(evenSds, 0x20, 0x12, 3, 2, 0x3);
3313 rtl9310_sds_field_w(evenSds, 0x20, 0x12, frc_lc_mode_bitnum, frc_lc_mode_bitnum, 1);
3314 rtl9310_sds_field_w(evenSds, 0x20, 0x12, frc_lc_mode_val_bitnum, frc_lc_mode_val_bitnum, 0);
3315 rtl9310_sds_field_w(evenSds, 0x20, 0x12, 12, 12, 1);
3316 rtl9310_sds_field_w(evenSds, 0x20, 0x12, 15, 13, frc_cmu_spd);
3317 }
3318
3319 pr_info("%s CMU page 0x28 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x28, 0x7));
3320 return;
3321 }
3322
3323 static void rtl931x_sds_rx_rst(u32 sds)
3324 {
3325 u32 asds = rtl931x_get_analog_sds(sds);
3326
3327 if (sds < 2)
3328 return;
3329
3330 rtl931x_write_sds_phy(asds, 0x2e, 0x12, 0x2740);
3331 rtl931x_write_sds_phy(asds, 0x2f, 0x0, 0x0);
3332 rtl931x_write_sds_phy(asds, 0x2f, 0x2, 0x2010);
3333 rtl931x_write_sds_phy(asds, 0x20, 0x0, 0xc10);
3334
3335 rtl931x_write_sds_phy(asds, 0x2e, 0x12, 0x27c0);
3336 rtl931x_write_sds_phy(asds, 0x2f, 0x0, 0xc000);
3337 rtl931x_write_sds_phy(asds, 0x2f, 0x2, 0x6010);
3338 rtl931x_write_sds_phy(asds, 0x20, 0x0, 0xc30);
3339
3340 mdelay(50);
3341 }
3342
3343 static void rtl931x_sds_disable(u32 sds)
3344 {
3345 u32 v = 0x1f;
3346
3347 v |= BIT(7);
3348 sw_w32(v, RTL931X_SERDES_MODE_CTRL + (sds >> 2) * 4);
3349 }
3350
3351 static void rtl931x_sds_mii_mode_set(u32 sds, phy_interface_t mode)
3352 {
3353 u32 val;
3354
3355 switch (mode) {
3356 case PHY_INTERFACE_MODE_QSGMII:
3357 val = 0x6;
3358 break;
3359 case PHY_INTERFACE_MODE_XGMII:
3360 val = 0x10; // serdes mode XSGMII
3361 break;
3362 case PHY_INTERFACE_MODE_USXGMII:
3363 case PHY_INTERFACE_MODE_2500BASEX:
3364 val = 0xD;
3365 break;
3366 case PHY_INTERFACE_MODE_HSGMII:
3367 val = 0x12;
3368 break;
3369 case PHY_INTERFACE_MODE_SGMII:
3370 val = 0x2;
3371 break;
3372 default:
3373 return;
3374 }
3375
3376 val |= (1 << 7);
3377
3378 sw_w32(val, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3379 }
3380
3381 static sds_config sds_config_10p3125g_type1[] = {
3382 { 0x2E, 0x00, 0x0107 }, { 0x2E, 0x01, 0x01A3 }, { 0x2E, 0x02, 0x6A24 },
3383 { 0x2E, 0x03, 0xD10D }, { 0x2E, 0x04, 0x8000 }, { 0x2E, 0x05, 0xA17E },
3384 { 0x2E, 0x06, 0xE31D }, { 0x2E, 0x07, 0x800E }, { 0x2E, 0x08, 0x0294 },
3385 { 0x2E, 0x09, 0x0CE4 }, { 0x2E, 0x0A, 0x7FC8 }, { 0x2E, 0x0B, 0xE0E7 },
3386 { 0x2E, 0x0C, 0x0200 }, { 0x2E, 0x0D, 0xDF80 }, { 0x2E, 0x0E, 0x0000 },
3387 { 0x2E, 0x0F, 0x1FC2 }, { 0x2E, 0x10, 0x0C3F }, { 0x2E, 0x11, 0x0000 },
3388 { 0x2E, 0x12, 0x27C0 }, { 0x2E, 0x13, 0x7E1D }, { 0x2E, 0x14, 0x1300 },
3389 { 0x2E, 0x15, 0x003F }, { 0x2E, 0x16, 0xBE7F }, { 0x2E, 0x17, 0x0090 },
3390 { 0x2E, 0x18, 0x0000 }, { 0x2E, 0x19, 0x4000 }, { 0x2E, 0x1A, 0x0000 },
3391 { 0x2E, 0x1B, 0x8000 }, { 0x2E, 0x1C, 0x011F }, { 0x2E, 0x1D, 0x0000 },
3392 { 0x2E, 0x1E, 0xC8FF }, { 0x2E, 0x1F, 0x0000 }, { 0x2F, 0x00, 0xC000 },
3393 { 0x2F, 0x01, 0xF000 }, { 0x2F, 0x02, 0x6010 }, { 0x2F, 0x12, 0x0EE7 },
3394 { 0x2F, 0x13, 0x0000 }
3395 };
3396
3397 static sds_config sds_config_10p3125g_cmu_type1[] = {
3398 { 0x2F, 0x03, 0x4210 }, { 0x2F, 0x04, 0x0000 }, { 0x2F, 0x05, 0x0019 },
3399 { 0x2F, 0x06, 0x18A6 }, { 0x2F, 0x07, 0x2990 }, { 0x2F, 0x08, 0xFFF4 },
3400 { 0x2F, 0x09, 0x1F08 }, { 0x2F, 0x0A, 0x0000 }, { 0x2F, 0x0B, 0x8000 },
3401 { 0x2F, 0x0C, 0x4224 }, { 0x2F, 0x0D, 0x0000 }, { 0x2F, 0x0E, 0x0000 },
3402 { 0x2F, 0x0F, 0xA470 }, { 0x2F, 0x10, 0x8000 }, { 0x2F, 0x11, 0x037B }
3403 };
3404
3405 void rtl931x_sds_init(u32 sds, phy_interface_t mode)
3406 {
3407
3408 u32 board_sds_tx_type1[] = { 0x1C3, 0x1C3, 0x1C3, 0x1A3, 0x1A3,
3409 0x1A3, 0x143, 0x143, 0x143, 0x143, 0x163, 0x163
3410 };
3411
3412 u32 board_sds_tx[] = { 0x1A00, 0x1A00, 0x200, 0x200, 0x200,
3413 0x200, 0x1A3, 0x1A3, 0x1A3, 0x1A3, 0x1E3, 0x1E3
3414 };
3415
3416 u32 board_sds_tx2[] = { 0xDC0, 0x1C0, 0x200, 0x180, 0x160,
3417 0x123, 0x123, 0x163, 0x1A3, 0x1A0, 0x1C3, 0x9C3
3418 };
3419
3420 u32 asds, dSds, ori, model_info, val;
3421 int chiptype = 0;
3422
3423 asds = rtl931x_get_analog_sds(sds);
3424
3425 if (sds > 13)
3426 return;
3427
3428 pr_info("%s: set sds %d to mode %d\n", __func__, sds, mode);
3429 val = rtl9310_sds_field_r(asds, 0x1F, 0x9, 11, 6);
3430
3431 pr_info("%s: fibermode %08X stored mode 0x%x analog SDS %d", __func__,
3432 rtl931x_read_sds_phy(asds, 0x1f, 0x9), val, asds);
3433 pr_info("%s: SGMII mode %08X in 0x24 0x9 analog SDS %d", __func__,
3434 rtl931x_read_sds_phy(asds, 0x24, 0x9), asds);
3435 pr_info("%s: CMU mode %08X stored even SDS %d", __func__,
3436 rtl931x_read_sds_phy(asds & ~1, 0x20, 0x12), asds & ~1);
3437 pr_info("%s: serdes_mode_ctrl %08X", __func__, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3438 pr_info("%s CMU page 0x24 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x24, 0x7));
3439 pr_info("%s CMU page 0x26 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x26, 0x7));
3440 pr_info("%s CMU page 0x28 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x28, 0x7));
3441 pr_info("%s XSG page 0x0 0xe %08x\n", __func__, rtl931x_read_sds_phy(dSds, 0x0, 0xe));
3442 pr_info("%s XSG2 page 0x0 0xe %08x\n", __func__, rtl931x_read_sds_phy(dSds + 1, 0x0, 0xe));
3443
3444 model_info = sw_r32(RTL93XX_MODEL_NAME_INFO);
3445 if ((model_info >> 4) & 0x1) {
3446 pr_info("detected chiptype 1\n");
3447 chiptype = 1;
3448 } else {
3449 pr_info("detected chiptype 0\n");
3450 }
3451
3452 if (sds < 2)
3453 dSds = sds;
3454 else
3455 dSds = (sds - 1) * 2;
3456
3457 pr_info("%s: 2.5gbit %08X dsds %d", __func__,
3458 rtl931x_read_sds_phy(dSds, 0x1, 0x14), dSds);
3459
3460 pr_info("%s: RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR 0x%08X\n", __func__, sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR));
3461 ori = sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3462 val = ori | (1 << sds);
3463 sw_w32(val, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3464
3465 switch (mode) {
3466 case PHY_INTERFACE_MODE_NA:
3467 break;
3468
3469 case PHY_INTERFACE_MODE_XGMII: // MII_XSGMII
3470
3471 if (chiptype) {
3472 u32 xsg_sdsid_1;
3473 xsg_sdsid_1 = dSds + 1;
3474 //fifo inv clk
3475 rtl9310_sds_field_w(dSds, 0x1, 0x1, 7, 4, 0xf);
3476 rtl9310_sds_field_w(dSds, 0x1, 0x1, 3, 0, 0xf);
3477
3478 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 0x1, 7, 4, 0xf);
3479 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 0x1, 3, 0, 0xf);
3480
3481 }
3482
3483 rtl9310_sds_field_w(dSds, 0x0, 0xE, 12, 12, 1);
3484 rtl9310_sds_field_w(dSds + 1, 0x0, 0xE, 12, 12, 1);
3485 break;
3486
3487 case PHY_INTERFACE_MODE_USXGMII: // MII_USXGMII_10GSXGMII/10GDXGMII/10GQXGMII:
3488 u32 i, evenSds;
3489 u32 op_code = 0x6003;
3490
3491 if (chiptype) {
3492 rtl9310_sds_field_w(asds, 0x6, 0x2, 12, 12, 1);
3493
3494 for (i = 0; i < sizeof(sds_config_10p3125g_type1) / sizeof(sds_config); ++i) {
3495 rtl931x_write_sds_phy(asds, sds_config_10p3125g_type1[i].page - 0x4, sds_config_10p3125g_type1[i].reg, sds_config_10p3125g_type1[i].data);
3496 }
3497
3498 evenSds = asds - (asds % 2);
3499
3500 for (i = 0; i < sizeof(sds_config_10p3125g_cmu_type1) / sizeof(sds_config); ++i) {
3501 rtl931x_write_sds_phy(evenSds,
3502 sds_config_10p3125g_cmu_type1[i].page - 0x4, sds_config_10p3125g_cmu_type1[i].reg, sds_config_10p3125g_cmu_type1[i].data);
3503 }
3504
3505 rtl9310_sds_field_w(asds, 0x6, 0x2, 12, 12, 0);
3506 } else {
3507
3508 rtl9310_sds_field_w(asds, 0x2e, 0xd, 6, 0, 0x0);
3509 rtl9310_sds_field_w(asds, 0x2e, 0xd, 7, 7, 0x1);
3510
3511 rtl9310_sds_field_w(asds, 0x2e, 0x1c, 5, 0, 0x1E);
3512 rtl9310_sds_field_w(asds, 0x2e, 0x1d, 11, 0, 0x00);
3513 rtl9310_sds_field_w(asds, 0x2e, 0x1f, 11, 0, 0x00);
3514 rtl9310_sds_field_w(asds, 0x2f, 0x0, 11, 0, 0x00);
3515 rtl9310_sds_field_w(asds, 0x2f, 0x1, 11, 0, 0x00);
3516
3517 rtl9310_sds_field_w(asds, 0x2e, 0xf, 12, 6, 0x7F);
3518 rtl931x_write_sds_phy(asds, 0x2f, 0x12, 0xaaa);
3519
3520 rtl931x_sds_rx_rst(sds);
3521
3522 rtl931x_write_sds_phy(asds, 0x7, 0x10, op_code);
3523 rtl931x_write_sds_phy(asds, 0x6, 0x1d, 0x0480);
3524 rtl931x_write_sds_phy(asds, 0x6, 0xe, 0x0400);
3525 }
3526 break;
3527
3528 case PHY_INTERFACE_MODE_10GBASER: // MII_10GR / MII_10GR1000BX_AUTO:
3529 // configure 10GR fiber mode=1
3530 rtl9310_sds_field_w(asds, 0x1f, 0xb, 1, 1, 1);
3531
3532 // init fiber_1g
3533 rtl9310_sds_field_w(dSds, 0x3, 0x13, 15, 14, 0);
3534
3535 rtl9310_sds_field_w(dSds, 0x2, 0x0, 12, 12, 1);
3536 rtl9310_sds_field_w(dSds, 0x2, 0x0, 6, 6, 1);
3537 rtl9310_sds_field_w(dSds, 0x2, 0x0, 13, 13, 0);
3538
3539 // init auto
3540 rtl9310_sds_field_w(asds, 0x1f, 13, 15, 0, 0x109e);
3541 rtl9310_sds_field_w(asds, 0x1f, 0x6, 14, 10, 0x8);
3542 rtl9310_sds_field_w(asds, 0x1f, 0x7, 10, 4, 0x7f);
3543 break;
3544
3545 case PHY_INTERFACE_MODE_HSGMII:
3546 rtl9310_sds_field_w(dSds, 0x1, 0x14, 8, 8, 1);
3547 break;
3548
3549 case PHY_INTERFACE_MODE_1000BASEX: // MII_1000BX_FIBER
3550 rtl9310_sds_field_w(dSds, 0x3, 0x13, 15, 14, 0);
3551
3552 rtl9310_sds_field_w(dSds, 0x2, 0x0, 12, 12, 1);
3553 rtl9310_sds_field_w(dSds, 0x2, 0x0, 6, 6, 1);
3554 rtl9310_sds_field_w(dSds, 0x2, 0x0, 13, 13, 0);
3555 break;
3556
3557 case PHY_INTERFACE_MODE_SGMII:
3558 rtl9310_sds_field_w(asds, 0x24, 0x9, 15, 15, 0);
3559 break;
3560
3561 case PHY_INTERFACE_MODE_2500BASEX:
3562 rtl9310_sds_field_w(dSds, 0x1, 0x14, 8, 8, 1);
3563 break;
3564
3565 case PHY_INTERFACE_MODE_QSGMII:
3566 default:
3567 pr_info("%s: PHY mode %s not supported by SerDes %d\n",
3568 __func__, phy_modes(mode), sds);
3569 return;
3570 }
3571
3572 rtl931x_cmu_type_set(asds, mode, chiptype);
3573
3574 if (sds >= 2 && sds <= 13) {
3575 if (chiptype)
3576 rtl931x_write_sds_phy(asds, 0x2E, 0x1, board_sds_tx_type1[sds - 2]);
3577 else {
3578 val = 0xa0000;
3579 sw_w32(val, RTL931X_CHIP_INFO_ADDR);
3580 val = sw_r32(RTL931X_CHIP_INFO_ADDR);
3581 if (val & BIT(28)) // consider 9311 etc. RTL9313_CHIP_ID == HWP_CHIP_ID(unit))
3582 {
3583 rtl931x_write_sds_phy(asds, 0x2E, 0x1, board_sds_tx2[sds - 2]);
3584 } else {
3585 rtl931x_write_sds_phy(asds, 0x2E, 0x1, board_sds_tx[sds - 2]);
3586 }
3587 val = 0;
3588 sw_w32(val, RTL931X_CHIP_INFO_ADDR);
3589 }
3590 }
3591
3592 val = ori & ~BIT(sds);
3593 sw_w32(val, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3594 pr_debug("%s: RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR 0x%08X\n", __func__, sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR));
3595
3596 if (mode == PHY_INTERFACE_MODE_XGMII || mode == PHY_INTERFACE_MODE_QSGMII
3597 || mode == PHY_INTERFACE_MODE_HSGMII || mode == PHY_INTERFACE_MODE_SGMII
3598 || mode == PHY_INTERFACE_MODE_USXGMII) {
3599 if (mode == PHY_INTERFACE_MODE_XGMII)
3600 rtl931x_sds_mii_mode_set(sds, mode);
3601 else
3602 rtl931x_sds_fiber_mode_set(sds, mode);
3603 }
3604 }
3605
3606 int rtl931x_sds_cmu_band_set(int sds, bool enable, u32 band, phy_interface_t mode)
3607 {
3608 u32 asds;
3609 int page = rtl931x_sds_cmu_page_get(mode);
3610
3611 sds -= (sds % 2);
3612 sds = sds & ~1;
3613 asds = rtl931x_get_analog_sds(sds);
3614 page += 1;
3615
3616 if (enable) {
3617 rtl9310_sds_field_w(asds, page, 0x7, 13, 13, 0);
3618 rtl9310_sds_field_w(asds, page, 0x7, 11, 11, 0);
3619 } else {
3620 rtl9310_sds_field_w(asds, page, 0x7, 13, 13, 0);
3621 rtl9310_sds_field_w(asds, page, 0x7, 11, 11, 0);
3622 }
3623
3624 rtl9310_sds_field_w(asds, page, 0x7, 4, 0, band);
3625
3626 rtl931x_sds_rst(sds);
3627
3628 return 0;
3629 }
3630
3631 int rtl931x_sds_cmu_band_get(int sds, phy_interface_t mode)
3632 {
3633 int page = rtl931x_sds_cmu_page_get(mode);
3634 u32 asds, band;
3635
3636 sds -= (sds % 2);
3637 asds = rtl931x_get_analog_sds(sds);
3638 page += 1;
3639 rtl931x_write_sds_phy(asds, 0x1f, 0x02, 73);
3640
3641 rtl9310_sds_field_w(asds, page, 0x5, 15, 15, 1);
3642 band = rtl9310_sds_field_r(asds, 0x1f, 0x15, 8, 3);
3643 pr_info("%s band is: %d\n", __func__, band);
3644
3645 return band;
3646 }
3647
3648
3649 int rtl931x_link_sts_get(u32 sds)
3650 {
3651 u32 sts, sts1, latch_sts, latch_sts1;
3652 if (0){
3653 u32 xsg_sdsid_0, xsg_sdsid_1;
3654
3655 xsg_sdsid_0 = sds < 2 ? sds : (sds - 1) * 2;
3656 xsg_sdsid_1 = xsg_sdsid_0 + 1;
3657
3658 sts = rtl9310_sds_field_r(xsg_sdsid_0, 0x1, 29, 8, 0);
3659 sts1 = rtl9310_sds_field_r(xsg_sdsid_1, 0x1, 29, 8, 0);
3660 latch_sts = rtl9310_sds_field_r(xsg_sdsid_0, 0x1, 30, 8, 0);
3661 latch_sts1 = rtl9310_sds_field_r(xsg_sdsid_1, 0x1, 30, 8, 0);
3662 } else {
3663 u32 asds, dsds;
3664
3665 asds = rtl931x_get_analog_sds(sds);
3666 sts = rtl9310_sds_field_r(asds, 0x5, 0, 12, 12);
3667 latch_sts = rtl9310_sds_field_r(asds, 0x4, 1, 2, 2);
3668
3669 dsds = sds < 2 ? sds : (sds - 1) * 2;
3670 latch_sts1 = rtl9310_sds_field_r(dsds, 0x2, 1, 2, 2);
3671 sts1 = rtl9310_sds_field_r(dsds, 0x2, 1, 2, 2);
3672 }
3673
3674 pr_info("%s: serdes %d sts %d, sts1 %d, latch_sts %d, latch_sts1 %d\n", __func__,
3675 sds, sts, sts1, latch_sts, latch_sts1);
3676 return sts1;
3677 }
3678
3679 static int rtl8214fc_phy_probe(struct phy_device *phydev)
3680 {
3681 struct device *dev = &phydev->mdio.dev;
3682 int addr = phydev->mdio.addr;
3683 int ret = 0;
3684
3685 /* 839x has internal SerDes */
3686 if (soc_info.id == 0x8393)
3687 return -ENODEV;
3688
3689 /* All base addresses of the PHYs start at multiples of 8 */
3690 devm_phy_package_join(dev, phydev, addr & (~7),
3691 sizeof(struct rtl83xx_shared_private));
3692
3693 if (!(addr % 8)) {
3694 struct rtl83xx_shared_private *shared = phydev->shared->priv;
3695 shared->name = "RTL8214FC";
3696 /* Configuration must be done while patching still possible */
3697 ret = rtl8380_configure_rtl8214fc(phydev);
3698 if (ret)
3699 return ret;
3700 }
3701
3702 return 0;
3703 }
3704
3705 static int rtl8214c_phy_probe(struct phy_device *phydev)
3706 {
3707 struct device *dev = &phydev->mdio.dev;
3708 int addr = phydev->mdio.addr;
3709
3710 /* All base addresses of the PHYs start at multiples of 8 */
3711 devm_phy_package_join(dev, phydev, addr & (~7),
3712 sizeof(struct rtl83xx_shared_private));
3713
3714 if (!(addr % 8)) {
3715 struct rtl83xx_shared_private *shared = phydev->shared->priv;
3716 shared->name = "RTL8214C";
3717 /* Configuration must be done whil patching still possible */
3718 return rtl8380_configure_rtl8214c(phydev);
3719 }
3720 return 0;
3721 }
3722
3723 static int rtl8218b_ext_phy_probe(struct phy_device *phydev)
3724 {
3725 struct device *dev = &phydev->mdio.dev;
3726 int addr = phydev->mdio.addr;
3727
3728 /* All base addresses of the PHYs start at multiples of 8 */
3729 devm_phy_package_join(dev, phydev, addr & (~7),
3730 sizeof(struct rtl83xx_shared_private));
3731
3732 if (!(addr % 8)) {
3733 struct rtl83xx_shared_private *shared = phydev->shared->priv;
3734 shared->name = "RTL8218B (external)";
3735 if (soc_info.family == RTL8380_FAMILY_ID) {
3736 /* Configuration must be done while patching still possible */
3737 return rtl8380_configure_ext_rtl8218b(phydev);
3738 }
3739 }
3740
3741 return 0;
3742 }
3743
3744 static int rtl8218b_int_phy_probe(struct phy_device *phydev)
3745 {
3746 struct device *dev = &phydev->mdio.dev;
3747 int addr = phydev->mdio.addr;
3748
3749 if (soc_info.family != RTL8380_FAMILY_ID)
3750 return -ENODEV;
3751 if (addr >= 24)
3752 return -ENODEV;
3753
3754 pr_debug("%s: id: %d\n", __func__, addr);
3755 /* All base addresses of the PHYs start at multiples of 8 */
3756 devm_phy_package_join(dev, phydev, addr & (~7),
3757 sizeof(struct rtl83xx_shared_private));
3758
3759 if (!(addr % 8)) {
3760 struct rtl83xx_shared_private *shared = phydev->shared->priv;
3761 shared->name = "RTL8218B (internal)";
3762 /* Configuration must be done while patching still possible */
3763 return rtl8380_configure_int_rtl8218b(phydev);
3764 }
3765
3766 return 0;
3767 }
3768
3769 static int rtl8218d_phy_probe(struct phy_device *phydev)
3770 {
3771 struct device *dev = &phydev->mdio.dev;
3772 int addr = phydev->mdio.addr;
3773
3774 pr_debug("%s: id: %d\n", __func__, addr);
3775 /* All base addresses of the PHYs start at multiples of 8 */
3776 devm_phy_package_join(dev, phydev, addr & (~7),
3777 sizeof(struct rtl83xx_shared_private));
3778
3779 /* All base addresses of the PHYs start at multiples of 8 */
3780 if (!(addr % 8)) {
3781 struct rtl83xx_shared_private *shared = phydev->shared->priv;
3782 shared->name = "RTL8218D";
3783 /* Configuration must be done while patching still possible */
3784 // TODO: return configure_rtl8218d(phydev);
3785 }
3786 return 0;
3787 }
3788
3789 static int rtl838x_serdes_probe(struct phy_device *phydev)
3790 {
3791 int addr = phydev->mdio.addr;
3792
3793 if (soc_info.family != RTL8380_FAMILY_ID)
3794 return -ENODEV;
3795 if (addr < 24)
3796 return -ENODEV;
3797
3798 /* On the RTL8380M, PHYs 24-27 connect to the internal SerDes */
3799 if (soc_info.id == 0x8380) {
3800 if (addr == 24)
3801 return rtl8380_configure_serdes(phydev);
3802 return 0;
3803 }
3804 return -ENODEV;
3805 }
3806
3807 static int rtl8393_serdes_probe(struct phy_device *phydev)
3808 {
3809 int addr = phydev->mdio.addr;
3810
3811 pr_info("%s: id: %d\n", __func__, addr);
3812 if (soc_info.family != RTL8390_FAMILY_ID)
3813 return -ENODEV;
3814
3815 if (addr < 24)
3816 return -ENODEV;
3817
3818 return rtl8390_configure_serdes(phydev);
3819 }
3820
3821 static int rtl8390_serdes_probe(struct phy_device *phydev)
3822 {
3823 int addr = phydev->mdio.addr;
3824
3825 if (soc_info.family != RTL8390_FAMILY_ID)
3826 return -ENODEV;
3827
3828 if (addr < 24)
3829 return -ENODEV;
3830
3831 return rtl8390_configure_generic(phydev);
3832 }
3833
3834 static int rtl9300_serdes_probe(struct phy_device *phydev)
3835 {
3836 if (soc_info.family != RTL9300_FAMILY_ID)
3837 return -ENODEV;
3838
3839 phydev_info(phydev, "Detected internal RTL9300 Serdes\n");
3840
3841 return rtl9300_configure_serdes(phydev);
3842 }
3843
3844 static struct phy_driver rtl83xx_phy_driver[] = {
3845 {
3846 PHY_ID_MATCH_MODEL(PHY_ID_RTL8214C),
3847 .name = "Realtek RTL8214C",
3848 .features = PHY_GBIT_FEATURES,
3849 .flags = PHY_HAS_REALTEK_PAGES,
3850 .match_phy_device = rtl8214c_match_phy_device,
3851 .probe = rtl8214c_phy_probe,
3852 .suspend = genphy_suspend,
3853 .resume = genphy_resume,
3854 .set_loopback = genphy_loopback,
3855 },
3856 {
3857 PHY_ID_MATCH_MODEL(PHY_ID_RTL8214FC),
3858 .name = "Realtek RTL8214FC",
3859 .features = PHY_GBIT_FIBRE_FEATURES,
3860 .flags = PHY_HAS_REALTEK_PAGES,
3861 .match_phy_device = rtl8214fc_match_phy_device,
3862 .probe = rtl8214fc_phy_probe,
3863 .suspend = rtl8214fc_suspend,
3864 .resume = rtl8214fc_resume,
3865 .set_loopback = genphy_loopback,
3866 .set_port = rtl8214fc_set_port,
3867 .get_port = rtl8214fc_get_port,
3868 .set_eee = rtl8214fc_set_eee,
3869 .get_eee = rtl8214fc_get_eee,
3870 },
3871 {
3872 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_E),
3873 .name = "Realtek RTL8218B (external)",
3874 .features = PHY_GBIT_FEATURES,
3875 .flags = PHY_HAS_REALTEK_PAGES,
3876 .match_phy_device = rtl8218b_ext_match_phy_device,
3877 .probe = rtl8218b_ext_phy_probe,
3878 .suspend = genphy_suspend,
3879 .resume = genphy_resume,
3880 .set_loopback = genphy_loopback,
3881 .set_eee = rtl8218b_set_eee,
3882 .get_eee = rtl8218b_get_eee,
3883 },
3884 {
3885 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218D),
3886 .name = "REALTEK RTL8218D",
3887 .features = PHY_GBIT_FEATURES,
3888 .flags = PHY_HAS_REALTEK_PAGES,
3889 .probe = rtl8218d_phy_probe,
3890 .suspend = genphy_suspend,
3891 .resume = genphy_resume,
3892 .set_loopback = genphy_loopback,
3893 .set_eee = rtl8218d_set_eee,
3894 .get_eee = rtl8218d_get_eee,
3895 },
3896 {
3897 PHY_ID_MATCH_MODEL(PHY_ID_RTL8221B),
3898 .name = "REALTEK RTL8221B",
3899 .features = PHY_GBIT_FEATURES,
3900 .flags = PHY_HAS_REALTEK_PAGES,
3901 .suspend = genphy_suspend,
3902 .resume = genphy_resume,
3903 .set_loopback = genphy_loopback,
3904 .read_page = rtl8226_read_page,
3905 .write_page = rtl8226_write_page,
3906 .read_status = rtl8226_read_status,
3907 .config_aneg = rtl8226_config_aneg,
3908 .set_eee = rtl8226_set_eee,
3909 .get_eee = rtl8226_get_eee,
3910 },
3911 {
3912 PHY_ID_MATCH_MODEL(PHY_ID_RTL8226),
3913 .name = "REALTEK RTL8226",
3914 .features = PHY_GBIT_FEATURES,
3915 .flags = PHY_HAS_REALTEK_PAGES,
3916 .suspend = genphy_suspend,
3917 .resume = genphy_resume,
3918 .set_loopback = genphy_loopback,
3919 .read_page = rtl8226_read_page,
3920 .write_page = rtl8226_write_page,
3921 .read_status = rtl8226_read_status,
3922 .config_aneg = rtl8226_config_aneg,
3923 .set_eee = rtl8226_set_eee,
3924 .get_eee = rtl8226_get_eee,
3925 },
3926 {
3927 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_I),
3928 .name = "Realtek RTL8218B (internal)",
3929 .features = PHY_GBIT_FEATURES,
3930 .flags = PHY_HAS_REALTEK_PAGES,
3931 .probe = rtl8218b_int_phy_probe,
3932 .suspend = genphy_suspend,
3933 .resume = genphy_resume,
3934 .set_loopback = genphy_loopback,
3935 .set_eee = rtl8218b_set_eee,
3936 .get_eee = rtl8218b_get_eee,
3937 },
3938 {
3939 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_I),
3940 .name = "Realtek RTL8380 SERDES",
3941 .features = PHY_GBIT_FIBRE_FEATURES,
3942 .flags = PHY_HAS_REALTEK_PAGES,
3943 .probe = rtl838x_serdes_probe,
3944 .suspend = genphy_suspend,
3945 .resume = genphy_resume,
3946 .set_loopback = genphy_loopback,
3947 .read_status = rtl8380_read_status,
3948 },
3949 {
3950 PHY_ID_MATCH_MODEL(PHY_ID_RTL8393_I),
3951 .name = "Realtek RTL8393 SERDES",
3952 .features = PHY_GBIT_FIBRE_FEATURES,
3953 .flags = PHY_HAS_REALTEK_PAGES,
3954 .probe = rtl8393_serdes_probe,
3955 .suspend = genphy_suspend,
3956 .resume = genphy_resume,
3957 .set_loopback = genphy_loopback,
3958 .read_status = rtl8393_read_status,
3959 },
3960 {
3961 PHY_ID_MATCH_MODEL(PHY_ID_RTL8390_GENERIC),
3962 .name = "Realtek RTL8390 Generic",
3963 .features = PHY_GBIT_FIBRE_FEATURES,
3964 .flags = PHY_HAS_REALTEK_PAGES,
3965 .probe = rtl8390_serdes_probe,
3966 .suspend = genphy_suspend,
3967 .resume = genphy_resume,
3968 .set_loopback = genphy_loopback,
3969 },
3970 {
3971 PHY_ID_MATCH_MODEL(PHY_ID_RTL9300_I),
3972 .name = "REALTEK RTL9300 SERDES",
3973 .features = PHY_GBIT_FIBRE_FEATURES,
3974 .flags = PHY_HAS_REALTEK_PAGES,
3975 .probe = rtl9300_serdes_probe,
3976 .suspend = genphy_suspend,
3977 .resume = genphy_resume,
3978 .set_loopback = genphy_loopback,
3979 .read_status = rtl9300_read_status,
3980 },
3981 };
3982
3983 module_phy_driver(rtl83xx_phy_driver);
3984
3985 static struct mdio_device_id __maybe_unused rtl83xx_tbl[] = {
3986 { PHY_ID_MATCH_MODEL(PHY_ID_RTL8214FC) },
3987 { }
3988 };
3989
3990 MODULE_DEVICE_TABLE(mdio, rtl83xx_tbl);
3991
3992 MODULE_AUTHOR("B. Koblitz");
3993 MODULE_DESCRIPTION("RTL83xx PHY driver");
3994 MODULE_LICENSE("GPL");
Staging tree of Jo-Philipp Wich