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realtek: add SFP support for RTL8214FC PHY
[openwrt/staging/jow.git] / target / linux / realtek / files-5.10 / drivers / net / phy / rtl83xx-phy.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Realtek RTL838X Ethernet MDIO interface driver
3 *
4 * Copyright (C) 2020 B. Koblitz
5 */
6
7 #include <linux/module.h>
8 #include <linux/delay.h>
9 #include <linux/phy.h>
10 #include <linux/netdevice.h>
11 #include <linux/firmware.h>
12 #include <linux/crc32.h>
13 #include <linux/sfp.h>
14
15 #include <asm/mach-rtl838x/mach-rtl83xx.h>
16 #include "rtl83xx-phy.h"
17
18 extern struct rtl83xx_soc_info soc_info;
19 extern struct mutex smi_lock;
20
21 #define PHY_CTRL_REG 0
22 #define PHY_POWER_BIT 11
23
24 #define PHY_PAGE_2 2
25 #define PHY_PAGE_4 4
26
27 /* all Clause-22 RealTek MDIO PHYs use register 0x1f for page select */
28 #define RTL8XXX_PAGE_SELECT 0x1f
29
30 #define RTL8XXX_PAGE_MAIN 0x0000
31 #define RTL821X_PAGE_PORT 0x0266
32 #define RTL821X_PAGE_POWER 0x0a40
33 #define RTL821X_PAGE_GPHY 0x0a42
34 #define RTL821X_PAGE_MAC 0x0a43
35 #define RTL821X_PAGE_STATE 0x0b80
36 #define RTL821X_PAGE_PATCH 0x0b82
37
38 /*
39 * Using the special page 0xfff with the MDIO controller found in
40 * RealTek SoCs allows to access the PHY in RAW mode, ie. bypassing
41 * the cache and paging engine of the MDIO controller.
42 */
43 #define RTL83XX_PAGE_RAW 0x0fff
44
45 /* internal RTL821X PHY uses register 0x1d to select media page */
46 #define RTL821XINT_MEDIA_PAGE_SELECT 0x1d
47 /* external RTL821X PHY uses register 0x1e to select media page */
48 #define RTL821XEXT_MEDIA_PAGE_SELECT 0x1e
49
50 #define RTL821X_MEDIA_PAGE_AUTO 0
51 #define RTL821X_MEDIA_PAGE_COPPER 1
52 #define RTL821X_MEDIA_PAGE_FIBRE 3
53 #define RTL821X_MEDIA_PAGE_INTERNAL 8
54
55 #define RTL9300_PHY_ID_MASK 0xf0ffffff
56
57 /*
58 * This lock protects the state of the SoC automatically polling the PHYs over the SMI
59 * bus to detect e.g. link and media changes. For operations on the PHYs such as
60 * patching or other configuration changes such as EEE, polling needs to be disabled
61 * since otherwise these operations may fails or lead to unpredictable results.
62 */
63 DEFINE_MUTEX(poll_lock);
64
65 static const struct firmware rtl838x_8380_fw;
66 static const struct firmware rtl838x_8214fc_fw;
67 static const struct firmware rtl838x_8218b_fw;
68
69 static u64 disable_polling(int port)
70 {
71 u64 saved_state;
72
73 mutex_lock(&poll_lock);
74
75 switch (soc_info.family) {
76 case RTL8380_FAMILY_ID:
77 saved_state = sw_r32(RTL838X_SMI_POLL_CTRL);
78 sw_w32_mask(BIT(port), 0, RTL838X_SMI_POLL_CTRL);
79 break;
80 case RTL8390_FAMILY_ID:
81 saved_state = sw_r32(RTL839X_SMI_PORT_POLLING_CTRL + 4);
82 saved_state <<= 32;
83 saved_state |= sw_r32(RTL839X_SMI_PORT_POLLING_CTRL);
84 sw_w32_mask(BIT(port % 32), 0,
85 RTL839X_SMI_PORT_POLLING_CTRL + ((port >> 5) << 2));
86 break;
87 case RTL9300_FAMILY_ID:
88 saved_state = sw_r32(RTL930X_SMI_POLL_CTRL);
89 sw_w32_mask(BIT(port), 0, RTL930X_SMI_POLL_CTRL);
90 break;
91 case RTL9310_FAMILY_ID:
92 pr_warn("%s not implemented for RTL931X\n", __func__);
93 break;
94 }
95
96 mutex_unlock(&poll_lock);
97
98 return saved_state;
99 }
100
101 static int resume_polling(u64 saved_state)
102 {
103 mutex_lock(&poll_lock);
104
105 switch (soc_info.family) {
106 case RTL8380_FAMILY_ID:
107 sw_w32(saved_state, RTL838X_SMI_POLL_CTRL);
108 break;
109 case RTL8390_FAMILY_ID:
110 sw_w32(saved_state >> 32, RTL839X_SMI_PORT_POLLING_CTRL + 4);
111 sw_w32(saved_state, RTL839X_SMI_PORT_POLLING_CTRL);
112 break;
113 case RTL9300_FAMILY_ID:
114 sw_w32(saved_state, RTL930X_SMI_POLL_CTRL);
115 break;
116 case RTL9310_FAMILY_ID:
117 pr_warn("%s not implemented for RTL931X\n", __func__);
118 break;
119 }
120
121 mutex_unlock(&poll_lock);
122
123 return 0;
124 }
125
126 static void rtl8380_int_phy_on_off(struct phy_device *phydev, bool on)
127 {
128 phy_modify(phydev, 0, BIT(11), on?0:BIT(11));
129 }
130
131 static void rtl8380_rtl8214fc_on_off(struct phy_device *phydev, bool on)
132 {
133 /* fiber ports */
134 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_FIBRE);
135 phy_modify(phydev, 0x10, BIT(11), on?0:BIT(11));
136
137 /* copper ports */
138 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
139 phy_modify_paged(phydev, RTL821X_PAGE_POWER, 0x10, BIT(11), on?0:BIT(11));
140 }
141
142 static void rtl8380_phy_reset(struct phy_device *phydev)
143 {
144 phy_modify(phydev, 0, BIT(15), BIT(15));
145 }
146
147 // The access registers for SDS_MODE_SEL and the LSB for each SDS within
148 u16 rtl9300_sds_regs[] = { 0x0194, 0x0194, 0x0194, 0x0194, 0x02a0, 0x02a0, 0x02a0, 0x02a0,
149 0x02A4, 0x02A4, 0x0198, 0x0198 };
150 u8 rtl9300_sds_lsb[] = { 0, 6, 12, 18, 0, 6, 12, 18, 0, 6, 0, 6};
151
152 /*
153 * Reset the SerDes by powering it off and set a new operations mode
154 * of the SerDes. 0x1f is off. Other modes are
155 * 0x02: SGMII 0x04: 1000BX_FIBER 0x05: FIBER100
156 * 0x06: QSGMII 0x09: RSGMII 0x0d: USXGMII
157 * 0x10: XSGMII 0x12: HISGMII 0x16: 2500Base_X
158 * 0x17: RXAUI_LITE 0x19: RXAUI_PLUS 0x1a: 10G Base-R
159 * 0x1b: 10GR1000BX_AUTO 0x1f: OFF
160 */
161 void rtl9300_sds_rst(int sds_num, u32 mode)
162 {
163 pr_info("%s %d\n", __func__, mode);
164 if (sds_num < 0 || sds_num > 11) {
165 pr_err("Wrong SerDes number: %d\n", sds_num);
166 return;
167 }
168
169 sw_w32_mask(0x1f << rtl9300_sds_lsb[sds_num], 0x1f << rtl9300_sds_lsb[sds_num],
170 rtl9300_sds_regs[sds_num]);
171 mdelay(10);
172
173 sw_w32_mask(0x1f << rtl9300_sds_lsb[sds_num], mode << rtl9300_sds_lsb[sds_num],
174 rtl9300_sds_regs[sds_num]);
175 mdelay(10);
176
177 pr_debug("%s: 194:%08x 198:%08x 2a0:%08x 2a4:%08x\n", __func__,
178 sw_r32(0x194), sw_r32(0x198), sw_r32(0x2a0), sw_r32(0x2a4));
179 }
180
181 void rtl9300_sds_set(int sds_num, u32 mode)
182 {
183 pr_info("%s %d\n", __func__, mode);
184 if (sds_num < 0 || sds_num > 11) {
185 pr_err("Wrong SerDes number: %d\n", sds_num);
186 return;
187 }
188
189 sw_w32_mask(0x1f << rtl9300_sds_lsb[sds_num], mode << rtl9300_sds_lsb[sds_num],
190 rtl9300_sds_regs[sds_num]);
191 mdelay(10);
192
193 pr_debug("%s: 194:%08x 198:%08x 2a0:%08x 2a4:%08x\n", __func__,
194 sw_r32(0x194), sw_r32(0x198), sw_r32(0x2a0), sw_r32(0x2a4));
195 }
196
197 u32 rtl9300_sds_mode_get(int sds_num)
198 {
199 u32 v;
200
201 if (sds_num < 0 || sds_num > 11) {
202 pr_err("Wrong SerDes number: %d\n", sds_num);
203 return 0;
204 }
205
206 v = sw_r32(rtl9300_sds_regs[sds_num]);
207 v >>= rtl9300_sds_lsb[sds_num];
208
209 return v & 0x1f;
210 }
211
212 /*
213 * On the RTL839x family of SoCs with inbuilt SerDes, these SerDes are accessed through
214 * a 2048 bit register that holds the contents of the PHY being simulated by the SoC.
215 */
216 int rtl839x_read_sds_phy(int phy_addr, int phy_reg)
217 {
218 int offset = 0;
219 int reg;
220 u32 val;
221
222 if (phy_addr == 49)
223 offset = 0x100;
224
225 /*
226 * For the RTL8393 internal SerDes, we simulate a PHY ID in registers 2/3
227 * which would otherwise read as 0.
228 */
229 if (soc_info.id == 0x8393) {
230 if (phy_reg == 2)
231 return 0x1c;
232 if (phy_reg == 3)
233 return 0x8393;
234 }
235
236 /*
237 * Register RTL839X_SDS12_13_XSG0 is 2048 bit broad, the MSB (bit 15) of the
238 * 0th PHY register is bit 1023 (in byte 0x80). Because PHY-registers are 16
239 * bit broad, we offset by reg << 1. In the SoC 2 registers are stored in
240 * one 32 bit register.
241 */
242 reg = (phy_reg << 1) & 0xfc;
243 val = sw_r32(RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);
244
245 if (phy_reg & 1)
246 val = (val >> 16) & 0xffff;
247 else
248 val &= 0xffff;
249 return val;
250 }
251
252 /*
253 * On the RTL930x family of SoCs, the internal SerDes are accessed through an IO
254 * register which simulates commands to an internal MDIO bus.
255 */
256 int rtl930x_read_sds_phy(int phy_addr, int page, int phy_reg)
257 {
258 int i;
259 u32 cmd = phy_addr << 2 | page << 7 | phy_reg << 13 | 1;
260
261 sw_w32(cmd, RTL930X_SDS_INDACS_CMD);
262
263 for (i = 0; i < 100; i++) {
264 if (!(sw_r32(RTL930X_SDS_INDACS_CMD) & 0x1))
265 break;
266 mdelay(1);
267 }
268
269 if (i >= 100)
270 return -EIO;
271
272 return sw_r32(RTL930X_SDS_INDACS_DATA) & 0xffff;
273 }
274
275 int rtl930x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v)
276 {
277 int i;
278 u32 cmd;
279
280 sw_w32(v, RTL930X_SDS_INDACS_DATA);
281 cmd = phy_addr << 2 | page << 7 | phy_reg << 13 | 0x3;
282
283 for (i = 0; i < 100; i++) {
284 if (!(sw_r32(RTL930X_SDS_INDACS_CMD) & 0x1))
285 break;
286 mdelay(1);
287 }
288
289
290 if (i >= 100) {
291 pr_info("%s ERROR !!!!!!!!!!!!!!!!!!!!\n", __func__);
292 return -EIO;
293 }
294
295 return 0;
296 }
297
298 int rtl931x_read_sds_phy(int phy_addr, int page, int phy_reg)
299 {
300 int i;
301 u32 cmd = phy_addr << 2 | page << 7 | phy_reg << 13 | 1;
302
303 pr_debug("%s: phy_addr(SDS-ID) %d, phy_reg: %d\n", __func__, phy_addr, phy_reg);
304 sw_w32(cmd, RTL931X_SERDES_INDRT_ACCESS_CTRL);
305
306 for (i = 0; i < 100; i++) {
307 if (!(sw_r32(RTL931X_SERDES_INDRT_ACCESS_CTRL) & 0x1))
308 break;
309 mdelay(1);
310 }
311
312 if (i >= 100)
313 return -EIO;
314
315 pr_debug("%s: returning %04x\n", __func__, sw_r32(RTL931X_SERDES_INDRT_DATA_CTRL) & 0xffff);
316 return sw_r32(RTL931X_SERDES_INDRT_DATA_CTRL) & 0xffff;
317 }
318
319 int rtl931x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v)
320 {
321 int i;
322 u32 cmd;
323
324 cmd = phy_addr << 2 | page << 7 | phy_reg << 13;
325 sw_w32(cmd, RTL931X_SERDES_INDRT_ACCESS_CTRL);
326
327 sw_w32(v, RTL931X_SERDES_INDRT_DATA_CTRL);
328
329 cmd = sw_r32(RTL931X_SERDES_INDRT_ACCESS_CTRL) | 0x3;
330 sw_w32(cmd, RTL931X_SERDES_INDRT_ACCESS_CTRL);
331
332 for (i = 0; i < 100; i++) {
333 if (!(sw_r32(RTL931X_SERDES_INDRT_ACCESS_CTRL) & 0x1))
334 break;
335 mdelay(1);
336 }
337
338 if (i >= 100)
339 return -EIO;
340
341 return 0;
342 }
343
344 /*
345 * On the RTL838x SoCs, the internal SerDes is accessed through direct access to
346 * standard PHY registers, where a 32 bit register holds a 16 bit word as found
347 * in a standard page 0 of a PHY
348 */
349 int rtl838x_read_sds_phy(int phy_addr, int phy_reg)
350 {
351 int offset = 0;
352 u32 val;
353
354 if (phy_addr == 26)
355 offset = 0x100;
356 val = sw_r32(RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2)) & 0xffff;
357
358 return val;
359 }
360
361 int rtl839x_write_sds_phy(int phy_addr, int phy_reg, u16 v)
362 {
363 int offset = 0;
364 int reg;
365 u32 val;
366
367 if (phy_addr == 49)
368 offset = 0x100;
369
370 reg = (phy_reg << 1) & 0xfc;
371 val = v;
372 if (phy_reg & 1) {
373 val = val << 16;
374 sw_w32_mask(0xffff0000, val,
375 RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);
376 } else {
377 sw_w32_mask(0xffff, val,
378 RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);
379 }
380
381 return 0;
382 }
383
384 /* Read the link and speed status of the 2 internal SGMII/1000Base-X
385 * ports of the RTL838x SoCs
386 */
387 static int rtl8380_read_status(struct phy_device *phydev)
388 {
389 int err;
390
391 err = genphy_read_status(phydev);
392
393 if (phydev->link) {
394 phydev->speed = SPEED_1000;
395 phydev->duplex = DUPLEX_FULL;
396 }
397
398 return err;
399 }
400
401 /* Read the link and speed status of the 2 internal SGMII/1000Base-X
402 * ports of the RTL8393 SoC
403 */
404 static int rtl8393_read_status(struct phy_device *phydev)
405 {
406 int offset = 0;
407 int err;
408 int phy_addr = phydev->mdio.addr;
409 u32 v;
410
411 err = genphy_read_status(phydev);
412 if (phy_addr == 49)
413 offset = 0x100;
414
415 if (phydev->link) {
416 phydev->speed = SPEED_100;
417 /* Read SPD_RD_00 (bit 13) and SPD_RD_01 (bit 6) out of the internal
418 * PHY registers
419 */
420 v = sw_r32(RTL839X_SDS12_13_XSG0 + offset + 0x80);
421 if (!(v & (1 << 13)) && (v & (1 << 6)))
422 phydev->speed = SPEED_1000;
423 phydev->duplex = DUPLEX_FULL;
424 }
425
426 return err;
427 }
428
429 static int rtl8226_read_page(struct phy_device *phydev)
430 {
431 return __phy_read(phydev, RTL8XXX_PAGE_SELECT);
432 }
433
434 static int rtl8226_write_page(struct phy_device *phydev, int page)
435 {
436 return __phy_write(phydev, RTL8XXX_PAGE_SELECT, page);
437 }
438
439 static int rtl8226_read_status(struct phy_device *phydev)
440 {
441 int ret = 0, i;
442 u32 val;
443
444 // TODO: ret = genphy_read_status(phydev);
445 // if (ret < 0) {
446 // pr_info("%s: genphy_read_status failed\n", __func__);
447 // return ret;
448 // }
449
450 // Link status must be read twice
451 for (i = 0; i < 2; i++) {
452 val = phy_read_mmd(phydev, MMD_VEND2, 0xA402);
453 }
454 phydev->link = val & BIT(2) ? 1 : 0;
455 if (!phydev->link)
456 goto out;
457
458 // Read duplex status
459 val = phy_read_mmd(phydev, MMD_VEND2, 0xA434);
460 if (val < 0)
461 goto out;
462 phydev->duplex = !!(val & BIT(3));
463
464 // Read speed
465 val = phy_read_mmd(phydev, MMD_VEND2, 0xA434);
466 switch (val & 0x0630) {
467 case 0x0000:
468 phydev->speed = SPEED_10;
469 break;
470 case 0x0010:
471 phydev->speed = SPEED_100;
472 break;
473 case 0x0020:
474 phydev->speed = SPEED_1000;
475 break;
476 case 0x0200:
477 phydev->speed = SPEED_10000;
478 break;
479 case 0x0210:
480 phydev->speed = SPEED_2500;
481 break;
482 case 0x0220:
483 phydev->speed = SPEED_5000;
484 break;
485 default:
486 break;
487 }
488 out:
489 return ret;
490 }
491
492 static int rtl8226_advertise_aneg(struct phy_device *phydev)
493 {
494 int ret = 0;
495 u32 v;
496
497 pr_info("In %s\n", __func__);
498
499 v = phy_read_mmd(phydev, MMD_AN, 16);
500 if (v < 0)
501 goto out;
502
503 v |= BIT(5); // HD 10M
504 v |= BIT(6); // FD 10M
505 v |= BIT(7); // HD 100M
506 v |= BIT(8); // FD 100M
507
508 ret = phy_write_mmd(phydev, MMD_AN, 16, v);
509
510 // Allow 1GBit
511 v = phy_read_mmd(phydev, MMD_VEND2, 0xA412);
512 if (v < 0)
513 goto out;
514 v |= BIT(9); // FD 1000M
515
516 ret = phy_write_mmd(phydev, MMD_VEND2, 0xA412, v);
517 if (ret < 0)
518 goto out;
519
520 // Allow 2.5G
521 v = phy_read_mmd(phydev, MMD_AN, 32);
522 if (v < 0)
523 goto out;
524
525 v |= BIT(7);
526 ret = phy_write_mmd(phydev, MMD_AN, 32, v);
527
528 out:
529 return ret;
530 }
531
532 static int rtl8226_config_aneg(struct phy_device *phydev)
533 {
534 int ret = 0;
535 u32 v;
536
537 pr_debug("In %s\n", __func__);
538 if (phydev->autoneg == AUTONEG_ENABLE) {
539 ret = rtl8226_advertise_aneg(phydev);
540 if (ret)
541 goto out;
542 // AutoNegotiationEnable
543 v = phy_read_mmd(phydev, MMD_AN, 0);
544 if (v < 0)
545 goto out;
546
547 v |= BIT(12); // Enable AN
548 ret = phy_write_mmd(phydev, MMD_AN, 0, v);
549 if (ret < 0)
550 goto out;
551
552 // RestartAutoNegotiation
553 v = phy_read_mmd(phydev, MMD_VEND2, 0xA400);
554 if (v < 0)
555 goto out;
556 v |= BIT(9);
557
558 ret = phy_write_mmd(phydev, MMD_VEND2, 0xA400, v);
559 }
560
561 // TODO: ret = __genphy_config_aneg(phydev, ret);
562
563 out:
564 return ret;
565 }
566
567 static int rtl8226_get_eee(struct phy_device *phydev,
568 struct ethtool_eee *e)
569 {
570 u32 val;
571 int addr = phydev->mdio.addr;
572
573 pr_debug("In %s, port %d, was enabled: %d\n", __func__, addr, e->eee_enabled);
574
575 val = phy_read_mmd(phydev, MMD_AN, 60);
576 if (e->eee_enabled) {
577 e->eee_enabled = !!(val & BIT(1));
578 if (!e->eee_enabled) {
579 val = phy_read_mmd(phydev, MMD_AN, 62);
580 e->eee_enabled = !!(val & BIT(0));
581 }
582 }
583 pr_debug("%s: enabled: %d\n", __func__, e->eee_enabled);
584
585 return 0;
586 }
587
588 static int rtl8226_set_eee(struct phy_device *phydev, struct ethtool_eee *e)
589 {
590 int port = phydev->mdio.addr;
591 u64 poll_state;
592 bool an_enabled;
593 u32 val;
594
595 pr_info("In %s, port %d, enabled %d\n", __func__, port, e->eee_enabled);
596
597 poll_state = disable_polling(port);
598
599 // Remember aneg state
600 val = phy_read_mmd(phydev, MMD_AN, 0);
601 an_enabled = !!(val & BIT(12));
602
603 // Setup 100/1000MBit
604 val = phy_read_mmd(phydev, MMD_AN, 60);
605 if (e->eee_enabled)
606 val |= 0x6;
607 else
608 val &= 0x6;
609 phy_write_mmd(phydev, MMD_AN, 60, val);
610
611 // Setup 2.5GBit
612 val = phy_read_mmd(phydev, MMD_AN, 62);
613 if (e->eee_enabled)
614 val |= 0x1;
615 else
616 val &= 0x1;
617 phy_write_mmd(phydev, MMD_AN, 62, val);
618
619 // RestartAutoNegotiation
620 val = phy_read_mmd(phydev, MMD_VEND2, 0xA400);
621 val |= BIT(9);
622 phy_write_mmd(phydev, MMD_VEND2, 0xA400, val);
623
624 resume_polling(poll_state);
625
626 return 0;
627 }
628
629 static struct fw_header *rtl838x_request_fw(struct phy_device *phydev,
630 const struct firmware *fw,
631 const char *name)
632 {
633 struct device *dev = &phydev->mdio.dev;
634 int err;
635 struct fw_header *h;
636 uint32_t checksum, my_checksum;
637
638 err = request_firmware(&fw, name, dev);
639 if (err < 0)
640 goto out;
641
642 if (fw->size < sizeof(struct fw_header)) {
643 pr_err("Firmware size too small.\n");
644 err = -EINVAL;
645 goto out;
646 }
647
648 h = (struct fw_header *) fw->data;
649 pr_info("Firmware loaded. Size %d, magic: %08x\n", fw->size, h->magic);
650
651 if (h->magic != 0x83808380) {
652 pr_err("Wrong firmware file: MAGIC mismatch.\n");
653 goto out;
654 }
655
656 checksum = h->checksum;
657 h->checksum = 0;
658 my_checksum = ~crc32(0xFFFFFFFFU, fw->data, fw->size);
659 if (checksum != my_checksum) {
660 pr_err("Firmware checksum mismatch.\n");
661 err = -EINVAL;
662 goto out;
663 }
664 h->checksum = checksum;
665
666 return h;
667 out:
668 dev_err(dev, "Unable to load firmware %s (%d)\n", name, err);
669 return NULL;
670 }
671
672 static void rtl821x_phy_setup_package_broadcast(struct phy_device *phydev, bool enable)
673 {
674 int mac = phydev->mdio.addr;
675
676 /* select main page 0 */
677 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
678 /* write to 0x8 to register 0x1d on main page 0 */
679 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL);
680 /* select page 0x266 */
681 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL821X_PAGE_PORT);
682 /* set phy id and target broadcast bitmap in register 0x16 on page 0x266 */
683 phy_write_paged(phydev, RTL83XX_PAGE_RAW, 0x16, (enable?0xff00:0x00) | mac);
684 /* return to main page 0 */
685 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
686 /* write to 0x0 to register 0x1d on main page 0 */
687 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
688 mdelay(1);
689 }
690
691 static int rtl8390_configure_generic(struct phy_device *phydev)
692 {
693 int mac = phydev->mdio.addr;
694 u32 val, phy_id;
695
696 val = phy_read(phydev, 2);
697 phy_id = val << 16;
698 val = phy_read(phydev, 3);
699 phy_id |= val;
700 pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
701
702 /* Read internal PHY ID */
703 phy_write_paged(phydev, 31, 27, 0x0002);
704 val = phy_read_paged(phydev, 31, 28);
705
706 /* Internal RTL8218B, version 2 */
707 phydev_info(phydev, "Detected unknown %x\n", val);
708 return 0;
709 }
710
711 static int rtl8380_configure_int_rtl8218b(struct phy_device *phydev)
712 {
713 u32 val, phy_id;
714 int i, p, ipd_flag;
715 int mac = phydev->mdio.addr;
716 struct fw_header *h;
717 u32 *rtl838x_6275B_intPhy_perport;
718 u32 *rtl8218b_6276B_hwEsd_perport;
719
720 val = phy_read(phydev, 2);
721 phy_id = val << 16;
722 val = phy_read(phydev, 3);
723 phy_id |= val;
724 pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
725
726 /* Read internal PHY ID */
727 phy_write_paged(phydev, 31, 27, 0x0002);
728 val = phy_read_paged(phydev, 31, 28);
729 if (val != 0x6275) {
730 phydev_err(phydev, "Expected internal RTL8218B, found PHY-ID %x\n", val);
731 return -1;
732 }
733
734 /* Internal RTL8218B, version 2 */
735 phydev_info(phydev, "Detected internal RTL8218B\n");
736
737 h = rtl838x_request_fw(phydev, &rtl838x_8380_fw, FIRMWARE_838X_8380_1);
738 if (!h)
739 return -1;
740
741 if (h->phy != 0x83800000) {
742 phydev_err(phydev, "Wrong firmware file: PHY mismatch.\n");
743 return -1;
744 }
745
746 rtl838x_6275B_intPhy_perport = (void *)h + sizeof(struct fw_header)
747 + h->parts[8].start;
748
749 rtl8218b_6276B_hwEsd_perport = (void *)h + sizeof(struct fw_header)
750 + h->parts[9].start;
751
752 if (sw_r32(RTL838X_DMY_REG31) == 0x1)
753 ipd_flag = 1;
754
755 val = phy_read(phydev, 0);
756 if (val & BIT(11))
757 rtl8380_int_phy_on_off(phydev, true);
758 else
759 rtl8380_phy_reset(phydev);
760 msleep(100);
761
762 /* Ready PHY for patch */
763 for (p = 0; p < 8; p++) {
764 phy_package_port_write_paged(phydev, p, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL821X_PAGE_PATCH);
765 phy_package_port_write_paged(phydev, p, RTL83XX_PAGE_RAW, 0x10, 0x0010);
766 }
767 msleep(500);
768 for (p = 0; p < 8; p++) {
769 for (i = 0; i < 100 ; i++) {
770 val = phy_package_port_read_paged(phydev, p, RTL821X_PAGE_STATE, 0x10);
771 if (val & 0x40)
772 break;
773 }
774 if (i >= 100) {
775 phydev_err(phydev,
776 "ERROR: Port %d not ready for patch.\n",
777 mac + p);
778 return -1;
779 }
780 }
781 for (p = 0; p < 8; p++) {
782 i = 0;
783 while (rtl838x_6275B_intPhy_perport[i * 2]) {
784 phy_package_port_write_paged(phydev, p, RTL83XX_PAGE_RAW,
785 rtl838x_6275B_intPhy_perport[i * 2],
786 rtl838x_6275B_intPhy_perport[i * 2 + 1]);
787 i++;
788 }
789 i = 0;
790 while (rtl8218b_6276B_hwEsd_perport[i * 2]) {
791 phy_package_port_write_paged(phydev, p, RTL83XX_PAGE_RAW,
792 rtl8218b_6276B_hwEsd_perport[i * 2],
793 rtl8218b_6276B_hwEsd_perport[i * 2 + 1]);
794 i++;
795 }
796 }
797 return 0;
798 }
799
800 static int rtl8380_configure_ext_rtl8218b(struct phy_device *phydev)
801 {
802 u32 val, ipd, phy_id;
803 int i, l;
804 int mac = phydev->mdio.addr;
805 struct fw_header *h;
806 u32 *rtl8380_rtl8218b_perchip;
807 u32 *rtl8218B_6276B_rtl8380_perport;
808 u32 *rtl8380_rtl8218b_perport;
809
810 if (soc_info.family == RTL8380_FAMILY_ID && mac != 0 && mac != 16) {
811 phydev_err(phydev, "External RTL8218B must have PHY-IDs 0 or 16!\n");
812 return -1;
813 }
814 val = phy_read(phydev, 2);
815 phy_id = val << 16;
816 val = phy_read(phydev, 3);
817 phy_id |= val;
818 pr_info("Phy on MAC %d: %x\n", mac, phy_id);
819
820 /* Read internal PHY ID */
821 phy_write_paged(phydev, 31, 27, 0x0002);
822 val = phy_read_paged(phydev, 31, 28);
823 if (val != 0x6276) {
824 phydev_err(phydev, "Expected external RTL8218B, found PHY-ID %x\n", val);
825 return -1;
826 }
827 phydev_info(phydev, "Detected external RTL8218B\n");
828
829 h = rtl838x_request_fw(phydev, &rtl838x_8218b_fw, FIRMWARE_838X_8218b_1);
830 if (!h)
831 return -1;
832
833 if (h->phy != 0x8218b000) {
834 phydev_err(phydev, "Wrong firmware file: PHY mismatch.\n");
835 return -1;
836 }
837
838 rtl8380_rtl8218b_perchip = (void *)h + sizeof(struct fw_header)
839 + h->parts[0].start;
840
841 rtl8218B_6276B_rtl8380_perport = (void *)h + sizeof(struct fw_header)
842 + h->parts[1].start;
843
844 rtl8380_rtl8218b_perport = (void *)h + sizeof(struct fw_header)
845 + h->parts[2].start;
846
847 val = phy_read(phydev, 0);
848 if (val & (1 << 11))
849 rtl8380_int_phy_on_off(phydev, true);
850 else
851 rtl8380_phy_reset(phydev);
852
853 msleep(100);
854
855 /* Get Chip revision */
856 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
857 phy_write_paged(phydev, RTL83XX_PAGE_RAW, 0x1b, 0x4);
858 val = phy_read_paged(phydev, RTL83XX_PAGE_RAW, 0x1c);
859
860 phydev_info(phydev, "Detected chip revision %04x\n", val);
861
862 i = 0;
863 while (rtl8380_rtl8218b_perchip[i * 3]
864 && rtl8380_rtl8218b_perchip[i * 3 + 1]) {
865 phy_package_port_write_paged(phydev, rtl8380_rtl8218b_perchip[i * 3],
866 RTL83XX_PAGE_RAW, rtl8380_rtl8218b_perchip[i * 3 + 1],
867 rtl8380_rtl8218b_perchip[i * 3 + 2]);
868 i++;
869 }
870
871 /* Enable PHY */
872 for (i = 0; i < 8; i++) {
873 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
874 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, 0x00, 0x1140);
875 }
876 mdelay(100);
877
878 /* Request patch */
879 for (i = 0; i < 8; i++) {
880 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL821X_PAGE_PATCH);
881 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, 0x10, 0x0010);
882 }
883
884 mdelay(300);
885
886 /* Verify patch readiness */
887 for (i = 0; i < 8; i++) {
888 for (l = 0; l < 100; l++) {
889 val = phy_package_port_read_paged(phydev, i, RTL821X_PAGE_STATE, 0x10);
890 if (val & 0x40)
891 break;
892 }
893 if (l >= 100) {
894 phydev_err(phydev, "Could not patch PHY\n");
895 return -1;
896 }
897 }
898
899 /* Use Broadcast ID method for patching */
900 rtl821x_phy_setup_package_broadcast(phydev, true);
901
902 phy_write_paged(phydev, RTL83XX_PAGE_RAW, 30, 8);
903 phy_write_paged(phydev, 0x26e, 17, 0xb);
904 phy_write_paged(phydev, 0x26e, 16, 0x2);
905 mdelay(1);
906 ipd = phy_read_paged(phydev, 0x26e, 19);
907 phy_write_paged(phydev, 0, 30, 0);
908 ipd = (ipd >> 4) & 0xf; /* unused ? */
909
910 i = 0;
911 while (rtl8218B_6276B_rtl8380_perport[i * 2]) {
912 phy_write_paged(phydev, RTL83XX_PAGE_RAW, rtl8218B_6276B_rtl8380_perport[i * 2],
913 rtl8218B_6276B_rtl8380_perport[i * 2 + 1]);
914 i++;
915 }
916
917 /*Disable broadcast ID*/
918 rtl821x_phy_setup_package_broadcast(phydev, false);
919
920 return 0;
921 }
922
923 static int rtl8218b_ext_match_phy_device(struct phy_device *phydev)
924 {
925 int addr = phydev->mdio.addr;
926
927 /* Both the RTL8214FC and the external RTL8218B have the same
928 * PHY ID. On the RTL838x, the RTL8218B can only be attached_dev
929 * at PHY IDs 0-7, while the RTL8214FC must be attached via
930 * the pair of SGMII/1000Base-X with higher PHY-IDs
931 */
932 if (soc_info.family == RTL8380_FAMILY_ID)
933 return phydev->phy_id == PHY_ID_RTL8218B_E && addr < 8;
934 else
935 return phydev->phy_id == PHY_ID_RTL8218B_E;
936 }
937
938 static bool rtl8214fc_media_is_fibre(struct phy_device *phydev)
939 {
940 int mac = phydev->mdio.addr;
941
942 static int reg[] = {16, 19, 20, 21};
943 u32 val;
944
945 phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL);
946 val = phy_package_read_paged(phydev, RTL821X_PAGE_PORT, reg[mac % 4]);
947 phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
948
949 if (val & BIT(11))
950 return false;
951
952 return true;
953 }
954
955 static void rtl8214fc_power_set(struct phy_device *phydev, int port, bool on)
956 {
957 char *state = on ? "on" : "off";
958
959 if (port == PORT_FIBRE) {
960 pr_info("%s: Powering %s FIBRE (port %d)\n", __func__, state, phydev->mdio.addr);
961 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_FIBRE);
962 } else {
963 pr_info("%s: Powering %s COPPER (port %d)\n", __func__, state, phydev->mdio.addr);
964 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
965 }
966
967 if (on) {
968 phy_modify_paged(phydev, RTL821X_PAGE_POWER, 0x10, BIT(11), 0);
969 } else {
970 phy_modify_paged(phydev, RTL821X_PAGE_POWER, 0x10, 0, BIT(11));
971 }
972
973 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
974 }
975
976 static int rtl8214fc_suspend(struct phy_device *phydev)
977 {
978 rtl8214fc_power_set(phydev, PORT_MII, false);
979 rtl8214fc_power_set(phydev, PORT_FIBRE, false);
980
981 return 0;
982 }
983
984 static int rtl8214fc_resume(struct phy_device *phydev)
985 {
986 if (rtl8214fc_media_is_fibre(phydev)) {
987 rtl8214fc_power_set(phydev, PORT_MII, false);
988 rtl8214fc_power_set(phydev, PORT_FIBRE, true);
989 } else {
990 rtl8214fc_power_set(phydev, PORT_FIBRE, false);
991 rtl8214fc_power_set(phydev, PORT_MII, true);
992 }
993
994 return 0;
995 }
996
997 static void rtl8214fc_media_set(struct phy_device *phydev, bool set_fibre)
998 {
999 int mac = phydev->mdio.addr;
1000
1001 static int reg[] = {16, 19, 20, 21};
1002 int val;
1003
1004 pr_info("%s: port %d, set_fibre: %d\n", __func__, mac, set_fibre);
1005 phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL);
1006 val = phy_package_read_paged(phydev, RTL821X_PAGE_PORT, reg[mac % 4]);
1007
1008 val |= BIT(10);
1009 if (set_fibre) {
1010 val &= ~BIT(11);
1011 } else {
1012 val |= BIT(11);
1013 }
1014
1015 phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL);
1016 phy_package_write_paged(phydev, RTL821X_PAGE_PORT, reg[mac % 4], val);
1017 phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1018
1019 if (!phydev->suspended) {
1020 if (set_fibre) {
1021 rtl8214fc_power_set(phydev, PORT_MII, false);
1022 rtl8214fc_power_set(phydev, PORT_FIBRE, true);
1023 } else {
1024 rtl8214fc_power_set(phydev, PORT_FIBRE, false);
1025 rtl8214fc_power_set(phydev, PORT_MII, true);
1026 }
1027 }
1028 }
1029
1030 static int rtl8214fc_set_port(struct phy_device *phydev, int port)
1031 {
1032 bool is_fibre = (port == PORT_FIBRE ? true : false);
1033 int addr = phydev->mdio.addr;
1034
1035 pr_debug("%s port %d to %d\n", __func__, addr, port);
1036
1037 rtl8214fc_media_set(phydev, is_fibre);
1038 return 0;
1039 }
1040
1041 static int rtl8214fc_get_port(struct phy_device *phydev)
1042 {
1043 int addr = phydev->mdio.addr;
1044
1045 pr_debug("%s: port %d\n", __func__, addr);
1046 if (rtl8214fc_media_is_fibre(phydev))
1047 return PORT_FIBRE;
1048 return PORT_MII;
1049 }
1050
1051 /*
1052 * Enable EEE on the RTL8218B PHYs
1053 * The method used is not the preferred way (which would be based on the MAC-EEE state,
1054 * but the only way that works since the kernel first enables EEE in the MAC
1055 * and then sets up the PHY. The MAC-based approach would require the oppsite.
1056 */
1057 void rtl8218d_eee_set(struct phy_device *phydev, bool enable)
1058 {
1059 u32 val;
1060 bool an_enabled;
1061
1062 pr_debug("In %s %d, enable %d\n", __func__, phydev->mdio.addr, enable);
1063 /* Set GPHY page to copper */
1064 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1065
1066 val = phy_read(phydev, 0);
1067 an_enabled = val & BIT(12);
1068
1069 /* Enable 100M (bit 1) / 1000M (bit 2) EEE */
1070 val = phy_read_mmd(phydev, 7, 60);
1071 val |= BIT(2) | BIT(1);
1072 phy_write_mmd(phydev, 7, 60, enable ? 0x6 : 0);
1073
1074 /* 500M EEE ability */
1075 val = phy_read_paged(phydev, RTL821X_PAGE_GPHY, 20);
1076 if (enable)
1077 val |= BIT(7);
1078 else
1079 val &= ~BIT(7);
1080 phy_write_paged(phydev, RTL821X_PAGE_GPHY, 20, val);
1081
1082 /* Restart AN if enabled */
1083 if (an_enabled) {
1084 val = phy_read(phydev, 0);
1085 val |= BIT(9);
1086 phy_write(phydev, 0, val);
1087 }
1088
1089 /* GPHY page back to auto*/
1090 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1091 }
1092
1093 static int rtl8218b_get_eee(struct phy_device *phydev,
1094 struct ethtool_eee *e)
1095 {
1096 u32 val;
1097 int addr = phydev->mdio.addr;
1098
1099 pr_debug("In %s, port %d, was enabled: %d\n", __func__, addr, e->eee_enabled);
1100
1101 /* Set GPHY page to copper */
1102 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1103
1104 val = phy_read_paged(phydev, 7, 60);
1105 if (e->eee_enabled) {
1106 // Verify vs MAC-based EEE
1107 e->eee_enabled = !!(val & BIT(7));
1108 if (!e->eee_enabled) {
1109 val = phy_read_paged(phydev, RTL821X_PAGE_MAC, 25);
1110 e->eee_enabled = !!(val & BIT(4));
1111 }
1112 }
1113 pr_debug("%s: enabled: %d\n", __func__, e->eee_enabled);
1114
1115 /* GPHY page to auto */
1116 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1117
1118 return 0;
1119 }
1120
1121 static int rtl8218d_get_eee(struct phy_device *phydev,
1122 struct ethtool_eee *e)
1123 {
1124 u32 val;
1125 int addr = phydev->mdio.addr;
1126
1127 pr_debug("In %s, port %d, was enabled: %d\n", __func__, addr, e->eee_enabled);
1128
1129 /* Set GPHY page to copper */
1130 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1131
1132 val = phy_read_paged(phydev, 7, 60);
1133 if (e->eee_enabled)
1134 e->eee_enabled = !!(val & BIT(7));
1135 pr_debug("%s: enabled: %d\n", __func__, e->eee_enabled);
1136
1137 /* GPHY page to auto */
1138 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1139
1140 return 0;
1141 }
1142
1143 static int rtl8214fc_set_eee(struct phy_device *phydev,
1144 struct ethtool_eee *e)
1145 {
1146 u32 poll_state;
1147 int port = phydev->mdio.addr;
1148 bool an_enabled;
1149 u32 val;
1150
1151 pr_debug("In %s port %d, enabled %d\n", __func__, port, e->eee_enabled);
1152
1153 if (rtl8214fc_media_is_fibre(phydev)) {
1154 netdev_err(phydev->attached_dev, "Port %d configured for FIBRE", port);
1155 return -ENOTSUPP;
1156 }
1157
1158 poll_state = disable_polling(port);
1159
1160 /* Set GPHY page to copper */
1161 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1162
1163 // Get auto-negotiation status
1164 val = phy_read(phydev, 0);
1165 an_enabled = val & BIT(12);
1166
1167 pr_info("%s: aneg: %d\n", __func__, an_enabled);
1168 val = phy_read_paged(phydev, RTL821X_PAGE_MAC, 25);
1169 val &= ~BIT(5); // Use MAC-based EEE
1170 phy_write_paged(phydev, RTL821X_PAGE_MAC, 25, val);
1171
1172 /* Enable 100M (bit 1) / 1000M (bit 2) EEE */
1173 phy_write_paged(phydev, 7, 60, e->eee_enabled ? 0x6 : 0);
1174
1175 /* 500M EEE ability */
1176 val = phy_read_paged(phydev, RTL821X_PAGE_GPHY, 20);
1177 if (e->eee_enabled)
1178 val |= BIT(7);
1179 else
1180 val &= ~BIT(7);
1181
1182 phy_write_paged(phydev, RTL821X_PAGE_GPHY, 20, val);
1183
1184 /* Restart AN if enabled */
1185 if (an_enabled) {
1186 pr_info("%s: doing aneg\n", __func__);
1187 val = phy_read(phydev, 0);
1188 val |= BIT(9);
1189 phy_write(phydev, 0, val);
1190 }
1191
1192 /* GPHY page back to auto*/
1193 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1194
1195 resume_polling(poll_state);
1196
1197 return 0;
1198 }
1199
1200 static int rtl8214fc_get_eee(struct phy_device *phydev,
1201 struct ethtool_eee *e)
1202 {
1203 int addr = phydev->mdio.addr;
1204
1205 pr_debug("In %s port %d, enabled %d\n", __func__, addr, e->eee_enabled);
1206 if (rtl8214fc_media_is_fibre(phydev)) {
1207 netdev_err(phydev->attached_dev, "Port %d configured for FIBRE", addr);
1208 return -ENOTSUPP;
1209 }
1210
1211 return rtl8218b_get_eee(phydev, e);
1212 }
1213
1214 static int rtl8218b_set_eee(struct phy_device *phydev, struct ethtool_eee *e)
1215 {
1216 int port = phydev->mdio.addr;
1217 u64 poll_state;
1218 u32 val;
1219 bool an_enabled;
1220
1221 pr_info("In %s, port %d, enabled %d\n", __func__, port, e->eee_enabled);
1222
1223 poll_state = disable_polling(port);
1224
1225 /* Set GPHY page to copper */
1226 phy_write(phydev, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1227 val = phy_read(phydev, 0);
1228 an_enabled = val & BIT(12);
1229
1230 if (e->eee_enabled) {
1231 /* 100/1000M EEE Capability */
1232 phy_write(phydev, 13, 0x0007);
1233 phy_write(phydev, 14, 0x003C);
1234 phy_write(phydev, 13, 0x4007);
1235 phy_write(phydev, 14, 0x0006);
1236
1237 val = phy_read_paged(phydev, RTL821X_PAGE_MAC, 25);
1238 val |= BIT(4);
1239 phy_write_paged(phydev, RTL821X_PAGE_MAC, 25, val);
1240 } else {
1241 /* 100/1000M EEE Capability */
1242 phy_write(phydev, 13, 0x0007);
1243 phy_write(phydev, 14, 0x003C);
1244 phy_write(phydev, 13, 0x0007);
1245 phy_write(phydev, 14, 0x0000);
1246
1247 val = phy_read_paged(phydev, RTL821X_PAGE_MAC, 25);
1248 val &= ~BIT(4);
1249 phy_write_paged(phydev, RTL821X_PAGE_MAC, 25, val);
1250 }
1251
1252 /* Restart AN if enabled */
1253 if (an_enabled) {
1254 val = phy_read(phydev, 0);
1255 val |= BIT(9);
1256 phy_write(phydev, 0, val);
1257 }
1258
1259 /* GPHY page back to auto*/
1260 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1261
1262 pr_info("%s done\n", __func__);
1263 resume_polling(poll_state);
1264
1265 return 0;
1266 }
1267
1268 static int rtl8218d_set_eee(struct phy_device *phydev, struct ethtool_eee *e)
1269 {
1270 int addr = phydev->mdio.addr;
1271 u64 poll_state;
1272
1273 pr_info("In %s, port %d, enabled %d\n", __func__, addr, e->eee_enabled);
1274
1275 poll_state = disable_polling(addr);
1276
1277 rtl8218d_eee_set(phydev, (bool) e->eee_enabled);
1278
1279 resume_polling(poll_state);
1280
1281 return 0;
1282 }
1283
1284 static int rtl8214c_match_phy_device(struct phy_device *phydev)
1285 {
1286 return phydev->phy_id == PHY_ID_RTL8214C;
1287 }
1288
1289 static int rtl8380_configure_rtl8214c(struct phy_device *phydev)
1290 {
1291 u32 phy_id, val;
1292 int mac = phydev->mdio.addr;
1293
1294 val = phy_read(phydev, 2);
1295 phy_id = val << 16;
1296 val = phy_read(phydev, 3);
1297 phy_id |= val;
1298 pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
1299
1300 phydev_info(phydev, "Detected external RTL8214C\n");
1301
1302 /* GPHY auto conf */
1303 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1304 return 0;
1305 }
1306
1307 static int rtl8380_configure_rtl8214fc(struct phy_device *phydev)
1308 {
1309 u32 phy_id, val, page = 0;
1310 int i, l;
1311 int mac = phydev->mdio.addr;
1312 struct fw_header *h;
1313 u32 *rtl8380_rtl8214fc_perchip;
1314 u32 *rtl8380_rtl8214fc_perport;
1315
1316 val = phy_read(phydev, 2);
1317 phy_id = val << 16;
1318 val = phy_read(phydev, 3);
1319 phy_id |= val;
1320 pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
1321
1322 /* Read internal PHY id */
1323 phy_write_paged(phydev, 0, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1324 phy_write_paged(phydev, 0x1f, 0x1b, 0x0002);
1325 val = phy_read_paged(phydev, 0x1f, 0x1c);
1326 if (val != 0x6276) {
1327 phydev_err(phydev, "Expected external RTL8214FC, found PHY-ID %x\n", val);
1328 return -1;
1329 }
1330 phydev_info(phydev, "Detected external RTL8214FC\n");
1331
1332 h = rtl838x_request_fw(phydev, &rtl838x_8214fc_fw, FIRMWARE_838X_8214FC_1);
1333 if (!h)
1334 return -1;
1335
1336 if (h->phy != 0x8214fc00) {
1337 phydev_err(phydev, "Wrong firmware file: PHY mismatch.\n");
1338 return -1;
1339 }
1340
1341 rtl8380_rtl8214fc_perchip = (void *)h + sizeof(struct fw_header)
1342 + h->parts[0].start;
1343
1344 rtl8380_rtl8214fc_perport = (void *)h + sizeof(struct fw_header)
1345 + h->parts[1].start;
1346
1347 /* detect phy version */
1348 phy_write_paged(phydev, RTL83XX_PAGE_RAW, 27, 0x0004);
1349 val = phy_read_paged(phydev, RTL83XX_PAGE_RAW, 28);
1350
1351 val = phy_read(phydev, 16);
1352 if (val & (1 << 11))
1353 rtl8380_rtl8214fc_on_off(phydev, true);
1354 else
1355 rtl8380_phy_reset(phydev);
1356
1357 msleep(100);
1358 phy_write_paged(phydev, 0, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1359
1360 i = 0;
1361 while (rtl8380_rtl8214fc_perchip[i * 3]
1362 && rtl8380_rtl8214fc_perchip[i * 3 + 1]) {
1363 if (rtl8380_rtl8214fc_perchip[i * 3 + 1] == 0x1f)
1364 page = rtl8380_rtl8214fc_perchip[i * 3 + 2];
1365 if (rtl8380_rtl8214fc_perchip[i * 3 + 1] == 0x13 && page == 0x260) {
1366 val = phy_read_paged(phydev, 0x260, 13);
1367 val = (val & 0x1f00) | (rtl8380_rtl8214fc_perchip[i * 3 + 2]
1368 & 0xe0ff);
1369 phy_write_paged(phydev, RTL83XX_PAGE_RAW,
1370 rtl8380_rtl8214fc_perchip[i * 3 + 1], val);
1371 } else {
1372 phy_write_paged(phydev, RTL83XX_PAGE_RAW,
1373 rtl8380_rtl8214fc_perchip[i * 3 + 1],
1374 rtl8380_rtl8214fc_perchip[i * 3 + 2]);
1375 }
1376 i++;
1377 }
1378
1379 /* Force copper medium */
1380 for (i = 0; i < 4; i++) {
1381 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
1382 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1383 }
1384
1385 /* Enable PHY */
1386 for (i = 0; i < 4; i++) {
1387 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
1388 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, 0x00, 0x1140);
1389 }
1390 mdelay(100);
1391
1392 /* Disable Autosensing */
1393 for (i = 0; i < 4; i++) {
1394 for (l = 0; l < 100; l++) {
1395 val = phy_package_port_read_paged(phydev, i, RTL821X_PAGE_GPHY, 0x10);
1396 if ((val & 0x7) >= 3)
1397 break;
1398 }
1399 if (l >= 100) {
1400 phydev_err(phydev, "Could not disable autosensing\n");
1401 return -1;
1402 }
1403 }
1404
1405 /* Request patch */
1406 for (i = 0; i < 4; i++) {
1407 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL821X_PAGE_PATCH);
1408 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, 0x10, 0x0010);
1409 }
1410 mdelay(300);
1411
1412 /* Verify patch readiness */
1413 for (i = 0; i < 4; i++) {
1414 for (l = 0; l < 100; l++) {
1415 val = phy_package_port_read_paged(phydev, i, RTL821X_PAGE_STATE, 0x10);
1416 if (val & 0x40)
1417 break;
1418 }
1419 if (l >= 100) {
1420 phydev_err(phydev, "Could not patch PHY\n");
1421 return -1;
1422 }
1423 }
1424 /* Use Broadcast ID method for patching */
1425 rtl821x_phy_setup_package_broadcast(phydev, true);
1426
1427 i = 0;
1428 while (rtl8380_rtl8214fc_perport[i * 2]) {
1429 phy_write_paged(phydev, RTL83XX_PAGE_RAW, rtl8380_rtl8214fc_perport[i * 2],
1430 rtl8380_rtl8214fc_perport[i * 2 + 1]);
1431 i++;
1432 }
1433
1434 /*Disable broadcast ID*/
1435 rtl821x_phy_setup_package_broadcast(phydev, false);
1436
1437 /* Auto medium selection */
1438 for (i = 0; i < 4; i++) {
1439 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
1440 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1441 }
1442
1443 return 0;
1444 }
1445
1446 static int rtl8214fc_match_phy_device(struct phy_device *phydev)
1447 {
1448 int addr = phydev->mdio.addr;
1449
1450 return phydev->phy_id == PHY_ID_RTL8214FC && addr >= 24;
1451 }
1452
1453 static int rtl8380_configure_serdes(struct phy_device *phydev)
1454 {
1455 u32 v;
1456 u32 sds_conf_value;
1457 int i;
1458 struct fw_header *h;
1459 u32 *rtl8380_sds_take_reset;
1460 u32 *rtl8380_sds_common;
1461 u32 *rtl8380_sds01_qsgmii_6275b;
1462 u32 *rtl8380_sds23_qsgmii_6275b;
1463 u32 *rtl8380_sds4_fiber_6275b;
1464 u32 *rtl8380_sds5_fiber_6275b;
1465 u32 *rtl8380_sds_reset;
1466 u32 *rtl8380_sds_release_reset;
1467
1468 phydev_info(phydev, "Detected internal RTL8380 SERDES\n");
1469
1470 h = rtl838x_request_fw(phydev, &rtl838x_8218b_fw, FIRMWARE_838X_8380_1);
1471 if (!h)
1472 return -1;
1473
1474 if (h->magic != 0x83808380) {
1475 phydev_err(phydev, "Wrong firmware file: magic number mismatch.\n");
1476 return -1;
1477 }
1478
1479 rtl8380_sds_take_reset = (void *)h + sizeof(struct fw_header)
1480 + h->parts[0].start;
1481
1482 rtl8380_sds_common = (void *)h + sizeof(struct fw_header)
1483 + h->parts[1].start;
1484
1485 rtl8380_sds01_qsgmii_6275b = (void *)h + sizeof(struct fw_header)
1486 + h->parts[2].start;
1487
1488 rtl8380_sds23_qsgmii_6275b = (void *)h + sizeof(struct fw_header)
1489 + h->parts[3].start;
1490
1491 rtl8380_sds4_fiber_6275b = (void *)h + sizeof(struct fw_header)
1492 + h->parts[4].start;
1493
1494 rtl8380_sds5_fiber_6275b = (void *)h + sizeof(struct fw_header)
1495 + h->parts[5].start;
1496
1497 rtl8380_sds_reset = (void *)h + sizeof(struct fw_header)
1498 + h->parts[6].start;
1499
1500 rtl8380_sds_release_reset = (void *)h + sizeof(struct fw_header)
1501 + h->parts[7].start;
1502
1503 /* Back up serdes power off value */
1504 sds_conf_value = sw_r32(RTL838X_SDS_CFG_REG);
1505 pr_info("SDS power down value: %x\n", sds_conf_value);
1506
1507 /* take serdes into reset */
1508 i = 0;
1509 while (rtl8380_sds_take_reset[2 * i]) {
1510 sw_w32(rtl8380_sds_take_reset[2 * i + 1], rtl8380_sds_take_reset[2 * i]);
1511 i++;
1512 udelay(1000);
1513 }
1514
1515 /* apply common serdes patch */
1516 i = 0;
1517 while (rtl8380_sds_common[2 * i]) {
1518 sw_w32(rtl8380_sds_common[2 * i + 1], rtl8380_sds_common[2 * i]);
1519 i++;
1520 udelay(1000);
1521 }
1522
1523 /* internal R/W enable */
1524 sw_w32(3, RTL838X_INT_RW_CTRL);
1525
1526 /* SerDes ports 4 and 5 are FIBRE ports */
1527 sw_w32_mask(0x7 | 0x38, 1 | (1 << 3), RTL838X_INT_MODE_CTRL);
1528
1529 /* SerDes module settings, SerDes 0-3 are QSGMII */
1530 v = 0x6 << 25 | 0x6 << 20 | 0x6 << 15 | 0x6 << 10;
1531 /* SerDes 4 and 5 are 1000BX FIBRE */
1532 v |= 0x4 << 5 | 0x4;
1533 sw_w32(v, RTL838X_SDS_MODE_SEL);
1534
1535 pr_info("PLL control register: %x\n", sw_r32(RTL838X_PLL_CML_CTRL));
1536 sw_w32_mask(0xfffffff0, 0xaaaaaaaf & 0xf, RTL838X_PLL_CML_CTRL);
1537 i = 0;
1538 while (rtl8380_sds01_qsgmii_6275b[2 * i]) {
1539 sw_w32(rtl8380_sds01_qsgmii_6275b[2 * i + 1],
1540 rtl8380_sds01_qsgmii_6275b[2 * i]);
1541 i++;
1542 }
1543
1544 i = 0;
1545 while (rtl8380_sds23_qsgmii_6275b[2 * i]) {
1546 sw_w32(rtl8380_sds23_qsgmii_6275b[2 * i + 1], rtl8380_sds23_qsgmii_6275b[2 * i]);
1547 i++;
1548 }
1549
1550 i = 0;
1551 while (rtl8380_sds4_fiber_6275b[2 * i]) {
1552 sw_w32(rtl8380_sds4_fiber_6275b[2 * i + 1], rtl8380_sds4_fiber_6275b[2 * i]);
1553 i++;
1554 }
1555
1556 i = 0;
1557 while (rtl8380_sds5_fiber_6275b[2 * i]) {
1558 sw_w32(rtl8380_sds5_fiber_6275b[2 * i + 1], rtl8380_sds5_fiber_6275b[2 * i]);
1559 i++;
1560 }
1561
1562 i = 0;
1563 while (rtl8380_sds_reset[2 * i]) {
1564 sw_w32(rtl8380_sds_reset[2 * i + 1], rtl8380_sds_reset[2 * i]);
1565 i++;
1566 }
1567
1568 i = 0;
1569 while (rtl8380_sds_release_reset[2 * i]) {
1570 sw_w32(rtl8380_sds_release_reset[2 * i + 1], rtl8380_sds_release_reset[2 * i]);
1571 i++;
1572 }
1573
1574 pr_info("SDS power down value now: %x\n", sw_r32(RTL838X_SDS_CFG_REG));
1575 sw_w32(sds_conf_value, RTL838X_SDS_CFG_REG);
1576
1577 pr_info("Configuration of SERDES done\n");
1578 return 0;
1579 }
1580
1581 static int rtl8390_configure_serdes(struct phy_device *phydev)
1582 {
1583 phydev_info(phydev, "Detected internal RTL8390 SERDES\n");
1584
1585 /* In autoneg state, force link, set SR4_CFG_EN_LINK_FIB1G */
1586 sw_w32_mask(0, 1 << 18, RTL839X_SDS12_13_XSG0 + 0x0a);
1587
1588 /* Disable EEE: Clear FRE16_EEE_RSG_FIB1G, FRE16_EEE_STD_FIB1G,
1589 * FRE16_C1_PWRSAV_EN_FIB1G, FRE16_C2_PWRSAV_EN_FIB1G
1590 * and FRE16_EEE_QUIET_FIB1G
1591 */
1592 sw_w32_mask(0x1f << 10, 0, RTL839X_SDS12_13_XSG0 + 0xe0);
1593
1594 return 0;
1595 }
1596
1597 void rtl9300_sds_field_w(int sds, u32 page, u32 reg, int end_bit, int start_bit, u32 v)
1598 {
1599 int l = end_bit - start_bit + 1;
1600 u32 data = v;
1601
1602 if (l < 32) {
1603 u32 mask = BIT(l) - 1;
1604
1605 data = rtl930x_read_sds_phy(sds, page, reg);
1606 data &= ~(mask << start_bit);
1607 data |= (v & mask) << start_bit;
1608 }
1609
1610 rtl930x_write_sds_phy(sds, page, reg, data);
1611 }
1612
1613 u32 rtl9300_sds_field_r(int sds, u32 page, u32 reg, int end_bit, int start_bit)
1614 {
1615 int l = end_bit - start_bit + 1;
1616 u32 v = rtl930x_read_sds_phy(sds, page, reg);
1617
1618 if (l >= 32)
1619 return v;
1620
1621 return (v >> start_bit) & (BIT(l) - 1);
1622 }
1623
1624 /* Read the link and speed status of the internal SerDes of the RTL9300
1625 */
1626 static int rtl9300_read_status(struct phy_device *phydev)
1627 {
1628 struct device *dev = &phydev->mdio.dev;
1629 int phy_addr = phydev->mdio.addr;
1630 struct device_node *dn;
1631 u32 sds_num = 0, status, latch_status, mode;
1632
1633 if (dev->of_node) {
1634 dn = dev->of_node;
1635
1636 if (of_property_read_u32(dn, "sds", &sds_num))
1637 sds_num = -1;
1638 pr_info("%s: Port %d, SerDes is %d\n", __func__, phy_addr, sds_num);
1639 } else {
1640 dev_err(dev, "No DT node.\n");
1641 return -EINVAL;
1642 }
1643
1644 if (sds_num < 0)
1645 return 0;
1646
1647 mode = rtl9300_sds_mode_get(sds_num);
1648 pr_info("%s got SDS mode %02x\n", __func__, mode);
1649 if (mode == 0x1a) { // 10GR mode
1650 status = rtl9300_sds_field_r(sds_num, 0x5, 0, 12, 12);
1651 latch_status = rtl9300_sds_field_r(sds_num, 0x4, 1, 2, 2);
1652 status |= rtl9300_sds_field_r(sds_num, 0x5, 0, 12, 12);
1653 latch_status |= rtl9300_sds_field_r(sds_num, 0x4, 1, 2, 2);
1654 } else {
1655 status = rtl9300_sds_field_r(sds_num, 0x1, 29, 8, 0);
1656 latch_status = rtl9300_sds_field_r(sds_num, 0x1, 30, 8, 0);
1657 status |= rtl9300_sds_field_r(sds_num, 0x1, 29, 8, 0);
1658 latch_status |= rtl9300_sds_field_r(sds_num, 0x1, 30, 8, 0);
1659 }
1660
1661 pr_info("%s link status: status: %d, latch %d\n", __func__, status, latch_status);
1662
1663 if (latch_status) {
1664 phydev->link = true;
1665 if (mode == 0x1a)
1666 phydev->speed = SPEED_10000;
1667 else
1668 phydev->speed = SPEED_1000;
1669
1670 phydev->duplex = DUPLEX_FULL;
1671 }
1672
1673 return 0;
1674 }
1675
1676 void rtl930x_sds_rx_rst(int sds_num, phy_interface_t phy_if)
1677 {
1678 int page = 0x2e; // 10GR and USXGMII
1679
1680 if (phy_if == PHY_INTERFACE_MODE_1000BASEX)
1681 page = 0x24;
1682
1683 rtl9300_sds_field_w(sds_num, page, 0x15, 4, 4, 0x1);
1684 mdelay(5);
1685 rtl9300_sds_field_w(sds_num, page, 0x15, 4, 4, 0x0);
1686 }
1687
1688 /*
1689 * Force PHY modes on 10GBit Serdes
1690 */
1691 void rtl9300_force_sds_mode(int sds, phy_interface_t phy_if)
1692 {
1693 int sds_mode;
1694 bool lc_on;
1695 int i, lc_value;
1696 int lane_0 = (sds % 2) ? sds - 1 : sds;
1697 u32 v, cr_0, cr_1, cr_2;
1698 u32 m_bit, l_bit;
1699
1700 pr_info("%s --------------------- serdes %d forcing to %x ...\n", __func__, sds, sds_mode);
1701 pr_info("%s: SDS: %d, mode %d\n", __func__, sds, phy_if);
1702 switch (phy_if) {
1703 case PHY_INTERFACE_MODE_SGMII:
1704 sds_mode = 0x2;
1705 lc_on = false;
1706 lc_value = 0x1;
1707 break;
1708
1709 case PHY_INTERFACE_MODE_HSGMII:
1710 sds_mode = 0x12;
1711 lc_value = 0x3;
1712 // Configure LC
1713 break;
1714
1715 case PHY_INTERFACE_MODE_1000BASEX:
1716 sds_mode = 0x04;
1717 lc_on = false;
1718 break;
1719
1720 case PHY_INTERFACE_MODE_2500BASEX:
1721 sds_mode = 0x16;
1722 lc_value = 0x3;
1723 // Configure LC
1724 break;
1725
1726 case PHY_INTERFACE_MODE_10GBASER:
1727 sds_mode = 0x1a;
1728 lc_on = true;
1729 lc_value = 0x5;
1730 break;
1731
1732 case PHY_INTERFACE_MODE_NA:
1733 // This will disable SerDes
1734 sds_mode = 0x1f;
1735 break;
1736
1737 default:
1738 pr_err("%s: unknown serdes mode: %s\n",
1739 __func__, phy_modes(phy_if));
1740 return;
1741 }
1742
1743 pr_info("%s: SDS mode %x\n", __func__, sds_mode);
1744 // Power down SerDes
1745 rtl9300_sds_field_w(sds, 0x20, 0, 7, 6, 0x3);
1746 if (sds == 5) pr_info("%s after %x\n", __func__, rtl930x_read_sds_phy(sds, 0x20, 0));
1747
1748 if (sds == 5) pr_info("%s a %x\n", __func__, rtl930x_read_sds_phy(sds, 0x1f, 9));
1749 // Force mode enable
1750 rtl9300_sds_field_w(sds, 0x1f, 9, 6, 6, 0x1);
1751 if (sds == 5) pr_info("%s b %x\n", __func__, rtl930x_read_sds_phy(sds, 0x1f, 9));
1752
1753 /* SerDes off */
1754 rtl9300_sds_field_w(sds, 0x1f, 9, 11, 7, 0x1f);
1755
1756 if (phy_if == PHY_INTERFACE_MODE_NA)
1757 return;
1758
1759 if (sds == 5) pr_info("%s c %x\n", __func__, rtl930x_read_sds_phy(sds, 0x20, 18));
1760 // Enable LC and ring
1761 rtl9300_sds_field_w(lane_0, 0x20, 18, 3, 0, 0xf);
1762
1763 if (sds == lane_0)
1764 rtl9300_sds_field_w(lane_0, 0x20, 18, 5, 4, 0x1);
1765 else
1766 rtl9300_sds_field_w(lane_0, 0x20, 18, 7, 6, 0x1);
1767
1768 rtl9300_sds_field_w(sds, 0x20, 0, 5, 4, 0x3);
1769
1770 if (lc_on)
1771 rtl9300_sds_field_w(lane_0, 0x20, 18, 11, 8, lc_value);
1772 else
1773 rtl9300_sds_field_w(lane_0, 0x20, 18, 15, 12, lc_value);
1774
1775 // Force analog LC & ring on
1776 rtl9300_sds_field_w(lane_0, 0x21, 11, 3, 0, 0xf);
1777
1778 v = lc_on ? 0x3 : 0x1;
1779
1780 if (sds == lane_0)
1781 rtl9300_sds_field_w(lane_0, 0x20, 18, 5, 4, v);
1782 else
1783 rtl9300_sds_field_w(lane_0, 0x20, 18, 7, 6, v);
1784
1785 // Force SerDes mode
1786 rtl9300_sds_field_w(sds, 0x1f, 9, 6, 6, 1);
1787 rtl9300_sds_field_w(sds, 0x1f, 9, 11, 7, sds_mode);
1788
1789 // Toggle LC or Ring
1790 for (i = 0; i < 20; i++) {
1791 mdelay(200);
1792
1793 rtl930x_write_sds_phy(lane_0, 0x1f, 2, 53);
1794
1795 m_bit = (lane_0 == sds) ? (4) : (5);
1796 l_bit = (lane_0 == sds) ? (4) : (5);
1797
1798 cr_0 = rtl9300_sds_field_r(lane_0, 0x1f, 20, m_bit, l_bit);
1799 mdelay(10);
1800 cr_1 = rtl9300_sds_field_r(lane_0, 0x1f, 20, m_bit, l_bit);
1801 mdelay(10);
1802 cr_2 = rtl9300_sds_field_r(lane_0, 0x1f, 20, m_bit, l_bit);
1803
1804 if (cr_0 && cr_1 && cr_2) {
1805 u32 t;
1806 if (phy_if != PHY_INTERFACE_MODE_10GBASER)
1807 break;
1808
1809 t = rtl9300_sds_field_r(sds, 0x6, 0x1, 2, 2);
1810 rtl9300_sds_field_w(sds, 0x6, 0x1, 2, 2, 0x1);
1811
1812 // Reset FSM
1813 rtl9300_sds_field_w(sds, 0x6, 0x2, 12, 12, 0x1);
1814 mdelay(10);
1815 rtl9300_sds_field_w(sds, 0x6, 0x2, 12, 12, 0x0);
1816 mdelay(10);
1817
1818 // Need to read this twice
1819 v = rtl9300_sds_field_r(sds, 0x5, 0, 12, 12);
1820 v = rtl9300_sds_field_r(sds, 0x5, 0, 12, 12);
1821
1822 rtl9300_sds_field_w(sds, 0x6, 0x1, 2, 2, t);
1823
1824 // Reset FSM again
1825 rtl9300_sds_field_w(sds, 0x6, 0x2, 12, 12, 0x1);
1826 mdelay(10);
1827 rtl9300_sds_field_w(sds, 0x6, 0x2, 12, 12, 0x0);
1828 mdelay(10);
1829
1830 if (v == 1)
1831 break;
1832 }
1833
1834 m_bit = (phy_if == PHY_INTERFACE_MODE_10GBASER) ? 3 : 1;
1835 l_bit = (phy_if == PHY_INTERFACE_MODE_10GBASER) ? 2 : 0;
1836
1837 rtl9300_sds_field_w(lane_0, 0x21, 11, m_bit, l_bit, 0x2);
1838 mdelay(10);
1839 rtl9300_sds_field_w(lane_0, 0x21, 11, m_bit, l_bit, 0x3);
1840 }
1841
1842 rtl930x_sds_rx_rst(sds, phy_if);
1843
1844 // Re-enable power
1845 rtl9300_sds_field_w(sds, 0x20, 0, 7, 6, 0);
1846
1847 pr_info("%s --------------------- serdes %d forced to %x DONE\n", __func__, sds, sds_mode);
1848 }
1849
1850 void rtl9300_sds_tx_config(int sds, phy_interface_t phy_if)
1851 {
1852 // parameters: rtl9303_80G_txParam_s2
1853 int impedance = 0x8;
1854 int pre_amp = 0x2;
1855 int main_amp = 0x9;
1856 int post_amp = 0x2;
1857 int pre_en = 0x1;
1858 int post_en = 0x1;
1859 int page;
1860
1861 switch(phy_if) {
1862 case PHY_INTERFACE_MODE_1000BASEX:
1863 page = 0x25;
1864 break;
1865 case PHY_INTERFACE_MODE_HSGMII:
1866 case PHY_INTERFACE_MODE_2500BASEX:
1867 page = 0x29;
1868 break;
1869 case PHY_INTERFACE_MODE_10GBASER:
1870 page = 0x2f;
1871 break;
1872 default:
1873 pr_err("%s: unsupported PHY mode\n", __func__);
1874 return;
1875 }
1876
1877 rtl9300_sds_field_w(sds, page, 0x1, 15, 11, pre_amp);
1878 rtl9300_sds_field_w(sds, page, 0x7, 0, 0, pre_en);
1879 rtl9300_sds_field_w(sds, page, 0x7, 8, 4, main_amp);
1880 rtl9300_sds_field_w(sds, page, 0x6, 4, 0, post_amp);
1881 rtl9300_sds_field_w(sds, page, 0x7, 3, 3, post_en);
1882 rtl9300_sds_field_w(sds, page, 0x18, 15, 12, impedance);
1883 }
1884
1885 /*
1886 * Wait for clock ready, this assumes the SerDes is in XGMII mode
1887 * timeout is in ms
1888 */
1889 int rtl9300_sds_clock_wait(int timeout)
1890 {
1891 u32 v;
1892 unsigned long start = jiffies;
1893
1894 do {
1895 rtl9300_sds_field_w(2, 0x1f, 0x2, 15, 0, 53);
1896 v = rtl9300_sds_field_r(2, 0x1f, 20, 5, 4);
1897 if (v == 3)
1898 return 0;
1899 } while (jiffies < start + (HZ / 1000) * timeout);
1900
1901 return 1;
1902 }
1903
1904 void rtl9300_serdes_mac_link_config(int sds, bool tx_normal, bool rx_normal)
1905 {
1906 u32 v10, v1;
1907
1908 v10 = rtl930x_read_sds_phy(sds, 6, 2); // 10GBit, page 6, reg 2
1909 v1 = rtl930x_read_sds_phy(sds, 0, 0); // 1GBit, page 0, reg 0
1910 pr_info("%s: registers before %08x %08x\n", __func__, v10, v1);
1911
1912 v10 &= ~(BIT(13) | BIT(14));
1913 v1 &= ~(BIT(8) | BIT(9));
1914
1915 v10 |= rx_normal ? 0 : BIT(13);
1916 v1 |= rx_normal ? 0 : BIT(9);
1917
1918 v10 |= tx_normal ? 0 : BIT(14);
1919 v1 |= tx_normal ? 0 : BIT(8);
1920
1921 rtl930x_write_sds_phy(sds, 6, 2, v10);
1922 rtl930x_write_sds_phy(sds, 0, 0, v1);
1923
1924 v10 = rtl930x_read_sds_phy(sds, 6, 2);
1925 v1 = rtl930x_read_sds_phy(sds, 0, 0);
1926 pr_info("%s: registers after %08x %08x\n", __func__, v10, v1);
1927 }
1928
1929 void rtl9300_sds_rxcal_dcvs_manual(u32 sds_num, u32 dcvs_id, bool manual, u32 dvcs_list[])
1930 {
1931 if (manual) {
1932 switch(dcvs_id) {
1933 case 0:
1934 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 14, 14, 0x1);
1935 rtl9300_sds_field_w(sds_num, 0x2f, 0x03, 5, 5, dvcs_list[0]);
1936 rtl9300_sds_field_w(sds_num, 0x2f, 0x03, 4, 0, dvcs_list[1]);
1937 break;
1938 case 1:
1939 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 13, 13, 0x1);
1940 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 15, 15, dvcs_list[0]);
1941 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 14, 11, dvcs_list[1]);
1942 break;
1943 case 2:
1944 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 12, 12, 0x1);
1945 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 10, 10, dvcs_list[0]);
1946 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 9, 6, dvcs_list[1]);
1947 break;
1948 case 3:
1949 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 11, 11, 0x1);
1950 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 5, 5, dvcs_list[0]);
1951 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 4, 1, dvcs_list[1]);
1952 break;
1953 case 4:
1954 rtl9300_sds_field_w(sds_num, 0x2e, 0x01, 15, 15, 0x1);
1955 rtl9300_sds_field_w(sds_num, 0x2e, 0x11, 10, 10, dvcs_list[0]);
1956 rtl9300_sds_field_w(sds_num, 0x2e, 0x11, 9, 6, dvcs_list[1]);
1957 break;
1958 case 5:
1959 rtl9300_sds_field_w(sds_num, 0x2e, 0x02, 11, 11, 0x1);
1960 rtl9300_sds_field_w(sds_num, 0x2e, 0x11, 4, 4, dvcs_list[0]);
1961 rtl9300_sds_field_w(sds_num, 0x2e, 0x11, 3, 0, dvcs_list[1]);
1962 break;
1963 default:
1964 break;
1965 }
1966 } else {
1967 switch(dcvs_id) {
1968 case 0:
1969 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 14, 14, 0x0);
1970 break;
1971 case 1:
1972 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 13, 13, 0x0);
1973 break;
1974 case 2:
1975 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 12, 12, 0x0);
1976 break;
1977 case 3:
1978 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 11, 11, 0x0);
1979 break;
1980 case 4:
1981 rtl9300_sds_field_w(sds_num, 0x2e, 0x01, 15, 15, 0x0);
1982 break;
1983 case 5:
1984 rtl9300_sds_field_w(sds_num, 0x2e, 0x02, 11, 11, 0x0);
1985 break;
1986 default:
1987 break;
1988 }
1989 mdelay(1);
1990 }
1991 }
1992
1993 void rtl9300_sds_rxcal_dcvs_get(u32 sds_num, u32 dcvs_id, u32 dcvs_list[])
1994 {
1995 u32 dcvs_sign_out = 0, dcvs_coef_bin = 0;
1996 bool dcvs_manual;
1997
1998 if (!(sds_num % 2))
1999 rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
2000 else
2001 rtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31);
2002
2003 // ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1]
2004 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
2005
2006 // ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x]
2007 rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x20);
2008
2009 switch(dcvs_id) {
2010 case 0:
2011 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x22);
2012 mdelay(1);
2013
2014 // ##DCVS0 Read Out
2015 dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2016 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2017 dcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 14, 14);
2018 break;
2019
2020 case 1:
2021 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x23);
2022 mdelay(1);
2023
2024 // ##DCVS0 Read Out
2025 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2026 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2027 dcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 13, 13);
2028 break;
2029
2030 case 2:
2031 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x24);
2032 mdelay(1);
2033
2034 // ##DCVS0 Read Out
2035 dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2036 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2037 dcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 12, 12);
2038 break;
2039 case 3:
2040 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x25);
2041 mdelay(1);
2042
2043 // ##DCVS0 Read Out
2044 dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2045 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2046 dcvs_manual = rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 11, 11);
2047 break;
2048
2049 case 4:
2050 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x2c);
2051 mdelay(1);
2052
2053 // ##DCVS0 Read Out
2054 dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2055 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2056 dcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x01, 15, 15);
2057 break;
2058
2059 case 5:
2060 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x2d);
2061 mdelay(1);
2062
2063 // ##DCVS0 Read Out
2064 dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2065 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2066 dcvs_manual = rtl9300_sds_field_r(sds_num, 0x2e, 0x02, 11, 11);
2067 break;
2068
2069 default:
2070 break;
2071 }
2072
2073 if (dcvs_sign_out)
2074 pr_info("%s DCVS %u Sign: -", __func__, dcvs_id);
2075 else
2076 pr_info("%s DCVS %u Sign: +", __func__, dcvs_id);
2077
2078 pr_info("DCVS %u even coefficient = %u", dcvs_id, dcvs_coef_bin);
2079 pr_info("DCVS %u manual = %u", dcvs_id, dcvs_manual);
2080
2081 dcvs_list[0] = dcvs_sign_out;
2082 dcvs_list[1] = dcvs_coef_bin;
2083 }
2084
2085 void rtl9300_sds_rxcal_leq_manual(u32 sds_num, bool manual, u32 leq_gray)
2086 {
2087 if (manual) {
2088 rtl9300_sds_field_w(sds_num, 0x2e, 0x18, 15, 15, 0x1);
2089 rtl9300_sds_field_w(sds_num, 0x2e, 0x16, 14, 10, leq_gray);
2090 } else {
2091 rtl9300_sds_field_w(sds_num, 0x2e, 0x18, 15, 15, 0x0);
2092 mdelay(100);
2093 }
2094 }
2095
2096 void rtl9300_sds_rxcal_leq_offset_manual(u32 sds_num, bool manual, u32 offset)
2097 {
2098 if (manual) {
2099 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 6, 2, offset);
2100 } else {
2101 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 6, 2, offset);
2102 mdelay(1);
2103 }
2104 }
2105
2106 #define GRAY_BITS 5
2107 u32 rtl9300_sds_rxcal_gray_to_binary(u32 gray_code)
2108 {
2109 int i, j, m;
2110 u32 g[GRAY_BITS];
2111 u32 c[GRAY_BITS];
2112 u32 leq_binary = 0;
2113
2114 for(i = 0; i < GRAY_BITS; i++)
2115 g[i] = (gray_code & BIT(i)) >> i;
2116
2117 m = GRAY_BITS - 1;
2118
2119 c[m] = g[m];
2120
2121 for(i = 0; i < m; i++) {
2122 c[i] = g[i];
2123 for(j = i + 1; j < GRAY_BITS; j++)
2124 c[i] = c[i] ^ g[j];
2125 }
2126
2127 for(i = 0; i < GRAY_BITS; i++)
2128 leq_binary += c[i] << i;
2129
2130 return leq_binary;
2131 }
2132
2133 u32 rtl9300_sds_rxcal_leq_read(int sds_num)
2134 {
2135 u32 leq_gray, leq_bin;
2136 bool leq_manual;
2137
2138 if (!(sds_num % 2))
2139 rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
2140 else
2141 rtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31);
2142
2143 // ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1]
2144 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
2145
2146 // ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[0 1 x x x x]
2147 rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x10);
2148 mdelay(1);
2149
2150 // ##LEQ Read Out
2151 leq_gray = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 7, 3);
2152 leq_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x18, 15, 15);
2153 leq_bin = rtl9300_sds_rxcal_gray_to_binary(leq_gray);
2154
2155 pr_info("LEQ_gray: %u, LEQ_bin: %u", leq_gray, leq_bin);
2156 pr_info("LEQ manual: %u", leq_manual);
2157
2158 return leq_bin;
2159 }
2160
2161 void rtl9300_sds_rxcal_vth_manual(u32 sds_num, bool manual, u32 vth_list[])
2162 {
2163 if (manual) {
2164 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, 13, 13, 0x1);
2165 rtl9300_sds_field_w(sds_num, 0x2e, 0x13, 5, 3, vth_list[0]);
2166 rtl9300_sds_field_w(sds_num, 0x2e, 0x13, 2, 0, vth_list[1]);
2167 } else {
2168 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, 13, 13, 0x0);
2169 mdelay(10);
2170 }
2171 }
2172
2173 void rtl9300_sds_rxcal_vth_get(u32 sds_num, u32 vth_list[])
2174 {
2175 u32 vth_manual;
2176
2177 //##Page0x1F, Reg0x02[15 0], REG_DBGO_SEL=[0x002F]; //Lane0
2178 //##Page0x1F, Reg0x02[15 0], REG_DBGO_SEL=[0x0031]; //Lane1
2179 if (!(sds_num % 2))
2180 rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
2181 else
2182 rtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31);
2183
2184 //##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1]
2185 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
2186 //##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x]
2187 rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x20);
2188 //##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 1 1 0 0]
2189 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0xc);
2190
2191 mdelay(1);
2192
2193 //##VthP & VthN Read Out
2194 vth_list[0] = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 2, 0); // v_thp set bin
2195 vth_list[1] = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 3); // v_thn set bin
2196
2197 pr_info("vth_set_bin = %d", vth_list[0]);
2198 pr_info("vth_set_bin = %d", vth_list[1]);
2199
2200 vth_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x0f, 13, 13);
2201 pr_info("Vth Maunal = %d", vth_manual);
2202 }
2203
2204 void rtl9300_sds_rxcal_tap_manual(u32 sds_num, int tap_id, bool manual, u32 tap_list[])
2205 {
2206 if (manual) {
2207 switch(tap_id) {
2208 case 0:
2209 //##REG0_LOAD_IN_INIT[0]=1; REG0_TAP0_INIT[5:0]=Tap0_Value
2210 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);
2211 rtl9300_sds_field_w(sds_num, 0x2f, 0x03, 5, 5, tap_list[0]);
2212 rtl9300_sds_field_w(sds_num, 0x2f, 0x03, 4, 0, tap_list[1]);
2213 break;
2214 case 1:
2215 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);
2216 rtl9300_sds_field_w(sds_num, 0x21, 0x07, 6, 6, tap_list[0]);
2217 rtl9300_sds_field_w(sds_num, 0x2e, 0x09, 11, 6, tap_list[1]);
2218 rtl9300_sds_field_w(sds_num, 0x21, 0x07, 5, 5, tap_list[2]);
2219 rtl9300_sds_field_w(sds_num, 0x2f, 0x12, 5, 0, tap_list[3]);
2220 break;
2221 case 2:
2222 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);
2223 rtl9300_sds_field_w(sds_num, 0x2e, 0x09, 5, 5, tap_list[0]);
2224 rtl9300_sds_field_w(sds_num, 0x2e, 0x09, 4, 0, tap_list[1]);
2225 rtl9300_sds_field_w(sds_num, 0x2e, 0x0a, 11, 11, tap_list[2]);
2226 rtl9300_sds_field_w(sds_num, 0x2e, 0x0a, 10, 6, tap_list[3]);
2227 break;
2228 case 3:
2229 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);
2230 rtl9300_sds_field_w(sds_num, 0x2e, 0x0a, 5, 5, tap_list[0]);
2231 rtl9300_sds_field_w(sds_num, 0x2e, 0x0a, 4, 0, tap_list[1]);
2232 rtl9300_sds_field_w(sds_num, 0x2e, 0x06, 5, 5, tap_list[2]);
2233 rtl9300_sds_field_w(sds_num, 0x2e, 0x06, 4, 0, tap_list[3]);
2234 break;
2235 case 4:
2236 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);
2237 rtl9300_sds_field_w(sds_num, 0x2f, 0x01, 5, 5, tap_list[0]);
2238 rtl9300_sds_field_w(sds_num, 0x2f, 0x01, 4, 0, tap_list[1]);
2239 rtl9300_sds_field_w(sds_num, 0x2e, 0x06, 11, 11, tap_list[2]);
2240 rtl9300_sds_field_w(sds_num, 0x2e, 0x06, 10, 6, tap_list[3]);
2241 break;
2242 default:
2243 break;
2244 }
2245 } else {
2246 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x0);
2247 mdelay(10);
2248 }
2249 }
2250
2251 void rtl9300_sds_rxcal_tap_get(u32 sds_num, u32 tap_id, u32 tap_list[])
2252 {
2253 u32 tap0_sign_out;
2254 u32 tap0_coef_bin;
2255 u32 tap_sign_out_even;
2256 u32 tap_coef_bin_even;
2257 u32 tap_sign_out_odd;
2258 u32 tap_coef_bin_odd;
2259 bool tap_manual;
2260
2261 if (!(sds_num % 2))
2262 rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
2263 else
2264 rtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31);
2265
2266 //##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1]
2267 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
2268 //##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x]
2269 rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x20);
2270
2271 if (!tap_id) {
2272 //##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 0 0 0 1]
2273 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0);
2274 //##Tap1 Even Read Out
2275 mdelay(1);
2276 tap0_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 5);
2277 tap0_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 0);
2278
2279 if (tap0_sign_out == 1)
2280 pr_info("Tap0 Sign : -");
2281 else
2282 pr_info("Tap0 Sign : +");
2283
2284 pr_info("tap0_coef_bin = %d", tap0_coef_bin);
2285
2286 tap_list[0] = tap0_sign_out;
2287 tap_list[1] = tap0_coef_bin;
2288
2289 tap_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x0f, 7, 7);
2290 pr_info("tap0 manual = %u",tap_manual);
2291 } else {
2292 //##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 0 0 0 1]
2293 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, tap_id);
2294 mdelay(1);
2295 //##Tap1 Even Read Out
2296 tap_sign_out_even = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 5);
2297 tap_coef_bin_even = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 0);
2298
2299 //##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 0 1 1 0]
2300 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, (tap_id + 5));
2301 //##Tap1 Odd Read Out
2302 tap_sign_out_odd = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 5);
2303 tap_coef_bin_odd = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 0);
2304
2305 if (tap_sign_out_even == 1)
2306 pr_info("Tap %u even sign: -", tap_id);
2307 else
2308 pr_info("Tap %u even sign: +", tap_id);
2309
2310 pr_info("Tap %u even coefficient = %u", tap_id, tap_coef_bin_even);
2311
2312 if (tap_sign_out_odd == 1)
2313 pr_info("Tap %u odd sign: -", tap_id);
2314 else
2315 pr_info("Tap %u odd sign: +", tap_id);
2316
2317 pr_info("Tap %u odd coefficient = %u", tap_id,tap_coef_bin_odd);
2318
2319 tap_list[0] = tap_sign_out_even;
2320 tap_list[1] = tap_coef_bin_even;
2321 tap_list[2] = tap_sign_out_odd;
2322 tap_list[3] = tap_coef_bin_odd;
2323
2324 tap_manual = rtl9300_sds_field_r(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7);
2325 pr_info("tap %u manual = %d",tap_id, tap_manual);
2326 }
2327 }
2328
2329 void rtl9300_do_rx_calibration_1(int sds, phy_interface_t phy_mode)
2330 {
2331 // From both rtl9300_rxCaliConf_serdes_myParam and rtl9300_rxCaliConf_phy_myParam
2332 int tap0_init_val = 0x1f; // Initial Decision Fed Equalizer 0 tap
2333 int vth_min = 0x0;
2334
2335 pr_info("start_1.1.1 initial value for sds %d\n", sds);
2336 rtl930x_write_sds_phy(sds, 6, 0, 0);
2337
2338 // FGCAL
2339 rtl9300_sds_field_w(sds, 0x2e, 0x01, 14, 14, 0x0);
2340 rtl9300_sds_field_w(sds, 0x2e, 0x1c, 10, 5, 0x20);
2341 rtl9300_sds_field_w(sds, 0x2f, 0x02, 0, 0, 0x1);
2342
2343 // DCVS
2344 rtl9300_sds_field_w(sds, 0x2e, 0x1e, 14, 11, 0x0);
2345 rtl9300_sds_field_w(sds, 0x2e, 0x01, 15, 15, 0x0);
2346 rtl9300_sds_field_w(sds, 0x2e, 0x02, 11, 11, 0x0);
2347 rtl9300_sds_field_w(sds, 0x2e, 0x1c, 4, 0, 0x0);
2348 rtl9300_sds_field_w(sds, 0x2e, 0x1d, 15, 11, 0x0);
2349 rtl9300_sds_field_w(sds, 0x2e, 0x1d, 10, 6, 0x0);
2350 rtl9300_sds_field_w(sds, 0x2e, 0x1d, 5, 1, 0x0);
2351 rtl9300_sds_field_w(sds, 0x2e, 0x02, 10, 6, 0x0);
2352 rtl9300_sds_field_w(sds, 0x2e, 0x11, 4, 0, 0x0);
2353 rtl9300_sds_field_w(sds, 0x2f, 0x00, 3, 0, 0xf);
2354 rtl9300_sds_field_w(sds, 0x2e, 0x04, 6, 6, 0x1);
2355 rtl9300_sds_field_w(sds, 0x2e, 0x04, 7, 7, 0x1);
2356
2357 // LEQ (Long Term Equivalent signal level)
2358 rtl9300_sds_field_w(sds, 0x2e, 0x16, 14, 8, 0x0);
2359
2360 // DFE (Decision Fed Equalizer)
2361 rtl9300_sds_field_w(sds, 0x2f, 0x03, 5, 0, tap0_init_val);
2362 rtl9300_sds_field_w(sds, 0x2e, 0x09, 11, 6, 0x0);
2363 rtl9300_sds_field_w(sds, 0x2e, 0x09, 5, 0, 0x0);
2364 rtl9300_sds_field_w(sds, 0x2e, 0x0a, 5, 0, 0x0);
2365 rtl9300_sds_field_w(sds, 0x2f, 0x01, 5, 0, 0x0);
2366 rtl9300_sds_field_w(sds, 0x2f, 0x12, 5, 0, 0x0);
2367 rtl9300_sds_field_w(sds, 0x2e, 0x0a, 11, 6, 0x0);
2368 rtl9300_sds_field_w(sds, 0x2e, 0x06, 5, 0, 0x0);
2369 rtl9300_sds_field_w(sds, 0x2f, 0x01, 5, 0, 0x0);
2370
2371 // Vth
2372 rtl9300_sds_field_w(sds, 0x2e, 0x13, 5, 3, 0x7);
2373 rtl9300_sds_field_w(sds, 0x2e, 0x13, 2, 0, 0x7);
2374 rtl9300_sds_field_w(sds, 0x2f, 0x0b, 5, 3, vth_min);
2375
2376 pr_info("end_1.1.1 --\n");
2377
2378 pr_info("start_1.1.2 Load DFE init. value\n");
2379
2380 rtl9300_sds_field_w(sds, 0x2e, 0x0f, 13, 7, 0x7f);
2381
2382 pr_info("end_1.1.2\n");
2383
2384 pr_info("start_1.1.3 disable LEQ training,enable DFE clock\n");
2385
2386 rtl9300_sds_field_w(sds, 0x2e, 0x17, 7, 7, 0x0);
2387 rtl9300_sds_field_w(sds, 0x2e, 0x17, 6, 2, 0x0);
2388 rtl9300_sds_field_w(sds, 0x2e, 0x0c, 8, 8, 0x0);
2389 rtl9300_sds_field_w(sds, 0x2e, 0x0b, 4, 4, 0x1);
2390 rtl9300_sds_field_w(sds, 0x2e, 0x12, 14, 14, 0x0);
2391 rtl9300_sds_field_w(sds, 0x2f, 0x02, 15, 15, 0x0);
2392
2393 pr_info("end_1.1.3 --\n");
2394
2395 pr_info("start_1.1.4 offset cali setting\n");
2396
2397 rtl9300_sds_field_w(sds, 0x2e, 0x0f, 15, 14, 0x3);
2398
2399 pr_info("end_1.1.4\n");
2400
2401 pr_info("start_1.1.5 LEQ and DFE setting\n");
2402
2403 // TODO: make this work for DAC cables of different lengths
2404 // For a 10GBit serdes wit Fibre, SDS 8 or 9
2405 if (phy_mode == PHY_INTERFACE_MODE_10GBASER || PHY_INTERFACE_MODE_1000BASEX)
2406 rtl9300_sds_field_w(sds, 0x2e, 0x16, 3, 2, 0x2);
2407 else
2408 pr_err("%s not PHY-based or SerDes, implement DAC!\n", __func__);
2409
2410 // No serdes, check for Aquantia PHYs
2411 rtl9300_sds_field_w(sds, 0x2e, 0x16, 3, 2, 0x2);
2412
2413 rtl9300_sds_field_w(sds, 0x2e, 0x0f, 6, 0, 0x5f);
2414 rtl9300_sds_field_w(sds, 0x2f, 0x05, 7, 2, 0x1f);
2415 rtl9300_sds_field_w(sds, 0x2e, 0x19, 9, 5, 0x1f);
2416 rtl9300_sds_field_w(sds, 0x2f, 0x0b, 15, 9, 0x3c);
2417 rtl9300_sds_field_w(sds, 0x2e, 0x0b, 1, 0, 0x3);
2418
2419 pr_info("end_1.1.5\n");
2420 }
2421
2422 void rtl9300_do_rx_calibration_2_1(u32 sds_num)
2423 {
2424 pr_info("start_1.2.1 ForegroundOffsetCal_Manual\n");
2425
2426 // Gray config endis to 1
2427 rtl9300_sds_field_w(sds_num, 0x2f, 0x02, 2, 2, 0x1);
2428
2429 // ForegroundOffsetCal_Manual(auto mode)
2430 rtl9300_sds_field_w(sds_num, 0x2e, 0x01, 14, 14, 0x0);
2431
2432 pr_info("end_1.2.1");
2433 }
2434
2435 void rtl9300_do_rx_calibration_2_2(int sds_num)
2436 {
2437 //Force Rx-Run = 0
2438 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 8, 8, 0x0);
2439
2440 rtl930x_sds_rx_rst(sds_num, PHY_INTERFACE_MODE_10GBASER);
2441 }
2442
2443 void rtl9300_do_rx_calibration_2_3(int sds_num)
2444 {
2445 u32 fgcal_binary, fgcal_gray;
2446 u32 offset_range;
2447
2448 pr_info("start_1.2.3 Foreground Calibration\n");
2449
2450 while(1) {
2451 if (!(sds_num % 2))
2452 rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
2453 else
2454 rtl930x_write_sds_phy(sds_num -1 , 0x1f, 0x2, 0x31);
2455
2456 // ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1]
2457 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
2458 // ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x]
2459 rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x20);
2460 // ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 1 1 1 1]
2461 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0xf);
2462 // ##FGCAL read gray
2463 fgcal_gray = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 0);
2464 // ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 1 1 1 0]
2465 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0xe);
2466 // ##FGCAL read binary
2467 fgcal_binary = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 0);
2468
2469 pr_info("%s: fgcal_gray: %d, fgcal_binary %d\n",
2470 __func__, fgcal_gray, fgcal_binary);
2471
2472 offset_range = rtl9300_sds_field_r(sds_num, 0x2e, 0x15, 15, 14);
2473
2474 if (fgcal_binary > 60 || fgcal_binary < 3) {
2475 if (offset_range == 3) {
2476 pr_info("%s: Foreground Calibration result marginal!", __func__);
2477 break;
2478 } else {
2479 offset_range++;
2480 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 15, 14, offset_range);
2481 rtl9300_do_rx_calibration_2_2(sds_num);
2482 }
2483 } else {
2484 break;
2485 }
2486 }
2487 pr_info("%s: end_1.2.3\n", __func__);
2488 }
2489
2490 void rtl9300_do_rx_calibration_2(int sds)
2491 {
2492 rtl930x_sds_rx_rst(sds, PHY_INTERFACE_MODE_10GBASER);
2493 rtl9300_do_rx_calibration_2_1(sds);
2494 rtl9300_do_rx_calibration_2_2(sds);
2495 rtl9300_do_rx_calibration_2_3(sds);
2496 }
2497
2498 void rtl9300_sds_rxcal_3_1(int sds_num, phy_interface_t phy_mode)
2499 {
2500 pr_info("start_1.3.1");
2501
2502 // ##1.3.1
2503 if (phy_mode != PHY_INTERFACE_MODE_10GBASER && phy_mode != PHY_INTERFACE_MODE_1000BASEX)
2504 rtl9300_sds_field_w(sds_num, 0x2e, 0xc, 8, 8, 0);
2505
2506 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 7, 7, 0x0);
2507 rtl9300_sds_rxcal_leq_manual(sds_num, false, 0);
2508
2509 pr_info("end_1.3.1");
2510 }
2511
2512 void rtl9300_sds_rxcal_3_2(int sds_num, phy_interface_t phy_mode)
2513 {
2514 u32 sum10 = 0, avg10, int10;
2515 int dac_long_cable_offset;
2516 bool eq_hold_enabled;
2517 int i;
2518
2519 if (phy_mode == PHY_INTERFACE_MODE_10GBASER || phy_mode == PHY_INTERFACE_MODE_1000BASEX) {
2520 // rtl9300_rxCaliConf_serdes_myParam
2521 dac_long_cable_offset = 3;
2522 eq_hold_enabled = true;
2523 } else {
2524 // rtl9300_rxCaliConf_phy_myParam
2525 dac_long_cable_offset = 0;
2526 eq_hold_enabled = false;
2527 }
2528
2529 if (phy_mode == PHY_INTERFACE_MODE_1000BASEX)
2530 pr_warn("%s: LEQ only valid for 10GR!\n", __func__);
2531
2532 pr_info("start_1.3.2");
2533
2534 for(i = 0; i < 10; i++) {
2535 sum10 += rtl9300_sds_rxcal_leq_read(sds_num);
2536 mdelay(10);
2537 }
2538
2539 avg10 = (sum10 / 10) + (((sum10 % 10) >= 5) ? 1 : 0);
2540 int10 = sum10 / 10;
2541
2542 pr_info("sum10:%u, avg10:%u, int10:%u", sum10, avg10, int10);
2543
2544 if (phy_mode == PHY_INTERFACE_MODE_10GBASER || phy_mode == PHY_INTERFACE_MODE_1000BASEX) {
2545 if (dac_long_cable_offset) {
2546 rtl9300_sds_rxcal_leq_offset_manual(sds_num, 1, dac_long_cable_offset);
2547 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 7, 7, eq_hold_enabled);
2548 if (phy_mode == PHY_INTERFACE_MODE_10GBASER)
2549 rtl9300_sds_rxcal_leq_manual(sds_num, true, avg10);
2550 } else {
2551 if (sum10 >= 5) {
2552 rtl9300_sds_rxcal_leq_offset_manual(sds_num, 1, 3);
2553 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 7, 7, 0x1);
2554 if (phy_mode == PHY_INTERFACE_MODE_10GBASER)
2555 rtl9300_sds_rxcal_leq_manual(sds_num, true, avg10);
2556 } else {
2557 rtl9300_sds_rxcal_leq_offset_manual(sds_num, 1, 0);
2558 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 7, 7, 0x1);
2559 if (phy_mode == PHY_INTERFACE_MODE_10GBASER)
2560 rtl9300_sds_rxcal_leq_manual(sds_num, true, avg10);
2561 }
2562 }
2563 }
2564
2565 pr_info("Sds:%u LEQ = %u",sds_num, rtl9300_sds_rxcal_leq_read(sds_num));
2566
2567 pr_info("end_1.3.2");
2568 }
2569
2570 void rtl9300_do_rx_calibration_3(int sds_num, phy_interface_t phy_mode)
2571 {
2572 rtl9300_sds_rxcal_3_1(sds_num, phy_mode);
2573
2574 if (phy_mode == PHY_INTERFACE_MODE_10GBASER || phy_mode == PHY_INTERFACE_MODE_1000BASEX)
2575 rtl9300_sds_rxcal_3_2(sds_num, phy_mode);
2576 }
2577
2578 void rtl9300_do_rx_calibration_4_1(int sds_num)
2579 {
2580 u32 vth_list[2] = {0, 0};
2581 u32 tap0_list[4] = {0, 0, 0, 0};
2582
2583 pr_info("start_1.4.1");
2584
2585 // ##1.4.1
2586 rtl9300_sds_rxcal_vth_manual(sds_num, false, vth_list);
2587 rtl9300_sds_rxcal_tap_manual(sds_num, 0, false, tap0_list);
2588 mdelay(200);
2589
2590 pr_info("end_1.4.1");
2591 }
2592
2593 void rtl9300_do_rx_calibration_4_2(u32 sds_num)
2594 {
2595 u32 vth_list[2];
2596 u32 tap_list[4];
2597
2598 pr_info("start_1.4.2");
2599
2600 rtl9300_sds_rxcal_vth_get(sds_num, vth_list);
2601 rtl9300_sds_rxcal_vth_manual(sds_num, true, vth_list);
2602
2603 mdelay(100);
2604
2605 rtl9300_sds_rxcal_tap_get(sds_num, 0, tap_list);
2606 rtl9300_sds_rxcal_tap_manual(sds_num, 0, true, tap_list);
2607
2608 pr_info("end_1.4.2");
2609 }
2610
2611 void rtl9300_do_rx_calibration_4(u32 sds_num)
2612 {
2613 rtl9300_do_rx_calibration_4_1(sds_num);
2614 rtl9300_do_rx_calibration_4_2(sds_num);
2615 }
2616
2617 void rtl9300_do_rx_calibration_5_2(u32 sds_num)
2618 {
2619 u32 tap1_list[4] = {0};
2620 u32 tap2_list[4] = {0};
2621 u32 tap3_list[4] = {0};
2622 u32 tap4_list[4] = {0};
2623
2624 pr_info("start_1.5.2");
2625
2626 rtl9300_sds_rxcal_tap_manual(sds_num, 1, false, tap1_list);
2627 rtl9300_sds_rxcal_tap_manual(sds_num, 2, false, tap2_list);
2628 rtl9300_sds_rxcal_tap_manual(sds_num, 3, false, tap3_list);
2629 rtl9300_sds_rxcal_tap_manual(sds_num, 4, false, tap4_list);
2630
2631 mdelay(30);
2632
2633 pr_info("end_1.5.2");
2634 }
2635
2636 void rtl9300_do_rx_calibration_5(u32 sds_num, phy_interface_t phy_mode)
2637 {
2638 if (phy_mode == PHY_INTERFACE_MODE_10GBASER) // dfeTap1_4Enable true
2639 rtl9300_do_rx_calibration_5_2(sds_num);
2640 }
2641
2642
2643 void rtl9300_do_rx_calibration_dfe_disable(u32 sds_num)
2644 {
2645 u32 tap1_list[4] = {0};
2646 u32 tap2_list[4] = {0};
2647 u32 tap3_list[4] = {0};
2648 u32 tap4_list[4] = {0};
2649
2650 rtl9300_sds_rxcal_tap_manual(sds_num, 1, true, tap1_list);
2651 rtl9300_sds_rxcal_tap_manual(sds_num, 2, true, tap2_list);
2652 rtl9300_sds_rxcal_tap_manual(sds_num, 3, true, tap3_list);
2653 rtl9300_sds_rxcal_tap_manual(sds_num, 4, true, tap4_list);
2654
2655 mdelay(10);
2656 }
2657
2658 void rtl9300_do_rx_calibration(int sds, phy_interface_t phy_mode)
2659 {
2660 u32 latch_sts;
2661
2662 rtl9300_do_rx_calibration_1(sds, phy_mode);
2663 rtl9300_do_rx_calibration_2(sds);
2664 rtl9300_do_rx_calibration_4(sds);
2665 rtl9300_do_rx_calibration_5(sds, phy_mode);
2666 mdelay(20);
2667
2668 // Do this only for 10GR mode, SDS active in mode 0x1a
2669 if (rtl9300_sds_field_r(sds, 0x1f, 9, 11, 7) == 0x1a) {
2670 pr_info("%s: SDS enabled\n", __func__);
2671 latch_sts = rtl9300_sds_field_r(sds, 0x4, 1, 2, 2);
2672 mdelay(1);
2673 latch_sts = rtl9300_sds_field_r(sds, 0x4, 1, 2, 2);
2674 if (latch_sts) {
2675 rtl9300_do_rx_calibration_dfe_disable(sds);
2676 rtl9300_do_rx_calibration_4(sds);
2677 rtl9300_do_rx_calibration_5(sds, phy_mode);
2678 }
2679 }
2680 }
2681
2682 int rtl9300_sds_sym_err_reset(int sds_num, phy_interface_t phy_mode)
2683 {
2684 switch (phy_mode) {
2685 case PHY_INTERFACE_MODE_XGMII:
2686 break;
2687
2688 case PHY_INTERFACE_MODE_10GBASER:
2689 // Read twice to clear
2690 rtl930x_read_sds_phy(sds_num, 5, 1);
2691 rtl930x_read_sds_phy(sds_num, 5, 1);
2692 break;
2693
2694 case PHY_INTERFACE_MODE_1000BASEX:
2695 rtl9300_sds_field_w(sds_num, 0x1, 24, 2, 0, 0);
2696 rtl9300_sds_field_w(sds_num, 0x1, 3, 15, 8, 0);
2697 rtl9300_sds_field_w(sds_num, 0x1, 2, 15, 0, 0);
2698 break;
2699
2700 default:
2701 pr_info("%s unsupported phy mode\n", __func__);
2702 return -1;
2703 }
2704
2705 return 0;
2706 }
2707
2708 u32 rtl9300_sds_sym_err_get(int sds_num, phy_interface_t phy_mode)
2709 {
2710 u32 v = 0;
2711
2712 switch (phy_mode) {
2713 case PHY_INTERFACE_MODE_XGMII:
2714 break;
2715
2716 case PHY_INTERFACE_MODE_10GBASER:
2717 v = rtl930x_read_sds_phy(sds_num, 5, 1);
2718 return v & 0xff;
2719
2720 default:
2721 pr_info("%s unsupported PHY-mode\n", __func__);
2722 }
2723
2724 return v;
2725 }
2726
2727 int rtl9300_sds_check_calibration(int sds_num, phy_interface_t phy_mode)
2728 {
2729 u32 errors1, errors2;
2730
2731 rtl9300_sds_sym_err_reset(sds_num, phy_mode);
2732 rtl9300_sds_sym_err_reset(sds_num, phy_mode);
2733
2734 // Count errors during 1ms
2735 errors1 = rtl9300_sds_sym_err_get(sds_num, phy_mode);
2736 mdelay(1);
2737 errors2 = rtl9300_sds_sym_err_get(sds_num, phy_mode);
2738
2739 switch (phy_mode) {
2740 case PHY_INTERFACE_MODE_XGMII:
2741
2742 if ((errors2 - errors1 > 100)
2743 || (errors1 >= 0xffff00) || (errors2 >= 0xffff00)) {
2744 pr_info("%s XSGMII error rate too high\n", __func__);
2745 return 1;
2746 }
2747 break;
2748 case PHY_INTERFACE_MODE_10GBASER:
2749 if (errors2 > 0) {
2750 pr_info("%s 10GBASER error rate too high\n", __func__);
2751 return 1;
2752 }
2753 break;
2754 default:
2755 return 1;
2756 }
2757 return 0;
2758 }
2759
2760 void rtl9300_phy_enable_10g_1g(int sds_num)
2761 {
2762 u32 v;
2763
2764 // Enable 1GBit PHY
2765 v = rtl930x_read_sds_phy(sds_num, PHY_PAGE_2, PHY_CTRL_REG);
2766 pr_info("%s 1gbit phy: %08x\n", __func__, v);
2767 v &= ~BIT(PHY_POWER_BIT);
2768 rtl930x_write_sds_phy(sds_num, PHY_PAGE_2, PHY_CTRL_REG, v);
2769 pr_info("%s 1gbit phy enabled: %08x\n", __func__, v);
2770
2771 // Enable 10GBit PHY
2772 v = rtl930x_read_sds_phy(sds_num, PHY_PAGE_4, PHY_CTRL_REG);
2773 pr_info("%s 10gbit phy: %08x\n", __func__, v);
2774 v &= ~BIT(PHY_POWER_BIT);
2775 rtl930x_write_sds_phy(sds_num, PHY_PAGE_4, PHY_CTRL_REG, v);
2776 pr_info("%s 10gbit phy after: %08x\n", __func__, v);
2777
2778 // dal_longan_construct_mac_default_10gmedia_fiber
2779 v = rtl930x_read_sds_phy(sds_num, 0x1f, 11);
2780 pr_info("%s set medium: %08x\n", __func__, v);
2781 v |= BIT(1);
2782 rtl930x_write_sds_phy(sds_num, 0x1f, 11, v);
2783 pr_info("%s set medium after: %08x\n", __func__, v);
2784 }
2785
2786 #define RTL930X_MAC_FORCE_MODE_CTRL (0xCA1C)
2787 // phy_mode = PHY_INTERFACE_MODE_10GBASER, sds_mode = 0x1a
2788 int rtl9300_serdes_setup(int sds_num, phy_interface_t phy_mode)
2789 {
2790 int sds_mode;
2791 int calib_tries = 0;
2792
2793 switch (phy_mode) {
2794 case PHY_INTERFACE_MODE_HSGMII:
2795 sds_mode = 0x12;
2796 break;
2797 case PHY_INTERFACE_MODE_1000BASEX:
2798 sds_mode = 0x04;
2799 break;
2800 case PHY_INTERFACE_MODE_XGMII:
2801 sds_mode = 0x10;
2802 break;
2803 case PHY_INTERFACE_MODE_10GBASER:
2804 sds_mode = 0x1a;
2805 break;
2806 case PHY_INTERFACE_MODE_USXGMII:
2807 sds_mode = 0x0d;
2808 break;
2809 default:
2810 pr_err("%s: unknown serdes mode: %s\n", __func__, phy_modes(phy_mode));
2811 return -EINVAL;
2812 }
2813
2814 // Maybe use dal_longan_sds_init
2815
2816 // dal_longan_construct_serdesConfig_init // Serdes Construct
2817 rtl9300_phy_enable_10g_1g(sds_num);
2818
2819 // Set Serdes Mode
2820 rtl9300_sds_set(sds_num, 0x1a); // 0x1b: RTK_MII_10GR1000BX_AUTO
2821
2822 // Do RX calibration
2823 do {
2824 rtl9300_do_rx_calibration(sds_num, phy_mode);
2825 calib_tries++;
2826 mdelay(50);
2827 } while (rtl9300_sds_check_calibration(sds_num, phy_mode) && calib_tries < 3);
2828
2829
2830 return 0;
2831 }
2832
2833 typedef struct {
2834 u8 page;
2835 u8 reg;
2836 u16 data;
2837 } sds_config;
2838
2839 sds_config rtl9300_a_sds_10gr_lane0[] =
2840 {
2841 /*1G*/
2842 {0x00, 0x0E, 0x3053}, {0x01, 0x14, 0x0100}, {0x21, 0x03, 0x8206},
2843 {0x21, 0x05, 0x40B0}, {0x21, 0x06, 0x0010}, {0x21, 0x07, 0xF09F},
2844 {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009}, {0x21, 0x0E, 0x0000},
2845 {0x21, 0x0F, 0x0008}, {0x24, 0x00, 0x0668}, {0x24, 0x02, 0xD020},
2846 {0x24, 0x06, 0xC000}, {0x24, 0x0B, 0x1892}, {0x24, 0x0F, 0xFFDF},
2847 {0x24, 0x12, 0x03C4}, {0x24, 0x13, 0x027F}, {0x24, 0x14, 0x1311},
2848 {0x24, 0x16, 0x00C9}, {0x24, 0x17, 0xA100}, {0x24, 0x1A, 0x0001},
2849 {0x24, 0x1C, 0x0400}, {0x25, 0x01, 0x0300}, {0x25, 0x02, 0x1017},
2850 {0x25, 0x03, 0xFFDF}, {0x25, 0x05, 0x7F7C}, {0x25, 0x07, 0x8100},
2851 {0x25, 0x08, 0x0001}, {0x25, 0x09, 0xFFD4}, {0x25, 0x0A, 0x7C2F},
2852 {0x25, 0x0E, 0x003F}, {0x25, 0x0F, 0x0121}, {0x25, 0x10, 0x0020},
2853 {0x25, 0x11, 0x8840}, {0x2B, 0x13, 0x0050}, {0x2B, 0x18, 0x8E88},
2854 {0x2B, 0x19, 0x4902}, {0x2B, 0x1D, 0x2501}, {0x2D, 0x13, 0x0050},
2855 {0x2D, 0x18, 0x8E88}, {0x2D, 0x19, 0x4902}, {0x2D, 0x1D, 0x2641},
2856 {0x2F, 0x13, 0x0050}, {0x2F, 0x18, 0x8E88}, {0x2F, 0x19, 0x4902},
2857 {0x2F, 0x1D, 0x66E1},
2858 /*3.125G*/
2859 {0x28, 0x00, 0x0668}, {0x28, 0x02, 0xD020}, {0x28, 0x06, 0xC000},
2860 {0x28, 0x0B, 0x1892}, {0x28, 0x0F, 0xFFDF}, {0x28, 0x12, 0x01C4},
2861 {0x28, 0x13, 0x027F}, {0x28, 0x14, 0x1311}, {0x28, 0x16, 0x00C9},
2862 {0x28, 0x17, 0xA100}, {0x28, 0x1A, 0x0001}, {0x28, 0x1C, 0x0400},
2863 {0x29, 0x01, 0x0300}, {0x29, 0x02, 0x1017}, {0x29, 0x03, 0xFFDF},
2864 {0x29, 0x05, 0x7F7C}, {0x29, 0x07, 0x8100}, {0x29, 0x08, 0x0001},
2865 {0x29, 0x09, 0xFFD4}, {0x29, 0x0A, 0x7C2F}, {0x29, 0x0E, 0x003F},
2866 {0x29, 0x0F, 0x0121}, {0x29, 0x10, 0x0020}, {0x29, 0x11, 0x8840},
2867 /*10G*/
2868 {0x06, 0x0D, 0x0F00}, {0x06, 0x00, 0x0000}, {0x06, 0x01, 0xC800},
2869 {0x21, 0x03, 0x8206}, {0x21, 0x05, 0x40B0}, {0x21, 0x06, 0x0010},
2870 {0x21, 0x07, 0xF09F}, {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009},
2871 {0x21, 0x0E, 0x0000}, {0x21, 0x0F, 0x0008}, {0x2E, 0x00, 0xA668},
2872 {0x2E, 0x02, 0xD020}, {0x2E, 0x06, 0xC000}, {0x2E, 0x0B, 0x1892},
2873 {0x2E, 0x0F, 0xFFDF}, {0x2E, 0x11, 0x8280}, {0x2E, 0x12, 0x0044},
2874 {0x2E, 0x13, 0x027F}, {0x2E, 0x14, 0x1311}, {0x2E, 0x17, 0xA100},
2875 {0x2E, 0x1A, 0x0001}, {0x2E, 0x1C, 0x0400}, {0x2F, 0x01, 0x0300},
2876 {0x2F, 0x02, 0x1217}, {0x2F, 0x03, 0xFFDF}, {0x2F, 0x05, 0x7F7C},
2877 {0x2F, 0x07, 0x80C4}, {0x2F, 0x08, 0x0001}, {0x2F, 0x09, 0xFFD4},
2878 {0x2F, 0x0A, 0x7C2F}, {0x2F, 0x0E, 0x003F}, {0x2F, 0x0F, 0x0121},
2879 {0x2F, 0x10, 0x0020}, {0x2F, 0x11, 0x8840}, {0x2F, 0x14, 0xE008},
2880 {0x2B, 0x13, 0x0050}, {0x2B, 0x18, 0x8E88}, {0x2B, 0x19, 0x4902},
2881 {0x2B, 0x1D, 0x2501}, {0x2D, 0x13, 0x0050}, {0x2D, 0x17, 0x4109},
2882 {0x2D, 0x18, 0x8E88}, {0x2D, 0x19, 0x4902}, {0x2D, 0x1C, 0x1109},
2883 {0x2D, 0x1D, 0x2641}, {0x2F, 0x13, 0x0050}, {0x2F, 0x18, 0x8E88},
2884 {0x2F, 0x19, 0x4902}, {0x2F, 0x1D, 0x76E1},
2885 };
2886
2887 sds_config rtl9300_a_sds_10gr_lane1[] =
2888 {
2889 /*1G*/
2890 {0x00, 0x0E, 0x3053}, {0x01, 0x14, 0x0100}, {0x21, 0x03, 0x8206},
2891 {0x21, 0x06, 0x0010}, {0x21, 0x07, 0xF09F}, {0x21, 0x0A, 0x0003},
2892 {0x21, 0x0B, 0x0005}, {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009},
2893 {0x21, 0x0E, 0x0000}, {0x21, 0x0F, 0x0008}, {0x24, 0x00, 0x0668},
2894 {0x24, 0x02, 0xD020}, {0x24, 0x06, 0xC000}, {0x24, 0x0B, 0x1892},
2895 {0x24, 0x0F, 0xFFDF}, {0x24, 0x12, 0x03C4}, {0x24, 0x13, 0x027F},
2896 {0x24, 0x14, 0x1311}, {0x24, 0x16, 0x00C9}, {0x24, 0x17, 0xA100},
2897 {0x24, 0x1A, 0x0001}, {0x24, 0x1C, 0x0400}, {0x25, 0x00, 0x820F},
2898 {0x25, 0x01, 0x0300}, {0x25, 0x02, 0x1017}, {0x25, 0x03, 0xFFDF},
2899 {0x25, 0x05, 0x7F7C}, {0x25, 0x07, 0x8100}, {0x25, 0x08, 0x0001},
2900 {0x25, 0x09, 0xFFD4}, {0x25, 0x0A, 0x7C2F}, {0x25, 0x0E, 0x003F},
2901 {0x25, 0x0F, 0x0121}, {0x25, 0x10, 0x0020}, {0x25, 0x11, 0x8840},
2902 {0x2B, 0x13, 0x3D87}, {0x2B, 0x14, 0x3108}, {0x2D, 0x13, 0x3C87},
2903 {0x2D, 0x14, 0x1808},
2904 /*3.125G*/
2905 {0x28, 0x00, 0x0668}, {0x28, 0x02, 0xD020}, {0x28, 0x06, 0xC000},
2906 {0x28, 0x0B, 0x1892}, {0x28, 0x0F, 0xFFDF}, {0x28, 0x12, 0x01C4},
2907 {0x28, 0x13, 0x027F}, {0x28, 0x14, 0x1311}, {0x28, 0x16, 0x00C9},
2908 {0x28, 0x17, 0xA100}, {0x28, 0x1A, 0x0001}, {0x28, 0x1C, 0x0400},
2909 {0x29, 0x00, 0x820F}, {0x29, 0x01, 0x0300}, {0x29, 0x02, 0x1017},
2910 {0x29, 0x03, 0xFFDF}, {0x29, 0x05, 0x7F7C}, {0x29, 0x07, 0x8100},
2911 {0x29, 0x08, 0x0001}, {0x29, 0x0A, 0x7C2F}, {0x29, 0x0E, 0x003F},
2912 {0x29, 0x0F, 0x0121}, {0x29, 0x10, 0x0020}, {0x29, 0x11, 0x8840},
2913 /*10G*/
2914 {0x06, 0x0D, 0x0F00}, {0x06, 0x00, 0x0000}, {0x06, 0x01, 0xC800},
2915 {0x21, 0x03, 0x8206}, {0x21, 0x05, 0x40B0}, {0x21, 0x06, 0x0010},
2916 {0x21, 0x07, 0xF09F}, {0x21, 0x0A, 0x0003}, {0x21, 0x0B, 0x0005},
2917 {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009}, {0x21, 0x0E, 0x0000},
2918 {0x21, 0x0F, 0x0008}, {0x2E, 0x00, 0xA668}, {0x2E, 0x02, 0xD020},
2919 {0x2E, 0x06, 0xC000}, {0x2E, 0x0B, 0x1892}, {0x2E, 0x0F, 0xFFDF},
2920 {0x2E, 0x11, 0x8280}, {0x2E, 0x12, 0x0044}, {0x2E, 0x13, 0x027F},
2921 {0x2E, 0x14, 0x1311}, {0x2E, 0x17, 0xA100}, {0x2E, 0x1A, 0x0001},
2922 {0x2E, 0x1C, 0x0400}, {0x2F, 0x00, 0x820F}, {0x2F, 0x01, 0x0300},
2923 {0x2F, 0x02, 0x1217}, {0x2F, 0x03, 0xFFDF}, {0x2F, 0x05, 0x7F7C},
2924 {0x2F, 0x07, 0x80C4}, {0x2F, 0x08, 0x0001}, {0x2F, 0x09, 0xFFD4},
2925 {0x2F, 0x0A, 0x7C2F}, {0x2F, 0x0E, 0x003F}, {0x2F, 0x0F, 0x0121},
2926 {0x2F, 0x10, 0x0020}, {0x2F, 0x11, 0x8840}, {0x2B, 0x13, 0x3D87},
2927 {0x2B, 0x14, 0x3108}, {0x2D, 0x13, 0x3C87}, {0x2D, 0x14, 0x1808},
2928 };
2929
2930 int rtl9300_sds_cmu_band_get(int sds)
2931 {
2932 u32 page;
2933 u32 en;
2934 u32 cmu_band;
2935
2936 // page = rtl9300_sds_cmu_page_get(sds);
2937 page = 0x25; // 10GR and 1000BX
2938 sds = (sds % 2) ? (sds - 1) : (sds);
2939
2940 rtl9300_sds_field_w(sds, page, 0x1c, 15, 15, 1);
2941 rtl9300_sds_field_w(sds + 1, page, 0x1c, 15, 15, 1);
2942
2943 en = rtl9300_sds_field_r(sds, page, 27, 1, 1);
2944 if(!en) { // Auto mode
2945 rtl930x_write_sds_phy(sds, 0x1f, 0x02, 31);
2946
2947 cmu_band = rtl9300_sds_field_r(sds, 0x1f, 0x15, 5, 1);
2948 } else {
2949 cmu_band = rtl9300_sds_field_r(sds, page, 30, 4, 0);
2950 }
2951
2952 return cmu_band;
2953 }
2954
2955 int rtl9300_configure_serdes(struct phy_device *phydev)
2956 {
2957 struct device *dev = &phydev->mdio.dev;
2958 int phy_addr = phydev->mdio.addr;
2959 struct device_node *dn;
2960 u32 sds_num = 0;
2961 int sds_mode, calib_tries = 0, phy_mode = PHY_INTERFACE_MODE_10GBASER, i;
2962
2963 if (dev->of_node) {
2964 dn = dev->of_node;
2965
2966 if (of_property_read_u32(dn, "sds", &sds_num))
2967 sds_num = -1;
2968 pr_info("%s: Port %d, SerDes is %d\n", __func__, phy_addr, sds_num);
2969 } else {
2970 dev_err(dev, "No DT node.\n");
2971 return -EINVAL;
2972 }
2973
2974 if (sds_num < 0)
2975 return 0;
2976
2977 if (phy_mode != PHY_INTERFACE_MODE_10GBASER) // TODO: for now we only patch 10GR SerDes
2978 return 0;
2979
2980 switch (phy_mode) {
2981 case PHY_INTERFACE_MODE_HSGMII:
2982 sds_mode = 0x12;
2983 break;
2984 case PHY_INTERFACE_MODE_1000BASEX:
2985 sds_mode = 0x04;
2986 break;
2987 case PHY_INTERFACE_MODE_XGMII:
2988 sds_mode = 0x10;
2989 break;
2990 case PHY_INTERFACE_MODE_10GBASER:
2991 sds_mode = 0x1a;
2992 break;
2993 case PHY_INTERFACE_MODE_USXGMII:
2994 sds_mode = 0x0d;
2995 break;
2996 default:
2997 pr_err("%s: unknown serdes mode: %s\n", __func__, phy_modes(phy_mode));
2998 return -EINVAL;
2999 }
3000
3001 pr_info("%s CMU BAND is %d\n", __func__, rtl9300_sds_cmu_band_get(sds_num));
3002
3003 // Turn Off Serdes
3004 rtl9300_sds_rst(sds_num, 0x1f);
3005
3006 pr_info("%s PATCHING SerDes %d\n", __func__, sds_num);
3007 if (sds_num % 2) {
3008 for (i = 0; i < sizeof(rtl9300_a_sds_10gr_lane1) / sizeof(sds_config); ++i) {
3009 rtl930x_write_sds_phy(sds_num, rtl9300_a_sds_10gr_lane1[i].page,
3010 rtl9300_a_sds_10gr_lane1[i].reg,
3011 rtl9300_a_sds_10gr_lane1[i].data);
3012 }
3013 } else {
3014 for (i = 0; i < sizeof(rtl9300_a_sds_10gr_lane0) / sizeof(sds_config); ++i) {
3015 rtl930x_write_sds_phy(sds_num, rtl9300_a_sds_10gr_lane0[i].page,
3016 rtl9300_a_sds_10gr_lane0[i].reg,
3017 rtl9300_a_sds_10gr_lane0[i].data);
3018 }
3019 }
3020
3021 rtl9300_phy_enable_10g_1g(sds_num);
3022
3023 // Disable MAC
3024 sw_w32_mask(0, 1, RTL930X_MAC_FORCE_MODE_CTRL);
3025 mdelay(20);
3026
3027 // ----> dal_longan_sds_mode_set
3028 pr_info("%s: Configuring RTL9300 SERDES %d, mode %02x\n", __func__, sds_num, sds_mode);
3029
3030 // Configure link to MAC
3031 rtl9300_serdes_mac_link_config(sds_num, true, true); // MAC Construct
3032
3033 // Disable MAC
3034 sw_w32_mask(0, 1, RTL930X_MAC_FORCE_MODE_CTRL);
3035 mdelay(20);
3036
3037 rtl9300_force_sds_mode(sds_num, PHY_INTERFACE_MODE_NA);
3038
3039 // Re-Enable MAC
3040 sw_w32_mask(1, 0, RTL930X_MAC_FORCE_MODE_CTRL);
3041
3042 rtl9300_force_sds_mode(sds_num, phy_mode);
3043
3044 // Do RX calibration
3045 do {
3046 rtl9300_do_rx_calibration(sds_num, phy_mode);
3047 calib_tries++;
3048 mdelay(50);
3049 } while (rtl9300_sds_check_calibration(sds_num, phy_mode) && calib_tries < 3);
3050
3051 if (calib_tries >= 3)
3052 pr_err("%s CALIBTRATION FAILED\n", __func__);
3053
3054 rtl9300_sds_tx_config(sds_num, phy_mode);
3055
3056 // The clock needs only to be configured on the FPGA implementation
3057
3058 return 0;
3059 }
3060
3061 void rtl9310_sds_field_w(int sds, u32 page, u32 reg, int end_bit, int start_bit, u32 v)
3062 {
3063 int l = end_bit - start_bit + 1;
3064 u32 data = v;
3065
3066 if (l < 32) {
3067 u32 mask = BIT(l) - 1;
3068
3069 data = rtl930x_read_sds_phy(sds, page, reg);
3070 data &= ~(mask << start_bit);
3071 data |= (v & mask) << start_bit;
3072 }
3073
3074 rtl931x_write_sds_phy(sds, page, reg, data);
3075 }
3076
3077
3078 u32 rtl9310_sds_field_r(int sds, u32 page, u32 reg, int end_bit, int start_bit)
3079 {
3080 int l = end_bit - start_bit + 1;
3081 u32 v = rtl931x_read_sds_phy(sds, page, reg);
3082
3083 if (l >= 32)
3084 return v;
3085
3086 return (v >> start_bit) & (BIT(l) - 1);
3087 }
3088
3089 static void rtl931x_sds_rst(u32 sds)
3090 {
3091 u32 o, v, o_mode;
3092 int shift = ((sds & 0x3) << 3);
3093
3094 // TODO: We need to lock this!
3095
3096 o = sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3097 v = o | BIT(sds);
3098 sw_w32(v, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3099
3100 o_mode = sw_r32(RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3101 v = BIT(7) | 0x1F;
3102 sw_w32_mask(0xff << shift, v << shift, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3103 sw_w32(o_mode, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3104
3105 sw_w32(o, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3106 }
3107
3108 static void rtl931x_symerr_clear(u32 sds, phy_interface_t mode)
3109 {
3110 u32 i;
3111 u32 xsg_sdsid_0, xsg_sdsid_1;
3112
3113 switch (mode) {
3114 case PHY_INTERFACE_MODE_NA:
3115 break;
3116 case PHY_INTERFACE_MODE_XGMII:
3117 if (sds < 2)
3118 xsg_sdsid_0 = sds;
3119 else
3120 xsg_sdsid_0 = (sds - 1) * 2;
3121 xsg_sdsid_1 = xsg_sdsid_0 + 1;
3122
3123 for (i = 0; i < 4; ++i) {
3124 rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 24, 2, 0, i);
3125 rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 3, 15, 8, 0x0);
3126 rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 2, 15, 0, 0x0);
3127 }
3128
3129 for (i = 0; i < 4; ++i) {
3130 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 24, 2, 0, i);
3131 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 3, 15, 8, 0x0);
3132 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 2, 15, 0, 0x0);
3133 }
3134
3135 rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 0, 15, 0, 0x0);
3136 rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 1, 15, 8, 0x0);
3137 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 0, 15, 0, 0x0);
3138 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 1, 15, 8, 0x0);
3139 break;
3140 default:
3141 break;
3142 }
3143
3144 return;
3145 }
3146
3147 static u32 rtl931x_get_analog_sds(u32 sds)
3148 {
3149 u32 sds_map[] = { 0, 1, 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23 };
3150
3151 if (sds < 14)
3152 return sds_map[sds];
3153 return sds;
3154 }
3155
3156 void rtl931x_sds_fiber_disable(u32 sds)
3157 {
3158 u32 v = 0x3F;
3159 u32 asds = rtl931x_get_analog_sds(sds);
3160
3161 rtl9310_sds_field_w(asds, 0x1F, 0x9, 11, 6, v);
3162 }
3163
3164 static void rtl931x_sds_fiber_mode_set(u32 sds, phy_interface_t mode)
3165 {
3166 u32 val, asds = rtl931x_get_analog_sds(sds);
3167
3168 /* clear symbol error count before changing mode */
3169 rtl931x_symerr_clear(sds, mode);
3170
3171 val = 0x9F;
3172 sw_w32(val, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3173
3174 switch (mode) {
3175 case PHY_INTERFACE_MODE_SGMII:
3176 val = 0x5;
3177 break;
3178
3179 case PHY_INTERFACE_MODE_1000BASEX:
3180 /* serdes mode FIBER1G */
3181 val = 0x9;
3182 break;
3183
3184 case PHY_INTERFACE_MODE_10GBASER:
3185 case PHY_INTERFACE_MODE_10GKR:
3186 val = 0x35;
3187 break;
3188 /* case MII_10GR1000BX_AUTO:
3189 val = 0x39;
3190 break; */
3191
3192
3193 case PHY_INTERFACE_MODE_USXGMII:
3194 val = 0x1B;
3195 break;
3196 default:
3197 val = 0x25;
3198 }
3199
3200 pr_info("%s writing analog SerDes Mode value %02x\n", __func__, val);
3201 rtl9310_sds_field_w(asds, 0x1F, 0x9, 11, 6, val);
3202
3203 return;
3204 }
3205
3206 static int rtl931x_sds_cmu_page_get(phy_interface_t mode)
3207 {
3208 switch (mode) {
3209 case PHY_INTERFACE_MODE_SGMII:
3210 case PHY_INTERFACE_MODE_1000BASEX: // MII_1000BX_FIBER / 100BX_FIBER / 1000BX100BX_AUTO
3211 return 0x24;
3212 case PHY_INTERFACE_MODE_HSGMII:
3213 case PHY_INTERFACE_MODE_2500BASEX: // MII_2500Base_X:
3214 return 0x28;
3215 // case MII_HISGMII_5G:
3216 // return 0x2a;
3217 case PHY_INTERFACE_MODE_QSGMII:
3218 return 0x2a; // Code also has 0x34
3219 case PHY_INTERFACE_MODE_XAUI: // MII_RXAUI_LITE:
3220 return 0x2c;
3221 case PHY_INTERFACE_MODE_XGMII: // MII_XSGMII
3222 case PHY_INTERFACE_MODE_10GKR:
3223 case PHY_INTERFACE_MODE_10GBASER: // MII_10GR
3224 return 0x2e;
3225 default:
3226 return -1;
3227 }
3228 return -1;
3229 }
3230
3231 static void rtl931x_cmu_type_set(u32 asds, phy_interface_t mode, int chiptype)
3232 {
3233 int cmu_type = 0; // Clock Management Unit
3234 u32 cmu_page = 0;
3235 u32 frc_cmu_spd;
3236 u32 evenSds;
3237 u32 lane, frc_lc_mode_bitnum, frc_lc_mode_val_bitnum;
3238
3239 switch (mode) {
3240 case PHY_INTERFACE_MODE_NA:
3241 case PHY_INTERFACE_MODE_10GKR:
3242 case PHY_INTERFACE_MODE_XGMII:
3243 case PHY_INTERFACE_MODE_10GBASER:
3244 case PHY_INTERFACE_MODE_USXGMII:
3245 return;
3246
3247 /* case MII_10GR1000BX_AUTO:
3248 if (chiptype)
3249 rtl9310_sds_field_w(asds, 0x24, 0xd, 14, 14, 0);
3250 return; */
3251
3252 case PHY_INTERFACE_MODE_QSGMII:
3253 cmu_type = 1;
3254 frc_cmu_spd = 0;
3255 break;
3256
3257 case PHY_INTERFACE_MODE_HSGMII:
3258 cmu_type = 1;
3259 frc_cmu_spd = 1;
3260 break;
3261
3262 case PHY_INTERFACE_MODE_1000BASEX:
3263 cmu_type = 1;
3264 frc_cmu_spd = 0;
3265 break;
3266
3267 /* case MII_1000BX100BX_AUTO:
3268 cmu_type = 1;
3269 frc_cmu_spd = 0;
3270 break; */
3271
3272 case PHY_INTERFACE_MODE_SGMII:
3273 cmu_type = 1;
3274 frc_cmu_spd = 0;
3275 break;
3276
3277 case PHY_INTERFACE_MODE_2500BASEX:
3278 cmu_type = 1;
3279 frc_cmu_spd = 1;
3280 break;
3281
3282 default:
3283 pr_info("SerDes %d mode is invalid\n", asds);
3284 return;
3285 }
3286
3287 if (cmu_type == 1)
3288 cmu_page = rtl931x_sds_cmu_page_get(mode);
3289
3290 lane = asds % 2;
3291
3292 if (!lane) {
3293 frc_lc_mode_bitnum = 4;
3294 frc_lc_mode_val_bitnum = 5;
3295 } else {
3296 frc_lc_mode_bitnum = 6;
3297 frc_lc_mode_val_bitnum = 7;
3298 }
3299
3300 evenSds = asds - lane;
3301
3302 pr_info("%s: cmu_type %0d cmu_page %x frc_cmu_spd %d lane %d asds %d\n",
3303 __func__, cmu_type, cmu_page, frc_cmu_spd, lane, asds);
3304
3305 if (cmu_type == 1) {
3306 pr_info("%s A CMU page 0x28 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x28, 0x7));
3307 rtl9310_sds_field_w(asds, cmu_page, 0x7, 15, 15, 0);
3308 pr_info("%s B CMU page 0x28 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x28, 0x7));
3309 if (chiptype) {
3310 rtl9310_sds_field_w(asds, cmu_page, 0xd, 14, 14, 0);
3311 }
3312
3313 rtl9310_sds_field_w(evenSds, 0x20, 0x12, 3, 2, 0x3);
3314 rtl9310_sds_field_w(evenSds, 0x20, 0x12, frc_lc_mode_bitnum, frc_lc_mode_bitnum, 1);
3315 rtl9310_sds_field_w(evenSds, 0x20, 0x12, frc_lc_mode_val_bitnum, frc_lc_mode_val_bitnum, 0);
3316 rtl9310_sds_field_w(evenSds, 0x20, 0x12, 12, 12, 1);
3317 rtl9310_sds_field_w(evenSds, 0x20, 0x12, 15, 13, frc_cmu_spd);
3318 }
3319
3320 pr_info("%s CMU page 0x28 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x28, 0x7));
3321 return;
3322 }
3323
3324 static void rtl931x_sds_rx_rst(u32 sds)
3325 {
3326 u32 asds = rtl931x_get_analog_sds(sds);
3327
3328 if (sds < 2)
3329 return;
3330
3331 rtl931x_write_sds_phy(asds, 0x2e, 0x12, 0x2740);
3332 rtl931x_write_sds_phy(asds, 0x2f, 0x0, 0x0);
3333 rtl931x_write_sds_phy(asds, 0x2f, 0x2, 0x2010);
3334 rtl931x_write_sds_phy(asds, 0x20, 0x0, 0xc10);
3335
3336 rtl931x_write_sds_phy(asds, 0x2e, 0x12, 0x27c0);
3337 rtl931x_write_sds_phy(asds, 0x2f, 0x0, 0xc000);
3338 rtl931x_write_sds_phy(asds, 0x2f, 0x2, 0x6010);
3339 rtl931x_write_sds_phy(asds, 0x20, 0x0, 0xc30);
3340
3341 mdelay(50);
3342 }
3343
3344 static void rtl931x_sds_disable(u32 sds)
3345 {
3346 u32 v = 0x1f;
3347
3348 v |= BIT(7);
3349 sw_w32(v, RTL931X_SERDES_MODE_CTRL + (sds >> 2) * 4);
3350 }
3351
3352 static void rtl931x_sds_mii_mode_set(u32 sds, phy_interface_t mode)
3353 {
3354 u32 val;
3355
3356 switch (mode) {
3357 case PHY_INTERFACE_MODE_QSGMII:
3358 val = 0x6;
3359 break;
3360 case PHY_INTERFACE_MODE_XGMII:
3361 val = 0x10; // serdes mode XSGMII
3362 break;
3363 case PHY_INTERFACE_MODE_USXGMII:
3364 case PHY_INTERFACE_MODE_2500BASEX:
3365 val = 0xD;
3366 break;
3367 case PHY_INTERFACE_MODE_HSGMII:
3368 val = 0x12;
3369 break;
3370 case PHY_INTERFACE_MODE_SGMII:
3371 val = 0x2;
3372 break;
3373 default:
3374 return;
3375 }
3376
3377 val |= (1 << 7);
3378
3379 sw_w32(val, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3380 }
3381
3382 static sds_config sds_config_10p3125g_type1[] = {
3383 { 0x2E, 0x00, 0x0107 }, { 0x2E, 0x01, 0x01A3 }, { 0x2E, 0x02, 0x6A24 },
3384 { 0x2E, 0x03, 0xD10D }, { 0x2E, 0x04, 0x8000 }, { 0x2E, 0x05, 0xA17E },
3385 { 0x2E, 0x06, 0xE31D }, { 0x2E, 0x07, 0x800E }, { 0x2E, 0x08, 0x0294 },
3386 { 0x2E, 0x09, 0x0CE4 }, { 0x2E, 0x0A, 0x7FC8 }, { 0x2E, 0x0B, 0xE0E7 },
3387 { 0x2E, 0x0C, 0x0200 }, { 0x2E, 0x0D, 0xDF80 }, { 0x2E, 0x0E, 0x0000 },
3388 { 0x2E, 0x0F, 0x1FC2 }, { 0x2E, 0x10, 0x0C3F }, { 0x2E, 0x11, 0x0000 },
3389 { 0x2E, 0x12, 0x27C0 }, { 0x2E, 0x13, 0x7E1D }, { 0x2E, 0x14, 0x1300 },
3390 { 0x2E, 0x15, 0x003F }, { 0x2E, 0x16, 0xBE7F }, { 0x2E, 0x17, 0x0090 },
3391 { 0x2E, 0x18, 0x0000 }, { 0x2E, 0x19, 0x4000 }, { 0x2E, 0x1A, 0x0000 },
3392 { 0x2E, 0x1B, 0x8000 }, { 0x2E, 0x1C, 0x011F }, { 0x2E, 0x1D, 0x0000 },
3393 { 0x2E, 0x1E, 0xC8FF }, { 0x2E, 0x1F, 0x0000 }, { 0x2F, 0x00, 0xC000 },
3394 { 0x2F, 0x01, 0xF000 }, { 0x2F, 0x02, 0x6010 }, { 0x2F, 0x12, 0x0EE7 },
3395 { 0x2F, 0x13, 0x0000 }
3396 };
3397
3398 static sds_config sds_config_10p3125g_cmu_type1[] = {
3399 { 0x2F, 0x03, 0x4210 }, { 0x2F, 0x04, 0x0000 }, { 0x2F, 0x05, 0x0019 },
3400 { 0x2F, 0x06, 0x18A6 }, { 0x2F, 0x07, 0x2990 }, { 0x2F, 0x08, 0xFFF4 },
3401 { 0x2F, 0x09, 0x1F08 }, { 0x2F, 0x0A, 0x0000 }, { 0x2F, 0x0B, 0x8000 },
3402 { 0x2F, 0x0C, 0x4224 }, { 0x2F, 0x0D, 0x0000 }, { 0x2F, 0x0E, 0x0000 },
3403 { 0x2F, 0x0F, 0xA470 }, { 0x2F, 0x10, 0x8000 }, { 0x2F, 0x11, 0x037B }
3404 };
3405
3406 void rtl931x_sds_init(u32 sds, phy_interface_t mode)
3407 {
3408
3409 u32 board_sds_tx_type1[] = { 0x1C3, 0x1C3, 0x1C3, 0x1A3, 0x1A3,
3410 0x1A3, 0x143, 0x143, 0x143, 0x143, 0x163, 0x163
3411 };
3412
3413 u32 board_sds_tx[] = { 0x1A00, 0x1A00, 0x200, 0x200, 0x200,
3414 0x200, 0x1A3, 0x1A3, 0x1A3, 0x1A3, 0x1E3, 0x1E3
3415 };
3416
3417 u32 board_sds_tx2[] = { 0xDC0, 0x1C0, 0x200, 0x180, 0x160,
3418 0x123, 0x123, 0x163, 0x1A3, 0x1A0, 0x1C3, 0x9C3
3419 };
3420
3421 u32 asds, dSds, ori, model_info, val;
3422 int chiptype = 0;
3423
3424 asds = rtl931x_get_analog_sds(sds);
3425
3426 if (sds > 13)
3427 return;
3428
3429 pr_info("%s: set sds %d to mode %d\n", __func__, sds, mode);
3430 val = rtl9310_sds_field_r(asds, 0x1F, 0x9, 11, 6);
3431
3432 pr_info("%s: fibermode %08X stored mode 0x%x analog SDS %d", __func__,
3433 rtl931x_read_sds_phy(asds, 0x1f, 0x9), val, asds);
3434 pr_info("%s: SGMII mode %08X in 0x24 0x9 analog SDS %d", __func__,
3435 rtl931x_read_sds_phy(asds, 0x24, 0x9), asds);
3436 pr_info("%s: CMU mode %08X stored even SDS %d", __func__,
3437 rtl931x_read_sds_phy(asds & ~1, 0x20, 0x12), asds & ~1);
3438 pr_info("%s: serdes_mode_ctrl %08X", __func__, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3439 pr_info("%s CMU page 0x24 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x24, 0x7));
3440 pr_info("%s CMU page 0x26 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x26, 0x7));
3441 pr_info("%s CMU page 0x28 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x28, 0x7));
3442 pr_info("%s XSG page 0x0 0xe %08x\n", __func__, rtl931x_read_sds_phy(dSds, 0x0, 0xe));
3443 pr_info("%s XSG2 page 0x0 0xe %08x\n", __func__, rtl931x_read_sds_phy(dSds + 1, 0x0, 0xe));
3444
3445 model_info = sw_r32(RTL93XX_MODEL_NAME_INFO);
3446 if ((model_info >> 4) & 0x1) {
3447 pr_info("detected chiptype 1\n");
3448 chiptype = 1;
3449 } else {
3450 pr_info("detected chiptype 0\n");
3451 }
3452
3453 if (sds < 2)
3454 dSds = sds;
3455 else
3456 dSds = (sds - 1) * 2;
3457
3458 pr_info("%s: 2.5gbit %08X dsds %d", __func__,
3459 rtl931x_read_sds_phy(dSds, 0x1, 0x14), dSds);
3460
3461 pr_info("%s: RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR 0x%08X\n", __func__, sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR));
3462 ori = sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3463 val = ori | (1 << sds);
3464 sw_w32(val, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3465
3466 switch (mode) {
3467 case PHY_INTERFACE_MODE_NA:
3468 break;
3469
3470 case PHY_INTERFACE_MODE_XGMII: // MII_XSGMII
3471
3472 if (chiptype) {
3473 u32 xsg_sdsid_1;
3474 xsg_sdsid_1 = dSds + 1;
3475 //fifo inv clk
3476 rtl9310_sds_field_w(dSds, 0x1, 0x1, 7, 4, 0xf);
3477 rtl9310_sds_field_w(dSds, 0x1, 0x1, 3, 0, 0xf);
3478
3479 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 0x1, 7, 4, 0xf);
3480 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 0x1, 3, 0, 0xf);
3481
3482 }
3483
3484 rtl9310_sds_field_w(dSds, 0x0, 0xE, 12, 12, 1);
3485 rtl9310_sds_field_w(dSds + 1, 0x0, 0xE, 12, 12, 1);
3486 break;
3487
3488 case PHY_INTERFACE_MODE_USXGMII: // MII_USXGMII_10GSXGMII/10GDXGMII/10GQXGMII:
3489 u32 i, evenSds;
3490 u32 op_code = 0x6003;
3491
3492 if (chiptype) {
3493 rtl9310_sds_field_w(asds, 0x6, 0x2, 12, 12, 1);
3494
3495 for (i = 0; i < sizeof(sds_config_10p3125g_type1) / sizeof(sds_config); ++i) {
3496 rtl931x_write_sds_phy(asds, sds_config_10p3125g_type1[i].page - 0x4, sds_config_10p3125g_type1[i].reg, sds_config_10p3125g_type1[i].data);
3497 }
3498
3499 evenSds = asds - (asds % 2);
3500
3501 for (i = 0; i < sizeof(sds_config_10p3125g_cmu_type1) / sizeof(sds_config); ++i) {
3502 rtl931x_write_sds_phy(evenSds,
3503 sds_config_10p3125g_cmu_type1[i].page - 0x4, sds_config_10p3125g_cmu_type1[i].reg, sds_config_10p3125g_cmu_type1[i].data);
3504 }
3505
3506 rtl9310_sds_field_w(asds, 0x6, 0x2, 12, 12, 0);
3507 } else {
3508
3509 rtl9310_sds_field_w(asds, 0x2e, 0xd, 6, 0, 0x0);
3510 rtl9310_sds_field_w(asds, 0x2e, 0xd, 7, 7, 0x1);
3511
3512 rtl9310_sds_field_w(asds, 0x2e, 0x1c, 5, 0, 0x1E);
3513 rtl9310_sds_field_w(asds, 0x2e, 0x1d, 11, 0, 0x00);
3514 rtl9310_sds_field_w(asds, 0x2e, 0x1f, 11, 0, 0x00);
3515 rtl9310_sds_field_w(asds, 0x2f, 0x0, 11, 0, 0x00);
3516 rtl9310_sds_field_w(asds, 0x2f, 0x1, 11, 0, 0x00);
3517
3518 rtl9310_sds_field_w(asds, 0x2e, 0xf, 12, 6, 0x7F);
3519 rtl931x_write_sds_phy(asds, 0x2f, 0x12, 0xaaa);
3520
3521 rtl931x_sds_rx_rst(sds);
3522
3523 rtl931x_write_sds_phy(asds, 0x7, 0x10, op_code);
3524 rtl931x_write_sds_phy(asds, 0x6, 0x1d, 0x0480);
3525 rtl931x_write_sds_phy(asds, 0x6, 0xe, 0x0400);
3526 }
3527 break;
3528
3529 case PHY_INTERFACE_MODE_10GBASER: // MII_10GR / MII_10GR1000BX_AUTO:
3530 // configure 10GR fiber mode=1
3531 rtl9310_sds_field_w(asds, 0x1f, 0xb, 1, 1, 1);
3532
3533 // init fiber_1g
3534 rtl9310_sds_field_w(dSds, 0x3, 0x13, 15, 14, 0);
3535
3536 rtl9310_sds_field_w(dSds, 0x2, 0x0, 12, 12, 1);
3537 rtl9310_sds_field_w(dSds, 0x2, 0x0, 6, 6, 1);
3538 rtl9310_sds_field_w(dSds, 0x2, 0x0, 13, 13, 0);
3539
3540 // init auto
3541 rtl9310_sds_field_w(asds, 0x1f, 13, 15, 0, 0x109e);
3542 rtl9310_sds_field_w(asds, 0x1f, 0x6, 14, 10, 0x8);
3543 rtl9310_sds_field_w(asds, 0x1f, 0x7, 10, 4, 0x7f);
3544 break;
3545
3546 case PHY_INTERFACE_MODE_HSGMII:
3547 rtl9310_sds_field_w(dSds, 0x1, 0x14, 8, 8, 1);
3548 break;
3549
3550 case PHY_INTERFACE_MODE_1000BASEX: // MII_1000BX_FIBER
3551 rtl9310_sds_field_w(dSds, 0x3, 0x13, 15, 14, 0);
3552
3553 rtl9310_sds_field_w(dSds, 0x2, 0x0, 12, 12, 1);
3554 rtl9310_sds_field_w(dSds, 0x2, 0x0, 6, 6, 1);
3555 rtl9310_sds_field_w(dSds, 0x2, 0x0, 13, 13, 0);
3556 break;
3557
3558 case PHY_INTERFACE_MODE_SGMII:
3559 rtl9310_sds_field_w(asds, 0x24, 0x9, 15, 15, 0);
3560 break;
3561
3562 case PHY_INTERFACE_MODE_2500BASEX:
3563 rtl9310_sds_field_w(dSds, 0x1, 0x14, 8, 8, 1);
3564 break;
3565
3566 case PHY_INTERFACE_MODE_QSGMII:
3567 default:
3568 pr_info("%s: PHY mode %s not supported by SerDes %d\n",
3569 __func__, phy_modes(mode), sds);
3570 return;
3571 }
3572
3573 rtl931x_cmu_type_set(asds, mode, chiptype);
3574
3575 if (sds >= 2 && sds <= 13) {
3576 if (chiptype)
3577 rtl931x_write_sds_phy(asds, 0x2E, 0x1, board_sds_tx_type1[sds - 2]);
3578 else {
3579 val = 0xa0000;
3580 sw_w32(val, RTL931X_CHIP_INFO_ADDR);
3581 val = sw_r32(RTL931X_CHIP_INFO_ADDR);
3582 if (val & BIT(28)) // consider 9311 etc. RTL9313_CHIP_ID == HWP_CHIP_ID(unit))
3583 {
3584 rtl931x_write_sds_phy(asds, 0x2E, 0x1, board_sds_tx2[sds - 2]);
3585 } else {
3586 rtl931x_write_sds_phy(asds, 0x2E, 0x1, board_sds_tx[sds - 2]);
3587 }
3588 val = 0;
3589 sw_w32(val, RTL931X_CHIP_INFO_ADDR);
3590 }
3591 }
3592
3593 val = ori & ~BIT(sds);
3594 sw_w32(val, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3595 pr_debug("%s: RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR 0x%08X\n", __func__, sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR));
3596
3597 if (mode == PHY_INTERFACE_MODE_XGMII || mode == PHY_INTERFACE_MODE_QSGMII
3598 || mode == PHY_INTERFACE_MODE_HSGMII || mode == PHY_INTERFACE_MODE_SGMII
3599 || mode == PHY_INTERFACE_MODE_USXGMII) {
3600 if (mode == PHY_INTERFACE_MODE_XGMII)
3601 rtl931x_sds_mii_mode_set(sds, mode);
3602 else
3603 rtl931x_sds_fiber_mode_set(sds, mode);
3604 }
3605 }
3606
3607 int rtl931x_sds_cmu_band_set(int sds, bool enable, u32 band, phy_interface_t mode)
3608 {
3609 u32 asds;
3610 int page = rtl931x_sds_cmu_page_get(mode);
3611
3612 sds -= (sds % 2);
3613 sds = sds & ~1;
3614 asds = rtl931x_get_analog_sds(sds);
3615 page += 1;
3616
3617 if (enable) {
3618 rtl9310_sds_field_w(asds, page, 0x7, 13, 13, 0);
3619 rtl9310_sds_field_w(asds, page, 0x7, 11, 11, 0);
3620 } else {
3621 rtl9310_sds_field_w(asds, page, 0x7, 13, 13, 0);
3622 rtl9310_sds_field_w(asds, page, 0x7, 11, 11, 0);
3623 }
3624
3625 rtl9310_sds_field_w(asds, page, 0x7, 4, 0, band);
3626
3627 rtl931x_sds_rst(sds);
3628
3629 return 0;
3630 }
3631
3632 int rtl931x_sds_cmu_band_get(int sds, phy_interface_t mode)
3633 {
3634 int page = rtl931x_sds_cmu_page_get(mode);
3635 u32 asds, band;
3636
3637 sds -= (sds % 2);
3638 asds = rtl931x_get_analog_sds(sds);
3639 page += 1;
3640 rtl931x_write_sds_phy(asds, 0x1f, 0x02, 73);
3641
3642 rtl9310_sds_field_w(asds, page, 0x5, 15, 15, 1);
3643 band = rtl9310_sds_field_r(asds, 0x1f, 0x15, 8, 3);
3644 pr_info("%s band is: %d\n", __func__, band);
3645
3646 return band;
3647 }
3648
3649
3650 int rtl931x_link_sts_get(u32 sds)
3651 {
3652 u32 sts, sts1, latch_sts, latch_sts1;
3653 if (0){
3654 u32 xsg_sdsid_0, xsg_sdsid_1;
3655
3656 xsg_sdsid_0 = sds < 2 ? sds : (sds - 1) * 2;
3657 xsg_sdsid_1 = xsg_sdsid_0 + 1;
3658
3659 sts = rtl9310_sds_field_r(xsg_sdsid_0, 0x1, 29, 8, 0);
3660 sts1 = rtl9310_sds_field_r(xsg_sdsid_1, 0x1, 29, 8, 0);
3661 latch_sts = rtl9310_sds_field_r(xsg_sdsid_0, 0x1, 30, 8, 0);
3662 latch_sts1 = rtl9310_sds_field_r(xsg_sdsid_1, 0x1, 30, 8, 0);
3663 } else {
3664 u32 asds, dsds;
3665
3666 asds = rtl931x_get_analog_sds(sds);
3667 sts = rtl9310_sds_field_r(asds, 0x5, 0, 12, 12);
3668 latch_sts = rtl9310_sds_field_r(asds, 0x4, 1, 2, 2);
3669
3670 dsds = sds < 2 ? sds : (sds - 1) * 2;
3671 latch_sts1 = rtl9310_sds_field_r(dsds, 0x2, 1, 2, 2);
3672 sts1 = rtl9310_sds_field_r(dsds, 0x2, 1, 2, 2);
3673 }
3674
3675 pr_info("%s: serdes %d sts %d, sts1 %d, latch_sts %d, latch_sts1 %d\n", __func__,
3676 sds, sts, sts1, latch_sts, latch_sts1);
3677 return sts1;
3678 }
3679
3680 static int rtl8214fc_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)
3681 {
3682 struct phy_device *phydev = upstream;
3683
3684 rtl8214fc_media_set(phydev, true);
3685
3686 return 0;
3687 }
3688
3689 static void rtl8214fc_sfp_remove(void *upstream)
3690 {
3691 struct phy_device *phydev = upstream;
3692
3693 rtl8214fc_media_set(phydev, false);
3694 }
3695
3696 static const struct sfp_upstream_ops rtl8214fc_sfp_ops = {
3697 .attach = phy_sfp_attach,
3698 .detach = phy_sfp_detach,
3699 .module_insert = rtl8214fc_sfp_insert,
3700 .module_remove = rtl8214fc_sfp_remove,
3701 };
3702
3703 static int rtl8214fc_phy_probe(struct phy_device *phydev)
3704 {
3705 struct device *dev = &phydev->mdio.dev;
3706 int addr = phydev->mdio.addr;
3707 int ret = 0;
3708
3709 /* 839x has internal SerDes */
3710 if (soc_info.id == 0x8393)
3711 return -ENODEV;
3712
3713 /* All base addresses of the PHYs start at multiples of 8 */
3714 devm_phy_package_join(dev, phydev, addr & (~7),
3715 sizeof(struct rtl83xx_shared_private));
3716
3717 if (!(addr % 8)) {
3718 struct rtl83xx_shared_private *shared = phydev->shared->priv;
3719 shared->name = "RTL8214FC";
3720 /* Configuration must be done while patching still possible */
3721 ret = rtl8380_configure_rtl8214fc(phydev);
3722 if (ret)
3723 return ret;
3724 }
3725
3726 return phy_sfp_probe(phydev, &rtl8214fc_sfp_ops);
3727 }
3728
3729 static int rtl8214c_phy_probe(struct phy_device *phydev)
3730 {
3731 struct device *dev = &phydev->mdio.dev;
3732 int addr = phydev->mdio.addr;
3733
3734 /* All base addresses of the PHYs start at multiples of 8 */
3735 devm_phy_package_join(dev, phydev, addr & (~7),
3736 sizeof(struct rtl83xx_shared_private));
3737
3738 if (!(addr % 8)) {
3739 struct rtl83xx_shared_private *shared = phydev->shared->priv;
3740 shared->name = "RTL8214C";
3741 /* Configuration must be done whil patching still possible */
3742 return rtl8380_configure_rtl8214c(phydev);
3743 }
3744 return 0;
3745 }
3746
3747 static int rtl8218b_ext_phy_probe(struct phy_device *phydev)
3748 {
3749 struct device *dev = &phydev->mdio.dev;
3750 int addr = phydev->mdio.addr;
3751
3752 /* All base addresses of the PHYs start at multiples of 8 */
3753 devm_phy_package_join(dev, phydev, addr & (~7),
3754 sizeof(struct rtl83xx_shared_private));
3755
3756 if (!(addr % 8)) {
3757 struct rtl83xx_shared_private *shared = phydev->shared->priv;
3758 shared->name = "RTL8218B (external)";
3759 if (soc_info.family == RTL8380_FAMILY_ID) {
3760 /* Configuration must be done while patching still possible */
3761 return rtl8380_configure_ext_rtl8218b(phydev);
3762 }
3763 }
3764
3765 return 0;
3766 }
3767
3768 static int rtl8218b_int_phy_probe(struct phy_device *phydev)
3769 {
3770 struct device *dev = &phydev->mdio.dev;
3771 int addr = phydev->mdio.addr;
3772
3773 if (soc_info.family != RTL8380_FAMILY_ID)
3774 return -ENODEV;
3775 if (addr >= 24)
3776 return -ENODEV;
3777
3778 pr_debug("%s: id: %d\n", __func__, addr);
3779 /* All base addresses of the PHYs start at multiples of 8 */
3780 devm_phy_package_join(dev, phydev, addr & (~7),
3781 sizeof(struct rtl83xx_shared_private));
3782
3783 if (!(addr % 8)) {
3784 struct rtl83xx_shared_private *shared = phydev->shared->priv;
3785 shared->name = "RTL8218B (internal)";
3786 /* Configuration must be done while patching still possible */
3787 return rtl8380_configure_int_rtl8218b(phydev);
3788 }
3789
3790 return 0;
3791 }
3792
3793 static int rtl8218d_phy_probe(struct phy_device *phydev)
3794 {
3795 struct device *dev = &phydev->mdio.dev;
3796 int addr = phydev->mdio.addr;
3797
3798 pr_debug("%s: id: %d\n", __func__, addr);
3799 /* All base addresses of the PHYs start at multiples of 8 */
3800 devm_phy_package_join(dev, phydev, addr & (~7),
3801 sizeof(struct rtl83xx_shared_private));
3802
3803 /* All base addresses of the PHYs start at multiples of 8 */
3804 if (!(addr % 8)) {
3805 struct rtl83xx_shared_private *shared = phydev->shared->priv;
3806 shared->name = "RTL8218D";
3807 /* Configuration must be done while patching still possible */
3808 // TODO: return configure_rtl8218d(phydev);
3809 }
3810 return 0;
3811 }
3812
3813 static int rtl838x_serdes_probe(struct phy_device *phydev)
3814 {
3815 int addr = phydev->mdio.addr;
3816
3817 if (soc_info.family != RTL8380_FAMILY_ID)
3818 return -ENODEV;
3819 if (addr < 24)
3820 return -ENODEV;
3821
3822 /* On the RTL8380M, PHYs 24-27 connect to the internal SerDes */
3823 if (soc_info.id == 0x8380) {
3824 if (addr == 24)
3825 return rtl8380_configure_serdes(phydev);
3826 return 0;
3827 }
3828 return -ENODEV;
3829 }
3830
3831 static int rtl8393_serdes_probe(struct phy_device *phydev)
3832 {
3833 int addr = phydev->mdio.addr;
3834
3835 pr_info("%s: id: %d\n", __func__, addr);
3836 if (soc_info.family != RTL8390_FAMILY_ID)
3837 return -ENODEV;
3838
3839 if (addr < 24)
3840 return -ENODEV;
3841
3842 return rtl8390_configure_serdes(phydev);
3843 }
3844
3845 static int rtl8390_serdes_probe(struct phy_device *phydev)
3846 {
3847 int addr = phydev->mdio.addr;
3848
3849 if (soc_info.family != RTL8390_FAMILY_ID)
3850 return -ENODEV;
3851
3852 if (addr < 24)
3853 return -ENODEV;
3854
3855 return rtl8390_configure_generic(phydev);
3856 }
3857
3858 static int rtl9300_serdes_probe(struct phy_device *phydev)
3859 {
3860 if (soc_info.family != RTL9300_FAMILY_ID)
3861 return -ENODEV;
3862
3863 phydev_info(phydev, "Detected internal RTL9300 Serdes\n");
3864
3865 return rtl9300_configure_serdes(phydev);
3866 }
3867
3868 static struct phy_driver rtl83xx_phy_driver[] = {
3869 {
3870 PHY_ID_MATCH_MODEL(PHY_ID_RTL8214C),
3871 .name = "Realtek RTL8214C",
3872 .features = PHY_GBIT_FEATURES,
3873 .flags = PHY_HAS_REALTEK_PAGES,
3874 .match_phy_device = rtl8214c_match_phy_device,
3875 .probe = rtl8214c_phy_probe,
3876 .suspend = genphy_suspend,
3877 .resume = genphy_resume,
3878 .set_loopback = genphy_loopback,
3879 },
3880 {
3881 PHY_ID_MATCH_MODEL(PHY_ID_RTL8214FC),
3882 .name = "Realtek RTL8214FC",
3883 .features = PHY_GBIT_FIBRE_FEATURES,
3884 .flags = PHY_HAS_REALTEK_PAGES,
3885 .match_phy_device = rtl8214fc_match_phy_device,
3886 .probe = rtl8214fc_phy_probe,
3887 .suspend = rtl8214fc_suspend,
3888 .resume = rtl8214fc_resume,
3889 .set_loopback = genphy_loopback,
3890 .set_port = rtl8214fc_set_port,
3891 .get_port = rtl8214fc_get_port,
3892 .set_eee = rtl8214fc_set_eee,
3893 .get_eee = rtl8214fc_get_eee,
3894 },
3895 {
3896 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_E),
3897 .name = "Realtek RTL8218B (external)",
3898 .features = PHY_GBIT_FEATURES,
3899 .flags = PHY_HAS_REALTEK_PAGES,
3900 .match_phy_device = rtl8218b_ext_match_phy_device,
3901 .probe = rtl8218b_ext_phy_probe,
3902 .suspend = genphy_suspend,
3903 .resume = genphy_resume,
3904 .set_loopback = genphy_loopback,
3905 .set_eee = rtl8218b_set_eee,
3906 .get_eee = rtl8218b_get_eee,
3907 },
3908 {
3909 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218D),
3910 .name = "REALTEK RTL8218D",
3911 .features = PHY_GBIT_FEATURES,
3912 .flags = PHY_HAS_REALTEK_PAGES,
3913 .probe = rtl8218d_phy_probe,
3914 .suspend = genphy_suspend,
3915 .resume = genphy_resume,
3916 .set_loopback = genphy_loopback,
3917 .set_eee = rtl8218d_set_eee,
3918 .get_eee = rtl8218d_get_eee,
3919 },
3920 {
3921 PHY_ID_MATCH_MODEL(PHY_ID_RTL8221B),
3922 .name = "REALTEK RTL8221B",
3923 .features = PHY_GBIT_FEATURES,
3924 .flags = PHY_HAS_REALTEK_PAGES,
3925 .suspend = genphy_suspend,
3926 .resume = genphy_resume,
3927 .set_loopback = genphy_loopback,
3928 .read_page = rtl8226_read_page,
3929 .write_page = rtl8226_write_page,
3930 .read_status = rtl8226_read_status,
3931 .config_aneg = rtl8226_config_aneg,
3932 .set_eee = rtl8226_set_eee,
3933 .get_eee = rtl8226_get_eee,
3934 },
3935 {
3936 PHY_ID_MATCH_MODEL(PHY_ID_RTL8226),
3937 .name = "REALTEK RTL8226",
3938 .features = PHY_GBIT_FEATURES,
3939 .flags = PHY_HAS_REALTEK_PAGES,
3940 .suspend = genphy_suspend,
3941 .resume = genphy_resume,
3942 .set_loopback = genphy_loopback,
3943 .read_page = rtl8226_read_page,
3944 .write_page = rtl8226_write_page,
3945 .read_status = rtl8226_read_status,
3946 .config_aneg = rtl8226_config_aneg,
3947 .set_eee = rtl8226_set_eee,
3948 .get_eee = rtl8226_get_eee,
3949 },
3950 {
3951 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_I),
3952 .name = "Realtek RTL8218B (internal)",
3953 .features = PHY_GBIT_FEATURES,
3954 .flags = PHY_HAS_REALTEK_PAGES,
3955 .probe = rtl8218b_int_phy_probe,
3956 .suspend = genphy_suspend,
3957 .resume = genphy_resume,
3958 .set_loopback = genphy_loopback,
3959 .set_eee = rtl8218b_set_eee,
3960 .get_eee = rtl8218b_get_eee,
3961 },
3962 {
3963 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_I),
3964 .name = "Realtek RTL8380 SERDES",
3965 .features = PHY_GBIT_FIBRE_FEATURES,
3966 .flags = PHY_HAS_REALTEK_PAGES,
3967 .probe = rtl838x_serdes_probe,
3968 .suspend = genphy_suspend,
3969 .resume = genphy_resume,
3970 .set_loopback = genphy_loopback,
3971 .read_status = rtl8380_read_status,
3972 },
3973 {
3974 PHY_ID_MATCH_MODEL(PHY_ID_RTL8393_I),
3975 .name = "Realtek RTL8393 SERDES",
3976 .features = PHY_GBIT_FIBRE_FEATURES,
3977 .flags = PHY_HAS_REALTEK_PAGES,
3978 .probe = rtl8393_serdes_probe,
3979 .suspend = genphy_suspend,
3980 .resume = genphy_resume,
3981 .set_loopback = genphy_loopback,
3982 .read_status = rtl8393_read_status,
3983 },
3984 {
3985 PHY_ID_MATCH_MODEL(PHY_ID_RTL8390_GENERIC),
3986 .name = "Realtek RTL8390 Generic",
3987 .features = PHY_GBIT_FIBRE_FEATURES,
3988 .flags = PHY_HAS_REALTEK_PAGES,
3989 .probe = rtl8390_serdes_probe,
3990 .suspend = genphy_suspend,
3991 .resume = genphy_resume,
3992 .set_loopback = genphy_loopback,
3993 },
3994 {
3995 PHY_ID_MATCH_MODEL(PHY_ID_RTL9300_I),
3996 .name = "REALTEK RTL9300 SERDES",
3997 .features = PHY_GBIT_FIBRE_FEATURES,
3998 .flags = PHY_HAS_REALTEK_PAGES,
3999 .probe = rtl9300_serdes_probe,
4000 .suspend = genphy_suspend,
4001 .resume = genphy_resume,
4002 .set_loopback = genphy_loopback,
4003 .read_status = rtl9300_read_status,
4004 },
4005 };
4006
4007 module_phy_driver(rtl83xx_phy_driver);
4008
4009 static struct mdio_device_id __maybe_unused rtl83xx_tbl[] = {
4010 { PHY_ID_MATCH_MODEL(PHY_ID_RTL8214FC) },
4011 { }
4012 };
4013
4014 MODULE_DEVICE_TABLE(mdio, rtl83xx_tbl);
4015
4016 MODULE_AUTHOR("B. Koblitz");
4017 MODULE_DESCRIPTION("RTL83xx PHY driver");
4018 MODULE_LICENSE("GPL");
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