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aece1356e40cf307d1fa92005f1d53a5c948c076
[openwrt/staging/stintel.git] / target / linux / realtek / files-5.10 / drivers / net / ethernet / rtl838x_eth.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * linux/drivers/net/ethernet/rtl838x_eth.c
4 * Copyright (C) 2020 B. Koblitz
5 */
6
7 #include <linux/dma-mapping.h>
8 #include <linux/etherdevice.h>
9 #include <linux/interrupt.h>
10 #include <linux/io.h>
11 #include <linux/platform_device.h>
12 #include <linux/sched.h>
13 #include <linux/slab.h>
14 #include <linux/of.h>
15 #include <linux/of_net.h>
16 #include <linux/of_mdio.h>
17 #include <linux/module.h>
18 #include <linux/phylink.h>
19 #include <linux/pkt_sched.h>
20 #include <net/dsa.h>
21 #include <net/switchdev.h>
22 #include <asm/cacheflush.h>
23
24 #include <asm/mach-rtl838x/mach-rtl83xx.h>
25 #include "rtl838x_eth.h"
26
27 extern struct rtl83xx_soc_info soc_info;
28
29 /*
30 * Maximum number of RX rings is 8 on RTL83XX and 32 on the 93XX
31 * The ring is assigned by switch based on packet/port priortity
32 * Maximum number of TX rings is 2, Ring 2 being the high priority
33 * ring on the RTL93xx SoCs. MAX_RXLEN gives the maximum length
34 * for an RX ring, MAX_ENTRIES the maximum number of entries
35 * available in total for all queues.
36 */
37 #define MAX_RXRINGS 32
38 #define MAX_RXLEN 300
39 #define MAX_ENTRIES (300 * 8)
40 #define TXRINGS 2
41 #define TXRINGLEN 160
42 #define NOTIFY_EVENTS 10
43 #define NOTIFY_BLOCKS 10
44 #define TX_EN 0x8
45 #define RX_EN 0x4
46 #define TX_EN_93XX 0x20
47 #define RX_EN_93XX 0x10
48 #define TX_DO 0x2
49 #define WRAP 0x2
50 #define MAX_PORTS 57
51 #define MAX_SMI_BUSSES 4
52
53 #define RING_BUFFER 1600
54
55 struct p_hdr {
56 uint8_t *buf;
57 uint16_t reserved;
58 uint16_t size; /* buffer size */
59 uint16_t offset;
60 uint16_t len; /* pkt len */
61 uint16_t cpu_tag[10];
62 } __packed __aligned(1);
63
64 struct n_event {
65 uint32_t type:2;
66 uint32_t fidVid:12;
67 uint64_t mac:48;
68 uint32_t slp:6;
69 uint32_t valid:1;
70 uint32_t reserved:27;
71 } __packed __aligned(1);
72
73 struct ring_b {
74 uint32_t rx_r[MAX_RXRINGS][MAX_RXLEN];
75 uint32_t tx_r[TXRINGS][TXRINGLEN];
76 struct p_hdr rx_header[MAX_RXRINGS][MAX_RXLEN];
77 struct p_hdr tx_header[TXRINGS][TXRINGLEN];
78 uint32_t c_rx[MAX_RXRINGS];
79 uint32_t c_tx[TXRINGS];
80 uint8_t tx_space[TXRINGS * TXRINGLEN * RING_BUFFER];
81 uint8_t *rx_space;
82 };
83
84 struct notify_block {
85 struct n_event events[NOTIFY_EVENTS];
86 };
87
88 struct notify_b {
89 struct notify_block blocks[NOTIFY_BLOCKS];
90 u32 reserved1[8];
91 u32 ring[NOTIFY_BLOCKS];
92 u32 reserved2[8];
93 };
94
95 static void rtl838x_create_tx_header(struct p_hdr *h, int dest_port, int prio)
96 {
97 prio &= 0x7;
98
99 if (dest_port > 0) {
100 // cpu_tag[0] is reserved on the RTL83XX SoCs
101 h->cpu_tag[1] = 0x0401; // BIT 10: RTL8380_CPU_TAG, BIT0: L2LEARNING on
102 h->cpu_tag[2] = 0x0200; // Set only AS_DPM, to enable DPM settings below
103 h->cpu_tag[3] = 0x0000;
104 h->cpu_tag[4] = BIT(dest_port) >> 16;
105 h->cpu_tag[5] = BIT(dest_port) & 0xffff;
106 // Set internal priority and AS_PRIO
107 if (prio >= 0)
108 h->cpu_tag[2] |= (prio | 0x8) << 12;
109 }
110 }
111
112 static void rtl839x_create_tx_header(struct p_hdr *h, int dest_port, int prio)
113 {
114 prio &= 0x7;
115
116 if (dest_port > 0) {
117 // cpu_tag[0] is reserved on the RTL83XX SoCs
118 h->cpu_tag[1] = 0x0100; // RTL8390_CPU_TAG marker
119 h->cpu_tag[2] = h->cpu_tag[3] = h->cpu_tag[4] = h->cpu_tag[5] = 0;
120 // h->cpu_tag[1] |= BIT(1) | BIT(0); // Bypass filter 1/2
121 if (dest_port >= 32) {
122 dest_port -= 32;
123 h->cpu_tag[2] = BIT(dest_port) >> 16;
124 h->cpu_tag[3] = BIT(dest_port) & 0xffff;
125 } else {
126 h->cpu_tag[4] = BIT(dest_port) >> 16;
127 h->cpu_tag[5] = BIT(dest_port) & 0xffff;
128 }
129 h->cpu_tag[2] |= BIT(4); // Enable destination port mask use
130 h->cpu_tag[2] |= BIT(8); // Enable L2 Learning
131 // Set internal priority and AS_PRIO
132 if (prio >= 0)
133 h->cpu_tag[1] |= prio | BIT(3);
134 }
135 }
136
137 static void rtl930x_create_tx_header(struct p_hdr *h, int dest_port, int prio)
138 {
139 h->cpu_tag[0] = 0x8000; // CPU tag marker
140 h->cpu_tag[1] = h->cpu_tag[2] = 0;
141 if (prio >= 0)
142 h->cpu_tag[2] = BIT(13) | prio << 8; // Enable and set Priority Queue
143 h->cpu_tag[3] = 0;
144 h->cpu_tag[4] = 0;
145 h->cpu_tag[5] = 0;
146 h->cpu_tag[6] = BIT(dest_port) >> 16;
147 h->cpu_tag[7] = BIT(dest_port) & 0xffff;
148 }
149
150 static void rtl931x_create_tx_header(struct p_hdr *h, int dest_port, int prio)
151 {
152 h->cpu_tag[0] = 0x8000; // CPU tag marker
153 h->cpu_tag[1] = h->cpu_tag[2] = 0;
154 if (prio >= 0)
155 h->cpu_tag[2] = BIT(13) | prio << 8; // Enable and set Priority Queue
156 h->cpu_tag[3] = 0;
157 h->cpu_tag[4] = h->cpu_tag[5] = h->cpu_tag[6] = h->cpu_tag[7] = 0;
158 if (dest_port >= 32) {
159 dest_port -= 32;
160 h->cpu_tag[4] = BIT(dest_port) >> 16;
161 h->cpu_tag[5] = BIT(dest_port) & 0xffff;
162 } else {
163 h->cpu_tag[6] = BIT(dest_port) >> 16;
164 h->cpu_tag[7] = BIT(dest_port) & 0xffff;
165 }
166 }
167
168 static void rtl93xx_header_vlan_set(struct p_hdr *h, int vlan)
169 {
170 h->cpu_tag[2] |= BIT(4); // Enable VLAN forwarding offload
171 h->cpu_tag[2] |= (vlan >> 8) & 0xf;
172 h->cpu_tag[3] |= (vlan & 0xff) << 8;
173 }
174
175 struct rtl838x_rx_q {
176 int id;
177 struct rtl838x_eth_priv *priv;
178 struct napi_struct napi;
179 };
180
181 struct rtl838x_eth_priv {
182 struct net_device *netdev;
183 struct platform_device *pdev;
184 void *membase;
185 spinlock_t lock;
186 struct mii_bus *mii_bus;
187 struct rtl838x_rx_q rx_qs[MAX_RXRINGS];
188 struct phylink *phylink;
189 struct phylink_config phylink_config;
190 u16 id;
191 u16 family_id;
192 const struct rtl838x_eth_reg *r;
193 u8 cpu_port;
194 u32 lastEvent;
195 u16 rxrings;
196 u16 rxringlen;
197 u8 smi_bus[MAX_PORTS];
198 u8 smi_addr[MAX_PORTS];
199 u32 sds_id[MAX_PORTS];
200 bool smi_bus_isc45[MAX_SMI_BUSSES];
201 bool phy_is_internal[MAX_PORTS];
202 phy_interface_t interfaces[MAX_PORTS];
203 };
204
205 extern int rtl838x_phy_init(struct rtl838x_eth_priv *priv);
206 extern int rtl838x_read_sds_phy(int phy_addr, int phy_reg);
207 extern int rtl839x_read_sds_phy(int phy_addr, int phy_reg);
208 extern int rtl839x_write_sds_phy(int phy_addr, int phy_reg, u16 v);
209 extern int rtl930x_read_sds_phy(int phy_addr, int page, int phy_reg);
210 extern int rtl930x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v);
211 extern int rtl931x_read_sds_phy(int phy_addr, int page, int phy_reg);
212 extern int rtl931x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v);
213 extern int rtl930x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val);
214 extern int rtl930x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val);
215 extern int rtl931x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val);
216 extern int rtl931x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val);
217
218 /*
219 * On the RTL93XX, the RTL93XX_DMA_IF_RX_RING_CNTR track the fill level of
220 * the rings. Writing x into these registers substracts x from its content.
221 * When the content reaches the ring size, the ASIC no longer adds
222 * packets to this receive queue.
223 */
224 void rtl838x_update_cntr(int r, int released)
225 {
226 // This feature is not available on RTL838x SoCs
227 }
228
229 void rtl839x_update_cntr(int r, int released)
230 {
231 // This feature is not available on RTL839x SoCs
232 }
233
234 void rtl930x_update_cntr(int r, int released)
235 {
236 int pos = (r % 3) * 10;
237 u32 reg = RTL930X_DMA_IF_RX_RING_CNTR + ((r / 3) << 2);
238 u32 v = sw_r32(reg);
239
240 v = (v >> pos) & 0x3ff;
241 pr_debug("RX: Work done %d, old value: %d, pos %d, reg %04x\n", released, v, pos, reg);
242 sw_w32_mask(0x3ff << pos, released << pos, reg);
243 sw_w32(v, reg);
244 }
245
246 void rtl931x_update_cntr(int r, int released)
247 {
248 int pos = (r % 3) * 10;
249 u32 reg = RTL931X_DMA_IF_RX_RING_CNTR + ((r / 3) << 2);
250 u32 v = sw_r32(reg);
251
252 v = (v >> pos) & 0x3ff;
253 sw_w32_mask(0x3ff << pos, released << pos, reg);
254 sw_w32(v, reg);
255 }
256
257 struct dsa_tag {
258 u8 reason;
259 u8 queue;
260 u16 port;
261 u8 l2_offloaded;
262 u8 prio;
263 bool crc_error;
264 };
265
266 bool rtl838x_decode_tag(struct p_hdr *h, struct dsa_tag *t)
267 {
268 t->reason = h->cpu_tag[3] & 0xf;
269 t->queue = (h->cpu_tag[0] & 0xe0) >> 5;
270 t->port = h->cpu_tag[1] & 0x1f;
271 t->crc_error = t->reason == 13;
272
273 pr_debug("Reason: %d\n", t->reason);
274 if (t->reason != 4) // NIC_RX_REASON_SPECIAL_TRAP
275 t->l2_offloaded = 1;
276 else
277 t->l2_offloaded = 0;
278
279 return t->l2_offloaded;
280 }
281
282 bool rtl839x_decode_tag(struct p_hdr *h, struct dsa_tag *t)
283 {
284 t->reason = h->cpu_tag[5] & 0x1f;
285 t->queue = (h->cpu_tag[3] & 0xe000) >> 13;
286 t->port = h->cpu_tag[1] & 0x3f;
287 t->crc_error = h->cpu_tag[3] & BIT(2);
288
289 pr_debug("Reason: %d\n", t->reason);
290 if ((t->reason >= 7 && t->reason <= 13) || // NIC_RX_REASON_RMA
291 (t->reason >= 23 && t->reason <= 25)) // NIC_RX_REASON_SPECIAL_TRAP
292 t->l2_offloaded = 0;
293 else
294 t->l2_offloaded = 1;
295
296 return t->l2_offloaded;
297 }
298
299 bool rtl930x_decode_tag(struct p_hdr *h, struct dsa_tag *t)
300 {
301 t->reason = h->cpu_tag[7] & 0x3f;
302 t->queue = (h->cpu_tag[2] >> 11) & 0x1f;
303 t->port = (h->cpu_tag[0] >> 8) & 0x1f;
304 t->crc_error = h->cpu_tag[1] & BIT(6);
305
306 pr_debug("Reason %d, port %d, queue %d\n", t->reason, t->port, t->queue);
307 if (t->reason >= 19 && t->reason <= 27)
308 t->l2_offloaded = 0;
309 else
310 t->l2_offloaded = 1;
311
312 return t->l2_offloaded;
313 }
314
315 bool rtl931x_decode_tag(struct p_hdr *h, struct dsa_tag *t)
316 {
317 t->reason = h->cpu_tag[7] & 0x3f;
318 t->queue = (h->cpu_tag[2] >> 11) & 0x1f;
319 t->port = (h->cpu_tag[0] >> 8) & 0x3f;
320 t->crc_error = h->cpu_tag[1] & BIT(6);
321
322 if (t->reason != 63)
323 pr_info("%s: Reason %d, port %d, queue %d\n", __func__, t->reason, t->port, t->queue);
324 if (t->reason >= 19 && t->reason <= 27) // NIC_RX_REASON_RMA
325 t->l2_offloaded = 0;
326 else
327 t->l2_offloaded = 1;
328
329 return t->l2_offloaded;
330 }
331
332 /*
333 * Discard the RX ring-buffers, called as part of the net-ISR
334 * when the buffer runs over
335 */
336 static void rtl838x_rb_cleanup(struct rtl838x_eth_priv *priv, int status)
337 {
338 int r;
339 u32 *last;
340 struct p_hdr *h;
341 struct ring_b *ring = priv->membase;
342
343 for (r = 0; r < priv->rxrings; r++) {
344 pr_debug("In %s working on r: %d\n", __func__, r);
345 last = (u32 *)KSEG1ADDR(sw_r32(priv->r->dma_if_rx_cur + r * 4));
346 do {
347 if ((ring->rx_r[r][ring->c_rx[r]] & 0x1))
348 break;
349 pr_debug("Got something: %d\n", ring->c_rx[r]);
350 h = &ring->rx_header[r][ring->c_rx[r]];
351 memset(h, 0, sizeof(struct p_hdr));
352 h->buf = (u8 *)KSEG1ADDR(ring->rx_space
353 + r * priv->rxringlen * RING_BUFFER
354 + ring->c_rx[r] * RING_BUFFER);
355 h->size = RING_BUFFER;
356 /* make sure the header is visible to the ASIC */
357 mb();
358
359 ring->rx_r[r][ring->c_rx[r]] = KSEG1ADDR(h) | 0x1
360 | (ring->c_rx[r] == (priv->rxringlen - 1) ? WRAP : 0x1);
361 ring->c_rx[r] = (ring->c_rx[r] + 1) % priv->rxringlen;
362 } while (&ring->rx_r[r][ring->c_rx[r]] != last);
363 }
364 }
365
366 struct fdb_update_work {
367 struct work_struct work;
368 struct net_device *ndev;
369 u64 macs[NOTIFY_EVENTS + 1];
370 };
371
372 void rtl838x_fdb_sync(struct work_struct *work)
373 {
374 const struct fdb_update_work *uw =
375 container_of(work, struct fdb_update_work, work);
376 struct switchdev_notifier_fdb_info info;
377 u8 addr[ETH_ALEN];
378 int i = 0;
379 int action;
380
381 while (uw->macs[i]) {
382 action = (uw->macs[i] & (1ULL << 63)) ? SWITCHDEV_FDB_ADD_TO_BRIDGE
383 : SWITCHDEV_FDB_DEL_TO_BRIDGE;
384 u64_to_ether_addr(uw->macs[i] & 0xffffffffffffULL, addr);
385 info.addr = &addr[0];
386 info.vid = 0;
387 info.offloaded = 1;
388 pr_debug("FDB entry %d: %llx, action %d\n", i, uw->macs[0], action);
389 call_switchdev_notifiers(action, uw->ndev, &info.info, NULL);
390 i++;
391 }
392 kfree(work);
393 }
394
395 static void rtl839x_l2_notification_handler(struct rtl838x_eth_priv *priv)
396 {
397 struct notify_b *nb = priv->membase + sizeof(struct ring_b);
398 u32 e = priv->lastEvent;
399 struct n_event *event;
400 int i;
401 u64 mac;
402 struct fdb_update_work *w;
403
404 while (!(nb->ring[e] & 1)) {
405 w = kzalloc(sizeof(*w), GFP_ATOMIC);
406 if (!w) {
407 pr_err("Out of memory: %s", __func__);
408 return;
409 }
410 INIT_WORK(&w->work, rtl838x_fdb_sync);
411
412 for (i = 0; i < NOTIFY_EVENTS; i++) {
413 event = &nb->blocks[e].events[i];
414 if (!event->valid)
415 continue;
416 mac = event->mac;
417 if (event->type)
418 mac |= 1ULL << 63;
419 w->ndev = priv->netdev;
420 w->macs[i] = mac;
421 }
422
423 /* Hand the ring entry back to the switch */
424 nb->ring[e] = nb->ring[e] | 1;
425 e = (e + 1) % NOTIFY_BLOCKS;
426
427 w->macs[i] = 0ULL;
428 schedule_work(&w->work);
429 }
430 priv->lastEvent = e;
431 }
432
433 static irqreturn_t rtl83xx_net_irq(int irq, void *dev_id)
434 {
435 struct net_device *dev = dev_id;
436 struct rtl838x_eth_priv *priv = netdev_priv(dev);
437 u32 status = sw_r32(priv->r->dma_if_intr_sts);
438 int i;
439
440 pr_debug("IRQ: %08x\n", status);
441
442 /* Ignore TX interrupt */
443 if ((status & 0xf0000)) {
444 /* Clear ISR */
445 sw_w32(0x000f0000, priv->r->dma_if_intr_sts);
446 }
447
448 /* RX interrupt */
449 if (status & 0x0ff00) {
450 /* ACK and disable RX interrupt for this ring */
451 sw_w32_mask(0xff00 & status, 0, priv->r->dma_if_intr_msk);
452 sw_w32(0x0000ff00 & status, priv->r->dma_if_intr_sts);
453 for (i = 0; i < priv->rxrings; i++) {
454 if (status & BIT(i + 8)) {
455 pr_debug("Scheduling queue: %d\n", i);
456 napi_schedule(&priv->rx_qs[i].napi);
457 }
458 }
459 }
460
461 /* RX buffer overrun */
462 if (status & 0x000ff) {
463 pr_debug("RX buffer overrun: status %x, mask: %x\n",
464 status, sw_r32(priv->r->dma_if_intr_msk));
465 sw_w32(status, priv->r->dma_if_intr_sts);
466 rtl838x_rb_cleanup(priv, status & 0xff);
467 }
468
469 if (priv->family_id == RTL8390_FAMILY_ID && status & 0x00100000) {
470 sw_w32(0x00100000, priv->r->dma_if_intr_sts);
471 rtl839x_l2_notification_handler(priv);
472 }
473
474 if (priv->family_id == RTL8390_FAMILY_ID && status & 0x00200000) {
475 sw_w32(0x00200000, priv->r->dma_if_intr_sts);
476 rtl839x_l2_notification_handler(priv);
477 }
478
479 if (priv->family_id == RTL8390_FAMILY_ID && status & 0x00400000) {
480 sw_w32(0x00400000, priv->r->dma_if_intr_sts);
481 rtl839x_l2_notification_handler(priv);
482 }
483
484 return IRQ_HANDLED;
485 }
486
487 static irqreturn_t rtl93xx_net_irq(int irq, void *dev_id)
488 {
489 struct net_device *dev = dev_id;
490 struct rtl838x_eth_priv *priv = netdev_priv(dev);
491 u32 status_rx_r = sw_r32(priv->r->dma_if_intr_rx_runout_sts);
492 u32 status_rx = sw_r32(priv->r->dma_if_intr_rx_done_sts);
493 u32 status_tx = sw_r32(priv->r->dma_if_intr_tx_done_sts);
494 int i;
495
496 pr_debug("In %s, status_tx: %08x, status_rx: %08x, status_rx_r: %08x\n",
497 __func__, status_tx, status_rx, status_rx_r);
498
499 /* Ignore TX interrupt */
500 if (status_tx) {
501 /* Clear ISR */
502 pr_debug("TX done\n");
503 sw_w32(status_tx, priv->r->dma_if_intr_tx_done_sts);
504 }
505
506 /* RX interrupt */
507 if (status_rx) {
508 pr_debug("RX IRQ\n");
509 /* ACK and disable RX interrupt for given rings */
510 sw_w32(status_rx, priv->r->dma_if_intr_rx_done_sts);
511 sw_w32_mask(status_rx, 0, priv->r->dma_if_intr_rx_done_msk);
512 for (i = 0; i < priv->rxrings; i++) {
513 if (status_rx & BIT(i)) {
514 pr_debug("Scheduling queue: %d\n", i);
515 napi_schedule(&priv->rx_qs[i].napi);
516 }
517 }
518 }
519
520 /* RX buffer overrun */
521 if (status_rx_r) {
522 pr_debug("RX buffer overrun: status %x, mask: %x\n",
523 status_rx_r, sw_r32(priv->r->dma_if_intr_rx_runout_msk));
524 sw_w32(status_rx_r, priv->r->dma_if_intr_rx_runout_sts);
525 rtl838x_rb_cleanup(priv, status_rx_r);
526 }
527
528 return IRQ_HANDLED;
529 }
530
531 static const struct rtl838x_eth_reg rtl838x_reg = {
532 .net_irq = rtl83xx_net_irq,
533 .mac_port_ctrl = rtl838x_mac_port_ctrl,
534 .dma_if_intr_sts = RTL838X_DMA_IF_INTR_STS,
535 .dma_if_intr_msk = RTL838X_DMA_IF_INTR_MSK,
536 .dma_if_ctrl = RTL838X_DMA_IF_CTRL,
537 .mac_force_mode_ctrl = RTL838X_MAC_FORCE_MODE_CTRL,
538 .dma_rx_base = RTL838X_DMA_RX_BASE,
539 .dma_tx_base = RTL838X_DMA_TX_BASE,
540 .dma_if_rx_ring_size = rtl838x_dma_if_rx_ring_size,
541 .dma_if_rx_ring_cntr = rtl838x_dma_if_rx_ring_cntr,
542 .dma_if_rx_cur = RTL838X_DMA_IF_RX_CUR,
543 .rst_glb_ctrl = RTL838X_RST_GLB_CTRL_0,
544 .get_mac_link_sts = rtl838x_get_mac_link_sts,
545 .get_mac_link_dup_sts = rtl838x_get_mac_link_dup_sts,
546 .get_mac_link_spd_sts = rtl838x_get_mac_link_spd_sts,
547 .get_mac_rx_pause_sts = rtl838x_get_mac_rx_pause_sts,
548 .get_mac_tx_pause_sts = rtl838x_get_mac_tx_pause_sts,
549 .mac = RTL838X_MAC,
550 .l2_tbl_flush_ctrl = RTL838X_L2_TBL_FLUSH_CTRL,
551 .update_cntr = rtl838x_update_cntr,
552 .create_tx_header = rtl838x_create_tx_header,
553 .decode_tag = rtl838x_decode_tag,
554 };
555
556 static const struct rtl838x_eth_reg rtl839x_reg = {
557 .net_irq = rtl83xx_net_irq,
558 .mac_port_ctrl = rtl839x_mac_port_ctrl,
559 .dma_if_intr_sts = RTL839X_DMA_IF_INTR_STS,
560 .dma_if_intr_msk = RTL839X_DMA_IF_INTR_MSK,
561 .dma_if_ctrl = RTL839X_DMA_IF_CTRL,
562 .mac_force_mode_ctrl = RTL839X_MAC_FORCE_MODE_CTRL,
563 .dma_rx_base = RTL839X_DMA_RX_BASE,
564 .dma_tx_base = RTL839X_DMA_TX_BASE,
565 .dma_if_rx_ring_size = rtl839x_dma_if_rx_ring_size,
566 .dma_if_rx_ring_cntr = rtl839x_dma_if_rx_ring_cntr,
567 .dma_if_rx_cur = RTL839X_DMA_IF_RX_CUR,
568 .rst_glb_ctrl = RTL839X_RST_GLB_CTRL,
569 .get_mac_link_sts = rtl839x_get_mac_link_sts,
570 .get_mac_link_dup_sts = rtl839x_get_mac_link_dup_sts,
571 .get_mac_link_spd_sts = rtl839x_get_mac_link_spd_sts,
572 .get_mac_rx_pause_sts = rtl839x_get_mac_rx_pause_sts,
573 .get_mac_tx_pause_sts = rtl839x_get_mac_tx_pause_sts,
574 .mac = RTL839X_MAC,
575 .l2_tbl_flush_ctrl = RTL839X_L2_TBL_FLUSH_CTRL,
576 .update_cntr = rtl839x_update_cntr,
577 .create_tx_header = rtl839x_create_tx_header,
578 .decode_tag = rtl839x_decode_tag,
579 };
580
581 static const struct rtl838x_eth_reg rtl930x_reg = {
582 .net_irq = rtl93xx_net_irq,
583 .mac_port_ctrl = rtl930x_mac_port_ctrl,
584 .dma_if_intr_rx_runout_sts = RTL930X_DMA_IF_INTR_RX_RUNOUT_STS,
585 .dma_if_intr_rx_done_sts = RTL930X_DMA_IF_INTR_RX_DONE_STS,
586 .dma_if_intr_tx_done_sts = RTL930X_DMA_IF_INTR_TX_DONE_STS,
587 .dma_if_intr_rx_runout_msk = RTL930X_DMA_IF_INTR_RX_RUNOUT_MSK,
588 .dma_if_intr_rx_done_msk = RTL930X_DMA_IF_INTR_RX_DONE_MSK,
589 .dma_if_intr_tx_done_msk = RTL930X_DMA_IF_INTR_TX_DONE_MSK,
590 .l2_ntfy_if_intr_sts = RTL930X_L2_NTFY_IF_INTR_STS,
591 .l2_ntfy_if_intr_msk = RTL930X_L2_NTFY_IF_INTR_MSK,
592 .dma_if_ctrl = RTL930X_DMA_IF_CTRL,
593 .mac_force_mode_ctrl = RTL930X_MAC_FORCE_MODE_CTRL,
594 .dma_rx_base = RTL930X_DMA_RX_BASE,
595 .dma_tx_base = RTL930X_DMA_TX_BASE,
596 .dma_if_rx_ring_size = rtl930x_dma_if_rx_ring_size,
597 .dma_if_rx_ring_cntr = rtl930x_dma_if_rx_ring_cntr,
598 .dma_if_rx_cur = RTL930X_DMA_IF_RX_CUR,
599 .rst_glb_ctrl = RTL930X_RST_GLB_CTRL_0,
600 .get_mac_link_sts = rtl930x_get_mac_link_sts,
601 .get_mac_link_dup_sts = rtl930x_get_mac_link_dup_sts,
602 .get_mac_link_spd_sts = rtl930x_get_mac_link_spd_sts,
603 .get_mac_rx_pause_sts = rtl930x_get_mac_rx_pause_sts,
604 .get_mac_tx_pause_sts = rtl930x_get_mac_tx_pause_sts,
605 .mac = RTL930X_MAC_L2_ADDR_CTRL,
606 .l2_tbl_flush_ctrl = RTL930X_L2_TBL_FLUSH_CTRL,
607 .update_cntr = rtl930x_update_cntr,
608 .create_tx_header = rtl930x_create_tx_header,
609 .decode_tag = rtl930x_decode_tag,
610 };
611
612 static const struct rtl838x_eth_reg rtl931x_reg = {
613 .net_irq = rtl93xx_net_irq,
614 .mac_port_ctrl = rtl931x_mac_port_ctrl,
615 .dma_if_intr_rx_runout_sts = RTL931X_DMA_IF_INTR_RX_RUNOUT_STS,
616 .dma_if_intr_rx_done_sts = RTL931X_DMA_IF_INTR_RX_DONE_STS,
617 .dma_if_intr_tx_done_sts = RTL931X_DMA_IF_INTR_TX_DONE_STS,
618 .dma_if_intr_rx_runout_msk = RTL931X_DMA_IF_INTR_RX_RUNOUT_MSK,
619 .dma_if_intr_rx_done_msk = RTL931X_DMA_IF_INTR_RX_DONE_MSK,
620 .dma_if_intr_tx_done_msk = RTL931X_DMA_IF_INTR_TX_DONE_MSK,
621 .l2_ntfy_if_intr_sts = RTL931X_L2_NTFY_IF_INTR_STS,
622 .l2_ntfy_if_intr_msk = RTL931X_L2_NTFY_IF_INTR_MSK,
623 .dma_if_ctrl = RTL931X_DMA_IF_CTRL,
624 .mac_force_mode_ctrl = RTL931X_MAC_FORCE_MODE_CTRL,
625 .dma_rx_base = RTL931X_DMA_RX_BASE,
626 .dma_tx_base = RTL931X_DMA_TX_BASE,
627 .dma_if_rx_ring_size = rtl931x_dma_if_rx_ring_size,
628 .dma_if_rx_ring_cntr = rtl931x_dma_if_rx_ring_cntr,
629 .dma_if_rx_cur = RTL931X_DMA_IF_RX_CUR,
630 .rst_glb_ctrl = RTL931X_RST_GLB_CTRL,
631 .get_mac_link_sts = rtl931x_get_mac_link_sts,
632 .get_mac_link_dup_sts = rtl931x_get_mac_link_dup_sts,
633 .get_mac_link_spd_sts = rtl931x_get_mac_link_spd_sts,
634 .get_mac_rx_pause_sts = rtl931x_get_mac_rx_pause_sts,
635 .get_mac_tx_pause_sts = rtl931x_get_mac_tx_pause_sts,
636 .mac = RTL931X_MAC_L2_ADDR_CTRL,
637 .l2_tbl_flush_ctrl = RTL931X_L2_TBL_FLUSH_CTRL,
638 .update_cntr = rtl931x_update_cntr,
639 .create_tx_header = rtl931x_create_tx_header,
640 .decode_tag = rtl931x_decode_tag,
641 };
642
643 static void rtl838x_hw_reset(struct rtl838x_eth_priv *priv)
644 {
645 u32 int_saved, nbuf;
646 u32 reset_mask;
647 int i, pos;
648
649 pr_info("RESETTING %x, CPU_PORT %d\n", priv->family_id, priv->cpu_port);
650 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(priv->cpu_port));
651 mdelay(100);
652
653 /* Disable and clear interrupts */
654 if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID) {
655 sw_w32(0x00000000, priv->r->dma_if_intr_rx_runout_msk);
656 sw_w32(0xffffffff, priv->r->dma_if_intr_rx_runout_sts);
657 sw_w32(0x00000000, priv->r->dma_if_intr_rx_done_msk);
658 sw_w32(0xffffffff, priv->r->dma_if_intr_rx_done_sts);
659 sw_w32(0x00000000, priv->r->dma_if_intr_tx_done_msk);
660 sw_w32(0x0000000f, priv->r->dma_if_intr_tx_done_sts);
661 } else {
662 sw_w32(0x00000000, priv->r->dma_if_intr_msk);
663 sw_w32(0xffffffff, priv->r->dma_if_intr_sts);
664 }
665
666 if (priv->family_id == RTL8390_FAMILY_ID) {
667 /* Preserve L2 notification and NBUF settings */
668 int_saved = sw_r32(priv->r->dma_if_intr_msk);
669 nbuf = sw_r32(RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL);
670
671 /* Disable link change interrupt on RTL839x */
672 sw_w32(0, RTL839X_IMR_PORT_LINK_STS_CHG);
673 sw_w32(0, RTL839X_IMR_PORT_LINK_STS_CHG + 4);
674
675 sw_w32(0x00000000, priv->r->dma_if_intr_msk);
676 sw_w32(0xffffffff, priv->r->dma_if_intr_sts);
677 }
678
679 /* Reset NIC (SW_NIC_RST) and queues (SW_Q_RST) */
680 if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID)
681 reset_mask = 0x6;
682 else
683 reset_mask = 0xc;
684
685 sw_w32(reset_mask, priv->r->rst_glb_ctrl);
686
687 do { /* Wait for reset of NIC and Queues done */
688 udelay(20);
689 } while (sw_r32(priv->r->rst_glb_ctrl) & reset_mask);
690 mdelay(100);
691
692 /* Setup Head of Line */
693 if (priv->family_id == RTL8380_FAMILY_ID)
694 sw_w32(0, RTL838X_DMA_IF_RX_RING_SIZE); // Disabled on RTL8380
695 if (priv->family_id == RTL8390_FAMILY_ID)
696 sw_w32(0xffffffff, RTL839X_DMA_IF_RX_RING_CNTR);
697 if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID) {
698 for (i = 0; i < priv->rxrings; i++) {
699 pos = (i % 3) * 10;
700 sw_w32_mask(0x3ff << pos, 0, priv->r->dma_if_rx_ring_size(i));
701 sw_w32_mask(0x3ff << pos, priv->rxringlen,
702 priv->r->dma_if_rx_ring_cntr(i));
703 }
704 }
705
706 /* Re-enable link change interrupt */
707 if (priv->family_id == RTL8390_FAMILY_ID) {
708 sw_w32(0xffffffff, RTL839X_ISR_PORT_LINK_STS_CHG);
709 sw_w32(0xffffffff, RTL839X_ISR_PORT_LINK_STS_CHG + 4);
710 sw_w32(0xffffffff, RTL839X_IMR_PORT_LINK_STS_CHG);
711 sw_w32(0xffffffff, RTL839X_IMR_PORT_LINK_STS_CHG + 4);
712
713 /* Restore notification settings: on RTL838x these bits are null */
714 sw_w32_mask(7 << 20, int_saved & (7 << 20), priv->r->dma_if_intr_msk);
715 sw_w32(nbuf, RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL);
716 }
717 }
718
719 static void rtl838x_hw_ring_setup(struct rtl838x_eth_priv *priv)
720 {
721 int i;
722 struct ring_b *ring = priv->membase;
723
724 for (i = 0; i < priv->rxrings; i++)
725 sw_w32(KSEG1ADDR(&ring->rx_r[i]), priv->r->dma_rx_base + i * 4);
726
727 for (i = 0; i < TXRINGS; i++)
728 sw_w32(KSEG1ADDR(&ring->tx_r[i]), priv->r->dma_tx_base + i * 4);
729 }
730
731 static void rtl838x_hw_en_rxtx(struct rtl838x_eth_priv *priv)
732 {
733 /* Disable Head of Line features for all RX rings */
734 sw_w32(0xffffffff, priv->r->dma_if_rx_ring_size(0));
735
736 /* Truncate RX buffer to 0x640 (1600) bytes, pad TX */
737 sw_w32(0x06400020, priv->r->dma_if_ctrl);
738
739 /* Enable RX done, RX overflow and TX done interrupts */
740 sw_w32(0xfffff, priv->r->dma_if_intr_msk);
741
742 /* Enable DMA, engine expects empty FCS field */
743 sw_w32_mask(0, RX_EN | TX_EN, priv->r->dma_if_ctrl);
744
745 /* Restart TX/RX to CPU port */
746 sw_w32_mask(0x0, 0x3, priv->r->mac_port_ctrl(priv->cpu_port));
747 /* Set Speed, duplex, flow control
748 * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
749 * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
750 * | MEDIA_SEL
751 */
752 sw_w32(0x6192F, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
753
754 /* Enable CRC checks on CPU-port */
755 sw_w32_mask(0, BIT(3), priv->r->mac_port_ctrl(priv->cpu_port));
756 }
757
758 static void rtl839x_hw_en_rxtx(struct rtl838x_eth_priv *priv)
759 {
760 /* Setup CPU-Port: RX Buffer */
761 sw_w32(0x0000c808, priv->r->dma_if_ctrl);
762
763 /* Enable Notify, RX done, RX overflow and TX done interrupts */
764 sw_w32(0x007fffff, priv->r->dma_if_intr_msk); // Notify IRQ!
765
766 /* Enable DMA */
767 sw_w32_mask(0, RX_EN | TX_EN, priv->r->dma_if_ctrl);
768
769 /* Restart TX/RX to CPU port, enable CRC checking */
770 sw_w32_mask(0x0, 0x3 | BIT(3), priv->r->mac_port_ctrl(priv->cpu_port));
771
772 /* CPU port joins Lookup Miss Flooding Portmask */
773 // TODO: The code below should also work for the RTL838x
774 sw_w32(0x28000, RTL839X_TBL_ACCESS_L2_CTRL);
775 sw_w32_mask(0, 0x80000000, RTL839X_TBL_ACCESS_L2_DATA(0));
776 sw_w32(0x38000, RTL839X_TBL_ACCESS_L2_CTRL);
777
778 /* Force CPU port link up */
779 sw_w32_mask(0, 3, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
780 }
781
782 static void rtl93xx_hw_en_rxtx(struct rtl838x_eth_priv *priv)
783 {
784 int i, pos;
785 u32 v;
786
787 /* Setup CPU-Port: RX Buffer truncated at 1600 Bytes */
788 sw_w32(0x06400040, priv->r->dma_if_ctrl);
789
790 for (i = 0; i < priv->rxrings; i++) {
791 pos = (i % 3) * 10;
792 sw_w32_mask(0x3ff << pos, priv->rxringlen << pos, priv->r->dma_if_rx_ring_size(i));
793
794 // Some SoCs have issues with missing underflow protection
795 v = (sw_r32(priv->r->dma_if_rx_ring_cntr(i)) >> pos) & 0x3ff;
796 sw_w32_mask(0x3ff << pos, v, priv->r->dma_if_rx_ring_cntr(i));
797 }
798
799 /* Enable Notify, RX done, RX overflow and TX done interrupts */
800 sw_w32(0xffffffff, priv->r->dma_if_intr_rx_runout_msk);
801 sw_w32(0xffffffff, priv->r->dma_if_intr_rx_done_msk);
802 sw_w32(0x0000000f, priv->r->dma_if_intr_tx_done_msk);
803
804 /* Enable DMA */
805 sw_w32_mask(0, RX_EN_93XX | TX_EN_93XX, priv->r->dma_if_ctrl);
806
807 /* Restart TX/RX to CPU port, enable CRC checking */
808 sw_w32_mask(0x0, 0x3 | BIT(4), priv->r->mac_port_ctrl(priv->cpu_port));
809
810 if (priv->family_id == RTL9300_FAMILY_ID)
811 sw_w32_mask(0, BIT(priv->cpu_port), RTL930X_L2_UNKN_UC_FLD_PMSK);
812 else
813 sw_w32_mask(0, BIT(priv->cpu_port), RTL931X_L2_UNKN_UC_FLD_PMSK);
814
815 if (priv->family_id == RTL9300_FAMILY_ID)
816 sw_w32(0x217, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
817 else
818 sw_w32(0x2a1d, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
819 }
820
821 static void rtl838x_setup_ring_buffer(struct rtl838x_eth_priv *priv, struct ring_b *ring)
822 {
823 int i, j;
824
825 struct p_hdr *h;
826
827 for (i = 0; i < priv->rxrings; i++) {
828 for (j = 0; j < priv->rxringlen; j++) {
829 h = &ring->rx_header[i][j];
830 memset(h, 0, sizeof(struct p_hdr));
831 h->buf = (u8 *)KSEG1ADDR(ring->rx_space
832 + i * priv->rxringlen * RING_BUFFER
833 + j * RING_BUFFER);
834 h->size = RING_BUFFER;
835 /* All rings owned by switch, last one wraps */
836 ring->rx_r[i][j] = KSEG1ADDR(h) | 1
837 | (j == (priv->rxringlen - 1) ? WRAP : 0);
838 }
839 ring->c_rx[i] = 0;
840 }
841
842 for (i = 0; i < TXRINGS; i++) {
843 for (j = 0; j < TXRINGLEN; j++) {
844 h = &ring->tx_header[i][j];
845 memset(h, 0, sizeof(struct p_hdr));
846 h->buf = (u8 *)KSEG1ADDR(ring->tx_space
847 + i * TXRINGLEN * RING_BUFFER
848 + j * RING_BUFFER);
849 h->size = RING_BUFFER;
850 ring->tx_r[i][j] = KSEG1ADDR(&ring->tx_header[i][j]);
851 }
852 /* Last header is wrapping around */
853 ring->tx_r[i][j-1] |= WRAP;
854 ring->c_tx[i] = 0;
855 }
856 }
857
858 static void rtl839x_setup_notify_ring_buffer(struct rtl838x_eth_priv *priv)
859 {
860 int i;
861 struct notify_b *b = priv->membase + sizeof(struct ring_b);
862
863 for (i = 0; i < NOTIFY_BLOCKS; i++)
864 b->ring[i] = KSEG1ADDR(&b->blocks[i]) | 1 | (i == (NOTIFY_BLOCKS - 1) ? WRAP : 0);
865
866 sw_w32((u32) b->ring, RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL);
867 sw_w32_mask(0x3ff << 2, 100 << 2, RTL839X_L2_NOTIFICATION_CTRL);
868
869 /* Setup notification events */
870 sw_w32_mask(0, 1 << 14, RTL839X_L2_CTRL_0); // RTL8390_L2_CTRL_0_FLUSH_NOTIFY_EN
871 sw_w32_mask(0, 1 << 12, RTL839X_L2_NOTIFICATION_CTRL); // SUSPEND_NOTIFICATION_EN
872
873 /* Enable Notification */
874 sw_w32_mask(0, 1 << 0, RTL839X_L2_NOTIFICATION_CTRL);
875 priv->lastEvent = 0;
876 }
877
878 static int rtl838x_eth_open(struct net_device *ndev)
879 {
880 unsigned long flags;
881 struct rtl838x_eth_priv *priv = netdev_priv(ndev);
882 struct ring_b *ring = priv->membase;
883 int i;
884
885 pr_debug("%s called: RX rings %d(length %d), TX rings %d(length %d)\n",
886 __func__, priv->rxrings, priv->rxringlen, TXRINGS, TXRINGLEN);
887
888 spin_lock_irqsave(&priv->lock, flags);
889 rtl838x_hw_reset(priv);
890 rtl838x_setup_ring_buffer(priv, ring);
891 if (priv->family_id == RTL8390_FAMILY_ID) {
892 rtl839x_setup_notify_ring_buffer(priv);
893 /* Make sure the ring structure is visible to the ASIC */
894 mb();
895 flush_cache_all();
896 }
897
898 rtl838x_hw_ring_setup(priv);
899 phylink_start(priv->phylink);
900
901 for (i = 0; i < priv->rxrings; i++)
902 napi_enable(&priv->rx_qs[i].napi);
903
904 switch (priv->family_id) {
905 case RTL8380_FAMILY_ID:
906 rtl838x_hw_en_rxtx(priv);
907 /* Trap IGMP/MLD traffic to CPU-Port */
908 sw_w32(0x3, RTL838X_SPCL_TRAP_IGMP_CTRL);
909 /* Flush learned FDB entries on link down of a port */
910 sw_w32_mask(0, BIT(7), RTL838X_L2_CTRL_0);
911 break;
912
913 case RTL8390_FAMILY_ID:
914 rtl839x_hw_en_rxtx(priv);
915 // Trap MLD and IGMP messages to CPU_PORT
916 sw_w32(0x3, RTL839X_SPCL_TRAP_IGMP_CTRL);
917 /* Flush learned FDB entries on link down of a port */
918 sw_w32_mask(0, BIT(7), RTL839X_L2_CTRL_0);
919 break;
920
921 case RTL9300_FAMILY_ID:
922 rtl93xx_hw_en_rxtx(priv);
923 /* Flush learned FDB entries on link down of a port */
924 sw_w32_mask(0, BIT(7), RTL930X_L2_CTRL);
925 // Trap MLD and IGMP messages to CPU_PORT
926 sw_w32((0x2 << 3) | 0x2, RTL930X_VLAN_APP_PKT_CTRL);
927 break;
928
929 case RTL9310_FAMILY_ID:
930 rtl93xx_hw_en_rxtx(priv);
931
932 // Trap MLD and IGMP messages to CPU_PORT
933 sw_w32((0x2 << 3) | 0x2, RTL931X_VLAN_APP_PKT_CTRL);
934
935 // Disable External CPU access to switch, clear EXT_CPU_EN
936 sw_w32_mask(BIT(2), 0, RTL931X_MAC_L2_GLOBAL_CTRL2);
937
938 // Set PCIE_PWR_DOWN
939 sw_w32_mask(0, BIT(1), RTL931X_PS_SOC_CTRL);
940 break;
941 }
942
943 netif_tx_start_all_queues(ndev);
944
945 spin_unlock_irqrestore(&priv->lock, flags);
946
947 return 0;
948 }
949
950 static void rtl838x_hw_stop(struct rtl838x_eth_priv *priv)
951 {
952 u32 force_mac = priv->family_id == RTL8380_FAMILY_ID ? 0x6192C : 0x75;
953 u32 clear_irq = priv->family_id == RTL8380_FAMILY_ID ? 0x000fffff : 0x007fffff;
954 int i;
955
956 // Disable RX/TX from/to CPU-port
957 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(priv->cpu_port));
958
959 /* Disable traffic */
960 if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID)
961 sw_w32_mask(RX_EN_93XX | TX_EN_93XX, 0, priv->r->dma_if_ctrl);
962 else
963 sw_w32_mask(RX_EN | TX_EN, 0, priv->r->dma_if_ctrl);
964 mdelay(200); // Test, whether this is needed
965
966 /* Block all ports */
967 if (priv->family_id == RTL8380_FAMILY_ID) {
968 sw_w32(0x03000000, RTL838X_TBL_ACCESS_DATA_0(0));
969 sw_w32(0x00000000, RTL838X_TBL_ACCESS_DATA_0(1));
970 sw_w32(1 << 15 | 2 << 12, RTL838X_TBL_ACCESS_CTRL_0);
971 }
972
973 /* Flush L2 address cache */
974 if (priv->family_id == RTL8380_FAMILY_ID) {
975 for (i = 0; i <= priv->cpu_port; i++) {
976 sw_w32(1 << 26 | 1 << 23 | i << 5, priv->r->l2_tbl_flush_ctrl);
977 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & (1 << 26));
978 }
979 } else if (priv->family_id == RTL8390_FAMILY_ID) {
980 for (i = 0; i <= priv->cpu_port; i++) {
981 sw_w32(1 << 28 | 1 << 25 | i << 5, priv->r->l2_tbl_flush_ctrl);
982 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & (1 << 28));
983 }
984 }
985 // TODO: L2 flush register is 64 bit on RTL931X and 930X
986
987 /* CPU-Port: Link down */
988 if (priv->family_id == RTL8380_FAMILY_ID || priv->family_id == RTL8390_FAMILY_ID)
989 sw_w32(force_mac, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
990 else if (priv->family_id == RTL9300_FAMILY_ID)
991 sw_w32_mask(0x3, 0, priv->r->mac_force_mode_ctrl + priv->cpu_port *4);
992 else if (priv->family_id == RTL9310_FAMILY_ID)
993 sw_w32_mask(BIT(0) | BIT(9), 0, priv->r->mac_force_mode_ctrl + priv->cpu_port *4);
994 mdelay(100);
995
996 /* Disable all TX/RX interrupts */
997 if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID) {
998 sw_w32(0x00000000, priv->r->dma_if_intr_rx_runout_msk);
999 sw_w32(0xffffffff, priv->r->dma_if_intr_rx_runout_sts);
1000 sw_w32(0x00000000, priv->r->dma_if_intr_rx_done_msk);
1001 sw_w32(0xffffffff, priv->r->dma_if_intr_rx_done_sts);
1002 sw_w32(0x00000000, priv->r->dma_if_intr_tx_done_msk);
1003 sw_w32(0x0000000f, priv->r->dma_if_intr_tx_done_sts);
1004 } else {
1005 sw_w32(0x00000000, priv->r->dma_if_intr_msk);
1006 sw_w32(clear_irq, priv->r->dma_if_intr_sts);
1007 }
1008
1009 /* Disable TX/RX DMA */
1010 sw_w32(0x00000000, priv->r->dma_if_ctrl);
1011 mdelay(200);
1012 }
1013
1014 static int rtl838x_eth_stop(struct net_device *ndev)
1015 {
1016 unsigned long flags;
1017 int i;
1018 struct rtl838x_eth_priv *priv = netdev_priv(ndev);
1019
1020 pr_info("in %s\n", __func__);
1021
1022 phylink_stop(priv->phylink);
1023 rtl838x_hw_stop(priv);
1024
1025 for (i = 0; i < priv->rxrings; i++)
1026 napi_disable(&priv->rx_qs[i].napi);
1027
1028 netif_tx_stop_all_queues(ndev);
1029
1030 return 0;
1031 }
1032
1033 static void rtl839x_eth_set_multicast_list(struct net_device *ndev)
1034 {
1035 if (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) {
1036 sw_w32(0x0, RTL839X_RMA_CTRL_0);
1037 sw_w32(0x0, RTL839X_RMA_CTRL_1);
1038 sw_w32(0x0, RTL839X_RMA_CTRL_2);
1039 sw_w32(0x0, RTL839X_RMA_CTRL_3);
1040 }
1041 if (ndev->flags & IFF_ALLMULTI) {
1042 sw_w32(0x7fffffff, RTL839X_RMA_CTRL_0);
1043 sw_w32(0x7fffffff, RTL839X_RMA_CTRL_1);
1044 sw_w32(0x7fffffff, RTL839X_RMA_CTRL_2);
1045 }
1046 if (ndev->flags & IFF_PROMISC) {
1047 sw_w32(0x7fffffff, RTL839X_RMA_CTRL_0);
1048 sw_w32(0x7fffffff, RTL839X_RMA_CTRL_1);
1049 sw_w32(0x7fffffff, RTL839X_RMA_CTRL_2);
1050 sw_w32(0x3ff, RTL839X_RMA_CTRL_3);
1051 }
1052 }
1053
1054 static void rtl838x_eth_set_multicast_list(struct net_device *ndev)
1055 {
1056 struct rtl838x_eth_priv *priv = netdev_priv(ndev);
1057
1058 if (priv->family_id == RTL8390_FAMILY_ID)
1059 return rtl839x_eth_set_multicast_list(ndev);
1060
1061 if (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) {
1062 sw_w32(0x0, RTL838X_RMA_CTRL_0);
1063 sw_w32(0x0, RTL838X_RMA_CTRL_1);
1064 }
1065 if (ndev->flags & IFF_ALLMULTI)
1066 sw_w32(0x1fffff, RTL838X_RMA_CTRL_0);
1067 if (ndev->flags & IFF_PROMISC) {
1068 sw_w32(0x1fffff, RTL838X_RMA_CTRL_0);
1069 sw_w32(0x7fff, RTL838X_RMA_CTRL_1);
1070 }
1071 }
1072
1073 static void rtl930x_eth_set_multicast_list(struct net_device *ndev)
1074 {
1075 if (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) {
1076 sw_w32(0x0, RTL930X_RMA_CTRL_0);
1077 sw_w32(0x0, RTL930X_RMA_CTRL_1);
1078 sw_w32(0x0, RTL930X_RMA_CTRL_2);
1079 }
1080 if (ndev->flags & IFF_ALLMULTI) {
1081 sw_w32(0x7fffffff, RTL930X_RMA_CTRL_0);
1082 sw_w32(0x7fffffff, RTL930X_RMA_CTRL_1);
1083 sw_w32(0x7fffffff, RTL930X_RMA_CTRL_2);
1084 }
1085 if (ndev->flags & IFF_PROMISC) {
1086 sw_w32(0x7fffffff, RTL930X_RMA_CTRL_0);
1087 sw_w32(0x7fffffff, RTL930X_RMA_CTRL_1);
1088 sw_w32(0x7fffffff, RTL930X_RMA_CTRL_2);
1089 }
1090 }
1091
1092 static void rtl931x_eth_set_multicast_list(struct net_device *ndev)
1093 {
1094 if (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) {
1095 sw_w32(0x0, RTL931X_RMA_CTRL_0);
1096 sw_w32(0x0, RTL931X_RMA_CTRL_1);
1097 sw_w32(0x0, RTL931X_RMA_CTRL_2);
1098 }
1099 if (ndev->flags & IFF_ALLMULTI) {
1100 sw_w32(0x7fffffff, RTL931X_RMA_CTRL_0);
1101 sw_w32(0x7fffffff, RTL931X_RMA_CTRL_1);
1102 sw_w32(0x7fffffff, RTL931X_RMA_CTRL_2);
1103 }
1104 if (ndev->flags & IFF_PROMISC) {
1105 sw_w32(0x7fffffff, RTL931X_RMA_CTRL_0);
1106 sw_w32(0x7fffffff, RTL931X_RMA_CTRL_1);
1107 sw_w32(0x7fffffff, RTL931X_RMA_CTRL_2);
1108 }
1109 }
1110
1111 static void rtl838x_eth_tx_timeout(struct net_device *ndev, unsigned int txqueue)
1112 {
1113 unsigned long flags;
1114 struct rtl838x_eth_priv *priv = netdev_priv(ndev);
1115
1116 pr_warn("%s\n", __func__);
1117 spin_lock_irqsave(&priv->lock, flags);
1118 rtl838x_hw_stop(priv);
1119 rtl838x_hw_ring_setup(priv);
1120 rtl838x_hw_en_rxtx(priv);
1121 netif_trans_update(ndev);
1122 netif_start_queue(ndev);
1123 spin_unlock_irqrestore(&priv->lock, flags);
1124 }
1125
1126 static int rtl838x_eth_tx(struct sk_buff *skb, struct net_device *dev)
1127 {
1128 int len, i;
1129 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1130 struct ring_b *ring = priv->membase;
1131 uint32_t val;
1132 int ret;
1133 unsigned long flags;
1134 struct p_hdr *h;
1135 int dest_port = -1;
1136 int q = skb_get_queue_mapping(skb) % TXRINGS;
1137
1138 if (q) // Check for high prio queue
1139 pr_debug("SKB priority: %d\n", skb->priority);
1140
1141 spin_lock_irqsave(&priv->lock, flags);
1142 len = skb->len;
1143
1144 /* Check for DSA tagging at the end of the buffer */
1145 if (netdev_uses_dsa(dev) && skb->data[len-4] == 0x80 && skb->data[len-3] > 0
1146 && skb->data[len-3] < priv->cpu_port && skb->data[len-2] == 0x10
1147 && skb->data[len-1] == 0x00) {
1148 /* Reuse tag space for CRC if possible */
1149 dest_port = skb->data[len-3];
1150 skb->data[len-4] = skb->data[len-3] = skb->data[len-2] = skb->data[len-1] = 0x00;
1151 len -= 4;
1152 }
1153
1154 len += 4; // Add space for CRC
1155
1156 if (skb_padto(skb, len)) {
1157 ret = NETDEV_TX_OK;
1158 goto txdone;
1159 }
1160
1161 /* We can send this packet if CPU owns the descriptor */
1162 if (!(ring->tx_r[q][ring->c_tx[q]] & 0x1)) {
1163
1164 /* Set descriptor for tx */
1165 h = &ring->tx_header[q][ring->c_tx[q]];
1166 h->size = len;
1167 h->len = len;
1168 // On RTL8380 SoCs, small packet lengths being sent need adjustments
1169 if (priv->family_id == RTL8380_FAMILY_ID) {
1170 if (len < ETH_ZLEN - 4)
1171 h->len -= 4;
1172 }
1173
1174 priv->r->create_tx_header(h, dest_port, skb->priority >> 1);
1175
1176 /* Copy packet data to tx buffer */
1177 memcpy((void *)KSEG1ADDR(h->buf), skb->data, len);
1178 /* Make sure packet data is visible to ASIC */
1179 wmb();
1180
1181 /* Hand over to switch */
1182 ring->tx_r[q][ring->c_tx[q]] |= 1;
1183
1184 // Before starting TX, prevent a Lextra bus bug on RTL8380 SoCs
1185 if (priv->family_id == RTL8380_FAMILY_ID) {
1186 for (i = 0; i < 10; i++) {
1187 val = sw_r32(priv->r->dma_if_ctrl);
1188 if ((val & 0xc) == 0xc)
1189 break;
1190 }
1191 }
1192
1193 /* Tell switch to send data */
1194 if (priv->family_id == RTL9310_FAMILY_ID
1195 || priv->family_id == RTL9300_FAMILY_ID) {
1196 // Ring ID q == 0: Low priority, Ring ID = 1: High prio queue
1197 if (!q)
1198 sw_w32_mask(0, BIT(2), priv->r->dma_if_ctrl);
1199 else
1200 sw_w32_mask(0, BIT(3), priv->r->dma_if_ctrl);
1201 } else {
1202 sw_w32_mask(0, TX_DO, priv->r->dma_if_ctrl);
1203 }
1204
1205 dev->stats.tx_packets++;
1206 dev->stats.tx_bytes += len;
1207 dev_kfree_skb(skb);
1208 ring->c_tx[q] = (ring->c_tx[q] + 1) % TXRINGLEN;
1209 ret = NETDEV_TX_OK;
1210 } else {
1211 dev_warn(&priv->pdev->dev, "Data is owned by switch\n");
1212 ret = NETDEV_TX_BUSY;
1213 }
1214 txdone:
1215 spin_unlock_irqrestore(&priv->lock, flags);
1216 return ret;
1217 }
1218
1219 /*
1220 * Return queue number for TX. On the RTL83XX, these queues have equal priority
1221 * so we do round-robin
1222 */
1223 u16 rtl83xx_pick_tx_queue(struct net_device *dev, struct sk_buff *skb,
1224 struct net_device *sb_dev)
1225 {
1226 static u8 last = 0;
1227
1228 last++;
1229 return last % TXRINGS;
1230 }
1231
1232 /*
1233 * Return queue number for TX. On the RTL93XX, queue 1 is the high priority queue
1234 */
1235 u16 rtl93xx_pick_tx_queue(struct net_device *dev, struct sk_buff *skb,
1236 struct net_device *sb_dev)
1237 {
1238 if (skb->priority >= TC_PRIO_CONTROL)
1239 return 1;
1240 return 0;
1241 }
1242
1243 static int rtl838x_hw_receive(struct net_device *dev, int r, int budget)
1244 {
1245 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1246 struct ring_b *ring = priv->membase;
1247 struct sk_buff *skb;
1248 unsigned long flags;
1249 int i, len, work_done = 0;
1250 u8 *data, *skb_data;
1251 unsigned int val;
1252 u32 *last;
1253 struct p_hdr *h;
1254 bool dsa = netdev_uses_dsa(dev);
1255 struct dsa_tag tag;
1256
1257 pr_debug("---------------------------------------------------------- RX - %d\n", r);
1258 spin_lock_irqsave(&priv->lock, flags);
1259 last = (u32 *)KSEG1ADDR(sw_r32(priv->r->dma_if_rx_cur + r * 4));
1260
1261 do {
1262 if ((ring->rx_r[r][ring->c_rx[r]] & 0x1)) {
1263 if (&ring->rx_r[r][ring->c_rx[r]] != last) {
1264 netdev_warn(dev, "Ring contention: r: %x, last %x, cur %x\n",
1265 r, (uint32_t)last, (u32) &ring->rx_r[r][ring->c_rx[r]]);
1266 }
1267 break;
1268 }
1269
1270 h = &ring->rx_header[r][ring->c_rx[r]];
1271 data = (u8 *)KSEG1ADDR(h->buf);
1272 len = h->len;
1273 if (!len)
1274 break;
1275 work_done++;
1276
1277 len -= 4; /* strip the CRC */
1278 /* Add 4 bytes for cpu_tag */
1279 if (dsa)
1280 len += 4;
1281
1282 skb = netdev_alloc_skb(dev, len + 4);
1283 skb_reserve(skb, NET_IP_ALIGN);
1284
1285 if (likely(skb)) {
1286 /* BUG: Prevent bug on RTL838x SoCs*/
1287 if (priv->family_id == RTL8380_FAMILY_ID) {
1288 sw_w32(0xffffffff, priv->r->dma_if_rx_ring_size(0));
1289 for (i = 0; i < priv->rxrings; i++) {
1290 /* Update each ring cnt */
1291 val = sw_r32(priv->r->dma_if_rx_ring_cntr(i));
1292 sw_w32(val, priv->r->dma_if_rx_ring_cntr(i));
1293 }
1294 }
1295
1296 skb_data = skb_put(skb, len);
1297 /* Make sure data is visible */
1298 mb();
1299 memcpy(skb->data, (u8 *)KSEG1ADDR(data), len);
1300 /* Overwrite CRC with cpu_tag */
1301 if (dsa) {
1302 priv->r->decode_tag(h, &tag);
1303 skb->data[len-4] = 0x80;
1304 skb->data[len-3] = tag.port;
1305 skb->data[len-2] = 0x10;
1306 skb->data[len-1] = 0x00;
1307 if (tag.l2_offloaded)
1308 skb->data[len-3] |= 0x40;
1309 }
1310
1311 if (tag.queue >= 0)
1312 pr_debug("Queue: %d, len: %d, reason %d port %d\n",
1313 tag.queue, len, tag.reason, tag.port);
1314
1315 skb->protocol = eth_type_trans(skb, dev);
1316 if (dev->features & NETIF_F_RXCSUM) {
1317 if (tag.crc_error)
1318 skb_checksum_none_assert(skb);
1319 else
1320 skb->ip_summed = CHECKSUM_UNNECESSARY;
1321 }
1322 dev->stats.rx_packets++;
1323 dev->stats.rx_bytes += len;
1324
1325 netif_receive_skb(skb);
1326 } else {
1327 if (net_ratelimit())
1328 dev_warn(&dev->dev, "low on memory - packet dropped\n");
1329 dev->stats.rx_dropped++;
1330 }
1331
1332 /* Reset header structure */
1333 memset(h, 0, sizeof(struct p_hdr));
1334 h->buf = data;
1335 h->size = RING_BUFFER;
1336
1337 ring->rx_r[r][ring->c_rx[r]] = KSEG1ADDR(h) | 0x1
1338 | (ring->c_rx[r] == (priv->rxringlen - 1) ? WRAP : 0x1);
1339 ring->c_rx[r] = (ring->c_rx[r] + 1) % priv->rxringlen;
1340 last = (u32 *)KSEG1ADDR(sw_r32(priv->r->dma_if_rx_cur + r * 4));
1341 } while (&ring->rx_r[r][ring->c_rx[r]] != last && work_done < budget);
1342
1343 // Update counters
1344 priv->r->update_cntr(r, 0);
1345
1346 spin_unlock_irqrestore(&priv->lock, flags);
1347
1348 return work_done;
1349 }
1350
1351 static int rtl838x_poll_rx(struct napi_struct *napi, int budget)
1352 {
1353 struct rtl838x_rx_q *rx_q = container_of(napi, struct rtl838x_rx_q, napi);
1354 struct rtl838x_eth_priv *priv = rx_q->priv;
1355 int work_done = 0;
1356 int r = rx_q->id;
1357 int work;
1358
1359 while (work_done < budget) {
1360 work = rtl838x_hw_receive(priv->netdev, r, budget - work_done);
1361 if (!work)
1362 break;
1363 work_done += work;
1364 }
1365
1366 if (work_done < budget) {
1367 napi_complete_done(napi, work_done);
1368
1369 /* Enable RX interrupt */
1370 if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID)
1371 sw_w32(0xffffffff, priv->r->dma_if_intr_rx_done_msk);
1372 else
1373 sw_w32_mask(0, 0xf00ff | BIT(r + 8), priv->r->dma_if_intr_msk);
1374 }
1375 return work_done;
1376 }
1377
1378
1379 static void rtl838x_validate(struct phylink_config *config,
1380 unsigned long *supported,
1381 struct phylink_link_state *state)
1382 {
1383 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
1384
1385 pr_debug("In %s\n", __func__);
1386
1387 if (!phy_interface_mode_is_rgmii(state->interface) &&
1388 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
1389 state->interface != PHY_INTERFACE_MODE_MII &&
1390 state->interface != PHY_INTERFACE_MODE_REVMII &&
1391 state->interface != PHY_INTERFACE_MODE_GMII &&
1392 state->interface != PHY_INTERFACE_MODE_QSGMII &&
1393 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
1394 state->interface != PHY_INTERFACE_MODE_SGMII) {
1395 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
1396 pr_err("Unsupported interface: %d\n", state->interface);
1397 return;
1398 }
1399
1400 /* Allow all the expected bits */
1401 phylink_set(mask, Autoneg);
1402 phylink_set_port_modes(mask);
1403 phylink_set(mask, Pause);
1404 phylink_set(mask, Asym_Pause);
1405
1406 /* With the exclusion of MII and Reverse MII, we support Gigabit,
1407 * including Half duplex
1408 */
1409 if (state->interface != PHY_INTERFACE_MODE_MII &&
1410 state->interface != PHY_INTERFACE_MODE_REVMII) {
1411 phylink_set(mask, 1000baseT_Full);
1412 phylink_set(mask, 1000baseT_Half);
1413 }
1414
1415 phylink_set(mask, 10baseT_Half);
1416 phylink_set(mask, 10baseT_Full);
1417 phylink_set(mask, 100baseT_Half);
1418 phylink_set(mask, 100baseT_Full);
1419
1420 bitmap_and(supported, supported, mask,
1421 __ETHTOOL_LINK_MODE_MASK_NBITS);
1422 bitmap_and(state->advertising, state->advertising, mask,
1423 __ETHTOOL_LINK_MODE_MASK_NBITS);
1424 }
1425
1426
1427 static void rtl838x_mac_config(struct phylink_config *config,
1428 unsigned int mode,
1429 const struct phylink_link_state *state)
1430 {
1431 /* This is only being called for the master device,
1432 * i.e. the CPU-Port. We don't need to do anything.
1433 */
1434
1435 pr_info("In %s, mode %x\n", __func__, mode);
1436 }
1437
1438 static void rtl838x_mac_an_restart(struct phylink_config *config)
1439 {
1440 struct net_device *dev = container_of(config->dev, struct net_device, dev);
1441 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1442
1443 /* This works only on RTL838x chips */
1444 if (priv->family_id != RTL8380_FAMILY_ID)
1445 return;
1446
1447 pr_debug("In %s\n", __func__);
1448 /* Restart by disabling and re-enabling link */
1449 sw_w32(0x6192D, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
1450 mdelay(20);
1451 sw_w32(0x6192F, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
1452 }
1453
1454 static void rtl838x_mac_pcs_get_state(struct phylink_config *config,
1455 struct phylink_link_state *state)
1456 {
1457 u32 speed;
1458 struct net_device *dev = container_of(config->dev, struct net_device, dev);
1459 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1460 int port = priv->cpu_port;
1461
1462 pr_info("In %s\n", __func__);
1463
1464 state->link = priv->r->get_mac_link_sts(port) ? 1 : 0;
1465 state->duplex = priv->r->get_mac_link_dup_sts(port) ? 1 : 0;
1466
1467 pr_info("%s link status is %d\n", __func__, state->link);
1468 speed = priv->r->get_mac_link_spd_sts(port);
1469 switch (speed) {
1470 case 0:
1471 state->speed = SPEED_10;
1472 break;
1473 case 1:
1474 state->speed = SPEED_100;
1475 break;
1476 case 2:
1477 state->speed = SPEED_1000;
1478 break;
1479 case 5:
1480 state->speed = SPEED_2500;
1481 break;
1482 case 6:
1483 state->speed = SPEED_5000;
1484 break;
1485 case 4:
1486 state->speed = SPEED_10000;
1487 break;
1488 default:
1489 state->speed = SPEED_UNKNOWN;
1490 break;
1491 }
1492
1493 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
1494 if (priv->r->get_mac_rx_pause_sts(port))
1495 state->pause |= MLO_PAUSE_RX;
1496 if (priv->r->get_mac_tx_pause_sts(port))
1497 state->pause |= MLO_PAUSE_TX;
1498 }
1499
1500 static void rtl838x_mac_link_down(struct phylink_config *config,
1501 unsigned int mode,
1502 phy_interface_t interface)
1503 {
1504 struct net_device *dev = container_of(config->dev, struct net_device, dev);
1505 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1506
1507 pr_debug("In %s\n", __func__);
1508 /* Stop TX/RX to port */
1509 sw_w32_mask(0x03, 0, priv->r->mac_port_ctrl(priv->cpu_port));
1510 }
1511
1512 static void rtl838x_mac_link_up(struct phylink_config *config,
1513 struct phy_device *phy, unsigned int mode,
1514 phy_interface_t interface, int speed, int duplex,
1515 bool tx_pause, bool rx_pause)
1516 {
1517 struct net_device *dev = container_of(config->dev, struct net_device, dev);
1518 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1519
1520 pr_debug("In %s\n", __func__);
1521 /* Restart TX/RX to port */
1522 sw_w32_mask(0, 0x03, priv->r->mac_port_ctrl(priv->cpu_port));
1523 }
1524
1525 static void rtl838x_set_mac_hw(struct net_device *dev, u8 *mac)
1526 {
1527 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1528 unsigned long flags;
1529
1530 spin_lock_irqsave(&priv->lock, flags);
1531 pr_debug("In %s\n", __func__);
1532 sw_w32((mac[0] << 8) | mac[1], priv->r->mac);
1533 sw_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5], priv->r->mac + 4);
1534
1535 if (priv->family_id == RTL8380_FAMILY_ID) {
1536 /* 2 more registers, ALE/MAC block */
1537 sw_w32((mac[0] << 8) | mac[1], RTL838X_MAC_ALE);
1538 sw_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
1539 (RTL838X_MAC_ALE + 4));
1540
1541 sw_w32((mac[0] << 8) | mac[1], RTL838X_MAC2);
1542 sw_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
1543 RTL838X_MAC2 + 4);
1544 }
1545 spin_unlock_irqrestore(&priv->lock, flags);
1546 }
1547
1548 static int rtl838x_set_mac_address(struct net_device *dev, void *p)
1549 {
1550 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1551 const struct sockaddr *addr = p;
1552 u8 *mac = (u8 *) (addr->sa_data);
1553
1554 if (!is_valid_ether_addr(addr->sa_data))
1555 return -EADDRNOTAVAIL;
1556
1557 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
1558 rtl838x_set_mac_hw(dev, mac);
1559
1560 pr_info("Using MAC %08x%08x\n", sw_r32(priv->r->mac), sw_r32(priv->r->mac + 4));
1561 return 0;
1562 }
1563
1564 static int rtl8390_init_mac(struct rtl838x_eth_priv *priv)
1565 {
1566 // We will need to set-up EEE and the egress-rate limitation
1567 return 0;
1568 }
1569
1570 static int rtl8380_init_mac(struct rtl838x_eth_priv *priv)
1571 {
1572 int i;
1573
1574 if (priv->family_id == 0x8390)
1575 return rtl8390_init_mac(priv);
1576
1577 // At present we do not know how to set up EEE on any other SoC than RTL8380
1578 if (priv->family_id != 0x8380)
1579 return 0;
1580
1581 pr_info("%s\n", __func__);
1582 /* fix timer for EEE */
1583 sw_w32(0x5001411, RTL838X_EEE_TX_TIMER_GIGA_CTRL);
1584 sw_w32(0x5001417, RTL838X_EEE_TX_TIMER_GELITE_CTRL);
1585
1586 /* Init VLAN. TODO: Understand what is being done, here */
1587 if (priv->id == 0x8382) {
1588 for (i = 0; i <= 28; i++)
1589 sw_w32(0, 0xd57c + i * 0x80);
1590 }
1591 if (priv->id == 0x8380) {
1592 for (i = 8; i <= 28; i++)
1593 sw_w32(0, 0xd57c + i * 0x80);
1594 }
1595 return 0;
1596 }
1597
1598 static int rtl838x_get_link_ksettings(struct net_device *ndev,
1599 struct ethtool_link_ksettings *cmd)
1600 {
1601 struct rtl838x_eth_priv *priv = netdev_priv(ndev);
1602
1603 pr_debug("%s called\n", __func__);
1604 return phylink_ethtool_ksettings_get(priv->phylink, cmd);
1605 }
1606
1607 static int rtl838x_set_link_ksettings(struct net_device *ndev,
1608 const struct ethtool_link_ksettings *cmd)
1609 {
1610 struct rtl838x_eth_priv *priv = netdev_priv(ndev);
1611
1612 pr_debug("%s called\n", __func__);
1613 return phylink_ethtool_ksettings_set(priv->phylink, cmd);
1614 }
1615
1616 static int rtl838x_mdio_read_paged(struct mii_bus *bus, int mii_id, u16 page, int regnum)
1617 {
1618 u32 val;
1619 int err;
1620 struct rtl838x_eth_priv *priv = bus->priv;
1621
1622 if (mii_id >= 24 && mii_id <= 27 && priv->id == 0x8380)
1623 return rtl838x_read_sds_phy(mii_id, regnum);
1624
1625 if (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD)) {
1626 err = rtl838x_read_mmd_phy(mii_id,
1627 mdiobus_c45_devad(regnum),
1628 regnum, &val);
1629 pr_debug("MMD: %d dev %x register %x read %x, err %d\n", mii_id,
1630 mdiobus_c45_devad(regnum), mdiobus_c45_regad(regnum),
1631 val, err);
1632 } else {
1633 pr_debug("PHY: %d register %x read %x, err %d\n", mii_id, regnum, val, err);
1634 err = rtl838x_read_phy(mii_id, page, regnum, &val);
1635 }
1636 if (err)
1637 return err;
1638 return val;
1639 }
1640
1641 static int rtl838x_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1642 {
1643 return rtl838x_mdio_read_paged(bus, mii_id, 0, regnum);
1644 }
1645
1646 static int rtl839x_mdio_read_paged(struct mii_bus *bus, int mii_id, u16 page, int regnum)
1647 {
1648 u32 val;
1649 int err;
1650 struct rtl838x_eth_priv *priv = bus->priv;
1651
1652 if (mii_id >= 48 && mii_id <= 49 && priv->id == 0x8393)
1653 return rtl839x_read_sds_phy(mii_id, regnum);
1654
1655 if (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD)) {
1656 err = rtl839x_read_mmd_phy(mii_id,
1657 mdiobus_c45_devad(regnum),
1658 regnum, &val);
1659 pr_debug("MMD: %d dev %x register %x read %x, err %d\n", mii_id,
1660 mdiobus_c45_devad(regnum), mdiobus_c45_regad(regnum),
1661 val, err);
1662 } else {
1663 err = rtl839x_read_phy(mii_id, page, regnum, &val);
1664 pr_debug("PHY: %d register %x read %x, err %d\n", mii_id, regnum, val, err);
1665 }
1666 if (err)
1667 return err;
1668 return val;
1669 }
1670
1671 static int rtl839x_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1672 {
1673 return rtl839x_mdio_read_paged(bus, mii_id, 0, regnum);
1674 }
1675
1676 static int rtl930x_mdio_read_paged(struct mii_bus *bus, int mii_id, u16 page, int regnum)
1677 {
1678 u32 val;
1679 int err;
1680 struct rtl838x_eth_priv *priv = bus->priv;
1681
1682 if (priv->phy_is_internal[mii_id])
1683 return rtl930x_read_sds_phy(priv->sds_id[mii_id], page, regnum);
1684
1685 if (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD)) {
1686 err = rtl930x_read_mmd_phy(mii_id,
1687 mdiobus_c45_devad(regnum),
1688 regnum, &val);
1689 pr_debug("MMD: %d dev %x register %x read %x, err %d\n", mii_id,
1690 mdiobus_c45_devad(regnum), mdiobus_c45_regad(regnum),
1691 val, err);
1692 } else {
1693 err = rtl930x_read_phy(mii_id, page, regnum, &val);
1694 pr_debug("PHY: %d register %x read %x, err %d\n", mii_id, regnum, val, err);
1695 }
1696 if (err)
1697 return err;
1698 return val;
1699 }
1700
1701 static int rtl930x_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1702 {
1703 return rtl930x_mdio_read_paged(bus, mii_id, 0, regnum);
1704 }
1705
1706 static int rtl931x_mdio_read_paged(struct mii_bus *bus, int mii_id, u16 page, int regnum)
1707 {
1708 u32 val;
1709 int err, v;
1710 struct rtl838x_eth_priv *priv = bus->priv;
1711
1712 pr_debug("%s: In here, port %d\n", __func__, mii_id);
1713 if (priv->phy_is_internal[mii_id]) {
1714 v = rtl931x_read_sds_phy(priv->sds_id[mii_id], page, regnum);
1715 if (v < 0) {
1716 err = v;
1717 } else {
1718 err = 0;
1719 val = v;
1720 }
1721 } else {
1722 if (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD)) {
1723 err = rtl931x_read_mmd_phy(mii_id,
1724 mdiobus_c45_devad(regnum),
1725 regnum, &val);
1726 pr_debug("MMD: %d dev %x register %x read %x, err %d\n", mii_id,
1727 mdiobus_c45_devad(regnum), mdiobus_c45_regad(regnum),
1728 val, err);
1729 } else {
1730 err = rtl931x_read_phy(mii_id, page, regnum, &val);
1731 pr_debug("PHY: %d register %x read %x, err %d\n", mii_id, regnum, val, err);
1732 }
1733 }
1734
1735 if (err)
1736 return err;
1737 return val;
1738 }
1739
1740 static int rtl931x_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1741 {
1742 return rtl931x_mdio_read_paged(bus, mii_id, 0, regnum);
1743 }
1744
1745 static int rtl838x_mdio_write_paged(struct mii_bus *bus, int mii_id, u16 page,
1746 int regnum, u16 value)
1747 {
1748 u32 offset = 0;
1749 struct rtl838x_eth_priv *priv = bus->priv;
1750 int err;
1751
1752 if (mii_id >= 24 && mii_id <= 27 && priv->id == 0x8380) {
1753 if (mii_id == 26)
1754 offset = 0x100;
1755 sw_w32(value, RTL838X_SDS4_FIB_REG0 + offset + (regnum << 2));
1756 return 0;
1757 }
1758
1759 if (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD)) {
1760 err = rtl838x_write_mmd_phy(mii_id, mdiobus_c45_devad(regnum),
1761 regnum, value);
1762 pr_debug("MMD: %d dev %x register %x write %x, err %d\n", mii_id,
1763 mdiobus_c45_devad(regnum), mdiobus_c45_regad(regnum),
1764 value, err);
1765
1766 return err;
1767 }
1768 err = rtl838x_write_phy(mii_id, page, regnum, value);
1769 pr_debug("PHY: %d register %x write %x, err %d\n", mii_id, regnum, value, err);
1770 return err;
1771 }
1772
1773 static int rtl838x_mdio_write(struct mii_bus *bus, int mii_id,
1774 int regnum, u16 value)
1775 {
1776 return rtl838x_mdio_write_paged(bus, mii_id, 0, regnum, value);
1777 }
1778
1779 static int rtl839x_mdio_write_paged(struct mii_bus *bus, int mii_id, u16 page,
1780 int regnum, u16 value)
1781 {
1782 struct rtl838x_eth_priv *priv = bus->priv;
1783 int err;
1784
1785 if (mii_id >= 48 && mii_id <= 49 && priv->id == 0x8393)
1786 return rtl839x_write_sds_phy(mii_id, regnum, value);
1787
1788 if (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD)) {
1789 err = rtl839x_write_mmd_phy(mii_id, mdiobus_c45_devad(regnum),
1790 regnum, value);
1791 pr_debug("MMD: %d dev %x register %x write %x, err %d\n", mii_id,
1792 mdiobus_c45_devad(regnum), mdiobus_c45_regad(regnum),
1793 value, err);
1794
1795 return err;
1796 }
1797
1798 err = rtl839x_write_phy(mii_id, page, regnum, value);
1799 pr_debug("PHY: %d register %x write %x, err %d\n", mii_id, regnum, value, err);
1800 return err;
1801 }
1802
1803 static int rtl839x_mdio_write(struct mii_bus *bus, int mii_id,
1804 int regnum, u16 value)
1805 {
1806 return rtl839x_mdio_write_paged(bus, mii_id, 0, regnum, value);
1807 }
1808
1809 static int rtl930x_mdio_write_paged(struct mii_bus *bus, int mii_id, u16 page,
1810 int regnum, u16 value)
1811 {
1812 struct rtl838x_eth_priv *priv = bus->priv;
1813 int err;
1814
1815 if (priv->phy_is_internal[mii_id])
1816 return rtl930x_write_sds_phy(priv->sds_id[mii_id], page, regnum, value);
1817
1818 if (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD))
1819 return rtl930x_write_mmd_phy(mii_id, mdiobus_c45_devad(regnum),
1820 regnum, value);
1821
1822 err = rtl930x_write_phy(mii_id, page, regnum, value);
1823 pr_debug("PHY: %d register %x write %x, err %d\n", mii_id, regnum, value, err);
1824 return err;
1825 }
1826
1827 static int rtl930x_mdio_write(struct mii_bus *bus, int mii_id,
1828 int regnum, u16 value)
1829 {
1830 return rtl930x_mdio_write_paged(bus, mii_id, 0, regnum, value);
1831 }
1832
1833 static int rtl931x_mdio_write_paged(struct mii_bus *bus, int mii_id, u16 page,
1834 int regnum, u16 value)
1835 {
1836 struct rtl838x_eth_priv *priv = bus->priv;
1837 int err;
1838
1839 if (priv->phy_is_internal[mii_id])
1840 return rtl931x_write_sds_phy(priv->sds_id[mii_id], page, regnum, value);
1841
1842 if (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD)) {
1843 err = rtl931x_write_mmd_phy(mii_id, mdiobus_c45_devad(regnum),
1844 regnum, value);
1845 pr_debug("MMD: %d dev %x register %x write %x, err %d\n", mii_id,
1846 mdiobus_c45_devad(regnum), mdiobus_c45_regad(regnum),
1847 value, err);
1848
1849 return err;
1850 }
1851
1852 err = rtl931x_write_phy(mii_id, page, regnum, value);
1853 pr_debug("PHY: %d register %x write %x, err %d\n", mii_id, regnum, value, err);
1854 return err;
1855 }
1856
1857 static int rtl931x_mdio_write(struct mii_bus *bus, int mii_id,
1858 int regnum, u16 value)
1859 {
1860 return rtl931x_mdio_write_paged(bus, mii_id, 0, regnum, value);
1861 }
1862
1863 static int rtl838x_mdio_reset(struct mii_bus *bus)
1864 {
1865 pr_debug("%s called\n", __func__);
1866 /* Disable MAC polling the PHY so that we can start configuration */
1867 sw_w32(0x00000000, RTL838X_SMI_POLL_CTRL);
1868
1869 /* Enable PHY control via SoC */
1870 sw_w32_mask(0, 1 << 15, RTL838X_SMI_GLB_CTRL);
1871
1872 // Probably should reset all PHYs here...
1873 return 0;
1874 }
1875
1876 static int rtl839x_mdio_reset(struct mii_bus *bus)
1877 {
1878 return 0;
1879
1880 pr_debug("%s called\n", __func__);
1881 /* BUG: The following does not work, but should! */
1882 /* Disable MAC polling the PHY so that we can start configuration */
1883 sw_w32(0x00000000, RTL839X_SMI_PORT_POLLING_CTRL);
1884 sw_w32(0x00000000, RTL839X_SMI_PORT_POLLING_CTRL + 4);
1885 /* Disable PHY polling via SoC */
1886 sw_w32_mask(1 << 7, 0, RTL839X_SMI_GLB_CTRL);
1887
1888 // Probably should reset all PHYs here...
1889 return 0;
1890 }
1891
1892 u8 mac_type_bit[RTL930X_CPU_PORT] = {0, 0, 0, 0, 2, 2, 2, 2, 4, 4, 4, 4, 6, 6, 6, 6,
1893 8, 8, 8, 8, 10, 10, 10, 10, 12, 15, 18, 21};
1894
1895 static int rtl930x_mdio_reset(struct mii_bus *bus)
1896 {
1897 int i;
1898 int pos;
1899 struct rtl838x_eth_priv *priv = bus->priv;
1900 u32 c45_mask = 0;
1901 u32 poll_sel[2];
1902 u32 poll_ctrl = 0;
1903 u32 private_poll_mask = 0;
1904 u32 v;
1905 bool uses_usxgmii = false; // For the Aquantia PHYs
1906 bool uses_hisgmii = false; // For the RTL8221/8226
1907
1908 // Mapping of port to phy-addresses on an SMI bus
1909 poll_sel[0] = poll_sel[1] = 0;
1910 for (i = 0; i < RTL930X_CPU_PORT; i++) {
1911 if (priv->smi_bus[i] > 3)
1912 continue;
1913 pos = (i % 6) * 5;
1914 sw_w32_mask(0x1f << pos, priv->smi_addr[i] << pos,
1915 RTL930X_SMI_PORT0_5_ADDR + (i / 6) * 4);
1916
1917 pos = (i * 2) % 32;
1918 poll_sel[i / 16] |= priv->smi_bus[i] << pos;
1919 poll_ctrl |= BIT(20 + priv->smi_bus[i]);
1920 }
1921
1922 // Configure which SMI bus is behind which port number
1923 sw_w32(poll_sel[0], RTL930X_SMI_PORT0_15_POLLING_SEL);
1924 sw_w32(poll_sel[1], RTL930X_SMI_PORT16_27_POLLING_SEL);
1925
1926 // Disable POLL_SEL for any SMI bus with a normal PHY (not RTL8295R for SFP+)
1927 sw_w32_mask(poll_ctrl, 0, RTL930X_SMI_GLB_CTRL);
1928
1929 // Configure which SMI busses are polled in c45 based on a c45 PHY being on that bus
1930 for (i = 0; i < 4; i++)
1931 if (priv->smi_bus_isc45[i])
1932 c45_mask |= BIT(i + 16);
1933
1934 pr_info("c45_mask: %08x\n", c45_mask);
1935 sw_w32_mask(0, c45_mask, RTL930X_SMI_GLB_CTRL);
1936
1937 // Set the MAC type of each port according to the PHY-interface
1938 // Values are FE: 2, GE: 3, XGE/2.5G: 0(SERDES) or 1(otherwise), SXGE: 0
1939 v = 0;
1940 for (i = 0; i < RTL930X_CPU_PORT; i++) {
1941 switch (priv->interfaces[i]) {
1942 case PHY_INTERFACE_MODE_10GBASER:
1943 break; // Serdes: Value = 0
1944
1945 case PHY_INTERFACE_MODE_HSGMII:
1946 private_poll_mask |= BIT(i);
1947 // fallthrough
1948 case PHY_INTERFACE_MODE_USXGMII:
1949 v |= BIT(mac_type_bit[i]);
1950 uses_usxgmii = true;
1951 break;
1952
1953 case PHY_INTERFACE_MODE_QSGMII:
1954 private_poll_mask |= BIT(i);
1955 v |= 3 << mac_type_bit[i];
1956 break;
1957
1958 default:
1959 break;
1960 }
1961 }
1962 sw_w32(v, RTL930X_SMI_MAC_TYPE_CTRL);
1963
1964 // Set the private polling mask for all Realtek PHYs (i.e. not the 10GBit Aquantia ones)
1965 sw_w32(private_poll_mask, RTL930X_SMI_PRVTE_POLLING_CTRL);
1966
1967 /* The following magic values are found in the port configuration, they seem to
1968 * define different ways of polling a PHY. The below is for the Aquantia PHYs of
1969 * the XGS1250 and the RTL8226 of the XGS1210 */
1970 if (uses_usxgmii) {
1971 sw_w32(0x01010000, RTL930X_SMI_10GPHY_POLLING_REG0_CFG);
1972 sw_w32(0x01E7C400, RTL930X_SMI_10GPHY_POLLING_REG9_CFG);
1973 sw_w32(0x01E7E820, RTL930X_SMI_10GPHY_POLLING_REG10_CFG);
1974 }
1975 if (uses_hisgmii) {
1976 sw_w32(0x011FA400, RTL930X_SMI_10GPHY_POLLING_REG0_CFG);
1977 sw_w32(0x013FA412, RTL930X_SMI_10GPHY_POLLING_REG9_CFG);
1978 sw_w32(0x017FA414, RTL930X_SMI_10GPHY_POLLING_REG10_CFG);
1979 }
1980
1981 pr_debug("%s: RTL930X_SMI_GLB_CTRL %08x\n", __func__,
1982 sw_r32(RTL930X_SMI_GLB_CTRL));
1983 pr_debug("%s: RTL930X_SMI_PORT0_15_POLLING_SEL %08x\n", __func__,
1984 sw_r32(RTL930X_SMI_PORT0_15_POLLING_SEL));
1985 pr_debug("%s: RTL930X_SMI_PORT16_27_POLLING_SEL %08x\n", __func__,
1986 sw_r32(RTL930X_SMI_PORT16_27_POLLING_SEL));
1987 pr_debug("%s: RTL930X_SMI_MAC_TYPE_CTRL %08x\n", __func__,
1988 sw_r32(RTL930X_SMI_MAC_TYPE_CTRL));
1989 pr_debug("%s: RTL930X_SMI_10GPHY_POLLING_REG0_CFG %08x\n", __func__,
1990 sw_r32(RTL930X_SMI_10GPHY_POLLING_REG0_CFG));
1991 pr_debug("%s: RTL930X_SMI_10GPHY_POLLING_REG9_CFG %08x\n", __func__,
1992 sw_r32(RTL930X_SMI_10GPHY_POLLING_REG9_CFG));
1993 pr_debug("%s: RTL930X_SMI_10GPHY_POLLING_REG10_CFG %08x\n", __func__,
1994 sw_r32(RTL930X_SMI_10GPHY_POLLING_REG10_CFG));
1995 pr_debug("%s: RTL930X_SMI_PRVTE_POLLING_CTRL %08x\n", __func__,
1996 sw_r32(RTL930X_SMI_PRVTE_POLLING_CTRL));
1997 return 0;
1998 }
1999
2000 static int rtl931x_mdio_reset(struct mii_bus *bus)
2001 {
2002 int i;
2003 int pos;
2004 struct rtl838x_eth_priv *priv = bus->priv;
2005 u32 c45_mask = 0;
2006 u32 poll_sel[4];
2007 u32 poll_ctrl = 0;
2008 bool mdc_on[4];
2009
2010 pr_info("%s called\n", __func__);
2011 // Disable port polling for configuration purposes
2012 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL);
2013 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL + 4);
2014 msleep(100);
2015
2016 mdc_on[0] = mdc_on[1] = mdc_on[2] = mdc_on[3] = false;
2017 // Mapping of port to phy-addresses on an SMI bus
2018 poll_sel[0] = poll_sel[1] = poll_sel[2] = poll_sel[3] = 0;
2019 for (i = 0; i < 56; i++) {
2020 pos = (i % 6) * 5;
2021 sw_w32_mask(0x1f << pos, priv->smi_addr[i] << pos, RTL931X_SMI_PORT_ADDR + (i / 6) * 4);
2022 pos = (i * 2) % 32;
2023 poll_sel[i / 16] |= priv->smi_bus[i] << pos;
2024 poll_ctrl |= BIT(20 + priv->smi_bus[i]);
2025 mdc_on[priv->smi_bus[i]] = true;
2026 }
2027
2028 // Configure which SMI bus is behind which port number
2029 for (i = 0; i < 4; i++) {
2030 pr_info("poll sel %d, %08x\n", i, poll_sel[i]);
2031 sw_w32(poll_sel[i], RTL931X_SMI_PORT_POLLING_SEL + (i * 4));
2032 }
2033
2034 // Configure which SMI busses
2035 pr_info("%s: WAS RTL931X_MAC_L2_GLOBAL_CTRL2 %08x\n", __func__, sw_r32(RTL931X_MAC_L2_GLOBAL_CTRL2));
2036 pr_info("c45_mask: %08x, RTL931X_SMI_GLB_CTRL0 was %X", c45_mask, sw_r32(RTL931X_SMI_GLB_CTRL0));
2037 for (i = 0; i < 4; i++) {
2038 // bus is polled in c45
2039 if (priv->smi_bus_isc45[i])
2040 c45_mask |= 0x2 << (i * 2); // Std. C45, non-standard is 0x3
2041 // Enable bus access via MDC
2042 if (mdc_on[i])
2043 sw_w32_mask(0, BIT(9 + i), RTL931X_MAC_L2_GLOBAL_CTRL2);
2044 }
2045
2046 pr_info("%s: RTL931X_MAC_L2_GLOBAL_CTRL2 %08x\n", __func__, sw_r32(RTL931X_MAC_L2_GLOBAL_CTRL2));
2047 pr_info("c45_mask: %08x, RTL931X_SMI_GLB_CTRL0 was %X", c45_mask, sw_r32(RTL931X_SMI_GLB_CTRL0));
2048
2049 /* We have a 10G PHY enable polling
2050 sw_w32(0x01010000, RTL931X_SMI_10GPHY_POLLING_SEL2);
2051 sw_w32(0x01E7C400, RTL931X_SMI_10GPHY_POLLING_SEL3);
2052 sw_w32(0x01E7E820, RTL931X_SMI_10GPHY_POLLING_SEL4);
2053 */
2054 sw_w32_mask(0xff, c45_mask, RTL931X_SMI_GLB_CTRL1);
2055
2056 return 0;
2057 }
2058
2059 static int rtl931x_chip_init(struct rtl838x_eth_priv *priv)
2060 {
2061 pr_info("In %s\n", __func__);
2062
2063 // Initialize Encapsulation memory and wait until finished
2064 sw_w32(0x1, RTL931X_MEM_ENCAP_INIT);
2065 do { } while (sw_r32(RTL931X_MEM_ENCAP_INIT) & 1);
2066 pr_info("%s: init ENCAP done\n", __func__);
2067
2068 // Initialize Managemen Information Base memory and wait until finished
2069 sw_w32(0x1, RTL931X_MEM_MIB_INIT);
2070 do { } while (sw_r32(RTL931X_MEM_MIB_INIT) & 1);
2071 pr_info("%s: init MIB done\n", __func__);
2072
2073 // Initialize ACL (PIE) memory and wait until finished
2074 sw_w32(0x1, RTL931X_MEM_ACL_INIT);
2075 do { } while (sw_r32(RTL931X_MEM_ACL_INIT) & 1);
2076 pr_info("%s: init ACL done\n", __func__);
2077
2078 // Initialize ALE memory and wait until finished
2079 sw_w32(0xFFFFFFFF, RTL931X_MEM_ALE_INIT_0);
2080 do { } while (sw_r32(RTL931X_MEM_ALE_INIT_0));
2081 sw_w32(0x7F, RTL931X_MEM_ALE_INIT_1);
2082 sw_w32(0x7ff, RTL931X_MEM_ALE_INIT_2);
2083 do { } while (sw_r32(RTL931X_MEM_ALE_INIT_2) & 0x7ff);
2084 pr_info("%s: init ALE done\n", __func__);
2085
2086 // Enable ESD auto recovery
2087 sw_w32(0x1, RTL931X_MDX_CTRL_RSVD);
2088
2089 // Init SPI, is this for thermal control or what?
2090 sw_w32_mask(0x7 << 11, 0x2 << 11, RTL931X_SPI_CTRL0);
2091
2092 return 0;
2093 }
2094
2095 static int rtl838x_mdio_init(struct rtl838x_eth_priv *priv)
2096 {
2097 struct device_node *mii_np, *dn;
2098 u32 pn;
2099 int ret;
2100
2101 pr_debug("%s called\n", __func__);
2102 mii_np = of_get_child_by_name(priv->pdev->dev.of_node, "mdio-bus");
2103
2104 if (!mii_np) {
2105 dev_err(&priv->pdev->dev, "no %s child node found", "mdio-bus");
2106 return -ENODEV;
2107 }
2108
2109 if (!of_device_is_available(mii_np)) {
2110 ret = -ENODEV;
2111 goto err_put_node;
2112 }
2113
2114 priv->mii_bus = devm_mdiobus_alloc(&priv->pdev->dev);
2115 if (!priv->mii_bus) {
2116 ret = -ENOMEM;
2117 goto err_put_node;
2118 }
2119
2120 switch(priv->family_id) {
2121 case RTL8380_FAMILY_ID:
2122 priv->mii_bus->name = "rtl838x-eth-mdio";
2123 priv->mii_bus->read = rtl838x_mdio_read;
2124 priv->mii_bus->read_paged = rtl838x_mdio_read_paged;
2125 priv->mii_bus->write = rtl838x_mdio_write;
2126 priv->mii_bus->write_paged = rtl838x_mdio_write_paged;
2127 priv->mii_bus->reset = rtl838x_mdio_reset;
2128 break;
2129 case RTL8390_FAMILY_ID:
2130 priv->mii_bus->name = "rtl839x-eth-mdio";
2131 priv->mii_bus->read = rtl839x_mdio_read;
2132 priv->mii_bus->read_paged = rtl839x_mdio_read_paged;
2133 priv->mii_bus->write = rtl839x_mdio_write;
2134 priv->mii_bus->write_paged = rtl839x_mdio_write_paged;
2135 priv->mii_bus->reset = rtl839x_mdio_reset;
2136 break;
2137 case RTL9300_FAMILY_ID:
2138 priv->mii_bus->name = "rtl930x-eth-mdio";
2139 priv->mii_bus->read = rtl930x_mdio_read;
2140 priv->mii_bus->read_paged = rtl930x_mdio_read_paged;
2141 priv->mii_bus->write = rtl930x_mdio_write;
2142 priv->mii_bus->write_paged = rtl930x_mdio_write_paged;
2143 priv->mii_bus->reset = rtl930x_mdio_reset;
2144 priv->mii_bus->probe_capabilities = MDIOBUS_C22_C45;
2145 break;
2146 case RTL9310_FAMILY_ID:
2147 priv->mii_bus->name = "rtl931x-eth-mdio";
2148 priv->mii_bus->read = rtl931x_mdio_read;
2149 priv->mii_bus->read_paged = rtl931x_mdio_read_paged;
2150 priv->mii_bus->write = rtl931x_mdio_write;
2151 priv->mii_bus->write_paged = rtl931x_mdio_write_paged;
2152 priv->mii_bus->reset = rtl931x_mdio_reset;
2153 priv->mii_bus->probe_capabilities = MDIOBUS_C22_C45;
2154 break;
2155 }
2156 priv->mii_bus->access_capabilities = MDIOBUS_ACCESS_C22_MMD;
2157 priv->mii_bus->priv = priv;
2158 priv->mii_bus->parent = &priv->pdev->dev;
2159
2160 for_each_node_by_name(dn, "ethernet-phy") {
2161 u32 smi_addr[2];
2162
2163 if (of_property_read_u32(dn, "reg", &pn))
2164 continue;
2165
2166 if (of_property_read_u32_array(dn, "rtl9300,smi-address", &smi_addr[0], 2)) {
2167 smi_addr[0] = 0;
2168 smi_addr[1] = pn;
2169 }
2170
2171 if (of_property_read_u32(dn, "sds", &priv->sds_id[pn]))
2172 priv->sds_id[pn] = -1;
2173 else {
2174 pr_info("set sds port %d to %d\n", pn, priv->sds_id[pn]);
2175 }
2176
2177 if (pn < MAX_PORTS) {
2178 priv->smi_bus[pn] = smi_addr[0];
2179 priv->smi_addr[pn] = smi_addr[1];
2180 } else {
2181 pr_err("%s: illegal port number %d\n", __func__, pn);
2182 }
2183
2184 if (of_device_is_compatible(dn, "ethernet-phy-ieee802.3-c45"))
2185 priv->smi_bus_isc45[smi_addr[0]] = true;
2186
2187 if (of_property_read_bool(dn, "phy-is-integrated")) {
2188 priv->phy_is_internal[pn] = true;
2189 }
2190 }
2191
2192 dn = of_find_compatible_node(NULL, NULL, "realtek,rtl83xx-switch");
2193 if (!dn) {
2194 dev_err(&priv->pdev->dev, "No RTL switch node in DTS\n");
2195 return -ENODEV;
2196 }
2197
2198 for_each_node_by_name(dn, "port") {
2199 if (of_property_read_u32(dn, "reg", &pn))
2200 continue;
2201 pr_debug("%s Looking at port %d\n", __func__, pn);
2202 if (pn > priv->cpu_port)
2203 continue;
2204 if (of_get_phy_mode(dn, &priv->interfaces[pn]))
2205 priv->interfaces[pn] = PHY_INTERFACE_MODE_NA;
2206 pr_debug("%s phy mode of port %d is %s\n", __func__, pn, phy_modes(priv->interfaces[pn]));
2207 }
2208
2209 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np);
2210 ret = of_mdiobus_register(priv->mii_bus, mii_np);
2211
2212 err_put_node:
2213 of_node_put(mii_np);
2214 return ret;
2215 }
2216
2217 static int rtl838x_mdio_remove(struct rtl838x_eth_priv *priv)
2218 {
2219 pr_debug("%s called\n", __func__);
2220 if (!priv->mii_bus)
2221 return 0;
2222
2223 mdiobus_unregister(priv->mii_bus);
2224 mdiobus_free(priv->mii_bus);
2225
2226 return 0;
2227 }
2228
2229 static netdev_features_t rtl838x_fix_features(struct net_device *dev,
2230 netdev_features_t features)
2231 {
2232 return features;
2233 }
2234
2235 static int rtl83xx_set_features(struct net_device *dev, netdev_features_t features)
2236 {
2237 struct rtl838x_eth_priv *priv = netdev_priv(dev);
2238
2239 if ((features ^ dev->features) & NETIF_F_RXCSUM) {
2240 if (!(features & NETIF_F_RXCSUM))
2241 sw_w32_mask(BIT(3), 0, priv->r->mac_port_ctrl(priv->cpu_port));
2242 else
2243 sw_w32_mask(0, BIT(4), priv->r->mac_port_ctrl(priv->cpu_port));
2244 }
2245
2246 return 0;
2247 }
2248
2249 static int rtl93xx_set_features(struct net_device *dev, netdev_features_t features)
2250 {
2251 struct rtl838x_eth_priv *priv = netdev_priv(dev);
2252
2253 if ((features ^ dev->features) & NETIF_F_RXCSUM) {
2254 if (!(features & NETIF_F_RXCSUM))
2255 sw_w32_mask(BIT(4), 0, priv->r->mac_port_ctrl(priv->cpu_port));
2256 else
2257 sw_w32_mask(0, BIT(4), priv->r->mac_port_ctrl(priv->cpu_port));
2258 }
2259
2260 return 0;
2261 }
2262
2263 static const struct net_device_ops rtl838x_eth_netdev_ops = {
2264 .ndo_open = rtl838x_eth_open,
2265 .ndo_stop = rtl838x_eth_stop,
2266 .ndo_start_xmit = rtl838x_eth_tx,
2267 .ndo_select_queue = rtl83xx_pick_tx_queue,
2268 .ndo_set_mac_address = rtl838x_set_mac_address,
2269 .ndo_validate_addr = eth_validate_addr,
2270 .ndo_set_rx_mode = rtl838x_eth_set_multicast_list,
2271 .ndo_tx_timeout = rtl838x_eth_tx_timeout,
2272 .ndo_set_features = rtl83xx_set_features,
2273 .ndo_fix_features = rtl838x_fix_features,
2274 .ndo_setup_tc = rtl83xx_setup_tc,
2275 };
2276
2277 static const struct net_device_ops rtl839x_eth_netdev_ops = {
2278 .ndo_open = rtl838x_eth_open,
2279 .ndo_stop = rtl838x_eth_stop,
2280 .ndo_start_xmit = rtl838x_eth_tx,
2281 .ndo_select_queue = rtl83xx_pick_tx_queue,
2282 .ndo_set_mac_address = rtl838x_set_mac_address,
2283 .ndo_validate_addr = eth_validate_addr,
2284 .ndo_set_rx_mode = rtl839x_eth_set_multicast_list,
2285 .ndo_tx_timeout = rtl838x_eth_tx_timeout,
2286 .ndo_set_features = rtl83xx_set_features,
2287 .ndo_fix_features = rtl838x_fix_features,
2288 .ndo_setup_tc = rtl83xx_setup_tc,
2289 };
2290
2291 static const struct net_device_ops rtl930x_eth_netdev_ops = {
2292 .ndo_open = rtl838x_eth_open,
2293 .ndo_stop = rtl838x_eth_stop,
2294 .ndo_start_xmit = rtl838x_eth_tx,
2295 .ndo_select_queue = rtl93xx_pick_tx_queue,
2296 .ndo_set_mac_address = rtl838x_set_mac_address,
2297 .ndo_validate_addr = eth_validate_addr,
2298 .ndo_set_rx_mode = rtl930x_eth_set_multicast_list,
2299 .ndo_tx_timeout = rtl838x_eth_tx_timeout,
2300 .ndo_set_features = rtl93xx_set_features,
2301 .ndo_fix_features = rtl838x_fix_features,
2302 .ndo_setup_tc = rtl83xx_setup_tc,
2303 };
2304
2305 static const struct net_device_ops rtl931x_eth_netdev_ops = {
2306 .ndo_open = rtl838x_eth_open,
2307 .ndo_stop = rtl838x_eth_stop,
2308 .ndo_start_xmit = rtl838x_eth_tx,
2309 .ndo_select_queue = rtl93xx_pick_tx_queue,
2310 .ndo_set_mac_address = rtl838x_set_mac_address,
2311 .ndo_validate_addr = eth_validate_addr,
2312 .ndo_set_rx_mode = rtl931x_eth_set_multicast_list,
2313 .ndo_tx_timeout = rtl838x_eth_tx_timeout,
2314 .ndo_set_features = rtl93xx_set_features,
2315 .ndo_fix_features = rtl838x_fix_features,
2316 };
2317
2318 static const struct phylink_mac_ops rtl838x_phylink_ops = {
2319 .validate = rtl838x_validate,
2320 .mac_pcs_get_state = rtl838x_mac_pcs_get_state,
2321 .mac_an_restart = rtl838x_mac_an_restart,
2322 .mac_config = rtl838x_mac_config,
2323 .mac_link_down = rtl838x_mac_link_down,
2324 .mac_link_up = rtl838x_mac_link_up,
2325 };
2326
2327 static const struct ethtool_ops rtl838x_ethtool_ops = {
2328 .get_link_ksettings = rtl838x_get_link_ksettings,
2329 .set_link_ksettings = rtl838x_set_link_ksettings,
2330 };
2331
2332 static int __init rtl838x_eth_probe(struct platform_device *pdev)
2333 {
2334 struct net_device *dev;
2335 struct device_node *dn = pdev->dev.of_node;
2336 struct rtl838x_eth_priv *priv;
2337 struct resource *res, *mem;
2338 phy_interface_t phy_mode;
2339 struct phylink *phylink;
2340 int err = 0, i, rxrings, rxringlen;
2341 struct ring_b *ring;
2342
2343 pr_info("Probing RTL838X eth device pdev: %x, dev: %x\n",
2344 (u32)pdev, (u32)(&(pdev->dev)));
2345
2346 if (!dn) {
2347 dev_err(&pdev->dev, "No DT found\n");
2348 return -EINVAL;
2349 }
2350
2351 rxrings = (soc_info.family == RTL8380_FAMILY_ID
2352 || soc_info.family == RTL8390_FAMILY_ID) ? 8 : 32;
2353 rxrings = rxrings > MAX_RXRINGS ? MAX_RXRINGS : rxrings;
2354 rxringlen = MAX_ENTRIES / rxrings;
2355 rxringlen = rxringlen > MAX_RXLEN ? MAX_RXLEN : rxringlen;
2356
2357 dev = alloc_etherdev_mqs(sizeof(struct rtl838x_eth_priv), TXRINGS, rxrings);
2358 if (!dev) {
2359 err = -ENOMEM;
2360 goto err_free;
2361 }
2362 SET_NETDEV_DEV(dev, &pdev->dev);
2363 priv = netdev_priv(dev);
2364
2365 /* obtain buffer memory space */
2366 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2367 if (res) {
2368 mem = devm_request_mem_region(&pdev->dev, res->start,
2369 resource_size(res), res->name);
2370 if (!mem) {
2371 dev_err(&pdev->dev, "cannot request memory space\n");
2372 err = -ENXIO;
2373 goto err_free;
2374 }
2375
2376 dev->mem_start = mem->start;
2377 dev->mem_end = mem->end;
2378 } else {
2379 dev_err(&pdev->dev, "cannot request IO resource\n");
2380 err = -ENXIO;
2381 goto err_free;
2382 }
2383
2384 /* Allocate buffer memory */
2385 priv->membase = dmam_alloc_coherent(&pdev->dev, rxrings * rxringlen * RING_BUFFER
2386 + sizeof(struct ring_b) + sizeof(struct notify_b),
2387 (void *)&dev->mem_start, GFP_KERNEL);
2388 if (!priv->membase) {
2389 dev_err(&pdev->dev, "cannot allocate DMA buffer\n");
2390 err = -ENOMEM;
2391 goto err_free;
2392 }
2393
2394 // Allocate ring-buffer space at the end of the allocated memory
2395 ring = priv->membase;
2396 ring->rx_space = priv->membase + sizeof(struct ring_b) + sizeof(struct notify_b);
2397
2398 spin_lock_init(&priv->lock);
2399
2400 dev->ethtool_ops = &rtl838x_ethtool_ops;
2401 dev->min_mtu = ETH_ZLEN;
2402 dev->max_mtu = 1536;
2403 dev->features = NETIF_F_RXCSUM | NETIF_F_HW_CSUM;
2404 dev->hw_features = NETIF_F_RXCSUM;
2405
2406 priv->id = soc_info.id;
2407 priv->family_id = soc_info.family;
2408 if (priv->id) {
2409 pr_info("Found SoC ID: %4x: %s, family %x\n",
2410 priv->id, soc_info.name, priv->family_id);
2411 } else {
2412 pr_err("Unknown chip id (%04x)\n", priv->id);
2413 return -ENODEV;
2414 }
2415
2416 switch (priv->family_id) {
2417 case RTL8380_FAMILY_ID:
2418 priv->cpu_port = RTL838X_CPU_PORT;
2419 priv->r = &rtl838x_reg;
2420 dev->netdev_ops = &rtl838x_eth_netdev_ops;
2421 break;
2422 case RTL8390_FAMILY_ID:
2423 priv->cpu_port = RTL839X_CPU_PORT;
2424 priv->r = &rtl839x_reg;
2425 dev->netdev_ops = &rtl839x_eth_netdev_ops;
2426 break;
2427 case RTL9300_FAMILY_ID:
2428 priv->cpu_port = RTL930X_CPU_PORT;
2429 priv->r = &rtl930x_reg;
2430 dev->netdev_ops = &rtl930x_eth_netdev_ops;
2431 break;
2432 case RTL9310_FAMILY_ID:
2433 priv->cpu_port = RTL931X_CPU_PORT;
2434 priv->r = &rtl931x_reg;
2435 dev->netdev_ops = &rtl931x_eth_netdev_ops;
2436 rtl931x_chip_init(priv);
2437 break;
2438 default:
2439 pr_err("Unknown SoC family\n");
2440 return -ENODEV;
2441 }
2442 priv->rxringlen = rxringlen;
2443 priv->rxrings = rxrings;
2444
2445 /* Obtain device IRQ number */
2446 dev->irq = platform_get_irq(pdev, 0);
2447 if (dev->irq < 0) {
2448 dev_err(&pdev->dev, "cannot obtain network-device IRQ\n");
2449 goto err_free;
2450 }
2451
2452 err = devm_request_irq(&pdev->dev, dev->irq, priv->r->net_irq,
2453 IRQF_SHARED, dev->name, dev);
2454 if (err) {
2455 dev_err(&pdev->dev, "%s: could not acquire interrupt: %d\n",
2456 __func__, err);
2457 goto err_free;
2458 }
2459
2460 rtl8380_init_mac(priv);
2461
2462 /* try to get mac address in the following order:
2463 * 1) from device tree data
2464 * 2) from internal registers set by bootloader
2465 */
2466 of_get_mac_address(pdev->dev.of_node, dev->dev_addr);
2467 if (is_valid_ether_addr(dev->dev_addr)) {
2468 rtl838x_set_mac_hw(dev, (u8 *)dev->dev_addr);
2469 } else {
2470 dev->dev_addr[0] = (sw_r32(priv->r->mac) >> 8) & 0xff;
2471 dev->dev_addr[1] = sw_r32(priv->r->mac) & 0xff;
2472 dev->dev_addr[2] = (sw_r32(priv->r->mac + 4) >> 24) & 0xff;
2473 dev->dev_addr[3] = (sw_r32(priv->r->mac + 4) >> 16) & 0xff;
2474 dev->dev_addr[4] = (sw_r32(priv->r->mac + 4) >> 8) & 0xff;
2475 dev->dev_addr[5] = sw_r32(priv->r->mac + 4) & 0xff;
2476 }
2477 /* if the address is invalid, use a random value */
2478 if (!is_valid_ether_addr(dev->dev_addr)) {
2479 struct sockaddr sa = { AF_UNSPEC };
2480
2481 netdev_warn(dev, "Invalid MAC address, using random\n");
2482 eth_hw_addr_random(dev);
2483 memcpy(sa.sa_data, dev->dev_addr, ETH_ALEN);
2484 if (rtl838x_set_mac_address(dev, &sa))
2485 netdev_warn(dev, "Failed to set MAC address.\n");
2486 }
2487 pr_info("Using MAC %08x%08x\n", sw_r32(priv->r->mac),
2488 sw_r32(priv->r->mac + 4));
2489 strcpy(dev->name, "eth%d");
2490 priv->pdev = pdev;
2491 priv->netdev = dev;
2492
2493 err = rtl838x_mdio_init(priv);
2494 if (err)
2495 goto err_free;
2496
2497 err = register_netdev(dev);
2498 if (err)
2499 goto err_free;
2500
2501 for (i = 0; i < priv->rxrings; i++) {
2502 priv->rx_qs[i].id = i;
2503 priv->rx_qs[i].priv = priv;
2504 netif_napi_add(dev, &priv->rx_qs[i].napi, rtl838x_poll_rx, 64);
2505 }
2506
2507 platform_set_drvdata(pdev, dev);
2508
2509 phy_mode = PHY_INTERFACE_MODE_NA;
2510 err = of_get_phy_mode(dn, &phy_mode);
2511 if (err < 0) {
2512 dev_err(&pdev->dev, "incorrect phy-mode\n");
2513 err = -EINVAL;
2514 goto err_free;
2515 }
2516 priv->phylink_config.dev = &dev->dev;
2517 priv->phylink_config.type = PHYLINK_NETDEV;
2518
2519 phylink = phylink_create(&priv->phylink_config, pdev->dev.fwnode,
2520 phy_mode, &rtl838x_phylink_ops);
2521
2522 if (IS_ERR(phylink)) {
2523 err = PTR_ERR(phylink);
2524 goto err_free;
2525 }
2526 priv->phylink = phylink;
2527
2528 return 0;
2529
2530 err_free:
2531 pr_err("Error setting up netdev, freeing it again.\n");
2532 free_netdev(dev);
2533 return err;
2534 }
2535
2536 static int rtl838x_eth_remove(struct platform_device *pdev)
2537 {
2538 struct net_device *dev = platform_get_drvdata(pdev);
2539 struct rtl838x_eth_priv *priv = netdev_priv(dev);
2540 int i;
2541
2542 if (dev) {
2543 pr_info("Removing platform driver for rtl838x-eth\n");
2544 rtl838x_mdio_remove(priv);
2545 rtl838x_hw_stop(priv);
2546
2547 netif_tx_stop_all_queues(dev);
2548
2549 for (i = 0; i < priv->rxrings; i++)
2550 netif_napi_del(&priv->rx_qs[i].napi);
2551
2552 unregister_netdev(dev);
2553 free_netdev(dev);
2554 }
2555 return 0;
2556 }
2557
2558 static const struct of_device_id rtl838x_eth_of_ids[] = {
2559 { .compatible = "realtek,rtl838x-eth"},
2560 { /* sentinel */ }
2561 };
2562 MODULE_DEVICE_TABLE(of, rtl838x_eth_of_ids);
2563
2564 static struct platform_driver rtl838x_eth_driver = {
2565 .probe = rtl838x_eth_probe,
2566 .remove = rtl838x_eth_remove,
2567 .driver = {
2568 .name = "rtl838x-eth",
2569 .pm = NULL,
2570 .of_match_table = rtl838x_eth_of_ids,
2571 },
2572 };
2573
2574 module_platform_driver(rtl838x_eth_driver);
2575
2576 MODULE_AUTHOR("B. Koblitz");
2577 MODULE_DESCRIPTION("RTL838X SoC Ethernet Driver");
2578 MODULE_LICENSE("GPL");
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