projects / openwrt / staging / jow.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
realtek: clean up rtl838x MDIO busy wait loop
[openwrt/staging/jow.git] / target / linux / realtek / files-5.10 / drivers / net / dsa / rtl83xx / rtl838x.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <asm/mach-rtl838x/mach-rtl83xx.h>
4 #include <net/nexthop.h>
5
6 #include "rtl83xx.h"
7
8 extern struct mutex smi_lock;
9
10 // see_dal_maple_acl_log2PhyTmplteField and src/app/diag_v2/src/diag_acl.c
11 /* Definition of the RTL838X-specific template field IDs as used in the PIE */
12 enum template_field_id {
13 TEMPLATE_FIELD_SPMMASK = 0,
14 TEMPLATE_FIELD_SPM0 = 1, // Source portmask ports 0-15
15 TEMPLATE_FIELD_SPM1 = 2, // Source portmask ports 16-28
16 TEMPLATE_FIELD_RANGE_CHK = 3,
17 TEMPLATE_FIELD_DMAC0 = 4, // Destination MAC [15:0]
18 TEMPLATE_FIELD_DMAC1 = 5, // Destination MAC [31:16]
19 TEMPLATE_FIELD_DMAC2 = 6, // Destination MAC [47:32]
20 TEMPLATE_FIELD_SMAC0 = 7, // Source MAC [15:0]
21 TEMPLATE_FIELD_SMAC1 = 8, // Source MAC [31:16]
22 TEMPLATE_FIELD_SMAC2 = 9, // Source MAC [47:32]
23 TEMPLATE_FIELD_ETHERTYPE = 10, // Ethernet typ
24 TEMPLATE_FIELD_OTAG = 11, // Outer VLAN tag
25 TEMPLATE_FIELD_ITAG = 12, // Inner VLAN tag
26 TEMPLATE_FIELD_SIP0 = 13, // IPv4 or IPv6 source IP[15:0] or ARP/RARP
27 // source protocol address in header
28 TEMPLATE_FIELD_SIP1 = 14, // IPv4 or IPv6 source IP[31:16] or ARP/RARP
29 TEMPLATE_FIELD_DIP0 = 15, // IPv4 or IPv6 destination IP[15:0]
30 TEMPLATE_FIELD_DIP1 = 16, // IPv4 or IPv6 destination IP[31:16]
31 TEMPLATE_FIELD_IP_TOS_PROTO = 17, // IPv4 TOS/IPv6 traffic class and
32 // IPv4 proto/IPv6 next header fields
33 TEMPLATE_FIELD_L34_HEADER = 18, // packet with extra tag and IPv6 with auth, dest,
34 // frag, route, hop-by-hop option header,
35 // IGMP type, TCP flag
36 TEMPLATE_FIELD_L4_SPORT = 19, // TCP/UDP source port
37 TEMPLATE_FIELD_L4_DPORT = 20, // TCP/UDP destination port
38 TEMPLATE_FIELD_ICMP_IGMP = 21,
39 TEMPLATE_FIELD_IP_RANGE = 22,
40 TEMPLATE_FIELD_FIELD_SELECTOR_VALID = 23, // Field selector mask
41 TEMPLATE_FIELD_FIELD_SELECTOR_0 = 24,
42 TEMPLATE_FIELD_FIELD_SELECTOR_1 = 25,
43 TEMPLATE_FIELD_FIELD_SELECTOR_2 = 26,
44 TEMPLATE_FIELD_FIELD_SELECTOR_3 = 27,
45 TEMPLATE_FIELD_SIP2 = 28, // IPv6 source IP[47:32]
46 TEMPLATE_FIELD_SIP3 = 29, // IPv6 source IP[63:48]
47 TEMPLATE_FIELD_SIP4 = 30, // IPv6 source IP[79:64]
48 TEMPLATE_FIELD_SIP5 = 31, // IPv6 source IP[95:80]
49 TEMPLATE_FIELD_SIP6 = 32, // IPv6 source IP[111:96]
50 TEMPLATE_FIELD_SIP7 = 33, // IPv6 source IP[127:112]
51 TEMPLATE_FIELD_DIP2 = 34, // IPv6 destination IP[47:32]
52 TEMPLATE_FIELD_DIP3 = 35, // IPv6 destination IP[63:48]
53 TEMPLATE_FIELD_DIP4 = 36, // IPv6 destination IP[79:64]
54 TEMPLATE_FIELD_DIP5 = 37, // IPv6 destination IP[95:80]
55 TEMPLATE_FIELD_DIP6 = 38, // IPv6 destination IP[111:96]
56 TEMPLATE_FIELD_DIP7 = 39, // IPv6 destination IP[127:112]
57 TEMPLATE_FIELD_FWD_VID = 40, // Forwarding VLAN-ID
58 TEMPLATE_FIELD_FLOW_LABEL = 41,
59 };
60
61 /*
62 * The RTL838X SoCs use 5 fixed templates with definitions for which data fields are to
63 * be copied from the Ethernet Frame header into the 12 User-definable fields of the Packet
64 * Inspection Engine's buffer. The following defines the field contents for each of the fixed
65 * templates. Additionally, 3 user-definable templates can be set up via the definitions
66 * in RTL838X_ACL_TMPLTE_CTRL control registers.
67 * TODO: See all src/app/diag_v2/src/diag_pie.c
68 */
69 #define N_FIXED_TEMPLATES 5
70 static enum template_field_id fixed_templates[N_FIXED_TEMPLATES][N_FIXED_FIELDS] =
71 {
72 {
73 TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1, TEMPLATE_FIELD_OTAG,
74 TEMPLATE_FIELD_SMAC0, TEMPLATE_FIELD_SMAC1, TEMPLATE_FIELD_SMAC2,
75 TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2,
76 TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_ITAG, TEMPLATE_FIELD_RANGE_CHK
77 }, {
78 TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0,
79 TEMPLATE_FIELD_DIP1,TEMPLATE_FIELD_IP_TOS_PROTO, TEMPLATE_FIELD_L4_SPORT,
80 TEMPLATE_FIELD_L4_DPORT, TEMPLATE_FIELD_ICMP_IGMP, TEMPLATE_FIELD_ITAG,
81 TEMPLATE_FIELD_RANGE_CHK, TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1
82 }, {
83 TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2,
84 TEMPLATE_FIELD_ITAG, TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_IP_TOS_PROTO,
85 TEMPLATE_FIELD_L4_DPORT, TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_SIP0,
86 TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0, TEMPLATE_FIELD_DIP1
87 }, {
88 TEMPLATE_FIELD_DIP0, TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_DIP2,
89 TEMPLATE_FIELD_DIP3, TEMPLATE_FIELD_DIP4, TEMPLATE_FIELD_DIP5,
90 TEMPLATE_FIELD_DIP6, TEMPLATE_FIELD_DIP7, TEMPLATE_FIELD_L4_DPORT,
91 TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_ICMP_IGMP, TEMPLATE_FIELD_IP_TOS_PROTO
92 }, {
93 TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_SIP2,
94 TEMPLATE_FIELD_SIP3, TEMPLATE_FIELD_SIP4, TEMPLATE_FIELD_SIP5,
95 TEMPLATE_FIELD_SIP6, TEMPLATE_FIELD_SIP7, TEMPLATE_FIELD_ITAG,
96 TEMPLATE_FIELD_RANGE_CHK, TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1
97 },
98 };
99
100 void rtl838x_print_matrix(void)
101 {
102 unsigned volatile int *ptr8;
103 int i;
104
105 ptr8 = RTL838X_SW_BASE + RTL838X_PORT_ISO_CTRL(0);
106 for (i = 0; i < 28; i += 8)
107 pr_debug("> %8x %8x %8x %8x %8x %8x %8x %8x\n",
108 ptr8[i + 0], ptr8[i + 1], ptr8[i + 2], ptr8[i + 3],
109 ptr8[i + 4], ptr8[i + 5], ptr8[i + 6], ptr8[i + 7]);
110 pr_debug("CPU_PORT> %8x\n", ptr8[28]);
111 }
112
113 static inline int rtl838x_port_iso_ctrl(int p)
114 {
115 return RTL838X_PORT_ISO_CTRL(p);
116 }
117
118 static inline void rtl838x_exec_tbl0_cmd(u32 cmd)
119 {
120 sw_w32(cmd, RTL838X_TBL_ACCESS_CTRL_0);
121 do { } while (sw_r32(RTL838X_TBL_ACCESS_CTRL_0) & BIT(15));
122 }
123
124 static inline void rtl838x_exec_tbl1_cmd(u32 cmd)
125 {
126 sw_w32(cmd, RTL838X_TBL_ACCESS_CTRL_1);
127 do { } while (sw_r32(RTL838X_TBL_ACCESS_CTRL_1) & BIT(15));
128 }
129
130 static inline int rtl838x_tbl_access_data_0(int i)
131 {
132 return RTL838X_TBL_ACCESS_DATA_0(i);
133 }
134
135 static void rtl838x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info)
136 {
137 u32 v;
138 // Read VLAN table (0) via register 0
139 struct table_reg *r = rtl_table_get(RTL8380_TBL_0, 0);
140
141 rtl_table_read(r, vlan);
142 info->tagged_ports = sw_r32(rtl_table_data(r, 0));
143 v = sw_r32(rtl_table_data(r, 1));
144 pr_debug("VLAN_READ %d: %016llx %08x\n", vlan, info->tagged_ports, v);
145 rtl_table_release(r);
146
147 info->profile_id = v & 0x7;
148 info->hash_mc_fid = !!(v & 0x8);
149 info->hash_uc_fid = !!(v & 0x10);
150 info->fid = (v >> 5) & 0x3f;
151
152 // Read UNTAG table (0) via table register 1
153 r = rtl_table_get(RTL8380_TBL_1, 0);
154 rtl_table_read(r, vlan);
155 info->untagged_ports = sw_r32(rtl_table_data(r, 0));
156 rtl_table_release(r);
157 }
158
159 static void rtl838x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info)
160 {
161 u32 v;
162 // Access VLAN table (0) via register 0
163 struct table_reg *r = rtl_table_get(RTL8380_TBL_0, 0);
164
165 sw_w32(info->tagged_ports, rtl_table_data(r, 0));
166
167 v = info->profile_id;
168 v |= info->hash_mc_fid ? 0x8 : 0;
169 v |= info->hash_uc_fid ? 0x10 : 0;
170 v |= ((u32)info->fid) << 5;
171 sw_w32(v, rtl_table_data(r, 1));
172
173 rtl_table_write(r, vlan);
174 rtl_table_release(r);
175 }
176
177 static void rtl838x_vlan_set_untagged(u32 vlan, u64 portmask)
178 {
179 // Access UNTAG table (0) via register 1
180 struct table_reg *r = rtl_table_get(RTL8380_TBL_1, 0);
181
182 sw_w32(portmask & 0x1fffffff, rtl_table_data(r, 0));
183 rtl_table_write(r, vlan);
184 rtl_table_release(r);
185 }
186
187 /* Sets the L2 forwarding to be based on either the inner VLAN tag or the outer
188 */
189 static void rtl838x_vlan_fwd_on_inner(int port, bool is_set)
190 {
191 if (is_set)
192 sw_w32_mask(BIT(port), 0, RTL838X_VLAN_PORT_FWD);
193 else
194 sw_w32_mask(0, BIT(port), RTL838X_VLAN_PORT_FWD);
195 }
196
197 static u64 rtl838x_l2_hash_seed(u64 mac, u32 vid)
198 {
199 return mac << 12 | vid;
200 }
201
202 /*
203 * Applies the same hash algorithm as the one used currently by the ASIC to the seed
204 * and returns a key into the L2 hash table
205 */
206 static u32 rtl838x_l2_hash_key(struct rtl838x_switch_priv *priv, u64 seed)
207 {
208 u32 h1, h2, h3, h;
209
210 if (sw_r32(priv->r->l2_ctrl_0) & 1) {
211 h1 = (seed >> 11) & 0x7ff;
212 h1 = ((h1 & 0x1f) << 6) | ((h1 >> 5) & 0x3f);
213
214 h2 = (seed >> 33) & 0x7ff;
215 h2 = ((h2 & 0x3f) << 5) | ((h2 >> 6) & 0x1f);
216
217 h3 = (seed >> 44) & 0x7ff;
218 h3 = ((h3 & 0x7f) << 4) | ((h3 >> 7) & 0xf);
219
220 h = h1 ^ h2 ^ h3 ^ ((seed >> 55) & 0x1ff);
221 h ^= ((seed >> 22) & 0x7ff) ^ (seed & 0x7ff);
222 } else {
223 h = ((seed >> 55) & 0x1ff) ^ ((seed >> 44) & 0x7ff)
224 ^ ((seed >> 33) & 0x7ff) ^ ((seed >> 22) & 0x7ff)
225 ^ ((seed >> 11) & 0x7ff) ^ (seed & 0x7ff);
226 }
227
228 return h;
229 }
230
231 static inline int rtl838x_mac_force_mode_ctrl(int p)
232 {
233 return RTL838X_MAC_FORCE_MODE_CTRL + (p << 2);
234 }
235
236 static inline int rtl838x_mac_port_ctrl(int p)
237 {
238 return RTL838X_MAC_PORT_CTRL(p);
239 }
240
241 static inline int rtl838x_l2_port_new_salrn(int p)
242 {
243 return RTL838X_L2_PORT_NEW_SALRN(p);
244 }
245
246 static inline int rtl838x_l2_port_new_sa_fwd(int p)
247 {
248 return RTL838X_L2_PORT_NEW_SA_FWD(p);
249 }
250
251 static inline int rtl838x_mac_link_spd_sts(int p)
252 {
253 return RTL838X_MAC_LINK_SPD_STS(p);
254 }
255
256 inline static int rtl838x_trk_mbr_ctr(int group)
257 {
258 return RTL838X_TRK_MBR_CTR + (group << 2);
259 }
260
261 /*
262 * Fills an L2 entry structure from the SoC registers
263 */
264 static void rtl838x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e)
265 {
266 /* Table contains different entry types, we need to identify the right one:
267 * Check for MC entries, first
268 * In contrast to the RTL93xx SoCs, there is no valid bit, use heuristics to
269 * identify valid entries
270 */
271 e->is_ip_mc = !!(r[0] & BIT(22));
272 e->is_ipv6_mc = !!(r[0] & BIT(21));
273 e->type = L2_INVALID;
274
275 if (!e->is_ip_mc && !e->is_ipv6_mc) {
276 e->mac[0] = (r[1] >> 20);
277 e->mac[1] = (r[1] >> 12);
278 e->mac[2] = (r[1] >> 4);
279 e->mac[3] = (r[1] & 0xf) << 4 | (r[2] >> 28);
280 e->mac[4] = (r[2] >> 20);
281 e->mac[5] = (r[2] >> 12);
282
283 e->rvid = r[2] & 0xfff;
284 e->vid = r[0] & 0xfff;
285
286 /* Is it a unicast entry? check multicast bit */
287 if (!(e->mac[0] & 1)) {
288 e->is_static = !!((r[0] >> 19) & 1);
289 e->port = (r[0] >> 12) & 0x1f;
290 e->block_da = !!(r[1] & BIT(30));
291 e->block_sa = !!(r[1] & BIT(31));
292 e->suspended = !!(r[1] & BIT(29));
293 e->next_hop = !!(r[1] & BIT(28));
294 if (e->next_hop) {
295 pr_debug("Found next hop entry, need to read extra data\n");
296 e->nh_vlan_target = !!(r[0] & BIT(9));
297 e->nh_route_id = r[0] & 0x1ff;
298 e->vid = e->rvid;
299 }
300 e->age = (r[0] >> 17) & 0x3;
301 e->valid = true;
302
303 /* A valid entry has one of mutli-cast, aging, sa/da-blocking,
304 * next-hop or static entry bit set */
305 if (!(r[0] & 0x007c0000) && !(r[1] & 0xd0000000))
306 e->valid = false;
307 else
308 e->type = L2_UNICAST;
309 } else { // L2 multicast
310 pr_debug("Got L2 MC entry: %08x %08x %08x\n", r[0], r[1], r[2]);
311 e->valid = true;
312 e->type = L2_MULTICAST;
313 e->mc_portmask_index = (r[0] >> 12) & 0x1ff;
314 }
315 } else { // IPv4 and IPv6 multicast
316 e->valid = true;
317 e->mc_portmask_index = (r[0] >> 12) & 0x1ff;
318 e->mc_gip = (r[1] << 20) | (r[2] >> 12);
319 e->rvid = r[2] & 0xfff;
320 }
321 if (e->is_ip_mc)
322 e->type = IP4_MULTICAST;
323 if (e->is_ipv6_mc)
324 e->type = IP6_MULTICAST;
325 }
326
327 /*
328 * Fills the 3 SoC table registers r[] with the information of in the rtl838x_l2_entry
329 */
330 static void rtl838x_fill_l2_row(u32 r[], struct rtl838x_l2_entry *e)
331 {
332 u64 mac = ether_addr_to_u64(e->mac);
333
334 if (!e->valid) {
335 r[0] = r[1] = r[2] = 0;
336 return;
337 }
338
339 r[0] = e->is_ip_mc ? BIT(22) : 0;
340 r[0] |= e->is_ipv6_mc ? BIT(21) : 0;
341
342 if (!e->is_ip_mc && !e->is_ipv6_mc) {
343 r[1] = mac >> 20;
344 r[2] = (mac & 0xfffff) << 12;
345
346 /* Is it a unicast entry? check multicast bit */
347 if (!(e->mac[0] & 1)) {
348 r[0] |= e->is_static ? BIT(19) : 0;
349 r[0] |= (e->port & 0x3f) << 12;
350 r[0] |= e->vid;
351 r[1] |= e->block_da ? BIT(30) : 0;
352 r[1] |= e->block_sa ? BIT(31) : 0;
353 r[1] |= e->suspended ? BIT(29) : 0;
354 r[2] |= e->rvid & 0xfff;
355 if (e->next_hop) {
356 r[1] |= BIT(28);
357 r[0] |= e->nh_vlan_target ? BIT(9) : 0;
358 r[0] |= e->nh_route_id & 0x1ff;
359 }
360 r[0] |= (e->age & 0x3) << 17;
361 } else { // L2 Multicast
362 r[0] |= (e->mc_portmask_index & 0x1ff) << 12;
363 r[2] |= e->rvid & 0xfff;
364 r[0] |= e->vid & 0xfff;
365 pr_debug("FILL MC: %08x %08x %08x\n", r[0], r[1], r[2]);
366 }
367 } else { // IPv4 and IPv6 multicast
368 r[0] |= (e->mc_portmask_index & 0x1ff) << 12;
369 r[1] = e->mc_gip >> 20;
370 r[2] = e->mc_gip << 12;
371 r[2] |= e->rvid;
372 }
373 }
374
375 /*
376 * Read an L2 UC or MC entry out of a hash bucket of the L2 forwarding table
377 * hash is the id of the bucket and pos is the position of the entry in that bucket
378 * The data read from the SoC is filled into rtl838x_l2_entry
379 */
380 static u64 rtl838x_read_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e)
381 {
382 u64 entry;
383 u32 r[3];
384 struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 0); // Access L2 Table 0
385 u32 idx = (0 << 14) | (hash << 2) | pos; // Search SRAM, with hash and at pos in bucket
386 int i;
387
388 rtl_table_read(q, idx);
389 for (i= 0; i < 3; i++)
390 r[i] = sw_r32(rtl_table_data(q, i));
391
392 rtl_table_release(q);
393
394 rtl838x_fill_l2_entry(r, e);
395 if (!e->valid)
396 return 0;
397
398 entry = (((u64) r[1]) << 32) | (r[2]); // mac and vid concatenated as hash seed
399 return entry;
400 }
401
402 static void rtl838x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e)
403 {
404 u32 r[3];
405 struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 0);
406 int i;
407
408 u32 idx = (0 << 14) | (hash << 2) | pos; // Access SRAM, with hash and at pos in bucket
409
410 rtl838x_fill_l2_row(r, e);
411
412 for (i= 0; i < 3; i++)
413 sw_w32(r[i], rtl_table_data(q, i));
414
415 rtl_table_write(q, idx);
416 rtl_table_release(q);
417 }
418
419 static u64 rtl838x_read_cam(int idx, struct rtl838x_l2_entry *e)
420 {
421 u64 entry;
422 u32 r[3];
423 struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 1); // Access L2 Table 1
424 int i;
425
426 rtl_table_read(q, idx);
427 for (i= 0; i < 3; i++)
428 r[i] = sw_r32(rtl_table_data(q, i));
429
430 rtl_table_release(q);
431
432 rtl838x_fill_l2_entry(r, e);
433 if (!e->valid)
434 return 0;
435
436 pr_debug("Found in CAM: R1 %x R2 %x R3 %x\n", r[0], r[1], r[2]);
437
438 // Return MAC with concatenated VID ac concatenated ID
439 entry = (((u64) r[1]) << 32) | r[2];
440 return entry;
441 }
442
443 static void rtl838x_write_cam(int idx, struct rtl838x_l2_entry *e)
444 {
445 u32 r[3];
446 struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 1); // Access L2 Table 1
447 int i;
448
449 rtl838x_fill_l2_row(r, e);
450
451 for (i= 0; i < 3; i++)
452 sw_w32(r[i], rtl_table_data(q, i));
453
454 rtl_table_write(q, idx);
455 rtl_table_release(q);
456 }
457
458 static u64 rtl838x_read_mcast_pmask(int idx)
459 {
460 u32 portmask;
461 // Read MC_PMSK (2) via register RTL8380_TBL_L2
462 struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 2);
463
464 rtl_table_read(q, idx);
465 portmask = sw_r32(rtl_table_data(q, 0));
466 rtl_table_release(q);
467
468 return portmask;
469 }
470
471 static void rtl838x_write_mcast_pmask(int idx, u64 portmask)
472 {
473 // Access MC_PMSK (2) via register RTL8380_TBL_L2
474 struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 2);
475
476 sw_w32(((u32)portmask) & 0x1fffffff, rtl_table_data(q, 0));
477 rtl_table_write(q, idx);
478 rtl_table_release(q);
479 }
480
481 static void rtl838x_vlan_profile_setup(int profile)
482 {
483 u32 pmask_id = UNKNOWN_MC_PMASK;
484 // Enable L2 Learning BIT 0, portmask UNKNOWN_MC_PMASK for unknown MC traffic flooding
485 u32 p = 1 | pmask_id << 1 | pmask_id << 10 | pmask_id << 19;
486
487 sw_w32(p, RTL838X_VLAN_PROFILE(profile));
488
489 /* RTL8380 and RTL8390 use an index into the portmask table to set the
490 * unknown multicast portmask, setup a default at a safe location
491 * On RTL93XX, the portmask is directly set in the profile,
492 * see e.g. rtl9300_vlan_profile_setup
493 */
494 rtl838x_write_mcast_pmask(UNKNOWN_MC_PMASK, 0x1fffffff);
495 }
496
497 static void rtl838x_l2_learning_setup(void)
498 {
499 /* Set portmask for broadcast traffic and unknown unicast address flooding
500 * to the reserved entry in the portmask table used also for
501 * multicast flooding */
502 sw_w32(UNKNOWN_MC_PMASK << 12 | UNKNOWN_MC_PMASK, RTL838X_L2_FLD_PMSK);
503
504 /* Enable learning constraint system-wide (bit 0), per-port (bit 1)
505 * and per vlan (bit 2) */
506 sw_w32(0x7, RTL838X_L2_LRN_CONSTRT_EN);
507
508 // Limit learning to maximum: 16k entries, after that just flood (bits 0-1)
509 sw_w32((0x3fff << 2) | 0, RTL838X_L2_LRN_CONSTRT);
510
511 // Do not trap ARP packets to CPU_PORT
512 sw_w32(0, RTL838X_SPCL_TRAP_ARP_CTRL);
513 }
514
515 static void rtl838x_enable_learning(int port, bool enable)
516 {
517 // Limit learning to maximum: 32k entries, after that just flood (bits 0-1)
518
519 if (enable) {
520 // flood after 32k entries
521 sw_w32((0x3fff << 2) | 0, RTL838X_L2_PORT_LRN_CONSTRT + (port << 2));
522 } else {
523 // just forward
524 sw_w32(0, RTL838X_L2_PORT_LRN_CONSTRT + (port << 2));
525 }
526 }
527
528 static void rtl838x_enable_flood(int port, bool enable)
529 {
530 u32 flood_mask = sw_r32(RTL838X_L2_PORT_LRN_CONSTRT + (port << 2));
531
532 if (enable) {
533 // flood
534 flood_mask &= ~3;
535 flood_mask |= 0;
536 sw_w32(flood_mask, RTL838X_L2_PORT_LRN_CONSTRT + (port << 2));
537 } else {
538 // drop (bit 1)
539 flood_mask &= ~3;
540 flood_mask |= 1;
541 sw_w32(flood_mask, RTL838X_L2_PORT_LRN_CONSTRT + (port << 2));
542 }
543 }
544
545 static void rtl838x_enable_mcast_flood(int port, bool enable)
546 {
547
548 }
549
550 static void rtl838x_enable_bcast_flood(int port, bool enable)
551 {
552
553 }
554
555 static void rtl838x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
556 {
557 int i;
558 u32 cmd = 1 << 15 /* Execute cmd */
559 | 1 << 14 /* Read */
560 | 2 << 12 /* Table type 0b10 */
561 | (msti & 0xfff);
562 priv->r->exec_tbl0_cmd(cmd);
563
564 for (i = 0; i < 2; i++)
565 port_state[i] = sw_r32(priv->r->tbl_access_data_0(i));
566 }
567
568 static void rtl838x_stp_set(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
569 {
570 int i;
571 u32 cmd = 1 << 15 /* Execute cmd */
572 | 0 << 14 /* Write */
573 | 2 << 12 /* Table type 0b10 */
574 | (msti & 0xfff);
575
576 for (i = 0; i < 2; i++)
577 sw_w32(port_state[i], priv->r->tbl_access_data_0(i));
578 priv->r->exec_tbl0_cmd(cmd);
579 }
580
581 u64 rtl838x_traffic_get(int source)
582 {
583 return rtl838x_get_port_reg(rtl838x_port_iso_ctrl(source));
584 }
585
586 void rtl838x_traffic_set(int source, u64 dest_matrix)
587 {
588 rtl838x_set_port_reg(dest_matrix, rtl838x_port_iso_ctrl(source));
589 }
590
591 void rtl838x_traffic_enable(int source, int dest)
592 {
593 rtl838x_mask_port_reg(0, BIT(dest), rtl838x_port_iso_ctrl(source));
594 }
595
596 void rtl838x_traffic_disable(int source, int dest)
597 {
598 rtl838x_mask_port_reg(BIT(dest), 0, rtl838x_port_iso_ctrl(source));
599 }
600
601 /*
602 * Enables or disables the EEE/EEEP capability of a port
603 */
604 static void rtl838x_port_eee_set(struct rtl838x_switch_priv *priv, int port, bool enable)
605 {
606 u32 v;
607
608 // This works only for Ethernet ports, and on the RTL838X, ports from 24 are SFP
609 if (port >= 24)
610 return;
611
612 pr_debug("In %s: setting port %d to %d\n", __func__, port, enable);
613 v = enable ? 0x3 : 0x0;
614
615 // Set EEE state for 100 (bit 9) & 1000MBit (bit 10)
616 sw_w32_mask(0x3 << 9, v << 9, priv->r->mac_force_mode_ctrl(port));
617
618 // Set TX/RX EEE state
619 if (enable) {
620 sw_w32_mask(0, BIT(port), RTL838X_EEE_PORT_TX_EN);
621 sw_w32_mask(0, BIT(port), RTL838X_EEE_PORT_RX_EN);
622 } else {
623 sw_w32_mask(BIT(port), 0, RTL838X_EEE_PORT_TX_EN);
624 sw_w32_mask(BIT(port), 0, RTL838X_EEE_PORT_RX_EN);
625 }
626 priv->ports[port].eee_enabled = enable;
627 }
628
629
630 /*
631 * Get EEE own capabilities and negotiation result
632 */
633 static int rtl838x_eee_port_ability(struct rtl838x_switch_priv *priv,
634 struct ethtool_eee *e, int port)
635 {
636 u64 link;
637
638 if (port >= 24)
639 return 0;
640
641 link = rtl839x_get_port_reg_le(RTL838X_MAC_LINK_STS);
642 if (!(link & BIT(port)))
643 return 0;
644
645 if (sw_r32(rtl838x_mac_force_mode_ctrl(port)) & BIT(9))
646 e->advertised |= ADVERTISED_100baseT_Full;
647
648 if (sw_r32(rtl838x_mac_force_mode_ctrl(port)) & BIT(10))
649 e->advertised |= ADVERTISED_1000baseT_Full;
650
651 if (sw_r32(RTL838X_MAC_EEE_ABLTY) & BIT(port)) {
652 e->lp_advertised = ADVERTISED_100baseT_Full;
653 e->lp_advertised |= ADVERTISED_1000baseT_Full;
654 return 1;
655 }
656
657 return 0;
658 }
659
660 static void rtl838x_init_eee(struct rtl838x_switch_priv *priv, bool enable)
661 {
662 int i;
663
664 pr_info("Setting up EEE, state: %d\n", enable);
665 sw_w32_mask(0x4, 0, RTL838X_SMI_GLB_CTRL);
666
667 /* Set timers for EEE */
668 sw_w32(0x5001411, RTL838X_EEE_TX_TIMER_GIGA_CTRL);
669 sw_w32(0x5001417, RTL838X_EEE_TX_TIMER_GELITE_CTRL);
670
671 // Enable EEE MAC support on ports
672 for (i = 0; i < priv->cpu_port; i++) {
673 if (priv->ports[i].phy)
674 rtl838x_port_eee_set(priv, i, enable);
675 }
676 priv->eee_enabled = enable;
677 }
678
679 static void rtl838x_pie_lookup_enable(struct rtl838x_switch_priv *priv, int index)
680 {
681 int block = index / PIE_BLOCK_SIZE;
682 u32 block_state = sw_r32(RTL838X_ACL_BLK_LOOKUP_CTRL);
683
684 // Make sure rule-lookup is enabled in the block
685 if (!(block_state & BIT(block)))
686 sw_w32(block_state | BIT(block), RTL838X_ACL_BLK_LOOKUP_CTRL);
687 }
688
689 static void rtl838x_pie_rule_del(struct rtl838x_switch_priv *priv, int index_from, int index_to)
690 {
691 int block_from = index_from / PIE_BLOCK_SIZE;
692 int block_to = index_to / PIE_BLOCK_SIZE;
693 u32 v = (index_from << 1)| (index_to << 12 ) | BIT(0);
694 int block;
695 u32 block_state;
696
697 pr_debug("%s: from %d to %d\n", __func__, index_from, index_to);
698 mutex_lock(&priv->reg_mutex);
699
700 // Remember currently active blocks
701 block_state = sw_r32(RTL838X_ACL_BLK_LOOKUP_CTRL);
702
703 // Make sure rule-lookup is disabled in the relevant blocks
704 for (block = block_from; block <= block_to; block++) {
705 if (block_state & BIT(block))
706 sw_w32(block_state & (~BIT(block)), RTL838X_ACL_BLK_LOOKUP_CTRL);
707 }
708
709 // Write from-to and execute bit into control register
710 sw_w32(v, RTL838X_ACL_CLR_CTRL);
711
712 // Wait until command has completed
713 do {
714 } while (sw_r32(RTL838X_ACL_CLR_CTRL) & BIT(0));
715
716 // Re-enable rule lookup
717 for (block = block_from; block <= block_to; block++) {
718 if (!(block_state & BIT(block)))
719 sw_w32(block_state | BIT(block), RTL838X_ACL_BLK_LOOKUP_CTRL);
720 }
721
722 mutex_unlock(&priv->reg_mutex);
723 }
724
725 /*
726 * Reads the intermediate representation of the templated match-fields of the
727 * PIE rule in the pie_rule structure and fills in the raw data fields in the
728 * raw register space r[].
729 * The register space configuration size is identical for the RTL8380/90 and RTL9300,
730 * however the RTL9310 has 2 more registers / fields and the physical field-ids
731 * are specific to every platform.
732 */
733 static void rtl838x_write_pie_templated(u32 r[], struct pie_rule *pr, enum template_field_id t[])
734 {
735 int i;
736 enum template_field_id field_type;
737 u16 data, data_m;
738
739 for (i = 0; i < N_FIXED_FIELDS; i++) {
740 field_type = t[i];
741 data = data_m = 0;
742
743 switch (field_type) {
744 case TEMPLATE_FIELD_SPM0:
745 data = pr->spm;
746 data_m = pr->spm_m;
747 break;
748 case TEMPLATE_FIELD_SPM1:
749 data = pr->spm >> 16;
750 data_m = pr->spm_m >> 16;
751 break;
752 case TEMPLATE_FIELD_OTAG:
753 data = pr->otag;
754 data_m = pr->otag_m;
755 break;
756 case TEMPLATE_FIELD_SMAC0:
757 data = pr->smac[4];
758 data = (data << 8) | pr->smac[5];
759 data_m = pr->smac_m[4];
760 data_m = (data_m << 8) | pr->smac_m[5];
761 break;
762 case TEMPLATE_FIELD_SMAC1:
763 data = pr->smac[2];
764 data = (data << 8) | pr->smac[3];
765 data_m = pr->smac_m[2];
766 data_m = (data_m << 8) | pr->smac_m[3];
767 break;
768 case TEMPLATE_FIELD_SMAC2:
769 data = pr->smac[0];
770 data = (data << 8) | pr->smac[1];
771 data_m = pr->smac_m[0];
772 data_m = (data_m << 8) | pr->smac_m[1];
773 break;
774 case TEMPLATE_FIELD_DMAC0:
775 data = pr->dmac[4];
776 data = (data << 8) | pr->dmac[5];
777 data_m = pr->dmac_m[4];
778 data_m = (data_m << 8) | pr->dmac_m[5];
779 break;
780 case TEMPLATE_FIELD_DMAC1:
781 data = pr->dmac[2];
782 data = (data << 8) | pr->dmac[3];
783 data_m = pr->dmac_m[2];
784 data_m = (data_m << 8) | pr->dmac_m[3];
785 break;
786 case TEMPLATE_FIELD_DMAC2:
787 data = pr->dmac[0];
788 data = (data << 8) | pr->dmac[1];
789 data_m = pr->dmac_m[0];
790 data_m = (data_m << 8) | pr->dmac_m[1];
791 break;
792 case TEMPLATE_FIELD_ETHERTYPE:
793 data = pr->ethertype;
794 data_m = pr->ethertype_m;
795 break;
796 case TEMPLATE_FIELD_ITAG:
797 data = pr->itag;
798 data_m = pr->itag_m;
799 break;
800 case TEMPLATE_FIELD_RANGE_CHK:
801 data = pr->field_range_check;
802 data_m = pr->field_range_check_m;
803 break;
804 case TEMPLATE_FIELD_SIP0:
805 if (pr->is_ipv6) {
806 data = pr->sip6.s6_addr16[7];
807 data_m = pr->sip6_m.s6_addr16[7];
808 } else {
809 data = pr->sip;
810 data_m = pr->sip_m;
811 }
812 break;
813 case TEMPLATE_FIELD_SIP1:
814 if (pr->is_ipv6) {
815 data = pr->sip6.s6_addr16[6];
816 data_m = pr->sip6_m.s6_addr16[6];
817 } else {
818 data = pr->sip >> 16;
819 data_m = pr->sip_m >> 16;
820 }
821 break;
822
823 case TEMPLATE_FIELD_SIP2:
824 case TEMPLATE_FIELD_SIP3:
825 case TEMPLATE_FIELD_SIP4:
826 case TEMPLATE_FIELD_SIP5:
827 case TEMPLATE_FIELD_SIP6:
828 case TEMPLATE_FIELD_SIP7:
829 data = pr->sip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)];
830 data_m = pr->sip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)];
831 break;
832
833 case TEMPLATE_FIELD_DIP0:
834 if (pr->is_ipv6) {
835 data = pr->dip6.s6_addr16[7];
836 data_m = pr->dip6_m.s6_addr16[7];
837 } else {
838 data = pr->dip;
839 data_m = pr->dip_m;
840 }
841 break;
842
843 case TEMPLATE_FIELD_DIP1:
844 if (pr->is_ipv6) {
845 data = pr->dip6.s6_addr16[6];
846 data_m = pr->dip6_m.s6_addr16[6];
847 } else {
848 data = pr->dip >> 16;
849 data_m = pr->dip_m >> 16;
850 }
851 break;
852
853 case TEMPLATE_FIELD_DIP2:
854 case TEMPLATE_FIELD_DIP3:
855 case TEMPLATE_FIELD_DIP4:
856 case TEMPLATE_FIELD_DIP5:
857 case TEMPLATE_FIELD_DIP6:
858 case TEMPLATE_FIELD_DIP7:
859 data = pr->dip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)];
860 data_m = pr->dip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)];
861 break;
862
863 case TEMPLATE_FIELD_IP_TOS_PROTO:
864 data = pr->tos_proto;
865 data_m = pr->tos_proto_m;
866 break;
867 case TEMPLATE_FIELD_L4_SPORT:
868 data = pr->sport;
869 data_m = pr->sport_m;
870 break;
871 case TEMPLATE_FIELD_L4_DPORT:
872 data = pr->dport;
873 data_m = pr->dport_m;
874 break;
875 case TEMPLATE_FIELD_ICMP_IGMP:
876 data = pr->icmp_igmp;
877 data_m = pr->icmp_igmp_m;
878 break;
879 default:
880 pr_info("%s: unknown field %d\n", __func__, field_type);
881 continue;
882 }
883 if (!(i % 2)) {
884 r[5 - i / 2] = data;
885 r[12 - i / 2] = data_m;
886 } else {
887 r[5 - i / 2] |= ((u32)data) << 16;
888 r[12 - i / 2] |= ((u32)data_m) << 16;
889 }
890 }
891 }
892
893 /*
894 * Creates the intermediate representation of the templated match-fields of the
895 * PIE rule in the pie_rule structure by reading the raw data fields in the
896 * raw register space r[].
897 * The register space configuration size is identical for the RTL8380/90 and RTL9300,
898 * however the RTL9310 has 2 more registers / fields and the physical field-ids
899 */
900 static void rtl838x_read_pie_templated(u32 r[], struct pie_rule *pr, enum template_field_id t[])
901 {
902 int i;
903 enum template_field_id field_type;
904 u16 data, data_m;
905
906 for (i = 0; i < N_FIXED_FIELDS; i++) {
907 field_type = t[i];
908 if (!(i % 2)) {
909 data = r[5 - i / 2];
910 data_m = r[12 - i / 2];
911 } else {
912 data = r[5 - i / 2] >> 16;
913 data_m = r[12 - i / 2] >> 16;
914 }
915
916 switch (field_type) {
917 case TEMPLATE_FIELD_SPM0:
918 pr->spm = (pr->spn << 16) | data;
919 pr->spm_m = (pr->spn << 16) | data_m;
920 break;
921 case TEMPLATE_FIELD_SPM1:
922 pr->spm = data;
923 pr->spm_m = data_m;
924 break;
925 case TEMPLATE_FIELD_OTAG:
926 pr->otag = data;
927 pr->otag_m = data_m;
928 break;
929 case TEMPLATE_FIELD_SMAC0:
930 pr->smac[4] = data >> 8;
931 pr->smac[5] = data;
932 pr->smac_m[4] = data >> 8;
933 pr->smac_m[5] = data;
934 break;
935 case TEMPLATE_FIELD_SMAC1:
936 pr->smac[2] = data >> 8;
937 pr->smac[3] = data;
938 pr->smac_m[2] = data >> 8;
939 pr->smac_m[3] = data;
940 break;
941 case TEMPLATE_FIELD_SMAC2:
942 pr->smac[0] = data >> 8;
943 pr->smac[1] = data;
944 pr->smac_m[0] = data >> 8;
945 pr->smac_m[1] = data;
946 break;
947 case TEMPLATE_FIELD_DMAC0:
948 pr->dmac[4] = data >> 8;
949 pr->dmac[5] = data;
950 pr->dmac_m[4] = data >> 8;
951 pr->dmac_m[5] = data;
952 break;
953 case TEMPLATE_FIELD_DMAC1:
954 pr->dmac[2] = data >> 8;
955 pr->dmac[3] = data;
956 pr->dmac_m[2] = data >> 8;
957 pr->dmac_m[3] = data;
958 break;
959 case TEMPLATE_FIELD_DMAC2:
960 pr->dmac[0] = data >> 8;
961 pr->dmac[1] = data;
962 pr->dmac_m[0] = data >> 8;
963 pr->dmac_m[1] = data;
964 break;
965 case TEMPLATE_FIELD_ETHERTYPE:
966 pr->ethertype = data;
967 pr->ethertype_m = data_m;
968 break;
969 case TEMPLATE_FIELD_ITAG:
970 pr->itag = data;
971 pr->itag_m = data_m;
972 break;
973 case TEMPLATE_FIELD_RANGE_CHK:
974 pr->field_range_check = data;
975 pr->field_range_check_m = data_m;
976 break;
977 case TEMPLATE_FIELD_SIP0:
978 pr->sip = data;
979 pr->sip_m = data_m;
980 break;
981 case TEMPLATE_FIELD_SIP1:
982 pr->sip = (pr->sip << 16) | data;
983 pr->sip_m = (pr->sip << 16) | data_m;
984 break;
985 case TEMPLATE_FIELD_SIP2:
986 pr->is_ipv6 = true;
987 // Make use of limitiations on the position of the match values
988 ipv6_addr_set(&pr->sip6, pr->sip, r[5 - i / 2],
989 r[4 - i / 2], r[3 - i / 2]);
990 ipv6_addr_set(&pr->sip6_m, pr->sip_m, r[5 - i / 2],
991 r[4 - i / 2], r[3 - i / 2]);
992 case TEMPLATE_FIELD_SIP3:
993 case TEMPLATE_FIELD_SIP4:
994 case TEMPLATE_FIELD_SIP5:
995 case TEMPLATE_FIELD_SIP6:
996 case TEMPLATE_FIELD_SIP7:
997 break;
998
999 case TEMPLATE_FIELD_DIP0:
1000 pr->dip = data;
1001 pr->dip_m = data_m;
1002 break;
1003 case TEMPLATE_FIELD_DIP1:
1004 pr->dip = (pr->dip << 16) | data;
1005 pr->dip_m = (pr->dip << 16) | data_m;
1006 break;
1007 case TEMPLATE_FIELD_DIP2:
1008 pr->is_ipv6 = true;
1009 ipv6_addr_set(&pr->dip6, pr->dip, r[5 - i / 2],
1010 r[4 - i / 2], r[3 - i / 2]);
1011 ipv6_addr_set(&pr->dip6_m, pr->dip_m, r[5 - i / 2],
1012 r[4 - i / 2], r[3 - i / 2]);
1013 case TEMPLATE_FIELD_DIP3:
1014 case TEMPLATE_FIELD_DIP4:
1015 case TEMPLATE_FIELD_DIP5:
1016 case TEMPLATE_FIELD_DIP6:
1017 case TEMPLATE_FIELD_DIP7:
1018 break;
1019 case TEMPLATE_FIELD_IP_TOS_PROTO:
1020 pr->tos_proto = data;
1021 pr->tos_proto_m = data_m;
1022 break;
1023 case TEMPLATE_FIELD_L4_SPORT:
1024 pr->sport = data;
1025 pr->sport_m = data_m;
1026 break;
1027 case TEMPLATE_FIELD_L4_DPORT:
1028 pr->dport = data;
1029 pr->dport_m = data_m;
1030 break;
1031 case TEMPLATE_FIELD_ICMP_IGMP:
1032 pr->icmp_igmp = data;
1033 pr->icmp_igmp_m = data_m;
1034 break;
1035 default:
1036 pr_info("%s: unknown field %d\n", __func__, field_type);
1037 }
1038 }
1039 }
1040
1041 static void rtl838x_read_pie_fixed_fields(u32 r[], struct pie_rule *pr)
1042 {
1043 pr->spmmask_fix = (r[6] >> 22) & 0x3;
1044 pr->spn = (r[6] >> 16) & 0x3f;
1045 pr->mgnt_vlan = (r[6] >> 15) & 1;
1046 pr->dmac_hit_sw = (r[6] >> 14) & 1;
1047 pr->not_first_frag = (r[6] >> 13) & 1;
1048 pr->frame_type_l4 = (r[6] >> 10) & 7;
1049 pr->frame_type = (r[6] >> 8) & 3;
1050 pr->otag_fmt = (r[6] >> 7) & 1;
1051 pr->itag_fmt = (r[6] >> 6) & 1;
1052 pr->otag_exist = (r[6] >> 5) & 1;
1053 pr->itag_exist = (r[6] >> 4) & 1;
1054 pr->frame_type_l2 = (r[6] >> 2) & 3;
1055 pr->tid = r[6] & 3;
1056
1057 pr->spmmask_fix_m = (r[13] >> 22) & 0x3;
1058 pr->spn_m = (r[13] >> 16) & 0x3f;
1059 pr->mgnt_vlan_m = (r[13] >> 15) & 1;
1060 pr->dmac_hit_sw_m = (r[13] >> 14) & 1;
1061 pr->not_first_frag_m = (r[13] >> 13) & 1;
1062 pr->frame_type_l4_m = (r[13] >> 10) & 7;
1063 pr->frame_type_m = (r[13] >> 8) & 3;
1064 pr->otag_fmt_m = (r[13] >> 7) & 1;
1065 pr->itag_fmt_m = (r[13] >> 6) & 1;
1066 pr->otag_exist_m = (r[13] >> 5) & 1;
1067 pr->itag_exist_m = (r[13] >> 4) & 1;
1068 pr->frame_type_l2_m = (r[13] >> 2) & 3;
1069 pr->tid_m = r[13] & 3;
1070
1071 pr->valid = r[14] & BIT(31);
1072 pr->cond_not = r[14] & BIT(30);
1073 pr->cond_and1 = r[14] & BIT(29);
1074 pr->cond_and2 = r[14] & BIT(28);
1075 pr->ivalid = r[14] & BIT(27);
1076
1077 pr->drop = (r[17] >> 14) & 3;
1078 pr->fwd_sel = r[17] & BIT(13);
1079 pr->ovid_sel = r[17] & BIT(12);
1080 pr->ivid_sel = r[17] & BIT(11);
1081 pr->flt_sel = r[17] & BIT(10);
1082 pr->log_sel = r[17] & BIT(9);
1083 pr->rmk_sel = r[17] & BIT(8);
1084 pr->meter_sel = r[17] & BIT(7);
1085 pr->tagst_sel = r[17] & BIT(6);
1086 pr->mir_sel = r[17] & BIT(5);
1087 pr->nopri_sel = r[17] & BIT(4);
1088 pr->cpupri_sel = r[17] & BIT(3);
1089 pr->otpid_sel = r[17] & BIT(2);
1090 pr->itpid_sel = r[17] & BIT(1);
1091 pr->shaper_sel = r[17] & BIT(0);
1092 }
1093
1094 static void rtl838x_write_pie_fixed_fields(u32 r[], struct pie_rule *pr)
1095 {
1096 r[6] = ((u32) (pr->spmmask_fix & 0x3)) << 22;
1097 r[6] |= ((u32) (pr->spn & 0x3f)) << 16;
1098 r[6] |= pr->mgnt_vlan ? BIT(15) : 0;
1099 r[6] |= pr->dmac_hit_sw ? BIT(14) : 0;
1100 r[6] |= pr->not_first_frag ? BIT(13) : 0;
1101 r[6] |= ((u32) (pr->frame_type_l4 & 0x7)) << 10;
1102 r[6] |= ((u32) (pr->frame_type & 0x3)) << 8;
1103 r[6] |= pr->otag_fmt ? BIT(7) : 0;
1104 r[6] |= pr->itag_fmt ? BIT(6) : 0;
1105 r[6] |= pr->otag_exist ? BIT(5) : 0;
1106 r[6] |= pr->itag_exist ? BIT(4) : 0;
1107 r[6] |= ((u32) (pr->frame_type_l2 & 0x3)) << 2;
1108 r[6] |= ((u32) (pr->tid & 0x3));
1109
1110 r[13] = ((u32) (pr->spmmask_fix_m & 0x3)) << 22;
1111 r[13] |= ((u32) (pr->spn_m & 0x3f)) << 16;
1112 r[13] |= pr->mgnt_vlan_m ? BIT(15) : 0;
1113 r[13] |= pr->dmac_hit_sw_m ? BIT(14) : 0;
1114 r[13] |= pr->not_first_frag_m ? BIT(13) : 0;
1115 r[13] |= ((u32) (pr->frame_type_l4_m & 0x7)) << 10;
1116 r[13] |= ((u32) (pr->frame_type_m & 0x3)) << 8;
1117 r[13] |= pr->otag_fmt_m ? BIT(7) : 0;
1118 r[13] |= pr->itag_fmt_m ? BIT(6) : 0;
1119 r[13] |= pr->otag_exist_m ? BIT(5) : 0;
1120 r[13] |= pr->itag_exist_m ? BIT(4) : 0;
1121 r[13] |= ((u32) (pr->frame_type_l2_m & 0x3)) << 2;
1122 r[13] |= ((u32) (pr->tid_m & 0x3));
1123
1124 r[14] = pr->valid ? BIT(31) : 0;
1125 r[14] |= pr->cond_not ? BIT(30) : 0;
1126 r[14] |= pr->cond_and1 ? BIT(29) : 0;
1127 r[14] |= pr->cond_and2 ? BIT(28) : 0;
1128 r[14] |= pr->ivalid ? BIT(27) : 0;
1129
1130 if (pr->drop)
1131 r[17] = 0x1 << 14; // Standard drop action
1132 else
1133 r[17] = 0;
1134 r[17] |= pr->fwd_sel ? BIT(13) : 0;
1135 r[17] |= pr->ovid_sel ? BIT(12) : 0;
1136 r[17] |= pr->ivid_sel ? BIT(11) : 0;
1137 r[17] |= pr->flt_sel ? BIT(10) : 0;
1138 r[17] |= pr->log_sel ? BIT(9) : 0;
1139 r[17] |= pr->rmk_sel ? BIT(8) : 0;
1140 r[17] |= pr->meter_sel ? BIT(7) : 0;
1141 r[17] |= pr->tagst_sel ? BIT(6) : 0;
1142 r[17] |= pr->mir_sel ? BIT(5) : 0;
1143 r[17] |= pr->nopri_sel ? BIT(4) : 0;
1144 r[17] |= pr->cpupri_sel ? BIT(3) : 0;
1145 r[17] |= pr->otpid_sel ? BIT(2) : 0;
1146 r[17] |= pr->itpid_sel ? BIT(1) : 0;
1147 r[17] |= pr->shaper_sel ? BIT(0) : 0;
1148 }
1149
1150 static int rtl838x_write_pie_action(u32 r[], struct pie_rule *pr)
1151 {
1152 u16 *aif = (u16 *)&r[17];
1153 u16 data;
1154 int fields_used = 0;
1155
1156 aif--;
1157
1158 pr_debug("%s, at %08x\n", __func__, (u32)aif);
1159 /* Multiple actions can be linked to a match of a PIE rule,
1160 * they have different precedence depending on their type and this precedence
1161 * defines which Action Information Field (0-4) in the IACL table stores
1162 * the additional data of the action (like e.g. the port number a packet is
1163 * forwarded to) */
1164 // TODO: count bits in selectors to limit to a maximum number of actions
1165 if (pr->fwd_sel) { // Forwarding action
1166 data = pr->fwd_act << 13;
1167 data |= pr->fwd_data;
1168 data |= pr->bypass_all ? BIT(12) : 0;
1169 data |= pr->bypass_ibc_sc ? BIT(11) : 0;
1170 data |= pr->bypass_igr_stp ? BIT(10) : 0;
1171 *aif-- = data;
1172 fields_used++;
1173 }
1174
1175 if (pr->ovid_sel) { // Outer VID action
1176 data = (pr->ovid_act & 0x3) << 12;
1177 data |= pr->ovid_data;
1178 *aif-- = data;
1179 fields_used++;
1180 }
1181
1182 if (pr->ivid_sel) { // Inner VID action
1183 data = (pr->ivid_act & 0x3) << 12;
1184 data |= pr->ivid_data;
1185 *aif-- = data;
1186 fields_used++;
1187 }
1188
1189 if (pr->flt_sel) { // Filter action
1190 *aif-- = pr->flt_data;
1191 fields_used++;
1192 }
1193
1194 if (pr->log_sel) { // Log action
1195 if (fields_used >= 4)
1196 return -1;
1197 *aif-- = pr->log_data;
1198 fields_used++;
1199 }
1200
1201 if (pr->rmk_sel) { // Remark action
1202 if (fields_used >= 4)
1203 return -1;
1204 *aif-- = pr->rmk_data;
1205 fields_used++;
1206 }
1207
1208 if (pr->meter_sel) { // Meter action
1209 if (fields_used >= 4)
1210 return -1;
1211 *aif-- = pr->meter_data;
1212 fields_used++;
1213 }
1214
1215 if (pr->tagst_sel) { // Egress Tag Status action
1216 if (fields_used >= 4)
1217 return -1;
1218 *aif-- = pr->tagst_data;
1219 fields_used++;
1220 }
1221
1222 if (pr->mir_sel) { // Mirror action
1223 if (fields_used >= 4)
1224 return -1;
1225 *aif-- = pr->mir_data;
1226 fields_used++;
1227 }
1228
1229 if (pr->nopri_sel) { // Normal Priority action
1230 if (fields_used >= 4)
1231 return -1;
1232 *aif-- = pr->nopri_data;
1233 fields_used++;
1234 }
1235
1236 if (pr->cpupri_sel) { // CPU Priority action
1237 if (fields_used >= 4)
1238 return -1;
1239 *aif-- = pr->nopri_data;
1240 fields_used++;
1241 }
1242
1243 if (pr->otpid_sel) { // OTPID action
1244 if (fields_used >= 4)
1245 return -1;
1246 *aif-- = pr->otpid_data;
1247 fields_used++;
1248 }
1249
1250 if (pr->itpid_sel) { // ITPID action
1251 if (fields_used >= 4)
1252 return -1;
1253 *aif-- = pr->itpid_data;
1254 fields_used++;
1255 }
1256
1257 if (pr->shaper_sel) { // Traffic shaper action
1258 if (fields_used >= 4)
1259 return -1;
1260 *aif-- = pr->shaper_data;
1261 fields_used++;
1262 }
1263
1264 return 0;
1265 }
1266
1267 static void rtl838x_read_pie_action(u32 r[], struct pie_rule *pr)
1268 {
1269 u16 *aif = (u16 *)&r[17];
1270
1271 aif--;
1272
1273 pr_debug("%s, at %08x\n", __func__, (u32)aif);
1274 if (pr->drop)
1275 pr_debug("%s: Action Drop: %d", __func__, pr->drop);
1276
1277 if (pr->fwd_sel){ // Forwarding action
1278 pr->fwd_act = *aif >> 13;
1279 pr->fwd_data = *aif--;
1280 pr->bypass_all = pr->fwd_data & BIT(12);
1281 pr->bypass_ibc_sc = pr->fwd_data & BIT(11);
1282 pr->bypass_igr_stp = pr->fwd_data & BIT(10);
1283 if (pr->bypass_all || pr->bypass_ibc_sc || pr->bypass_igr_stp)
1284 pr->bypass_sel = true;
1285 }
1286 if (pr->ovid_sel) // Outer VID action
1287 pr->ovid_data = *aif--;
1288 if (pr->ivid_sel) // Inner VID action
1289 pr->ivid_data = *aif--;
1290 if (pr->flt_sel) // Filter action
1291 pr->flt_data = *aif--;
1292 if (pr->log_sel) // Log action
1293 pr->log_data = *aif--;
1294 if (pr->rmk_sel) // Remark action
1295 pr->rmk_data = *aif--;
1296 if (pr->meter_sel) // Meter action
1297 pr->meter_data = *aif--;
1298 if (pr->tagst_sel) // Egress Tag Status action
1299 pr->tagst_data = *aif--;
1300 if (pr->mir_sel) // Mirror action
1301 pr->mir_data = *aif--;
1302 if (pr->nopri_sel) // Normal Priority action
1303 pr->nopri_data = *aif--;
1304 if (pr->cpupri_sel) // CPU Priority action
1305 pr->nopri_data = *aif--;
1306 if (pr->otpid_sel) // OTPID action
1307 pr->otpid_data = *aif--;
1308 if (pr->itpid_sel) // ITPID action
1309 pr->itpid_data = *aif--;
1310 if (pr->shaper_sel) // Traffic shaper action
1311 pr->shaper_data = *aif--;
1312 }
1313
1314 static void rtl838x_pie_rule_dump_raw(u32 r[])
1315 {
1316 pr_info("Raw IACL table entry:\n");
1317 pr_info("Match : %08x %08x %08x %08x %08x %08x\n", r[0], r[1], r[2], r[3], r[4], r[5]);
1318 pr_info("Fixed : %08x\n", r[6]);
1319 pr_info("Match M: %08x %08x %08x %08x %08x %08x\n", r[7], r[8], r[9], r[10], r[11], r[12]);
1320 pr_info("Fixed M: %08x\n", r[13]);
1321 pr_info("AIF : %08x %08x %08x\n", r[14], r[15], r[16]);
1322 pr_info("Sel : %08x\n", r[17]);
1323 }
1324
1325 static void rtl838x_pie_rule_dump(struct pie_rule *pr)
1326 {
1327 pr_info("Drop: %d, fwd: %d, ovid: %d, ivid: %d, flt: %d, log: %d, rmk: %d, meter: %d tagst: %d, mir: %d, nopri: %d, cpupri: %d, otpid: %d, itpid: %d, shape: %d\n",
1328 pr->drop, pr->fwd_sel, pr->ovid_sel, pr->ivid_sel, pr->flt_sel, pr->log_sel, pr->rmk_sel, pr->log_sel, pr->tagst_sel, pr->mir_sel, pr->nopri_sel,
1329 pr->cpupri_sel, pr->otpid_sel, pr->itpid_sel, pr->shaper_sel);
1330 if (pr->fwd_sel)
1331 pr_info("FWD: %08x\n", pr->fwd_data);
1332 pr_info("TID: %x, %x\n", pr->tid, pr->tid_m);
1333 }
1334
1335 static int rtl838x_pie_rule_read(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr)
1336 {
1337 // Read IACL table (1) via register 0
1338 struct table_reg *q = rtl_table_get(RTL8380_TBL_0, 1);
1339 u32 r[18];
1340 int i;
1341 int block = idx / PIE_BLOCK_SIZE;
1342 u32 t_select = sw_r32(RTL838X_ACL_BLK_TMPLTE_CTRL(block));
1343
1344 memset(pr, 0, sizeof(*pr));
1345 rtl_table_read(q, idx);
1346 for (i = 0; i < 18; i++)
1347 r[i] = sw_r32(rtl_table_data(q, i));
1348
1349 rtl_table_release(q);
1350
1351 rtl838x_read_pie_fixed_fields(r, pr);
1352 if (!pr->valid)
1353 return 0;
1354
1355 pr_info("%s: template_selectors %08x, tid: %d\n", __func__, t_select, pr->tid);
1356 rtl838x_pie_rule_dump_raw(r);
1357
1358 rtl838x_read_pie_templated(r, pr, fixed_templates[(t_select >> (pr->tid * 3)) & 0x7]);
1359
1360 rtl838x_read_pie_action(r, pr);
1361
1362 return 0;
1363 }
1364
1365 static int rtl838x_pie_rule_write(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr)
1366 {
1367 // Access IACL table (1) via register 0
1368 struct table_reg *q = rtl_table_get(RTL8380_TBL_0, 1);
1369 u32 r[18];
1370 int i, err = 0;
1371 int block = idx / PIE_BLOCK_SIZE;
1372 u32 t_select = sw_r32(RTL838X_ACL_BLK_TMPLTE_CTRL(block));
1373
1374 pr_debug("%s: %d, t_select: %08x\n", __func__, idx, t_select);
1375
1376 for (i = 0; i < 18; i++)
1377 r[i] = 0;
1378
1379 if (!pr->valid)
1380 goto err_out;
1381
1382 rtl838x_write_pie_fixed_fields(r, pr);
1383
1384 pr_debug("%s: template %d\n", __func__, (t_select >> (pr->tid * 3)) & 0x7);
1385 rtl838x_write_pie_templated(r, pr, fixed_templates[(t_select >> (pr->tid * 3)) & 0x7]);
1386
1387 if (rtl838x_write_pie_action(r, pr)) {
1388 pr_err("Rule actions too complex\n");
1389 goto err_out;
1390 }
1391
1392 // rtl838x_pie_rule_dump_raw(r);
1393
1394 for (i = 0; i < 18; i++)
1395 sw_w32(r[i], rtl_table_data(q, i));
1396
1397 err_out:
1398 rtl_table_write(q, idx);
1399 rtl_table_release(q);
1400
1401 return err;
1402 }
1403
1404 static bool rtl838x_pie_templ_has(int t, enum template_field_id field_type)
1405 {
1406 int i;
1407 enum template_field_id ft;
1408
1409 for (i = 0; i < N_FIXED_FIELDS; i++) {
1410 ft = fixed_templates[t][i];
1411 if (field_type == ft)
1412 return true;
1413 }
1414
1415 return false;
1416 }
1417
1418 static int rtl838x_pie_verify_template(struct rtl838x_switch_priv *priv,
1419 struct pie_rule *pr, int t, int block)
1420 {
1421 int i;
1422
1423 if (!pr->is_ipv6 && pr->sip_m && !rtl838x_pie_templ_has(t, TEMPLATE_FIELD_SIP0))
1424 return -1;
1425
1426 if (!pr->is_ipv6 && pr->dip_m && !rtl838x_pie_templ_has(t, TEMPLATE_FIELD_DIP0))
1427 return -1;
1428
1429 if (pr->is_ipv6) {
1430 if ((pr->sip6_m.s6_addr32[0] || pr->sip6_m.s6_addr32[1]
1431 || pr->sip6_m.s6_addr32[2] || pr->sip6_m.s6_addr32[3])
1432 && !rtl838x_pie_templ_has(t, TEMPLATE_FIELD_SIP2))
1433 return -1;
1434 if ((pr->dip6_m.s6_addr32[0] || pr->dip6_m.s6_addr32[1]
1435 || pr->dip6_m.s6_addr32[2] || pr->dip6_m.s6_addr32[3])
1436 && !rtl838x_pie_templ_has(t, TEMPLATE_FIELD_DIP2))
1437 return -1;
1438 }
1439
1440 if (ether_addr_to_u64(pr->smac) && !rtl838x_pie_templ_has(t, TEMPLATE_FIELD_SMAC0))
1441 return -1;
1442
1443 if (ether_addr_to_u64(pr->dmac) && !rtl838x_pie_templ_has(t, TEMPLATE_FIELD_DMAC0))
1444 return -1;
1445
1446 // TODO: Check more
1447
1448 i = find_first_zero_bit(&priv->pie_use_bm[block * 4], PIE_BLOCK_SIZE);
1449
1450 if (i >= PIE_BLOCK_SIZE)
1451 return -1;
1452
1453 return i + PIE_BLOCK_SIZE * block;
1454 }
1455
1456 static int rtl838x_pie_rule_add(struct rtl838x_switch_priv *priv, struct pie_rule *pr)
1457 {
1458 int idx, block, j, t;
1459
1460 pr_debug("In %s\n", __func__);
1461
1462 mutex_lock(&priv->pie_mutex);
1463
1464 for (block = 0; block < priv->n_pie_blocks; block++) {
1465 for (j = 0; j < 3; j++) {
1466 t = (sw_r32(RTL838X_ACL_BLK_TMPLTE_CTRL(block)) >> (j * 3)) & 0x7;
1467 pr_debug("Testing block %d, template %d, template id %d\n", block, j, t);
1468 idx = rtl838x_pie_verify_template(priv, pr, t, block);
1469 if (idx >= 0)
1470 break;
1471 }
1472 if (j < 3)
1473 break;
1474 }
1475
1476 if (block >= priv->n_pie_blocks) {
1477 mutex_unlock(&priv->pie_mutex);
1478 return -EOPNOTSUPP;
1479 }
1480
1481 pr_debug("Using block: %d, index %d, template-id %d\n", block, idx, j);
1482 set_bit(idx, priv->pie_use_bm);
1483
1484 pr->valid = true;
1485 pr->tid = j; // Mapped to template number
1486 pr->tid_m = 0x3;
1487 pr->id = idx;
1488
1489 rtl838x_pie_lookup_enable(priv, idx);
1490 rtl838x_pie_rule_write(priv, idx, pr);
1491
1492 mutex_unlock(&priv->pie_mutex);
1493 return 0;
1494 }
1495
1496 static void rtl838x_pie_rule_rm(struct rtl838x_switch_priv *priv, struct pie_rule *pr)
1497 {
1498 int idx = pr->id;
1499
1500 rtl838x_pie_rule_del(priv, idx, idx);
1501 clear_bit(idx, priv->pie_use_bm);
1502 }
1503
1504 /*
1505 * Initializes the Packet Inspection Engine:
1506 * powers it up, enables default matching templates for all blocks
1507 * and clears all rules possibly installed by u-boot
1508 */
1509 static void rtl838x_pie_init(struct rtl838x_switch_priv *priv)
1510 {
1511 int i;
1512 u32 template_selectors;
1513
1514 mutex_init(&priv->pie_mutex);
1515
1516 // Enable ACL lookup on all ports, including CPU_PORT
1517 for (i = 0; i <= priv->cpu_port; i++)
1518 sw_w32(1, RTL838X_ACL_PORT_LOOKUP_CTRL(i));
1519
1520 // Power on all PIE blocks
1521 for (i = 0; i < priv->n_pie_blocks; i++)
1522 sw_w32_mask(0, BIT(i), RTL838X_ACL_BLK_PWR_CTRL);
1523
1524 // Include IPG in metering
1525 sw_w32(1, RTL838X_METER_GLB_CTRL);
1526
1527 // Delete all present rules
1528 rtl838x_pie_rule_del(priv, 0, priv->n_pie_blocks * PIE_BLOCK_SIZE - 1);
1529
1530 // Routing bypasses source port filter: disable write-protection, first
1531 sw_w32_mask(0, 3, RTL838X_INT_RW_CTRL);
1532 sw_w32_mask(0, 1, RTL838X_DMY_REG27);
1533 sw_w32_mask(3, 0, RTL838X_INT_RW_CTRL);
1534
1535 // Enable predefined templates 0, 1 and 2 for even blocks
1536 template_selectors = 0 | (1 << 3) | (2 << 6);
1537 for (i = 0; i < 6; i += 2)
1538 sw_w32(template_selectors, RTL838X_ACL_BLK_TMPLTE_CTRL(i));
1539
1540 // Enable predefined templates 0, 3 and 4 (IPv6 support) for odd blocks
1541 template_selectors = 0 | (3 << 3) | (4 << 6);
1542 for (i = 1; i < priv->n_pie_blocks; i += 2)
1543 sw_w32(template_selectors, RTL838X_ACL_BLK_TMPLTE_CTRL(i));
1544
1545 // Group each pair of physical blocks together to a logical block
1546 sw_w32(0b10101010101, RTL838X_ACL_BLK_GROUP_CTRL);
1547 }
1548
1549 static u32 rtl838x_packet_cntr_read(int counter)
1550 {
1551 u32 v;
1552
1553 // Read LOG table (3) via register RTL8380_TBL_0
1554 struct table_reg *r = rtl_table_get(RTL8380_TBL_0, 3);
1555
1556 pr_debug("In %s, id %d\n", __func__, counter);
1557 rtl_table_read(r, counter / 2);
1558
1559 pr_debug("Registers: %08x %08x\n",
1560 sw_r32(rtl_table_data(r, 0)), sw_r32(rtl_table_data(r, 1)));
1561 // The table has a size of 2 registers
1562 if (counter % 2)
1563 v = sw_r32(rtl_table_data(r, 0));
1564 else
1565 v = sw_r32(rtl_table_data(r, 1));
1566
1567 rtl_table_release(r);
1568
1569 return v;
1570 }
1571
1572 static void rtl838x_packet_cntr_clear(int counter)
1573 {
1574 // Access LOG table (3) via register RTL8380_TBL_0
1575 struct table_reg *r = rtl_table_get(RTL8380_TBL_0, 3);
1576
1577 pr_debug("In %s, id %d\n", __func__, counter);
1578 // The table has a size of 2 registers
1579 if (counter % 2)
1580 sw_w32(0, rtl_table_data(r, 0));
1581 else
1582 sw_w32(0, rtl_table_data(r, 1));
1583
1584 rtl_table_write(r, counter / 2);
1585
1586 rtl_table_release(r);
1587 }
1588
1589 static void rtl838x_route_read(int idx, struct rtl83xx_route *rt)
1590 {
1591 // Read ROUTING table (2) via register RTL8380_TBL_1
1592 struct table_reg *r = rtl_table_get(RTL8380_TBL_1, 2);
1593
1594 pr_debug("In %s, id %d\n", __func__, idx);
1595 rtl_table_read(r, idx);
1596
1597 // The table has a size of 2 registers
1598 rt->nh.gw = sw_r32(rtl_table_data(r, 0));
1599 rt->nh.gw <<= 32;
1600 rt->nh.gw |= sw_r32(rtl_table_data(r, 1));
1601
1602 rtl_table_release(r);
1603 }
1604
1605 static void rtl838x_route_write(int idx, struct rtl83xx_route *rt)
1606 {
1607 // Access ROUTING table (2) via register RTL8380_TBL_1
1608 struct table_reg *r = rtl_table_get(RTL8380_TBL_1, 2);
1609
1610 pr_debug("In %s, id %d, gw: %016llx\n", __func__, idx, rt->nh.gw);
1611 sw_w32(rt->nh.gw >> 32, rtl_table_data(r, 0));
1612 sw_w32(rt->nh.gw, rtl_table_data(r, 1));
1613 rtl_table_write(r, idx);
1614
1615 rtl_table_release(r);
1616 }
1617
1618 static int rtl838x_l3_setup(struct rtl838x_switch_priv *priv)
1619 {
1620 // Nothing to be done
1621 return 0;
1622 }
1623
1624 void rtl838x_vlan_port_pvidmode_set(int port, enum pbvlan_type type, enum pbvlan_mode mode)
1625 {
1626 if (type == PBVLAN_TYPE_INNER)
1627 sw_w32_mask(0x3, mode, RTL838X_VLAN_PORT_PB_VLAN + (port << 2));
1628 else
1629 sw_w32_mask(0x3 << 14, mode << 14, RTL838X_VLAN_PORT_PB_VLAN + (port << 2));
1630 }
1631
1632 void rtl838x_vlan_port_pvid_set(int port, enum pbvlan_type type, int pvid)
1633 {
1634 if (type == PBVLAN_TYPE_INNER)
1635 sw_w32_mask(0xfff << 2, pvid << 2, RTL838X_VLAN_PORT_PB_VLAN + (port << 2));
1636 else
1637 sw_w32_mask(0xfff << 16, pvid << 16, RTL838X_VLAN_PORT_PB_VLAN + (port << 2));
1638 }
1639
1640 static int rtl838x_set_ageing_time(unsigned long msec)
1641 {
1642 int t = sw_r32(RTL838X_L2_CTRL_1);
1643
1644 t &= 0x7FFFFF;
1645 t = t * 128 / 625; /* Aging time in seconds. 0: L2 aging disabled */
1646 pr_debug("L2 AGING time: %d sec\n", t);
1647
1648 t = (msec * 625 + 127000) / 128000;
1649 t = t > 0x7FFFFF ? 0x7FFFFF : t;
1650 sw_w32_mask(0x7FFFFF, t, RTL838X_L2_CTRL_1);
1651 pr_debug("Dynamic aging for ports: %x\n", sw_r32(RTL838X_L2_PORT_AGING_OUT));
1652
1653 return 0;
1654 }
1655
1656 static void rtl838x_set_igr_filter(int port, enum igr_filter state)
1657 {
1658 sw_w32_mask(0x3 << ((port & 0xf)<<1), state << ((port & 0xf)<<1),
1659 RTL838X_VLAN_PORT_IGR_FLTR + (((port >> 4) << 2)));
1660 }
1661
1662 static void rtl838x_set_egr_filter(int port, enum egr_filter state)
1663 {
1664 sw_w32_mask(0x1 << (port % 0x1d), state << (port % 0x1d),
1665 RTL838X_VLAN_PORT_EGR_FLTR + (((port / 29) << 2)));
1666 }
1667
1668 void rtl838x_set_distribution_algorithm(int group, int algoidx, u32 algomsk)
1669 {
1670 algoidx &= 1; // RTL838X only supports 2 concurrent algorithms
1671 sw_w32_mask(1 << (group % 8), algoidx << (group % 8),
1672 RTL838X_TRK_HASH_IDX_CTRL + ((group >> 3) << 2));
1673 sw_w32(algomsk, RTL838X_TRK_HASH_CTRL + (algoidx << 2));
1674 }
1675
1676 void rtl838x_set_receive_management_action(int port, rma_ctrl_t type, action_type_t action)
1677 {
1678 switch(type) {
1679 case BPDU:
1680 sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1),
1681 RTL838X_RMA_BPDU_CTRL + ((port >> 4) << 2));
1682 break;
1683 case PTP:
1684 sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1),
1685 RTL838X_RMA_PTP_CTRL + ((port >> 4) << 2));
1686 break;
1687 case LLTP:
1688 sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1),
1689 RTL838X_RMA_LLTP_CTRL + ((port >> 4) << 2));
1690 break;
1691 default:
1692 break;
1693 }
1694 }
1695
1696 const struct rtl838x_reg rtl838x_reg = {
1697 .mask_port_reg_be = rtl838x_mask_port_reg,
1698 .set_port_reg_be = rtl838x_set_port_reg,
1699 .get_port_reg_be = rtl838x_get_port_reg,
1700 .mask_port_reg_le = rtl838x_mask_port_reg,
1701 .set_port_reg_le = rtl838x_set_port_reg,
1702 .get_port_reg_le = rtl838x_get_port_reg,
1703 .stat_port_rst = RTL838X_STAT_PORT_RST,
1704 .stat_rst = RTL838X_STAT_RST,
1705 .stat_port_std_mib = RTL838X_STAT_PORT_STD_MIB,
1706 .port_iso_ctrl = rtl838x_port_iso_ctrl,
1707 .traffic_enable = rtl838x_traffic_enable,
1708 .traffic_disable = rtl838x_traffic_disable,
1709 .traffic_get = rtl838x_traffic_get,
1710 .traffic_set = rtl838x_traffic_set,
1711 .l2_ctrl_0 = RTL838X_L2_CTRL_0,
1712 .l2_ctrl_1 = RTL838X_L2_CTRL_1,
1713 .l2_port_aging_out = RTL838X_L2_PORT_AGING_OUT,
1714 .set_ageing_time = rtl838x_set_ageing_time,
1715 .smi_poll_ctrl = RTL838X_SMI_POLL_CTRL,
1716 .l2_tbl_flush_ctrl = RTL838X_L2_TBL_FLUSH_CTRL,
1717 .exec_tbl0_cmd = rtl838x_exec_tbl0_cmd,
1718 .exec_tbl1_cmd = rtl838x_exec_tbl1_cmd,
1719 .tbl_access_data_0 = rtl838x_tbl_access_data_0,
1720 .isr_glb_src = RTL838X_ISR_GLB_SRC,
1721 .isr_port_link_sts_chg = RTL838X_ISR_PORT_LINK_STS_CHG,
1722 .imr_port_link_sts_chg = RTL838X_IMR_PORT_LINK_STS_CHG,
1723 .imr_glb = RTL838X_IMR_GLB,
1724 .vlan_tables_read = rtl838x_vlan_tables_read,
1725 .vlan_set_tagged = rtl838x_vlan_set_tagged,
1726 .vlan_set_untagged = rtl838x_vlan_set_untagged,
1727 .mac_force_mode_ctrl = rtl838x_mac_force_mode_ctrl,
1728 .vlan_profile_dump = rtl838x_vlan_profile_dump,
1729 .vlan_profile_setup = rtl838x_vlan_profile_setup,
1730 .vlan_fwd_on_inner = rtl838x_vlan_fwd_on_inner,
1731 .set_vlan_igr_filter = rtl838x_set_igr_filter,
1732 .set_vlan_egr_filter = rtl838x_set_egr_filter,
1733 .enable_learning = rtl838x_enable_learning,
1734 .enable_flood = rtl838x_enable_flood,
1735 .enable_mcast_flood = rtl838x_enable_mcast_flood,
1736 .enable_bcast_flood = rtl838x_enable_bcast_flood,
1737 .stp_get = rtl838x_stp_get,
1738 .stp_set = rtl838x_stp_set,
1739 .mac_port_ctrl = rtl838x_mac_port_ctrl,
1740 .l2_port_new_salrn = rtl838x_l2_port_new_salrn,
1741 .l2_port_new_sa_fwd = rtl838x_l2_port_new_sa_fwd,
1742 .mir_ctrl = RTL838X_MIR_CTRL,
1743 .mir_dpm = RTL838X_MIR_DPM_CTRL,
1744 .mir_spm = RTL838X_MIR_SPM_CTRL,
1745 .mac_link_sts = RTL838X_MAC_LINK_STS,
1746 .mac_link_dup_sts = RTL838X_MAC_LINK_DUP_STS,
1747 .mac_link_spd_sts = rtl838x_mac_link_spd_sts,
1748 .mac_rx_pause_sts = RTL838X_MAC_RX_PAUSE_STS,
1749 .mac_tx_pause_sts = RTL838X_MAC_TX_PAUSE_STS,
1750 .read_l2_entry_using_hash = rtl838x_read_l2_entry_using_hash,
1751 .write_l2_entry_using_hash = rtl838x_write_l2_entry_using_hash,
1752 .read_cam = rtl838x_read_cam,
1753 .write_cam = rtl838x_write_cam,
1754 .vlan_port_tag_sts_ctrl = RTL838X_VLAN_PORT_TAG_STS_CTRL,
1755 .vlan_port_pvidmode_set = rtl838x_vlan_port_pvidmode_set,
1756 .vlan_port_pvid_set = rtl838x_vlan_port_pvid_set,
1757 .trk_mbr_ctr = rtl838x_trk_mbr_ctr,
1758 .rma_bpdu_fld_pmask = RTL838X_RMA_BPDU_FLD_PMSK,
1759 .spcl_trap_eapol_ctrl = RTL838X_SPCL_TRAP_EAPOL_CTRL,
1760 .init_eee = rtl838x_init_eee,
1761 .port_eee_set = rtl838x_port_eee_set,
1762 .eee_port_ability = rtl838x_eee_port_ability,
1763 .l2_hash_seed = rtl838x_l2_hash_seed,
1764 .l2_hash_key = rtl838x_l2_hash_key,
1765 .read_mcast_pmask = rtl838x_read_mcast_pmask,
1766 .write_mcast_pmask = rtl838x_write_mcast_pmask,
1767 .pie_init = rtl838x_pie_init,
1768 .pie_rule_read = rtl838x_pie_rule_read,
1769 .pie_rule_write = rtl838x_pie_rule_write,
1770 .pie_rule_add = rtl838x_pie_rule_add,
1771 .pie_rule_rm = rtl838x_pie_rule_rm,
1772 .l2_learning_setup = rtl838x_l2_learning_setup,
1773 .packet_cntr_read = rtl838x_packet_cntr_read,
1774 .packet_cntr_clear = rtl838x_packet_cntr_clear,
1775 .route_read = rtl838x_route_read,
1776 .route_write = rtl838x_route_write,
1777 .l3_setup = rtl838x_l3_setup,
1778 .set_distribution_algorithm = rtl838x_set_distribution_algorithm,
1779 .set_receive_management_action = rtl838x_set_receive_management_action,
1780 };
1781
1782 irqreturn_t rtl838x_switch_irq(int irq, void *dev_id)
1783 {
1784 struct dsa_switch *ds = dev_id;
1785 u32 status = sw_r32(RTL838X_ISR_GLB_SRC);
1786 u32 ports = sw_r32(RTL838X_ISR_PORT_LINK_STS_CHG);
1787 u32 link;
1788 int i;
1789
1790 /* Clear status */
1791 sw_w32(ports, RTL838X_ISR_PORT_LINK_STS_CHG);
1792 pr_info("RTL8380 Link change: status: %x, ports %x\n", status, ports);
1793
1794 for (i = 0; i < 28; i++) {
1795 if (ports & BIT(i)) {
1796 link = sw_r32(RTL838X_MAC_LINK_STS);
1797 if (link & BIT(i))
1798 dsa_port_phylink_mac_change(ds, i, true);
1799 else
1800 dsa_port_phylink_mac_change(ds, i, false);
1801 }
1802 }
1803 return IRQ_HANDLED;
1804 }
1805
1806 int rtl838x_smi_wait_op(int timeout)
1807 {
1808 unsigned long end = jiffies + usecs_to_jiffies(timeout);
1809
1810 while (1) {
1811 if (!(sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1) & 0x1))
1812 return 0;
1813
1814 if (time_after(jiffies, end))
1815 break;
1816
1817 usleep_range(10, 20);
1818 }
1819
1820 pr_err("rtl838x_smi_wait_op: timeout\n");
1821 return -1;
1822 }
1823
1824 /*
1825 * Reads a register in a page from the PHY
1826 */
1827 int rtl838x_read_phy(u32 port, u32 page, u32 reg, u32 *val)
1828 {
1829 u32 v;
1830 u32 park_page;
1831
1832 if (port > 31) {
1833 *val = 0xffff;
1834 return 0;
1835 }
1836
1837 if (page > 4095 || reg > 31)
1838 return -ENOTSUPP;
1839
1840 mutex_lock(&smi_lock);
1841
1842 if (rtl838x_smi_wait_op(100000))
1843 goto timeout;
1844
1845 sw_w32_mask(0xffff0000, port << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);
1846
1847 park_page = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1) & ((0x1f << 15) | 0x2);
1848 v = reg << 20 | page << 3;
1849 sw_w32(v | park_page, RTL838X_SMI_ACCESS_PHY_CTRL_1);
1850 sw_w32_mask(0, 1, RTL838X_SMI_ACCESS_PHY_CTRL_1);
1851
1852 if (rtl838x_smi_wait_op(100000))
1853 goto timeout;
1854
1855 *val = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_2) & 0xffff;
1856
1857 mutex_unlock(&smi_lock);
1858 return 0;
1859
1860 timeout:
1861 mutex_unlock(&smi_lock);
1862 return -ETIMEDOUT;
1863 }
1864
1865 /*
1866 * Write to a register in a page of the PHY
1867 */
1868 int rtl838x_write_phy(u32 port, u32 page, u32 reg, u32 val)
1869 {
1870 u32 v;
1871 u32 park_page;
1872
1873 val &= 0xffff;
1874 if (port > 31 || page > 4095 || reg > 31)
1875 return -ENOTSUPP;
1876
1877 mutex_lock(&smi_lock);
1878 if (rtl838x_smi_wait_op(100000))
1879 goto timeout;
1880
1881 sw_w32(BIT(port), RTL838X_SMI_ACCESS_PHY_CTRL_0);
1882 mdelay(10);
1883
1884 sw_w32_mask(0xffff0000, val << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);
1885
1886 park_page = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1) & ((0x1f << 15) | 0x2);
1887 v = reg << 20 | page << 3 | 0x4;
1888 sw_w32(v | park_page, RTL838X_SMI_ACCESS_PHY_CTRL_1);
1889 sw_w32_mask(0, 1, RTL838X_SMI_ACCESS_PHY_CTRL_1);
1890
1891 if (rtl838x_smi_wait_op(100000))
1892 goto timeout;
1893
1894 mutex_unlock(&smi_lock);
1895 return 0;
1896
1897 timeout:
1898 mutex_unlock(&smi_lock);
1899 return -ETIMEDOUT;
1900 }
1901
1902 /*
1903 * Read an mmd register of a PHY
1904 */
1905 int rtl838x_read_mmd_phy(u32 port, u32 addr, u32 reg, u32 *val)
1906 {
1907 u32 v;
1908
1909 mutex_lock(&smi_lock);
1910
1911 if (rtl838x_smi_wait_op(100000))
1912 goto timeout;
1913
1914 sw_w32(1 << port, RTL838X_SMI_ACCESS_PHY_CTRL_0);
1915 mdelay(10);
1916
1917 sw_w32_mask(0xffff0000, port << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);
1918
1919 v = addr << 16 | reg;
1920 sw_w32(v, RTL838X_SMI_ACCESS_PHY_CTRL_3);
1921
1922 /* mmd-access | read | cmd-start */
1923 v = 1 << 1 | 0 << 2 | 1;
1924 sw_w32(v, RTL838X_SMI_ACCESS_PHY_CTRL_1);
1925
1926 if (rtl838x_smi_wait_op(100000))
1927 goto timeout;
1928
1929 *val = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_2) & 0xffff;
1930
1931 mutex_unlock(&smi_lock);
1932 return 0;
1933
1934 timeout:
1935 mutex_unlock(&smi_lock);
1936 return -ETIMEDOUT;
1937 }
1938
1939 /*
1940 * Write to an mmd register of a PHY
1941 */
1942 int rtl838x_write_mmd_phy(u32 port, u32 addr, u32 reg, u32 val)
1943 {
1944 u32 v;
1945
1946 pr_debug("MMD write: port %d, dev %d, reg %d, val %x\n", port, addr, reg, val);
1947 val &= 0xffff;
1948 mutex_lock(&smi_lock);
1949
1950 if (rtl838x_smi_wait_op(100000))
1951 goto timeout;
1952
1953 sw_w32(1 << port, RTL838X_SMI_ACCESS_PHY_CTRL_0);
1954 mdelay(10);
1955
1956 sw_w32_mask(0xffff0000, val << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);
1957
1958 sw_w32_mask(0x1f << 16, addr << 16, RTL838X_SMI_ACCESS_PHY_CTRL_3);
1959 sw_w32_mask(0xffff, reg, RTL838X_SMI_ACCESS_PHY_CTRL_3);
1960 /* mmd-access | write | cmd-start */
1961 v = 1 << 1 | 1 << 2 | 1;
1962 sw_w32(v, RTL838X_SMI_ACCESS_PHY_CTRL_1);
1963
1964 if (rtl838x_smi_wait_op(100000))
1965 goto timeout;
1966
1967 mutex_unlock(&smi_lock);
1968 return 0;
1969
1970 timeout:
1971 mutex_unlock(&smi_lock);
1972 return -ETIMEDOUT;
1973 }
1974
1975 void rtl8380_get_version(struct rtl838x_switch_priv *priv)
1976 {
1977 u32 rw_save, info_save;
1978 u32 info;
1979
1980 rw_save = sw_r32(RTL838X_INT_RW_CTRL);
1981 sw_w32(rw_save | 0x3, RTL838X_INT_RW_CTRL);
1982
1983 info_save = sw_r32(RTL838X_CHIP_INFO);
1984 sw_w32(info_save | 0xA0000000, RTL838X_CHIP_INFO);
1985
1986 info = sw_r32(RTL838X_CHIP_INFO);
1987 sw_w32(info_save, RTL838X_CHIP_INFO);
1988 sw_w32(rw_save, RTL838X_INT_RW_CTRL);
1989
1990 if ((info & 0xFFFF) == 0x6275) {
1991 if (((info >> 16) & 0x1F) == 0x1)
1992 priv->version = RTL8380_VERSION_A;
1993 else if (((info >> 16) & 0x1F) == 0x2)
1994 priv->version = RTL8380_VERSION_B;
1995 else
1996 priv->version = RTL8380_VERSION_B;
1997 } else {
1998 priv->version = '-';
1999 }
2000 }
2001
2002 void rtl838x_vlan_profile_dump(int profile)
2003 {
2004 u32 p;
2005
2006 if (profile < 0 || profile > 7)
2007 return;
2008
2009 p = sw_r32(RTL838X_VLAN_PROFILE(profile));
2010
2011 pr_info("VLAN profile %d: L2 learning: %d, UNKN L2MC FLD PMSK %d, \
2012 UNKN IPMC FLD PMSK %d, UNKN IPv6MC FLD PMSK: %d",
2013 profile, p & 1, (p >> 1) & 0x1ff, (p >> 10) & 0x1ff, (p >> 19) & 0x1ff);
2014 }
2015
2016 void rtl8380_sds_rst(int mac)
2017 {
2018 u32 offset = (mac == 24) ? 0 : 0x100;
2019
2020 sw_w32_mask(1 << 11, 0, RTL838X_SDS4_FIB_REG0 + offset);
2021 sw_w32_mask(0x3, 0, RTL838X_SDS4_REG28 + offset);
2022 sw_w32_mask(0x3, 0x3, RTL838X_SDS4_REG28 + offset);
2023 sw_w32_mask(0, 0x1 << 6, RTL838X_SDS4_DUMMY0 + offset);
2024 sw_w32_mask(0x1 << 6, 0, RTL838X_SDS4_DUMMY0 + offset);
2025 pr_debug("SERDES reset: %d\n", mac);
2026 }
2027
2028 int rtl8380_sds_power(int mac, int val)
2029 {
2030 u32 mode = (val == 1) ? 0x4 : 0x9;
2031 u32 offset = (mac == 24) ? 5 : 0;
2032
2033 if ((mac != 24) && (mac != 26)) {
2034 pr_err("%s: not a fibre port: %d\n", __func__, mac);
2035 return -1;
2036 }
2037
2038 sw_w32_mask(0x1f << offset, mode << offset, RTL838X_SDS_MODE_SEL);
2039
2040 rtl8380_sds_rst(mac);
2041
2042 return 0;
2043 }
Staging tree of Jo-Philipp Wich